From 76177aa280494bb36d7a0bcbda1078d4db717020 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Mon, 9 Dec 2019 11:25:19 +0100 Subject: Official ARM version: v4.5 --- Documentation/Core/html/struct_s_c_b___type.html | 460 +++++++++++++++++++++++ 1 file changed, 460 insertions(+) create mode 100644 Documentation/Core/html/struct_s_c_b___type.html (limited to 'Documentation/Core/html/struct_s_c_b___type.html') diff --git a/Documentation/Core/html/struct_s_c_b___type.html b/Documentation/Core/html/struct_s_c_b___type.html new file mode 100644 index 0000000..2bc4a47 --- /dev/null +++ b/Documentation/Core/html/struct_s_c_b___type.html @@ -0,0 +1,460 @@ + + + + + +SCB_Type Struct Reference +CMSIS-CORE: SCB_Type Struct Reference + + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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SCB_Type Struct Reference
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Structure type to access the System Control Block (SCB). +

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__IM uint32_t CPUID
 Offset: 0x000 (R/ ) CPUID Base Register.
 
__IOM uint32_t ICSR
 Offset: 0x004 (R/W) Interrupt Control and State Register.
 
__IOM uint32_t VTOR
 Offset: 0x008 (R/W) Vector Table Offset Register.
 
__IOM uint32_t AIRCR
 Offset: 0x00C (R/W) Application Interrupt and Reset Control Register.
 
__IOM uint32_t SCR
 Offset: 0x010 (R/W) System Control Register.
 
__IOM uint32_t CCR
 Offset: 0x014 (R/W) Configuration Control Register.
 
__IOM uint8_t SHP [12]
 Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
 
__IOM uint32_t SHCSR
 Offset: 0x024 (R/W) System Handler Control and State Register.
 
__IOM uint32_t CFSR
 Offset: 0x028 (R/W) Configurable Fault Status Register.
 
__IOM uint32_t HFSR
 Offset: 0x02C (R/W) HardFault Status Register.
 
__IOM uint32_t DFSR
 Offset: 0x030 (R/W) Debug Fault Status Register.
 
__IOM uint32_t MMFAR
 Offset: 0x034 (R/W) MemManage Fault Address Register.
 
__IOM uint32_t BFAR
 Offset: 0x038 (R/W) BusFault Address Register.
 
__IOM uint32_t AFSR
 Offset: 0x03C (R/W) Auxiliary Fault Status Register.
 
__IM uint32_t PFR [2]
 Offset: 0x040 (R/ ) Processor Feature Register.
 
__IM uint32_t DFR
 Offset: 0x048 (R/ ) Debug Feature Register.
 
__IM uint32_t ADR
 Offset: 0x04C (R/ ) Auxiliary Feature Register.
 
__IM uint32_t MMFR [4]
 Offset: 0x050 (R/ ) Memory Model Feature Register.
 
__IM uint32_t ISAR [5]
 Offset: 0x060 (R/ ) Instruction Set Attributes Register.
 
uint32_t RESERVED0 [5]
 Reserved.
 
__IOM uint32_t CPACR
 Offset: 0x088 (R/W) Coprocessor Access Control Register.
 
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Field Documentation

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__IM uint32_t SCB_Type::ADR
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__IOM uint32_t SCB_Type::AFSR
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__IOM uint32_t SCB_Type::AIRCR
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__IOM uint32_t SCB_Type::BFAR
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__IOM uint32_t SCB_Type::CCR
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__IOM uint32_t SCB_Type::CFSR
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__IOM uint32_t SCB_Type::CPACR
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__IM uint32_t SCB_Type::CPUID
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__IM uint32_t SCB_Type::DFR
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__IOM uint32_t SCB_Type::DFSR
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__IOM uint32_t SCB_Type::HFSR
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__IOM uint32_t SCB_Type::ICSR
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__IM uint32_t SCB_Type::ISAR[5]
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__IOM uint32_t SCB_Type::MMFAR
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__IM uint32_t SCB_Type::MMFR[4]
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__IM uint32_t SCB_Type::PFR[2]
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uint32_t SCB_Type::RESERVED0[5]
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__IOM uint32_t SCB_Type::SCR
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__IOM uint32_t SCB_Type::SHCSR
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__IOM uint8_t SCB_Type::SHP[12]
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__IOM uint32_t SCB_Type::VTOR
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