From 76177aa280494bb36d7a0bcbda1078d4db717020 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Mon, 9 Dec 2019 11:25:19 +0100 Subject: Official ARM version: v4.5 --- Documentation/Core/html/struct_n_v_i_c___type.html | 340 +++++++++++++++++++++ 1 file changed, 340 insertions(+) create mode 100644 Documentation/Core/html/struct_n_v_i_c___type.html (limited to 'Documentation/Core/html/struct_n_v_i_c___type.html') diff --git a/Documentation/Core/html/struct_n_v_i_c___type.html b/Documentation/Core/html/struct_n_v_i_c___type.html new file mode 100644 index 0000000..a6b9a0a --- /dev/null +++ b/Documentation/Core/html/struct_n_v_i_c___type.html @@ -0,0 +1,340 @@ + + + + + +NVIC_Type Struct Reference +CMSIS-CORE: NVIC_Type Struct Reference + + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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+Data Fields
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NVIC_Type Struct Reference
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Structure type to access the Nested Vectored Interrupt Controller (NVIC). +

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__IOM uint32_t ISER [8]
 Offset: 0x000 (R/W) Interrupt Set Enable Register.
 
uint32_t RESERVED0 [24]
 Reserved.
 
__IOM uint32_t ICER [8]
 Offset: 0x080 (R/W) Interrupt Clear Enable Register.
 
uint32_t RSERVED1 [24]
 Reserved.
 
__IOM uint32_t ISPR [8]
 Offset: 0x100 (R/W) Interrupt Set Pending Register.
 
uint32_t RESERVED2 [24]
 Reserved.
 
__IOM uint32_t ICPR [8]
 Offset: 0x180 (R/W) Interrupt Clear Pending Register.
 
uint32_t RESERVED3 [24]
 Reserved.
 
__IOM uint32_t IABR [8]
 Offset: 0x200 (R/W) Interrupt Active bit Register.
 
uint32_t RESERVED4 [56]
 Reserved.
 
__IOM uint8_t IP [240]
 Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
 
uint32_t RESERVED5 [644]
 Reserved.
 
__OM uint32_t STIR
 Offset: 0xE00 ( /W) Software Trigger Interrupt Register.
 
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Field Documentation

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__IOM uint32_t NVIC_Type::IABR[8]
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__IOM uint32_t NVIC_Type::ICER[8]
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__IOM uint32_t NVIC_Type::ICPR[8]
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__IOM uint8_t NVIC_Type::IP[240]
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__IOM uint32_t NVIC_Type::ISER[8]
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__IOM uint32_t NVIC_Type::ISPR[8]
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uint32_t NVIC_Type::RESERVED0[24]
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uint32_t NVIC_Type::RESERVED2[24]
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uint32_t NVIC_Type::RESERVED3[24]
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uint32_t NVIC_Type::RESERVED4[56]
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uint32_t NVIC_Type::RESERVED5[644]
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uint32_t NVIC_Type::RSERVED1[24]
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__OM uint32_t NVIC_Type::STIR
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