From 76177aa280494bb36d7a0bcbda1078d4db717020 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Mon, 9 Dec 2019 11:25:19 +0100 Subject: Official ARM version: v4.5 --- Documentation/Core/html/struct_i_t_m___type.html | 296 +++++++++++++++++++++++ 1 file changed, 296 insertions(+) create mode 100644 Documentation/Core/html/struct_i_t_m___type.html (limited to 'Documentation/Core/html/struct_i_t_m___type.html') diff --git a/Documentation/Core/html/struct_i_t_m___type.html b/Documentation/Core/html/struct_i_t_m___type.html new file mode 100644 index 0000000..ba162b2 --- /dev/null +++ b/Documentation/Core/html/struct_i_t_m___type.html @@ -0,0 +1,296 @@ + + + + + +ITM_Type Struct Reference +CMSIS-CORE: ITM_Type Struct Reference + + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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ITM_Type Struct Reference
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Structure type to access the Instrumentation Trace Macrocell Register (ITM). +

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union {
   __OM uint8_t   u8
 Offset: 0x000 ( /W) ITM Stimulus Port 8-bit.
 
   __OM uint16_t   u16
 Offset: 0x000 ( /W) ITM Stimulus Port 16-bit.
 
   __OM uint32_t   u32
 Offset: 0x000 ( /W) ITM Stimulus Port 32-bit.
 
} PORT [32]
 Offset: 0x000 ( /W) ITM Stimulus Port Registers.
 
uint32_t RESERVED0 [864]
 Reserved.
 
__IOM uint32_t TER
 Offset: 0xE00 (R/W) ITM Trace Enable Register.
 
uint32_t RESERVED1 [15]
 Reserved.
 
__IOM uint32_t TPR
 Offset: 0xE40 (R/W) ITM Trace Privilege Register.
 
uint32_t RESERVED2 [15]
 Reserved.
 
__IOM uint32_t TCR
 Offset: 0xE80 (R/W) ITM Trace Control Register.
 
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Field Documentation

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__OM { ... } ITM_Type::PORT[32]
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uint32_t ITM_Type::RESERVED0[864]
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uint32_t ITM_Type::RESERVED1[15]
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uint32_t ITM_Type::RESERVED2[15]
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__IOM uint32_t ITM_Type::TCR
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__IOM uint32_t ITM_Type::TER
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__IOM uint32_t ITM_Type::TPR
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__OM uint16_t ITM_Type::u16
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__OM uint32_t ITM_Type::u32
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__OM uint8_t ITM_Type::u8
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