From 76177aa280494bb36d7a0bcbda1078d4db717020 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Mon, 9 Dec 2019 11:25:19 +0100 Subject: Official ARM version: v4.5 --- .../Core/html/struct_core_debug___type.html | 205 +++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 Documentation/Core/html/struct_core_debug___type.html (limited to 'Documentation/Core/html/struct_core_debug___type.html') diff --git a/Documentation/Core/html/struct_core_debug___type.html b/Documentation/Core/html/struct_core_debug___type.html new file mode 100644 index 0000000..9f82c8c --- /dev/null +++ b/Documentation/Core/html/struct_core_debug___type.html @@ -0,0 +1,205 @@ + + + + + +CoreDebug_Type Struct Reference +CMSIS-CORE: CoreDebug_Type Struct Reference + + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.30 +
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CMSIS-CORE support for Cortex-M processor-based devices
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+Data Fields
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CoreDebug_Type Struct Reference
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Structure type to access the Core Debug Register (CoreDebug). +

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__IOM uint32_t DHCSR
 Offset: 0x000 (R/W) Debug Halting Control and Status Register.
 
__OM uint32_t DCRSR
 Offset: 0x004 ( /W) Debug Core Register Selector Register.
 
__IOM uint32_t DCRDR
 Offset: 0x008 (R/W) Debug Core Register Data Register.
 
__IOM uint32_t DEMCR
 Offset: 0x00C (R/W) Debug Exception and Monitor Control Register.
 
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Field Documentation

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__IOM uint32_t CoreDebug_Type::DCRDR
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__OM uint32_t CoreDebug_Type::DCRSR
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__IOM uint32_t CoreDebug_Type::DEMCR
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__IOM uint32_t CoreDebug_Type::DHCSR
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+ + + + -- cgit