From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- .../Core/html/group__cache__functions__m7.html | 152 --------------------- 1 file changed, 152 deletions(-) delete mode 100644 Documentation/Core/html/group__cache__functions__m7.html (limited to 'Documentation/Core/html/group__cache__functions__m7.html') diff --git a/Documentation/Core/html/group__cache__functions__m7.html b/Documentation/Core/html/group__cache__functions__m7.html deleted file mode 100644 index 7ba5f9a..0000000 --- a/Documentation/Core/html/group__cache__functions__m7.html +++ /dev/null @@ -1,152 +0,0 @@ - - - - - -Cache Functions (only Cortex-M7) -CMSIS-CORE: Cache Functions (only Cortex-M7) - - - - - - - - - - - - - - - -
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CMSIS-CORE support for Cortex-M processor-based devices
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Cache Functions (only Cortex-M7)
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Functions for Instruction and Data Cache. -More...

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 I-Cache Functions
 Functions for the instruction cache.
 
 D-Cache Functions
 Functions for the data cache.
 
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Description

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Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of [0;4;8;16;32;64]KB. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.

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All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.

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Note
After reset, you must invalidate each cache before enabling it.
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The functions are grouped for:

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