From 9f95ff5b6ba01db09552b84a0ab79607060a2666 Mon Sep 17 00:00:00 2001 From: Ali Labbene Date: Wed, 11 Dec 2019 08:59:21 +0100 Subject: Official ARM version: v5.4.0 Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3 --- .../DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx | 3266 +++++ .../DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx | 11798 +++++++++++++++++++ .../DspLibTest_FVP/ARM/Lib/.gitignore | 4 + .../DspLibTest_FVP/ARM/Logs/.gitignore | 4 + .../DspLibTest_FVP/ARMCM23_config.txt | 163 + .../DspLibTest_FVP/ARMCM33_DSP_FP_config.txt | 183 + .../DspLibTest_FVP/ARMCM33_DSP_config.txt | 183 + .../DspLibTest_FVP/ARMCM33_FP_config.txt | 183 + .../DspLibTest_FVP/ARMCM33_config.txt | 183 + .../DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx | 3242 +++++ .../DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx | 10153 ++++++++++++++++ .../DspLibTest_FVP/GCC/Lib/.gitignore | 4 + .../DspLibTest_FVP/GCC/Logs/.gitignore | 4 + 13 files changed, 29370 insertions(+) create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvprojx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Lib/.gitignore create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Logs/.gitignore create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvprojx create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Lib/.gitignore create mode 100644 DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Logs/.gitignore (limited to 'DSP/DSP_Lib_TestSuite/DspLibTest_FVP') diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx new file mode 100644 index 0000000..5145d60 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/DspLibTest_FVP.uvoptx @@ -0,0 +1,3266 @@ + + + + 1.0 + +
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### uVision Project, (C) Keil Software
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..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM3l + 0x4 + ARM-ADS + + + ARMCM3 + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h + + + + + + + + + + $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM3l\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM3l\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + python Scripts/get_ref_and_dsp_libs.py ARM M3l + python Scripts/get_ref_and_dsp_libs.py GCC M3l + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM3 + + ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM3\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM3 + ARM_MATH_CM3 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM4l + 0x4 + ARM-ADS + + + ARMCM4 + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4$Device\ARM\ARMCM4\Include\ARMCM4.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM4l\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM4l\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + python Scripts/get_ref_and_dsp_libs.py ARM M4l + python Scripts/get_ref_and_dsp_libs.py GCC M4l + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM4 + ARM_MATH_CM4 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM4lf + 0x4 + ARM-ADS + + + ARMCM4_FP + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM4lf\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM4lf\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + python Scripts/get_ref_and_dsp_libs.py ARM M4lf + python Scripts/get_ref_and_dsp_libs.py GCC M4lf + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM4 __FPU_PRESENT=1U + + ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM4\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM4 + ARM_MATH_CM4 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM7l + 0x4 + ARM-ADS + + + ARMCM7 + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM7$Device\ARM\ARMCM7\Include\ARMCM7.h + + + + + + + + + + $$Device:ARMCM7$Device\ARM\SVD\ARMCM7.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM7l\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM7l\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + python Scripts/get_ref_and_dsp_libs.py ARM M4l + python Scripts/get_ref_and_dsp_libs.py GCC M4l + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 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..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 + ARM_MATH_CM7 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM7lfsp + 0x4 + ARM-ADS + + + ARMCM7_SP + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM7_SP$Device\ARM\ARMCM7\Include\ARMCM7_SP.h + + + + + + + + + + $$Device:ARMCM7_SP$Device\ARM\SVD\ARMCM7.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM7lfsp\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM7lfsp\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + python Scripts/get_ref_and_dsp_libs.py ARM M4lf + python Scripts/get_ref_and_dsp_libs.py GCC M4lf + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM7 __FPU_PRESENT=1U + + ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 + ARM_MATH_CM7 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + cortexM7lfdp + 0x4 + ARM-ADS + + + ARMCM7_DP + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_DP$Device\ARM\Flash\NEW_DEVICE.FLM)) + 0 + $$Device:ARMCM7_DP$Device\ARM\ARMCM7\Include\ARMCM7_DP.h + + + + + + + + + + $$Device:ARMCM7_DP$Device\ARM\SVD\ARMCM7.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\cortexM7lfdp\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\cortexM7lfdp\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + ARM_MATH_CM7 __FPU_PRESENT=1U + + ..\..\..\Include;..\..\..\..\Device\ARM\ARMCM7\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc --cpreproc_opts=-D,ARM_MATH_CM7 + ARM_MATH_CM7 + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + 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0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + ARMv8MMLldfdp.DoNotUse + 0x4 + ARM-ADS + 6060000::V6.6::.\ARMCLANG + + + ARMv8MML_DSP_DP + ARM + ARM.CMSIS.5.0.1-dev6 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("ARMV8MML") FPU3(DFPU) DSP TZ CLOCK(12000000) ESEL ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMv8MML_DSP_DP$Device\ARM\ARMv8MML\Include\ARMv8MML_DSP_DP.h + + + + + + + + + + $$Device:ARMv8MML_DSP_DP$Device\ARM\SVD\ARMv8MML.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\IntermediateFiles\ARMv8MMLldfdp\ + DspLibTest_FVP + 1 + 0 + 0 + 1 + 1 + .\IntermediateFiles\ARMv8MMLldfdp\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + -MPU + TCM.DLL + -pV8MML + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "ARMV8MML" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 3 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 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..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + ARM_MATH_ARMV8MML __CC_ARM + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + Libraries + + + arm_math.lib + 4 + .\Lib\arm_math.lib + + + arm_ref.lib + 4 + .\Lib\arm_ref.lib + + + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 2 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_common_data.c + + + abs_tests.c + 1 + ..\..\Common\src\basic_math_tests\abs_tests.c + + + basic_math_test_group.c + 1 + ..\..\Common\src\basic_math_tests\basic_math_test_group.c + + + negate_tests.c + 1 + ..\..\Common\src\basic_math_tests\negate_tests.c + + + add_tests.c + 1 + ..\..\Common\src\basic_math_tests\add_tests.c + + + mult_tests.c + 1 + ..\..\Common\src\basic_math_tests\mult_tests.c + + + sub_tests.c + 1 + ..\..\Common\src\basic_math_tests\sub_tests.c + + + dot_prod_tests.c + 1 + ..\..\Common\src\basic_math_tests\dot_prod_tests.c + + + offset_tests.c + 1 + ..\..\Common\src\basic_math_tests\offset_tests.c + + + shift_tests.c + 1 + ..\..\Common\src\basic_math_tests\shift_tests.c + + + scale_tests.c + 1 + ..\..\Common\src\basic_math_tests\scale_tests.c + + + + + ComplexMath + + + complex_math_test_group.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_group.c + + + complex_math_test_common_data.c + 1 + ..\..\Common\src\complex_math_tests\complex_math_test_common_data.c + + + cmplx_conj_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_conj_tests.c + + + cmplx_mag_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_tests.c + + + cmplx_mag_squared_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mag_squared_tests.c + + + cmplx_dot_prod_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_dot_prod_tests.c + + + cmplx_mult_cmplx_tests.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_cmplx_tests.c + + + cmplx_mult_real_test.c + 1 + ..\..\Common\src\complex_math_tests\cmplx_mult_real_test.c + + + + + Controller + + + controller_test_group.c + 1 + ..\..\Common\src\controller_tests\controller_test_group.c + + + pid_reset_tests.c + 1 + ..\..\Common\src\controller_tests\pid_reset_tests.c + + + sin_cos_tests.c + 1 + ..\..\Common\src\controller_tests\sin_cos_tests.c + + + pid_tests.c + 1 + ..\..\Common\src\controller_tests\pid_tests.c + + + controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + + + + + + + + diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Lib/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Lib/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Lib/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Logs/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Logs/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARM/Logs/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt new file mode 100644 index 0000000..79e96c4 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM23_config.txt @@ -0,0 +1,163 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt new file mode 100644 index 0000000..8ff1d62 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt new file mode 100644 index 0000000..e6f8798 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_DSP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt new file mode 100644 index 0000000..5c562f2 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_FP_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt new file mode 100644 index 0000000..de6a271 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/ARMCM33_config.txt @@ -0,0 +1,183 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.FPU=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +cpu0.DSP=0 # (bool , init-time) default = '1' : Set whether the model has the DSP extension +cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored : [0x0..0x10] +cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions : [0x0..0x10] +cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included +cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority : [0x3..0x8] +cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode +cpu0.INITSVTOR=0x00000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.INITNSVTOR=0x0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset : [0x0..0xFFFFFF80] +cpu0.SAU=0x0 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) : [0x0..0x8] +cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset +cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set +cpu0.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write +cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write +cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write +cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included +cpu0.SECEXT=0 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.NUM_IDAU_REGION=0x0 # (int , init-time) default = '0xA' : +fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF] +fvp_mps2.platform_type=0x0 # (int , init-time) default = '0x0' : 0:MPS2 ; 1:IoT Kit ; 2:Castor : [0x0..0x2] +fvp_mps2.extra_psram=0 # (bool , init-time) default = '0' : Increases PSRAM to 32Mb +fvp_mps2.UART2.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART2.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART2.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART2.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.UART1.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART1.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART1.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART1.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.mps2_visualisation.rate_limit-enable=1 # (bool , init-time) default = '1' : Rate limit simulation. +fvp_mps2.mps2_visualisation.disable-visualisation=0 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.mps2_visualisation.window_title="CLCD %cpu%" # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) +fvp_mps2.mps2_visualisation.idler.delay_ms=0x32 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. +fvp_mps2.telnetterminal0.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal0.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal1.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal1.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal1.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.telnetterminal2.mode="telnet" # (string, init-time) default = 'telnet' : Terminal initialisation mode +fvp_mps2.telnetterminal2.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected +fvp_mps2.telnetterminal2.start_port=0x1388 # (int , init-time) default = '0x1388' : Telnet TCP Port Number : [0x0..0xFFFFFFFF] +fvp_mps2.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +fvp_mps2.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) +fvp_mps2.PSRAM_M7.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM_M7.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM_M7.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.UART0.out_file="" # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +fvp_mps2.UART0.in_file="" # (string, init-time) default = '' : Input file for data to be read by the UART +fvp_mps2.UART0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output +fvp_mps2.UART0.in_file_escape_sequence="##" # (string, init-time) default = '##' : Input file escape sequence +fvp_mps2.UART0.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +fvp_mps2.UART0.shutdown_tag="" # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted +fvp_mps2.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.secure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.nonsecure_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. +fvp_mps2.PSRAM.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.PSRAM.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.PSRAM.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.ssram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.ssram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.stub.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram0.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram0.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram1.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram1.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram2.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram2.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.size=0x100000000 # (int , init-time) default = '0x100000000' : Memory Size +fvp_mps2.iotss_internal_sram3.fill1=0xDFDFDFCF # (int , init-time) default = '0xDFDFDFCF' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.iotss_internal_sram3.fill2=0xCFDFDFDF # (int , init-time) default = '0xCFDFDFDF' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern +fvp_mps2.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.sys_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu0dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1core_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1core_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cpu1dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cpu1dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.crypto_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.cordio_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.cordio_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.dbg_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram0_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram0_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram1_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram1_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram2_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram2_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.ram3_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal +fvp_mps2.ram3_ppu.revision="r0p0" # (string, init-time) default = 'r0p0' : Revision +fvp_mps2.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled +fvp_mps2.smsc_91c111.mac_address="00:02:f7:ef:5d:a2" # (string, init-time) default = '00:02:f7:ef:5d:a2' : Host/model MAC address +fvp_mps2.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode +fvp_mps2.hostbridge.interfaceName="ARM0" # (string, init-time) default = 'ARM0' : Host Interface +fvp_mps2.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking +fvp_mps2.hostbridge.userNetSubnet="172.20.51.0/24" # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking +fvp_mps2.hostbridge.userNetPorts="" # (string, init-time) default = '' : Listening ports to expose in user-mode networking +fvp_mps2.secure_control_register_block.FLASH_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : Flash Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.SRAM_BLOCK_CFG=0x3 # (int , init-time) default = '0x3' : SRAM Block size configuration : [0x0..0x31] +fvp_mps2.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported +fvp_mps2.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported +fvp_mps2.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_psram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_psram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_psram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram1.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram1.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram1.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_zbtsram2.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_zbtsram2.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_zbtsram2.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.exclusive_monitor_iotss_internal_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component +fvp_mps2.exclusive_monitor_iotss_internal_sram.number_of_monitors=0x8 # (int , init-time) default = '0x8' : Number of monitors : [0x1..0xFFFFFFFF] +fvp_mps2.exclusive_monitor_iotss_internal_sram.log2_granule_size=0x0 # (int , init-time) default = '0x0' : log2 of address granule size : [0x0..0xB] +fvp_mps2.exclusive_monitor_iotss_internal_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master +fvp_mps2.exclusive_monitor_iotss_internal_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit +fvp_mps2.exclusive_monitor_iotss_internal_sram.shareability_domain=0x3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) : [0x0..0x3] +fvp_mps2.exclusive_monitor_iotss_internal_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores +fvp_mps2.dma0_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma0_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma1_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma1_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma2_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma2_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma3_securitymodifier.behaviour_ns_to_s=0x0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S +fvp_mps2.dma3_securitymodifier.behaviour_s_to_ns=0x0 # (int , init-time) default = '0x0' : Behaviour for S transactions to NS space : 0:block 1:transmit 2:convert to NS +fvp_mps2.dma0.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma0.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma0.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma1.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma1.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma1.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma2.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma2.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma2.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) default = '0x10' : Channel FIFO size in bytes +fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer +fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response +fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay +fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot +fvp_mps2.iotss_cpuidentity.debugger_master_id=0xFFFFFFFF # (int , init-time) default = '0xFFFFFFFF' : : [0x0..0xFFFFFFFF] +#---------------------------------------------------------------------------------------------- diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx new file mode 100644 index 0000000..48cafe1 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/DspLibTest_FVP.uvoptx @@ -0,0 +1,3242 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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..\..\..\Include;..\..\..\..\Device\ARM\ARMv8MML\Include;..\..\RefLibs\inc;..\..\Common\JTest\inc;..\..\Common\JTest\inc\arr_desc;..\..\Common\inc;..\..\Common\inc\templates;..\..\Common\inc\basic_math_tests;..\..\Common\inc\complex_math_tests;..\..\Common\inc\statistics_tests;..\..\Common\inc\matrix_tests;..\..\Common\inc\support_tests;..\..\Common\inc\controller_tests;..\..\Common\inc\transform_tests;..\..\Common\inc\fast_math_tests;..\..\Common\inc\filtering_tests;..\..\Common\inc\intrinsics_tests + + + + 0 + 0 + + + ARM_MATH_ARMV8MML + + + + + + 1 + 0 + 0 + 0 + 1 + + + + arm_math -larm_ref + .\Lib + -Wl,--gc-sections -march=armv8-m.main+dsp -mfpu=fpv5-d16 -mfloat-abi=hard + ..\..\Common\platform\GCC\ARMCMx.ld + + + + + + Libraries + + + Startup + + + main.c + 1 + ..\..\Common\src\main.c + + + system_generic.c + 1 + ..\..\Common\platform\system_generic.c + + + startup_generic.S + 1 + ..\..\Common\platform\startup_generic.S + + + + + JTest + + + jtest_cycle.c + 1 + ..\..\Common\JTest\src\jtest_cycle.c + + + jtest_fw.c + 1 + ..\..\Common\JTest\src\jtest_fw.c + + + jtest_dump_str_segments.c + 1 + ..\..\Common\JTest\src\jtest_dump_str_segments.c + + + jtest_trigger_action.c + 1 + ..\..\Common\JTest\src\jtest_trigger_action.c + + + + + AllTests + + + all_tests.c + 1 + ..\..\Common\src\all_tests.c + + + + + Transform + + + cfft_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_tests.c + + + transform_test_group.c + 1 + ..\..\Common\src\transform_tests\transform_test_group.c + + + transform_tests_common_data.c + 1 + ..\..\Common\src\transform_tests\transform_tests_common_data.c + + + cfft_family_tests.c + 1 + ..\..\Common\src\transform_tests\cfft_family_tests.c + + + rfft_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_tests.c + + + rfft_fast_tests.c + 1 + ..\..\Common\src\transform_tests\rfft_fast_tests.c + + + dct4_tests.c + 1 + ..\..\Common\src\transform_tests\dct4_tests.c + + + + + BasicMath + + + basic_math_test_common_data.c + 1 + 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controller_test_common_data.c + 1 + ..\..\Common\src\controller_tests\controller_test_common_data.c + + + + + FastMath + + + fast_math_tests.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests.c + + + fast_math_tests_common_data.c + 1 + ..\..\Common\src\fast_math_tests\fast_math_tests_common_data.c + + + + + Filtering + + + filtering_test_common_data.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_common_data.c + + + filtering_test_group.c + 1 + ..\..\Common\src\filtering_tests\filtering_test_group.c + + + biquad_tests.c + 1 + ..\..\Common\src\filtering_tests\biquad_tests.c + + + conv_tests.c + 1 + ..\..\Common\src\filtering_tests\conv_tests.c + + + correlate_tests.c + 1 + ..\..\Common\src\filtering_tests\correlate_tests.c + + + fir_tests.c + 1 + ..\..\Common\src\filtering_tests\fir_tests.c + + + iir_tests.c + 1 + ..\..\Common\src\filtering_tests\iir_tests.c + + + lms_tests.c + 1 + ..\..\Common\src\filtering_tests\lms_tests.c + + + + + Matrix + + + matrix_test_common_data.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_common_data.c + + + matrix_test_group.c + 1 + ..\..\Common\src\matrix_tests\matrix_test_group.c + + + mat_cmplx_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_cmplx_mult_tests.c + + + mat_add_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_add_tests.c + + + mat_mult_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_tests.c + + + mat_mult_fast_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_mult_fast_tests.c + + + mat_sub_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_sub_tests.c + + + mat_inverse_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_inverse_tests.c + + + mat_trans_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_trans_tests.c + + + mat_init_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_init_tests.c + + + mat_scale_tests.c + 1 + ..\..\Common\src\matrix_tests\mat_scale_tests.c + + + + + Statistics + + + max_tests.c + 1 + ..\..\Common\src\statistics_tests\max_tests.c + + + statistics_test_common_data.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_common_data.c + + + statistics_test_group.c + 1 + ..\..\Common\src\statistics_tests\statistics_test_group.c + + + mean_tests.c + 1 + ..\..\Common\src\statistics_tests\mean_tests.c + + + min_tests.c + 1 + ..\..\Common\src\statistics_tests\min_tests.c + + + power_tests.c + 1 + ..\..\Common\src\statistics_tests\power_tests.c + + + rms_tests.c + 1 + ..\..\Common\src\statistics_tests\rms_tests.c + + + std_tests.c + 1 + ..\..\Common\src\statistics_tests\std_tests.c + + + var_tests.c + 1 + ..\..\Common\src\statistics_tests\var_tests.c + + + + + Support + + + copy_tests.c + 1 + ..\..\Common\src\support_tests\copy_tests.c + + + support_test_common_data.c + 1 + ..\..\Common\src\support_tests\support_test_common_data.c + + + support_test_group.c + 1 + ..\..\Common\src\support_tests\support_test_group.c + + + fill_tests.c + 1 + ..\..\Common\src\support_tests\fill_tests.c + + + x_to_y_tests.c + 1 + ..\..\Common\src\support_tests\x_to_y_tests.c + + + + + Intrinsics + + + intrinsics_tests.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests.c + + + intrinsics_tests_common_data.c + 1 + ..\..\Common\src\intrinsics_tests\intrinsics_tests_common_data.c + + + + + MathHelper + + + math_helper.c + 1 + ..\..\Common\src\math_helper.c + + + + + + + + + + + + + + diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Lib/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Lib/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Lib/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Logs/.gitignore b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Logs/.gitignore new file mode 100644 index 0000000..5e7d273 --- /dev/null +++ b/DSP/DSP_Lib_TestSuite/DspLibTest_FVP/GCC/Logs/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore -- cgit