From 96d6da4e252b06dcfdc041e7df23e86161c33007 Mon Sep 17 00:00:00 2001 From: rihab kouki Date: Tue, 28 Jul 2020 11:24:49 +0100 Subject: Official ARM version: v5.6.0 --- ARM.CMSIS.pdsc | 1365 ++++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 940 insertions(+), 425 deletions(-) (limited to 'ARM.CMSIS.pdsc') diff --git a/ARM.CMSIS.pdsc b/ARM.CMSIS.pdsc index 0684a32..90f5845 100644 --- a/ARM.CMSIS.pdsc +++ b/ARM.CMSIS.pdsc @@ -8,6 +8,70 @@ http://www.keil.com/pack/ + + CMSIS-Core(M): 5.3.0 (see revision history for details) + - Added provisions for compiler-independent C startup code. + CMSIS-Core(A): 1.1.4 (see revision history for details) + - Fixed __FPU_Enable. + CMSIS-DSP: 1.7.0 (see revision history for details) + - New Neon versions of f32 functions + - Python wrapper + - Preliminary cmake build + - Compilation flags for FFTs + - Changes to arm_math.h + CMSIS-NN: 1.2.0 (see revision history for details) + - New function for depthwise convolution with asymmetric quantization. + - New support functions for requantization. + CMSIS-RTOS: + - RTX 4.82.0 (updated provisions for Arm Compiler 6 when using Cortex-M0/M0+) + CMSIS-RTOS2: + - RTX 5.5.1 (see revision history for details) + CMSIS-Driver: 2.7.1 + - WiFi Interface API 1.0.0 + Devices: + - Generalized C startup code for all Cortex-M familiy devices. + - Updated Cortex-A default memory regions and MMU configurations + - Moved Cortex-A memory and system config files to avoid include path issues + + + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.1 (see revision history for details) + - Fixed compilation issue in cmsis_armclang_ltm.h + + + The following folders have been removed: + - CMSIS/Lib/ (superseded by CMSIS/DSP/Lib/) + - CMSIS/DSP_Lib/ (superseded by CMSIS/DSP/) + The following folders are deprecated + - CMSIS/Include/ (superseded by CMSIS/DSP/Include/ and CMSIS/Core/Include/) + + CMSIS-Core(M): 5.2.0 (see revision history for details) + - Reworked Stack/Heap configuration for ARM startup files. + - Added Cortex-M35P device support. + - Added generic Armv8.1-M Mainline device support. + CMSIS-Core(A): 1.1.3 (see revision history for details) + CMSIS-DSP: 1.6.0 (see revision history for details) + - reworked DSP library source files + - reworked DSP library documentation + - Changed DSP folder structure + - moved DSP libraries to folder ./DSP/Lib + - ARM DSP Libraries are built with ARMCLANG + - Added DSP Libraries Source variant + CMSIS-RTOS2: + - RTX 5.5.0 (see revision history for details) + CMSIS-Driver: 2.7.0 + - Added WiFi Interface API 1.0.0-beta + - Added components for project specific driver implementations + CMSIS-Pack: 1.6.0 (see revision history for details) + Devices: + - Added Cortex-M35P and ARMv81MML device templates. + - Fixed C-Startup Code for GCC (aligned with other compilers) + Utilities: + - SVDConv 3.3.25 + - PackChk 1.3.82 + Aligned pack structure with repository. The following folders are deprecated: @@ -183,7 +247,7 @@ - added Taxonomy for Graphics - updated Taxonomy for unified drivers from "Drivers" to "CMSIS Drivers" - + + - CMSIS-RTOS 4.74 (see revision history for details) - PACK Extensions (Boards, Device Features, Flash Programming, Generators, Configuration Wizard). Schema version 1.1. - + + + + + Software components for audio processing Generic Interfaces for Evaluation and Development Boards + Drivers that support an external component available on an evaluation board + Compiler Software Extensions Cortex Microcontroller Software Interface Components - Startup, System Setup Unified Device Drivers compliant to CMSIS-Driver Specifications + Startup, System Setup + Data exchange or data formatter + Drivers that support an extension board or shield File Drive Support and File System + IoT cloud client connector + IoT specific software utility Graphical User Interface Network Stack using Internet Protocols - Universal Serial Bus Stack - Compiler Software Extensions Real-time Operating System + Encryption for secure communication or storage + Universal Serial Bus Stack + Generic software utility components @@ -455,6 +527,54 @@ class processor based on the Armv8-M mainline architecture with Arm TrustZone se + + + + +The Arm Cortex-M35P is the most configurable of all Cortex-M processors. It is a full featured microcontroller +class processor based on the Armv8-M mainline architecture with Arm TrustZone security designed for a broad range of secure embedded applications. + + + + + + + + + + + + + no DSP Instructions, no Floating Point Unit, no TrustZone + + + + + + + + no DSP Instructions, no Floating Point Unit, TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, no TrustZone + + + + + + + + DSP Instructions, Single Precision Floating Point Unit, TrustZone + + + + + @@ -575,6 +695,29 @@ Armv8-M Mainline based device with TrustZone + + + + + +Armv8.1-M Mainline based device with TrustZone and MVE + + + + + + + + + + + + + Double Precision Vector Extensions, DSP Instructions, Double Precision Floating Point Unit, TrustZone + + + + @@ -585,11 +728,13 @@ virtual memory capabilities. The Cortex-A5 processor implements the Armv7-A arch Arm instructions and 16-bit and 32-bit Thumb instructions. The Cortex-A5 is the smallest member of the Cortex-A processor family. - - + + + + - + @@ -603,11 +748,13 @@ The Cortex-A7 MPCore processor has one to four processors in a single multiproce an optional integrated GIC, and an optional L2 cache controller. - - + + + + - + @@ -621,11 +768,13 @@ The Cortex-A9 processor implements the Armv7-A architecture and runs 32-bit Arm and 8-bit Java bytecodes in Jazelle state. - - + + + + - + @@ -753,6 +902,13 @@ and 8-bit Java bytecodes in Jazelle state. + + WiFi driver + + + + + @@ -803,8 +959,10 @@ and 8-bit Java bytecodes in Jazelle state. Armv8-M architecture based device + + Armv8-M architecture based device with TrustZone @@ -884,6 +1042,14 @@ and 8-bit Java bytecodes in Jazelle state. Cortex-M33 processor based device using Floating Point Unit + + Cortex-M35P processor based device + + + + Cortex-M35P processor based device using Floating Point Unit + + Armv8-M Baseline processor based device @@ -915,6 +1081,23 @@ and 8-bit Java bytecodes in Jazelle state. + + CM35P, no DSP, no FPU + + + + CM35P, DSP, no FPU + + + + CM35P, no DSP, SP FPU + + + + CM35P, DSP, SP FPU + + + Armv8-M Mainline, no DSP, no FPU @@ -1109,11 +1292,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M23 processor based device in big endian mode for the Arm Compiler - - - Cortex-M33 processor based device for the Arm Compiler @@ -1125,11 +1303,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device in big endian mode for the Arm Compiler - - - Cortex-M33 processor based device using Floating Point Unit for the Arm Compiler @@ -1141,11 +1314,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device using Floating Point Unit in big endian mode for the Arm Compiler - - - Cortex-M33 processor, no DSP, no FPU, Arm Compiler @@ -1188,6 +1356,69 @@ and 8-bit Java bytecodes in Jazelle state. + + Cortex-M35P processor based device for the Arm Compiler + + + + + Cortex-M35P processor based device in little endian mode for the Arm Compiler + + + + + + Cortex-M35P processor based device using Floating Point Unit for the Arm Compiler + + + + + Cortex-M35P processor based device using Floating Point Unit in little endian mode for the Arm Compiler + + + + + + Cortex-M35P processor, no DSP, no FPU, Arm Compiler + + + + + Cortex-M35P processor, DSP, no FPU, Arm Compiler + + + + + Cortex-M35P processor, no DSP, SP FPU, Arm Compiler + + + + + Cortex-M35P processor, DSP, SP FPU, Arm Compiler + + + + + Cortex-M35P processor, little endian, no DSP, no FPU, Arm Compiler + + + + + Cortex-M35P processor, little endian, DSP, no FPU, Arm Compiler + + + + + Cortex-M35P processor, little endian, no DSP, SP FPU, Arm Compiler + + + + + Cortex-M35P processor, little endian, DSP, SP FPU, Arm Compiler + + + + Armv8-M Baseline processor based device for the Arm Compiler @@ -1198,11 +1429,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Baseline processor based device in big endian mode for the Arm Compiler - - - Armv8-M Mainline processor based device for the Arm Compiler @@ -1214,11 +1440,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device in big endian mode for the Arm Compiler - - - Armv8-M Mainline processor based device using Floating Point Unit for the Arm Compiler @@ -1230,11 +1451,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the Arm Compiler - - - Armv8-M Mainline, no DSP, no FPU, Arm Compiler @@ -1276,7 +1492,7 @@ and 8-bit Java bytecodes in Jazelle state. - + Cortex-A5, Cortex-A7 or Cortex-A9 processor based device for the GCC Compiler @@ -1406,11 +1622,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M7 processor based device using Floating Point Unit (SP) in big endian mode for the GCC Compiler - - - Cortex-M7 processor based device using Floating Point Unit (DP) for the GCC Compiler @@ -1422,11 +1633,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M7 processor based device using Floating Point Unit (DP) in big endian mode for the GCC Compiler - - - Cortex-M23 processor based device for the GCC Compiler @@ -1438,11 +1644,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M23 processor based device in big endian mode for the GCC Compiler - - - Cortex-M33 processor based device for the GCC Compiler @@ -1454,11 +1655,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device in big endian mode for the GCC Compiler - - - Cortex-M33 processor based device using Floating Point Unit for the GCC Compiler @@ -1470,11 +1666,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device using Floating Point Unit in big endian mode for the GCC Compiler - - - CM33, no DSP, no FPU, GCC Compiler @@ -1517,6 +1708,69 @@ and 8-bit Java bytecodes in Jazelle state. + + Cortex-M35P processor based device for the GCC Compiler + + + + + Cortex-M35P processor based device in little endian mode for the GCC Compiler + + + + + + Cortex-M35P processor based device using Floating Point Unit for the GCC Compiler + + + + + Cortex-M35P processor based device using Floating Point Unit in little endian mode for the GCC Compiler + + + + + + CM35P, no DSP, no FPU, GCC Compiler + + + + + CM35P, DSP, no FPU, GCC Compiler + + + + + CM35P, no DSP, SP FPU, GCC Compiler + + + + + CM35P, DSP, SP FPU, GCC Compiler + + + + + CM35P, little endian, no DSP, no FPU, GCC Compiler + + + + + CM35P, little endian, DSP, no FPU, GCC Compiler + + + + + CM35P, little endian, no DSP, SP FPU, GCC Compiler + + + + + CM35P, little endian, DSP, SP FPU, GCC Compiler + + + + Armv8-M Baseline processor based device for the GCC Compiler @@ -1527,11 +1781,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Baseline processor based device in big endian mode for the GCC Compiler - - - Armv8-M Mainline processor based device for the GCC Compiler @@ -1543,11 +1792,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device in big endian mode for the GCC Compiler - - - Armv8-M Mainline processor based device using Floating Point Unit for the GCC Compiler @@ -1559,11 +1803,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the GCC Compiler - - - Armv8-M Mainline, no DSP, no FPU, GCC Compiler @@ -1767,11 +2006,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M23 processor based device in big endian mode for the IAR Compiler - - - Cortex-M33 processor based device for the IAR Compiler @@ -1783,11 +2017,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device in big endian mode for the IAR Compiler - - - Cortex-M33 processor based device using Floating Point Unit for the IAR Compiler @@ -1799,11 +2028,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Cortex-M33 processor based device using Floating Point Unit in big endian mode for the IAR Compiler - - - CM33, no DSP, no FPU, IAR Compiler @@ -1846,6 +2070,69 @@ and 8-bit Java bytecodes in Jazelle state. + + Cortex-M35P processor based device for the IAR Compiler + + + + + Cortex-M35P processor based device in little endian mode for the IAR Compiler + + + + + + Cortex-M35P processor based device using Floating Point Unit for the IAR Compiler + + + + + Cortex-M35P processor based device using Floating Point Unit in little endian mode for the IAR Compiler + + + + + + CM35P, no DSP, no FPU, IAR Compiler + + + + + CM35P, DSP, no FPU, IAR Compiler + + + + + CM35P, no DSP, SP FPU, IAR Compiler + + + + + CM35P, DSP, SP FPU, IAR Compiler + + + + + CM35P, little endian, no DSP, no FPU, IAR Compiler + + + + + CM35P, little endian, DSP, no FPU, IAR Compiler + + + + + CM35P, little endian, no DSP, SP FPU, IAR Compiler + + + + + CM35P, little endian, DSP, SP FPU, IAR Compiler + + + + Armv8-M Baseline processor based device for the IAR Compiler @@ -1856,11 +2143,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Baseline processor based device in big endian mode for the IAR Compiler - - - Armv8-M Mainline processor based device for the IAR Compiler @@ -1872,11 +2154,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device in big endian mode for the IAR Compiler - - - Armv8-M Mainline processor based device using Floating Point Unit for the IAR Compiler @@ -1888,11 +2165,6 @@ and 8-bit Java bytecodes in Jazelle state. - - Armv8-M Mainline processor based device using Floating Point Unit in big endian mode for the IAR Compiler - - - Armv8-M Mainline, no DSP, no FPU, IAR Compiler @@ -1936,93 +2208,58 @@ and 8-bit Java bytecodes in Jazelle state. - Generic Arm Cortex-M0 device startup and depends on CMSIS Core - - Generic ARM Cortex-M0 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M0+ device startup and depends on CMSIS Core - - Generic Arm Cortex-M0+ device startup and depends CMSIS Core requiring GCC - - - Generic Arm Cortex-M1 device startup and depends on CMSIS Core - - Generic ARM Cortex-M1 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M3 device startup and depends on CMSIS Core - - Generic Arm Cortex-M3 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M4 device startup and depends on CMSIS Core - - Generic Arm Cortex-M4 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M7 device startup and depends on CMSIS Core - - Generic Arm Cortex-M7 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M23 device startup and depends on CMSIS Core - - Generic Arm Cortex-M23 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm Cortex-M33 device startup and depends on CMSIS Core - - Generic Arm Cortex-M33 device startup and depends on CMSIS Core requiring GCC - - + + + Generic Arm Cortex-M35P device startup and depends on CMSIS Core + + @@ -2030,43 +2267,29 @@ and 8-bit Java bytecodes in Jazelle state. - - Generic Arm SC000 device startup and depends on CMSIS Core requiring GCC - - - Generic Arm SC300 device startup and depends on CMSIS Core - - Generic Arm SC300 device startup and dependson CMSIS Core requiring GCC - - - Generic Armv8-M Baseline device startup and depends on CMSIS Core - - Generic Armv8-M Baseline device startup and depends on CMSIS Core requiring GCC - - - Generic Armv8-M Mainline device startup and depends on CMSIS Core - - Generic Armv8-M Mainline device startup and depends on CMSIS Core requiring GCC - - + + + Generic Armv8.1-M Mainline device startup and depends on CMSIS Core + + @@ -2171,20 +2394,20 @@ and 8-bit Java bytecodes in Jazelle state. - - CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M + + CMSIS-CORE for Cortex-M, SC000, SC300, ARMv8-M, ARMv8.1-M - - + + - - + + CMSIS-CORE for Cortex-A @@ -2195,185 +2418,198 @@ and 8-bit Java bytecodes in Jazelle state. - + System and Startup for Generic Arm Cortex-M0 device - - - - + + + + - - System and Startup for Generic Arm Cortex-M0 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M0 device - - + + + + - + System and Startup for Generic Arm Cortex-M0+ device - - - - + + + + - - System and Startup for Generic Arm Cortex-M0+ device + + DEPRECATED: System and Startup for Generic Arm Cortex-M0+ device - - + + + + - + System and Startup for Generic Arm Cortex-M1 device - - - - + + + + - - System and Startup for Generic Arm Cortex-M1 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M1 device - - + + + + - + System and Startup for Generic Arm Cortex-M3 device - - - - + + + + - - System and Startup for Generic Arm Cortex-M3 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M3 device - - + + + + - + System and Startup for Generic Arm Cortex-M4 device - - - - + + + + - - System and Startup for Generic Arm Cortex-M4 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M4 device - - + + + + - + System and Startup for Generic Arm Cortex-M7 device - - - - + + + + - - System and Startup for Generic Arm Cortex-M7 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M7 device - - + + + + - + System and Startup for Generic Arm Cortex-M23 device - - - - + + + - - System and Startup for Generic Arm Cortex-M23 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M23 device - - + + + + @@ -2381,145 +2617,199 @@ and 8-bit Java bytecodes in Jazelle state. - + System and Startup for Generic Arm Cortex-M33 device - - - - + + + - + - - System and Startup for Generic Arm Cortex-M33 device + + DEPRECATED: System and Startup for Generic Arm Cortex-M33 device - - + + + + - + + + + + + + System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + + + + DEPRECATED: System and Startup for Generic Arm Cortex-M35P device + + + + + + + + + + + - + System and Startup for Generic Arm SC000 device - - - - + + + + - - System and Startup for Generic Arm SC000 device + + DEPRECATED: System and Startup for Generic Arm SC000 device - - + + + + - + System and Startup for Generic Arm SC300 device - - - - + + + + - - System and Startup for Generic Arm SC300 device + + DEPRECATED: System and Startup for Generic Arm SC300 device - - + + + + - + System and Startup for Generic Armv8-M Baseline device - - - - + + + + - + - - System and Startup for Generic Armv8-M Baseline device + + DEPRECATED: System and Startup for Generic Armv8-M Baseline device - - - + + + + - + - + System and Startup for Generic Armv8-M Mainline device - - - - + + + + - + - - System and Startup for Generic Armv8-M Mainline device + + DEPRECATED: System and Startup for Generic Armv8-M Mainline device - - - + + + + - + + + + System and Startup for Generic Armv8.1-M Mainline device + + + + + + + + + + + + + System and Startup for Generic Arm Cortex-A5 device @@ -2535,10 +2825,10 @@ and 8-bit Java bytecodes in Jazelle state. - - - - + + + + @@ -2558,10 +2848,10 @@ and 8-bit Java bytecodes in Jazelle state. - - - - + + + + @@ -2580,10 +2870,10 @@ and 8-bit Java bytecodes in Jazelle state. - - - - + + + + @@ -2611,7 +2901,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-DSP Library for Cortex-M, SC000, and SC300 @@ -2620,97 +2910,128 @@ and 8-bit Java bytecodes in Jazelle state. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CMSIS-DSP Library for Cortex-M, SC000, and SC300 + + + + + + + + + + + + + + + + - + CMSIS-NN Neural Network Library @@ -2733,6 +3054,7 @@ and 8-bit Java bytecodes in Jazelle state. + @@ -2755,7 +3077,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS RTX implementation for Cortex-M, SC000, and SC300 @@ -2832,7 +3154,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS RTX implementation for Infineon XMC4 series affected by PMU_CM.001 errata @@ -2872,7 +3194,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS RTX5 implementation for Cortex-M, SC000, and SC300 @@ -2888,7 +3210,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Library) @@ -2903,11 +3225,11 @@ and 8-bit Java bytecodes in Jazelle state. - + - + @@ -2933,6 +3255,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -2947,6 +3271,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -2958,9 +3284,17 @@ and 8-bit Java bytecodes in Jazelle state. + + + + + + + + - + CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Library) @@ -2976,11 +3310,11 @@ and 8-bit Java bytecodes in Jazelle state. - + - + @@ -2999,6 +3333,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3006,12 +3342,23 @@ and 8-bit Java bytecodes in Jazelle state. + + + + + + + + + + + - + CMSIS-RTOS2 RTX5 for Cortex-M, SC000, C300 and Armv8-M (Source) @@ -3027,11 +3374,11 @@ and 8-bit Java bytecodes in Jazelle state. - + - + @@ -3068,6 +3415,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3082,6 +3431,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3096,6 +3447,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3103,7 +3456,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS2 RTX5 for Armv7-A (Source) @@ -3119,13 +3472,13 @@ and 8-bit Java bytecodes in Jazelle state. - + - + @@ -3160,7 +3513,7 @@ and 8-bit Java bytecodes in Jazelle state. - + CMSIS-RTOS2 RTX5 for Armv8-M Non-Secure Domain (Source) @@ -3177,11 +3530,11 @@ and 8-bit Java bytecodes in Jazelle state. - + - + @@ -3211,6 +3564,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3218,6 +3573,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3225,6 +3582,8 @@ and 8-bit Java bytecodes in Jazelle state. + + @@ -3232,7 +3591,108 @@ and 8-bit Java bytecodes in Jazelle state. - + + + + Access to #include Driver_USART.h file and code template for custom implementation + + + + + + + Access to #include Driver_SPI.h file and code template for custom implementation + + + + + + + Access to #include Driver_SAI.h file and code template for custom implementation + + + + + + + Access to #include Driver_I2C.h file and code template for custom implementation + + + + + + + Access to #include Driver_CAN.h file and code template for custom implementation + + + + + + + Access to #include Driver_Flash.h file and code template for custom implementation + + + + + + + Access to #include Driver_MCI.h file and code template for custom implementation + + + + + + + Access to #include Driver_NAND.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY/MAC.h files and code templates for custom implementation + + + + + + + + + Access to #include Driver_ETH_MAC.h file and code template for custom implementation + + + + + + + Access to #include Driver_ETH_PHY.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBD.h file and code template for custom implementation + + + + + + + Access to #include Driver_USBH.h file and code template for custom implementation + + + + + + + Access to #include Driver_WiFi.h file + + + + + @@ -3258,13 +3718,38 @@ and 8-bit Java bytecodes in Jazelle state. + + + + - - Fixed Virtual Platform - - - + + EWARM Simulator + + + + + + + + + + + + + + + + + + + + + + + + @@ -3438,6 +3923,21 @@ and 8-bit Java bytecodes in Jazelle state. + + Neural Network CIFAR10 example + + + + + + + + + + Getting Started + + + Neural Network GRU example @@ -3453,6 +3953,21 @@ and 8-bit Java bytecodes in Jazelle state. + + Neural Network GRU example + + + + + + + + + + Getting Started + + + CMSIS-RTOS2 Blinky example @@ -3498,7 +4013,7 @@ and 8-bit Java bytecodes in Jazelle state. CMSIS-RTOS2 Memory Pool Example - + -- cgit