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diff --git a/docs/Core_A/html/group__irq__mode__defs.html b/docs/Core_A/html/group__irq__mode__defs.html new file mode 100644 index 0000000..bfa8b83 --- /dev/null +++ b/docs/Core_A/html/group__irq__mode__defs.html @@ -0,0 +1,457 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>IRQ Mode Bit-Masks</title> +<title>CMSIS-Core (Cortex-A): IRQ Mode Bit-Masks</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> 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class="contents"> + +<p>Configure interrupt line mode. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:gabc31ba71612436a6ccc49342f35fec58"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gabc31ba71612436a6ccc49342f35fec58">IRQ_MODE_TRIG_LEVEL</a>   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:gabc31ba71612436a6ccc49342f35fec58"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: level triggered interrupt. <a href="#gabc31ba71612436a6ccc49342f35fec58">More...</a><br/></td></tr> +<tr class="separator:gabc31ba71612436a6ccc49342f35fec58"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga326df9e34f6447583895a6f809ee160a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga326df9e34f6447583895a6f809ee160a">IRQ_MODE_TRIG_LEVEL_LOW</a>   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:ga326df9e34f6447583895a6f809ee160a"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: low level triggered interrupt. <a href="#ga326df9e34f6447583895a6f809ee160a">More...</a><br/></td></tr> +<tr class="separator:ga326df9e34f6447583895a6f809ee160a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafeb539b2a564ca35abc57f87d71e7206"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gafeb539b2a564ca35abc57f87d71e7206">IRQ_MODE_TRIG_LEVEL_HIGH</a>   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:gafeb539b2a564ca35abc57f87d71e7206"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: high level triggered interrupt. <a href="#gafeb539b2a564ca35abc57f87d71e7206">More...</a><br/></td></tr> +<tr class="separator:gafeb539b2a564ca35abc57f87d71e7206"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa9a8e0968a4ccd57eb7544a16d05f24d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gaa9a8e0968a4ccd57eb7544a16d05f24d">IRQ_MODE_TRIG_EDGE</a>   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:gaa9a8e0968a4ccd57eb7544a16d05f24d"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: edge triggered interrupt. <a href="#gaa9a8e0968a4ccd57eb7544a16d05f24d">More...</a><br/></td></tr> +<tr class="separator:gaa9a8e0968a4ccd57eb7544a16d05f24d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga2dbbbb7100be0fee6e048cd3deb50e28"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga2dbbbb7100be0fee6e048cd3deb50e28">IRQ_MODE_TRIG_EDGE_RISING</a>   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:ga2dbbbb7100be0fee6e048cd3deb50e28"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: rising edge triggered interrupt. <a href="#ga2dbbbb7100be0fee6e048cd3deb50e28">More...</a><br/></td></tr> +<tr class="separator:ga2dbbbb7100be0fee6e048cd3deb50e28"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga99e0f3f6945991d50e766b19e71e0222"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga99e0f3f6945991d50e766b19e71e0222">IRQ_MODE_TRIG_EDGE_FALLING</a>   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:ga99e0f3f6945991d50e766b19e71e0222"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: falling edge triggered interrupt. <a href="#ga99e0f3f6945991d50e766b19e71e0222">More...</a><br/></td></tr> +<tr class="separator:ga99e0f3f6945991d50e766b19e71e0222"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga8b0142ff767a9b1b1287e638eacf707b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga8b0142ff767a9b1b1287e638eacf707b">IRQ_MODE_TRIG_EDGE_BOTH</a>   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)</td></tr> +<tr class="memdesc:ga8b0142ff767a9b1b1287e638eacf707b"><td class="mdescLeft"> </td><td class="mdescRight">Trigger: rising and falling edge triggered interrupt. <a href="#ga8b0142ff767a9b1b1287e638eacf707b">More...</a><br/></td></tr> +<tr class="separator:ga8b0142ff767a9b1b1287e638eacf707b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab0d022bbd15beb1a6578b5535d95f9cf"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gab0d022bbd15beb1a6578b5535d95f9cf">IRQ_MODE_TYPE_IRQ</a>   (0x00UL << IRQ_MODE_TYPE_Pos)</td></tr> +<tr class="memdesc:gab0d022bbd15beb1a6578b5535d95f9cf"><td class="mdescLeft"> </td><td class="mdescRight">Type: interrupt source triggers CPU IRQ line. <a href="#gab0d022bbd15beb1a6578b5535d95f9cf">More...</a><br/></td></tr> +<tr class="separator:gab0d022bbd15beb1a6578b5535d95f9cf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaec01a80010bc42b1482388ce3ae4d2a3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gaec01a80010bc42b1482388ce3ae4d2a3">IRQ_MODE_TYPE_FIQ</a>   (0x01UL << IRQ_MODE_TYPE_Pos)</td></tr> +<tr class="memdesc:gaec01a80010bc42b1482388ce3ae4d2a3"><td class="mdescLeft"> </td><td class="mdescRight">Type: interrupt source triggers CPU FIQ line. <a href="#gaec01a80010bc42b1482388ce3ae4d2a3">More...</a><br/></td></tr> +<tr class="separator:gaec01a80010bc42b1482388ce3ae4d2a3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7498851a6a7f3e2c5e087041617f5be7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga7498851a6a7f3e2c5e087041617f5be7">IRQ_MODE_DOMAIN_NONSECURE</a>   (0x00UL << IRQ_MODE_DOMAIN_Pos)</td></tr> +<tr class="memdesc:ga7498851a6a7f3e2c5e087041617f5be7"><td class="mdescLeft"> </td><td class="mdescRight">Domain: interrupt is targeting non-secure domain. <a href="#ga7498851a6a7f3e2c5e087041617f5be7">More...</a><br/></td></tr> +<tr class="separator:ga7498851a6a7f3e2c5e087041617f5be7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga15cdeb10ef2b8081c5cd7a87e22e65e6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga15cdeb10ef2b8081c5cd7a87e22e65e6">IRQ_MODE_DOMAIN_SECURE</a>   (0x01UL << IRQ_MODE_DOMAIN_Pos)</td></tr> +<tr class="memdesc:ga15cdeb10ef2b8081c5cd7a87e22e65e6"><td class="mdescLeft"> </td><td class="mdescRight">Domain: interrupt is targeting secure domain. <a href="#ga15cdeb10ef2b8081c5cd7a87e22e65e6">More...</a><br/></td></tr> +<tr class="separator:ga15cdeb10ef2b8081c5cd7a87e22e65e6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad3d0505689768247c67495b7359e147f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gad3d0505689768247c67495b7359e147f">IRQ_MODE_CPU_ALL</a>   (0x00UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:gad3d0505689768247c67495b7359e147f"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets all CPUs. <a href="#gad3d0505689768247c67495b7359e147f">More...</a><br/></td></tr> +<tr class="separator:gad3d0505689768247c67495b7359e147f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gacb276aa0488a9bf1aa56e1072d2a15a5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gacb276aa0488a9bf1aa56e1072d2a15a5">IRQ_MODE_CPU_0</a>   (0x01UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:gacb276aa0488a9bf1aa56e1072d2a15a5"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 0. <a href="#gacb276aa0488a9bf1aa56e1072d2a15a5">More...</a><br/></td></tr> +<tr class="separator:gacb276aa0488a9bf1aa56e1072d2a15a5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab09616a5ccd05d75d81ab80a37387a9a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gab09616a5ccd05d75d81ab80a37387a9a">IRQ_MODE_CPU_1</a>   (0x02UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:gab09616a5ccd05d75d81ab80a37387a9a"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 1. <a href="#gab09616a5ccd05d75d81ab80a37387a9a">More...</a><br/></td></tr> +<tr class="separator:gab09616a5ccd05d75d81ab80a37387a9a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3c8c5ec0226d772c3200d9efa2d3bf1a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga3c8c5ec0226d772c3200d9efa2d3bf1a">IRQ_MODE_CPU_2</a>   (0x04UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:ga3c8c5ec0226d772c3200d9efa2d3bf1a"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 2. <a href="#ga3c8c5ec0226d772c3200d9efa2d3bf1a">More...</a><br/></td></tr> +<tr class="separator:ga3c8c5ec0226d772c3200d9efa2d3bf1a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7fe46ac2f03063dc5ed2ca793c9cca85"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga7fe46ac2f03063dc5ed2ca793c9cca85">IRQ_MODE_CPU_3</a>   (0x08UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:ga7fe46ac2f03063dc5ed2ca793c9cca85"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 3. <a href="#ga7fe46ac2f03063dc5ed2ca793c9cca85">More...</a><br/></td></tr> +<tr class="separator:ga7fe46ac2f03063dc5ed2ca793c9cca85"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4d428c7ab66cb22eb375a109735e9a3a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga4d428c7ab66cb22eb375a109735e9a3a">IRQ_MODE_CPU_4</a>   (0x10UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:ga4d428c7ab66cb22eb375a109735e9a3a"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 4. <a href="#ga4d428c7ab66cb22eb375a109735e9a3a">More...</a><br/></td></tr> +<tr class="separator:ga4d428c7ab66cb22eb375a109735e9a3a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga94faa9eab45bbc6fa6b2a3c9d92bbb37"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#ga94faa9eab45bbc6fa6b2a3c9d92bbb37">IRQ_MODE_CPU_5</a>   (0x20UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:ga94faa9eab45bbc6fa6b2a3c9d92bbb37"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 5. <a href="#ga94faa9eab45bbc6fa6b2a3c9d92bbb37">More...</a><br/></td></tr> +<tr class="separator:ga94faa9eab45bbc6fa6b2a3c9d92bbb37"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gadb512fc8a31bc771c3ce0d006b821bb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gadb512fc8a31bc771c3ce0d006b821bb9">IRQ_MODE_CPU_6</a>   (0x40UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:gadb512fc8a31bc771c3ce0d006b821bb9"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 6. <a href="#gadb512fc8a31bc771c3ce0d006b821bb9">More...</a><br/></td></tr> +<tr class="separator:gadb512fc8a31bc771c3ce0d006b821bb9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa66525a1ee05c56f367540b2135e81ed"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gaa66525a1ee05c56f367540b2135e81ed">IRQ_MODE_CPU_7</a>   (0x80UL << IRQ_MODE_CPU_Pos)</td></tr> +<tr class="memdesc:gaa66525a1ee05c56f367540b2135e81ed"><td class="mdescLeft"> </td><td class="mdescRight">CPU: interrupt targets CPU 7. <a href="#gaa66525a1ee05c56f367540b2135e81ed">More...</a><br/></td></tr> +<tr class="separator:gaa66525a1ee05c56f367540b2135e81ed"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaacb93ae158e548c54698a7230647804a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__irq__mode__defs.html#gaacb93ae158e548c54698a7230647804a">IRQ_MODE_ERROR</a>   (0x80000000UL)</td></tr> +<tr class="memdesc:gaacb93ae158e548c54698a7230647804a"><td class="mdescLeft"> </td><td class="mdescRight">Bit indicating mode value error. <a href="#gaacb93ae158e548c54698a7230647804a">More...</a><br/></td></tr> +<tr class="separator:gaacb93ae158e548c54698a7230647804a"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following codes are used as values for the parameter <em>mode</em> of the function <a class="el" href="group__irq__ctrl__gr.html#gab35da69354d2e515931580a1308a3a85">IRQ_SetMode</a> to configure interrupt line mode. They are also returned by the function <a class="el" href="group__irq__ctrl__gr.html#gadba142ee49ae8f52f76b603c926ad711">IRQ_GetMode</a> when retrieving interrupt line mode.</p> +<p>The values of <b>IRQ_MODE_TRIG_x</b> definitions specify The values of <b>IRQ_MODE_TYPE_x</b> definitions specify The values of <b>IRQ_MODE_DOMAIN_x</b> definitions specify The values of <b>IRQ_MODE_CPU_x</b> definitions specify</p> +<p>Interrupt mode bit-masks </p> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="gacb276aa0488a9bf1aa56e1072d2a15a5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_0   (0x01UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gab09616a5ccd05d75d81ab80a37387a9a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_1   (0x02UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga3c8c5ec0226d772c3200d9efa2d3bf1a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_2   (0x04UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga7fe46ac2f03063dc5ed2ca793c9cca85"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_3   (0x08UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga4d428c7ab66cb22eb375a109735e9a3a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_4   (0x10UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga94faa9eab45bbc6fa6b2a3c9d92bbb37"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_5   (0x20UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gadb512fc8a31bc771c3ce0d006b821bb9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_6   (0x40UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaa66525a1ee05c56f367540b2135e81ed"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_7   (0x80UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gad3d0505689768247c67495b7359e147f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_CPU_ALL   (0x00UL << IRQ_MODE_CPU_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga7498851a6a7f3e2c5e087041617f5be7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_DOMAIN_NONSECURE   (0x00UL << IRQ_MODE_DOMAIN_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga15cdeb10ef2b8081c5cd7a87e22e65e6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_DOMAIN_SECURE   (0x01UL << IRQ_MODE_DOMAIN_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaacb93ae158e548c54698a7230647804a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_ERROR   (0x80000000UL)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaa9a8e0968a4ccd57eb7544a16d05f24d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_EDGE   (0x04UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga8b0142ff767a9b1b1287e638eacf707b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_EDGE_BOTH   (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga99e0f3f6945991d50e766b19e71e0222"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_EDGE_FALLING   (0x06UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga2dbbbb7100be0fee6e048cd3deb50e28"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_EDGE_RISING   (0x05UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gabc31ba71612436a6ccc49342f35fec58"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_LEVEL   (0x00UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gafeb539b2a564ca35abc57f87d71e7206"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_LEVEL_HIGH   (0x02UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga326df9e34f6447583895a6f809ee160a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TRIG_LEVEL_LOW   (0x01UL /*<< IRQ_MODE_TRIG_Pos*/)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaec01a80010bc42b1482388ce3ae4d2a3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TYPE_FIQ   (0x01UL << IRQ_MODE_TYPE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gab0d022bbd15beb1a6578b5535d95f9cf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define IRQ_MODE_TYPE_IRQ   (0x00UL << IRQ_MODE_TYPE_Pos)</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |