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diff --git a/docs/Core_A/html/group__L1__cache__functions.html b/docs/Core_A/html/group__L1__cache__functions.html new file mode 100644 index 0000000..91f9d82 --- /dev/null +++ b/docs/Core_A/html/group__L1__cache__functions.html @@ -0,0 +1,445 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>L1 Cache Functions</title> +<title>CMSIS-Core (Cortex-A): L1 Cache Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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+</div><!--header--> +<div class="contents"> + +<p>L1 Cache Functions give support to enable, clean and invalidate level 1 instruction and data caches, as well as to enable branch target address cache. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gaff8a4966eff1ada5cba80f2b689446db"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaff8a4966eff1ada5cba80f2b689446db">L1C_EnableCaches</a> (void)</td></tr> +<tr class="memdesc:gaff8a4966eff1ada5cba80f2b689446db"><td class="mdescLeft"> </td><td class="mdescRight">Enable Caches by setting I and C bits in SCTLR register. <a href="#gaff8a4966eff1ada5cba80f2b689446db">More...</a><br/></td></tr> +<tr class="separator:gaff8a4966eff1ada5cba80f2b689446db"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga320ef6fd1dd65f2f82e64c096a4994a6">L1C_DisableCaches</a> (void)</td></tr> +<tr class="memdesc:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="mdescLeft"> </td><td class="mdescRight">Disable Caches by clearing I and C bits in SCTLR register. <a href="#ga320ef6fd1dd65f2f82e64c096a4994a6">More...</a><br/></td></tr> +<tr class="separator:ga320ef6fd1dd65f2f82e64c096a4994a6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa5fb36b4496e64472849f7811970c581"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gaa5fb36b4496e64472849f7811970c581">L1C_EnableBTAC</a> (void)</td></tr> +<tr class="memdesc:gaa5fb36b4496e64472849f7811970c581"><td class="mdescLeft"> </td><td class="mdescRight">Enable Branch Prediction by setting Z bit in SCTLR register. <a href="#gaa5fb36b4496e64472849f7811970c581">More...</a><br/></td></tr> +<tr class="separator:gaa5fb36b4496e64472849f7811970c581"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gab8695cf1f4a7f3789b93c41dc4eeb51d">L1C_DisableBTAC</a> (void)</td></tr> +<tr class="memdesc:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="mdescLeft"> </td><td class="mdescRight">Disable Branch Prediction by clearing Z bit in SCTLR register. <a href="#gab8695cf1f4a7f3789b93c41dc4eeb51d">More...</a><br/></td></tr> +<tr class="separator:gab8695cf1f4a7f3789b93c41dc4eeb51d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad0d732293be6a928db184b59aadc1979"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gad0d732293be6a928db184b59aadc1979">L1C_InvalidateBTAC</a> (void)</td></tr> +<tr class="memdesc:gad0d732293be6a928db184b59aadc1979"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate entire branch predictor array. <a href="#gad0d732293be6a928db184b59aadc1979">More...</a><br/></td></tr> +<tr class="separator:gad0d732293be6a928db184b59aadc1979"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac932810cfe83f087590859010972645e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gac932810cfe83f087590859010972645e">L1C_InvalidateICacheAll</a> (void)</td></tr> +<tr class="memdesc:gac932810cfe83f087590859010972645e"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole instruction cache. <a href="#gac932810cfe83f087590859010972645e">More...</a><br/></td></tr> +<tr class="separator:gac932810cfe83f087590859010972645e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9eb6f0a7c9c04cc49efd964eb59ba26f">L1C_CleanDCacheMVA</a> (void *va)</td></tr> +<tr class="memdesc:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="mdescLeft"> </td><td class="mdescRight">Clean data cache line by address. <a href="#ga9eb6f0a7c9c04cc49efd964eb59ba26f">More...</a><br/></td></tr> +<tr class="separator:ga9eb6f0a7c9c04cc49efd964eb59ba26f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9209853937940991daf70edd6bc633fe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga9209853937940991daf70edd6bc633fe">L1C_InvalidateDCacheMVA</a> (void *va)</td></tr> +<tr class="memdesc:ga9209853937940991daf70edd6bc633fe"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate data cache line by address. <a href="#ga9209853937940991daf70edd6bc633fe">More...</a><br/></td></tr> +<tr class="separator:ga9209853937940991daf70edd6bc633fe"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7646a5e01b529566968f393e485f46a2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga7646a5e01b529566968f393e485f46a2">L1C_CleanInvalidateDCacheMVA</a> (void *va)</td></tr> +<tr class="memdesc:ga7646a5e01b529566968f393e485f46a2"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate data cache by address. <a href="#ga7646a5e01b529566968f393e485f46a2">More...</a><br/></td></tr> +<tr class="separator:ga7646a5e01b529566968f393e485f46a2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga30d7632156a30a3b75064f6d15b8f850"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga30d7632156a30a3b75064f6d15b8f850">L1C_CleanInvalidateCache</a> (uint32_t op)</td></tr> +<tr class="memdesc:ga30d7632156a30a3b75064f6d15b8f850"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. <a href="#ga30d7632156a30a3b75064f6d15b8f850">More...</a><br/></td></tr> +<tr class="separator:ga30d7632156a30a3b75064f6d15b8f850"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae895f75c4f3539058232f555d79e5df3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#gae895f75c4f3539058232f555d79e5df3">L1C_InvalidateDCacheAll</a> (void)</td></tr> +<tr class="memdesc:gae895f75c4f3539058232f555d79e5df3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate the whole data cache. <a href="#gae895f75c4f3539058232f555d79e5df3">More...</a><br/></td></tr> +<tr class="separator:gae895f75c4f3539058232f555d79e5df3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga70359d824bf26f376e3d7cb9c787da27"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga70359d824bf26f376e3d7cb9c787da27">L1C_CleanDCacheAll</a> (void)</td></tr> +<tr class="memdesc:ga70359d824bf26f376e3d7cb9c787da27"><td class="mdescLeft"> </td><td class="mdescRight">Clean the whole data cache. <a href="#ga70359d824bf26f376e3d7cb9c787da27">More...</a><br/></td></tr> +<tr class="separator:ga70359d824bf26f376e3d7cb9c787da27"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga92b5babf7317abe3815f61a2731735c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga92b5babf7317abe3815f61a2731735c3">L1C_CleanInvalidateDCacheAll</a> (void)</td></tr> +<tr class="memdesc:ga92b5babf7317abe3815f61a2731735c3"><td class="mdescLeft"> </td><td class="mdescRight">Clean and invalidate the whole data cache. <a href="#ga92b5babf7317abe3815f61a2731735c3">More...</a><br/></td></tr> +<tr class="separator:ga92b5babf7317abe3815f61a2731735c3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#acdc36c1b3d3e16c17a73889b7d06d0d2">CMSIS_DEPRECATED</a> <br class="typebreak"/> +<a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__L1__cache__functions.html#ga722ceb077e491bb4befcfbb3aee9b20b">__L1C_CleanInvalidateCache</a> (uint32_t op)</td></tr> +<tr class="memdesc:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="mdescLeft"> </td><td class="mdescRight">Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. <a href="#ga722ceb077e491bb4befcfbb3aee9b20b">More...</a><br/></td></tr> +<tr class="separator:ga722ceb077e491bb4befcfbb3aee9b20b"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga722ceb077e491bb4befcfbb3aee9b20b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> <a class="el" href="group__comp__cntrl__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> void __L1C_CleanInvalidateCache </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>op</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">op</td><td>0 - invalidate, 1 - clean, otherwise - invalidate and clean </td></tr> + </table> + </dd> +</dl> +<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000001">Deprecated:</a></b></dt><dd>Use generic L1C_CleanInvalidateCache instead. </dd></dl> +<p>Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.</p> +<p>The parameter <b>op</b> defines which cleaning/invalidation strategy should be used:</p> +<ul> +<li>0 - Cache is invalidated using DCISW register.</li> +<li>1 - Cache is cleaned using DCCSW register.</li> +<li>other - Cache is invalidated and cleaned using DCCISW register. </li> +</ul> + +</div> +</div> +<a class="anchor" id="ga70359d824bf26f376e3d7cb9c787da27"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_CleanDCacheAll </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga9eb6f0a7c9c04cc49efd964eb59ba26f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_CleanDCacheMVA </td> + <td>(</td> + <td class="paramtype">void * </td> + <td class="paramname"><em>va</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">va</td><td>Pointer to data to clear the cache for. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga30d7632156a30a3b75064f6d15b8f850"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_CleanInvalidateCache </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>op</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">op</td><td>0 - invalidate, 1 - clean, otherwise - invalidate and clean</td></tr> + </table> + </dd> +</dl> +<p>Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. </p> + +</div> +</div> +<a class="anchor" id="ga92b5babf7317abe3815f61a2731735c3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_CleanInvalidateDCacheAll </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga7646a5e01b529566968f393e485f46a2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_CleanInvalidateDCacheMVA </td> + <td>(</td> + <td class="paramtype">void * </td> + <td class="paramname"><em>va</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">va</td><td>Pointer to data to invalidate the cache for. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gab8695cf1f4a7f3789b93c41dc4eeb51d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_DisableBTAC </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga320ef6fd1dd65f2f82e64c096a4994a6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_DisableCaches </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaa5fb36b4496e64472849f7811970c581"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_EnableBTAC </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gaff8a4966eff1ada5cba80f2b689446db"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_EnableCaches </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gad0d732293be6a928db184b59aadc1979"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_InvalidateBTAC </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="gae895f75c4f3539058232f555d79e5df3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_InvalidateDCacheAll </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ga9209853937940991daf70edd6bc633fe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_InvalidateDCacheMVA </td> + <td>(</td> + <td class="paramtype">void * </td> + <td class="paramname"><em>va</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">va</td><td>Pointer to data to invalidate the cache for. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gac932810cfe83f087590859010972645e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void L1C_InvalidateICacheAll </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |