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Diffstat (limited to 'docs/Core_A/html/group__CMSIS__core__register.js')
| -rw-r--r-- | docs/Core_A/html/group__CMSIS__core__register.js | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/docs/Core_A/html/group__CMSIS__core__register.js b/docs/Core_A/html/group__CMSIS__core__register.js new file mode 100644 index 0000000..d076e1a --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__core__register.js @@ -0,0 +1,26 @@ +var group__CMSIS__core__register = +[ + [ "Auxiliary Control Register (ACTLR)", "group__CMSIS__ACTLR.html", "group__CMSIS__ACTLR" ], + [ "Cache and branch predictor maintenance operations", "group__CMSIS__CBPM.html", "group__CMSIS__CBPM" ], + [ "Configuration Base Address Register (CBAR)", "group__CMSIS__CBAR.html", "group__CMSIS__CBAR" ], + [ "Coprocessor Access Control Register (CPACR)", "group__CMSIS__CPACR.html", "group__CMSIS__CPACR" ], + [ "Current Program Status Register (CPSR)", "group__CMSIS__CPSR.html", "group__CMSIS__CPSR" ], + [ "Data Fault Status Register (DFSR)", "group__CMSIS__DFSR.html", "group__CMSIS__DFSR" ], + [ "Domain Access Control Register (DACR)", "group__CMSIS__DACR.html", "group__CMSIS__DACR" ], + [ "Floating-Point Exception Control register (FPEXC)", "group__CMSIS__FPEXC.html", "group__CMSIS__FPEXC" ], + [ "Floating-point Status and Control Register (FPSCR)", "group__CMSIS__FPSCR.html", "group__CMSIS__FPSCR" ], + [ "Instruction Fault Status Register (IFSR)", "group__CMSIS__IFSR.html", "group__CMSIS__IFSR" ], + [ "Interrupt Status Register (ISR)", "group__CMSIS__ISR.html", "group__CMSIS__ISR" ], + [ "Multiprocessor Affinity Register (MPIDR)", "group__CMSIS__MPIDR.html", "group__CMSIS__MPIDR" ], + [ "Counter Frequency register (CNTFRQ)", "group__CMSIS__CNTFRQ.html", "group__CMSIS__CNTFRQ" ], + [ "PL1 Physical Timer Control register (CNTP_CTL)", "group__CMSIS__CNTP__CTL.html", "group__CMSIS__CNTP__CTL" ], + [ "PL1 Physical Timer Compare Value register (CNTP_CVAL)", "group__CMSIS__CNTP__CVAL.html", "group__CMSIS__CNTP__CVAL" ], + [ "PL1 Physical Timer Value register (CNTP_TVAL)", "group__CMSIS__CNTP__TVAL.html", "group__CMSIS__CNTP__TVAL" ], + [ "PL1 Physical Count register (CNTPCT)", "group__CMSIS__CNTPCT.html", "group__CMSIS__CNTPCT" ], + [ "Stack Pointer (SP/R13)", "group__CMSIS__SP.html", "group__CMSIS__SP" ], + [ "System Control Register (SCTLR)", "group__CMSIS__SCTLR.html", "group__CMSIS__SCTLR" ], + [ "TLB maintenance operations", "group__CMSIS__TLB.html", "group__CMSIS__TLB" ], + [ "Translation Table Base Registers (TTBR0/TTBR1)", "group__CMSIS__TTBR.html", "group__CMSIS__TTBR" ], + [ "Vector Base Address Register (VBAR)", "group__CMSIS__VBAR.html", "group__CMSIS__VBAR" ], + [ "Monitor Vector Base Address Register (MVBAR)", "group__CMSIS__MVBAR.html", "group__CMSIS__MVBAR" ] +];
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