diff options
Diffstat (limited to 'docs/Core_A/html/group__CMSIS__core__register.html')
| -rw-r--r-- | docs/Core_A/html/group__CMSIS__core__register.html | 207 |
1 files changed, 207 insertions, 0 deletions
diff --git a/docs/Core_A/html/group__CMSIS__core__register.html b/docs/Core_A/html/group__CMSIS__core__register.html new file mode 100644 index 0000000..120f536 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__core__register.html @@ -0,0 +1,207 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Core Register Access</title> +<title>CMSIS-Core (Cortex-A): Core Register Access</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-A) +  <span id="projectnumber">Version 1.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__CMSIS__core__register.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Macros</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(9)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(10)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#groups">Content</a> </div> + <div class="headertitle"> +<div class="title">Core Register Access</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions to access the Cortex-A core registers. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a> +Content</h2></td></tr> +<tr class="memitem:group__CMSIS__ACTLR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ACTLR.html">Auxiliary Control Register (ACTLR)</a></td></tr> +<tr class="memdesc:group__CMSIS__ACTLR"><td class="mdescLeft"> </td><td class="mdescRight">The ACTLR provides IMPLEMENTATION DEFINED configuration and control options. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CBPM"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBPM.html">Cache and branch predictor maintenance operations</a></td></tr> +<tr class="memdesc:group__CMSIS__CBPM"><td class="mdescLeft"> </td><td class="mdescRight">This section describes the cache and branch predictor maintenance operations. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CBAR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CBAR.html">Configuration Base Address Register (CBAR)</a></td></tr> +<tr class="memdesc:group__CMSIS__CBAR"><td class="mdescLeft"> </td><td class="mdescRight">Takes the physical base address value of the memory-mapped SCU peripherals at reset from the external signal PERIPHBASE[31:13]. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CPACR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPACR.html">Coprocessor Access Control Register (CPACR)</a></td></tr> +<tr class="memdesc:group__CMSIS__CPACR"><td class="mdescLeft"> </td><td class="mdescRight">The CPACR controls access to coprocessors CP0 to CP13. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CPSR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CPSR.html">Current Program Status Register (CPSR)</a></td></tr> +<tr class="memdesc:group__CMSIS__CPSR"><td class="mdescLeft"> </td><td class="mdescRight">The Current Program Status Register (CPSR) holds processor status and control information. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__DFSR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DFSR.html">Data Fault Status Register (DFSR)</a></td></tr> +<tr class="memdesc:group__CMSIS__DFSR"><td class="mdescLeft"> </td><td class="mdescRight">The DFSR holds status information about the last data fault. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__DACR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__DACR.html">Domain Access Control Register (DACR)</a></td></tr> +<tr class="memdesc:group__CMSIS__DACR"><td class="mdescLeft"> </td><td class="mdescRight">DACR defines the access permission for each of the sixteen memory domains. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__FPEXC"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPEXC.html">Floating-Point Exception Control register (FPEXC)</a></td></tr> +<tr class="memdesc:group__CMSIS__FPEXC"><td class="mdescLeft"> </td><td class="mdescRight">Provides a global enable for the Advanced SIMD and Floating-point (VFP) Extensions, and indicates how the state of these extensions is recorded. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__FPSCR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__FPSCR.html">Floating-point Status and Control Register (FPSCR)</a></td></tr> +<tr class="memdesc:group__CMSIS__FPSCR"><td class="mdescLeft"> </td><td class="mdescRight">Provides floating-point system status information and control. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__IFSR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__IFSR.html">Instruction Fault Status Register (IFSR)</a></td></tr> +<tr class="memdesc:group__CMSIS__IFSR"><td class="mdescLeft"> </td><td class="mdescRight">The IFSR holds status information about the last instruction fault. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__ISR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__ISR.html">Interrupt Status Register (ISR)</a></td></tr> +<tr class="memdesc:group__CMSIS__ISR"><td class="mdescLeft"> </td><td class="mdescRight">The ISR shows whether an IRQ, FIQ, or external abort is pending. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__MPIDR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MPIDR.html">Multiprocessor Affinity Register (MPIDR)</a></td></tr> +<tr class="memdesc:group__CMSIS__MPIDR"><td class="mdescLeft"> </td><td class="mdescRight">In a multiprocessor system, the MPIDR provides an additional processor identification mechanism for scheduling purposes, and indicates whether the implementation includes the Multiprocessing Extensions. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CNTFRQ"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTFRQ.html">Counter Frequency register (CNTFRQ)</a></td></tr> +<tr class="memdesc:group__CMSIS__CNTFRQ"><td class="mdescLeft"> </td><td class="mdescRight">Indicates the clock frequency of the system counter. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CNTP__CTL"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CTL.html">PL1 Physical Timer Control register (CNTP_CTL)</a></td></tr> +<tr class="memdesc:group__CMSIS__CNTP__CTL"><td class="mdescLeft"> </td><td class="mdescRight">The control register for the physical timer. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CNTP__CVAL"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__CVAL.html">PL1 Physical Timer Compare Value register (CNTP_CVAL)</a></td></tr> +<tr class="memdesc:group__CMSIS__CNTP__CVAL"><td class="mdescLeft"> </td><td class="mdescRight">Holds the 64-bit compare value for the PL1 physical timer. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CNTP__TVAL"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTP__TVAL.html">PL1 Physical Timer Value register (CNTP_TVAL)</a></td></tr> +<tr class="memdesc:group__CMSIS__CNTP__TVAL"><td class="mdescLeft"> </td><td class="mdescRight">Holds the timer value for the PL1 physical timer. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__CNTPCT"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__CNTPCT.html">PL1 Physical Count register (CNTPCT)</a></td></tr> +<tr class="memdesc:group__CMSIS__CNTPCT"><td class="mdescLeft"> </td><td class="mdescRight">Holds the 64-bit physical count value. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__SP"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SP.html">Stack Pointer (SP/R13)</a></td></tr> +<tr class="memdesc:group__CMSIS__SP"><td class="mdescLeft"> </td><td class="mdescRight">The processor uses SP as a pointer to the active stack. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__SCTLR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__SCTLR.html">System Control Register (SCTLR)</a></td></tr> +<tr class="memdesc:group__CMSIS__SCTLR"><td class="mdescLeft"> </td><td class="mdescRight">The SCTLR provides the top level control of the system, including its memory system. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__TLB"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TLB.html">TLB maintenance operations</a></td></tr> +<tr class="memdesc:group__CMSIS__TLB"><td class="mdescLeft"> </td><td class="mdescRight">This section describes the TLB operations that are implemented on all Armv7-A implementations. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__TTBR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html">Translation Table Base Registers (TTBR0/TTBR1)</a></td></tr> +<tr class="memdesc:group__CMSIS__TTBR"><td class="mdescLeft"> </td><td class="mdescRight">TTBRn holds the base address of translation table n, and information about the memory it occupies. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__VBAR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__VBAR.html">Vector Base Address Register (VBAR)</a></td></tr> +<tr class="memdesc:group__CMSIS__VBAR"><td class="mdescLeft"> </td><td class="mdescRight">When high exception vectors are not selected, the VBAR holds the exception base address for exceptions that are not taken to Monitor mode or to Hyp mode. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__CMSIS__MVBAR"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__MVBAR.html">Monitor Vector Base Address Register (MVBAR)</a></td></tr> +<tr class="memdesc:group__CMSIS__MVBAR"><td class="mdescLeft"> </td><td class="mdescRight">The MVBAR holds the exception base address for all exceptions that are taken to Monitor mode. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |