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diff --git a/docs/Core_A/html/group__CMSIS__TTBR.html b/docs/Core_A/html/group__CMSIS__TTBR.html new file mode 100644 index 0000000..3aacae2 --- /dev/null +++ b/docs/Core_A/html/group__CMSIS__TTBR.html @@ -0,0 +1,229 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Translation Table Base Registers (TTBR0/TTBR1)</title> +<title>CMSIS-Core (Cortex-A): Translation Table Base Registers (TTBR0/TTBR1)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link 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Access</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>TTBRn holds the base address of translation table n, and information about the memory it occupies. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga678997bc01f6d8d48b1d407cec24809d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html#ga678997bc01f6d8d48b1d407cec24809d">__get_TTBR0</a> (void)</td></tr> +<tr class="memdesc:ga678997bc01f6d8d48b1d407cec24809d"><td class="mdescLeft"> </td><td class="mdescRight">Get TTBR0. <a href="#ga678997bc01f6d8d48b1d407cec24809d">More...</a><br/></td></tr> +<tr class="separator:ga678997bc01f6d8d48b1d407cec24809d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad2ccad052f77c18897c5ceaaf307711e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="cmsis__armcc_8h.html#ab904513442afdf77d4f8c74f23cbb040">__STATIC_FORCEINLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__CMSIS__TTBR.html#gad2ccad052f77c18897c5ceaaf307711e">__set_TTBR0</a> (uint32_t ttbr0)</td></tr> +<tr class="memdesc:gad2ccad052f77c18897c5ceaaf307711e"><td class="mdescLeft"> </td><td class="mdescRight">Set TTBR0. <a href="#gad2ccad052f77c18897c5ceaaf307711e">More...</a><br/></td></tr> +<tr class="separator:gad2ccad052f77c18897c5ceaaf307711e"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p><b>32-bit TTBR format</b> </p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:x] </td><td align="left">BADDR </td><td align="left">Translation table base address, bits[31:x]. </td></tr> +<tr> +<td align="left">[x-1:7] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[6] </td><td align="left">IRGN[0] </td><td align="left">Inner region bit 0. </td></tr> +<tr> +<td align="left">[5] </td><td align="left">NOS </td><td align="left">Not Outer Shareable bit. </td></tr> +<tr> +<td align="left">[4:3] </td><td align="left">RGN </td><td align="left">Region bits. </td></tr> +<tr> +<td align="left">[2] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[1] </td><td align="left">S </td><td align="left">Shareable bit. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">C/IRGN[1] </td><td align="left">Cacheable bit. / Inner region bit 1. </td></tr> +</table> +<dl class="section note"><dt>Note</dt><dd>The width of TTBR0 BADDR field depends on the setting in TTBCR N field, giving <code>x=14-N</code>. </dd> +<dd> +The width of TTBR1 BADDR field is fixed at <code>x=14</code>.</dd></dl> +<p><b>64-bit TTBR format</b> </p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[63:56] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[55:48] </td><td align="left">ASID </td><td align="left">An ASID for the translation table base address. </td></tr> +<tr> +<td align="left">[47:40] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[39:x] </td><td align="left">BADDR </td><td align="left">Translation table base address, bits[39:x]. </td></tr> +<tr> +<td align="left">[x-1:0] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +</table> +<dl class="section note"><dt>Note</dt><dd>The width of TBBR0/TBBR1 BADDR fields depends on the settings in TTBCR T0SZ/T1SZ fields respectively, giving <code>x=14-TnSZ</code>.</dd></dl> +<p>Consider using <a class="el" href="group__CMSIS__TTBR.html#ga678997bc01f6d8d48b1d407cec24809d">__get_TTBR0</a> and <a class="el" href="group__CMSIS__TTBR.html#gad2ccad052f77c18897c5ceaaf307711e">__set_TTBR0</a> for accessing TTBR0 register. </p> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga678997bc01f6d8d48b1d407cec24809d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t __get_TTBR0 </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function returns the value of the Translation Table Base Register 0.</p> +<dl class="section return"><dt>Returns</dt><dd>Translation Table Base Register 0 value</dd></dl> +<p>This function returns the value of the Translation Table Base Register 0. </p> + +</div> +</div> +<a class="anchor" id="gad2ccad052f77c18897c5ceaaf307711e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__comp__cntrl__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void __set_TTBR0 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ttbr0</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function assigns the given value to the Translation Table Base Register 0.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ttbr0</td><td>Translation Table Base Register 0 value to set</td></tr> + </table> + </dd> +</dl> +<p>This function assigns the given value to the Translation Table Base Register 0. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> |