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PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Data Structures</title> +<title>CMSIS-Core (Cortex-M): Data Structures</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script 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+ </div> + </li> + </ul> + </div> + <div id="navrow2" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li> + <li><a href="functions.html"><span>Data Fields</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('annotated.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Data Structures</div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory"> +<table class="directory"> +<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionAPSR__Type.html" target="_self">APSR_Type</a></td><td class="desc">Union type to access the Application Program Status Register (APSR) </td></tr> +<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structARM__MPU__Region__t.html" target="_self">ARM_MPU_Region_t</a></td><td class="desc">Setup information of a single MPU Region </td></tr> +<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionCONTROL__Type.html" target="_self">CONTROL_Type</a></td><td class="desc">Union type to access the Control Registers (CONTROL) </td></tr> +<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structCoreDebug__Type.html" target="_self">CoreDebug_Type</a></td><td class="desc">Structure type to access the Core Debug Register (CoreDebug) </td></tr> +<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structDWT__Type.html" target="_self">DWT_Type</a></td><td class="desc">Structure type to access the Data Watchpoint and Trace Register (DWT) </td></tr> +<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structFPU__Type.html" target="_self">FPU_Type</a></td><td class="desc">Structure type to access the Floating Point Unit (FPU) </td></tr> +<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionIPSR__Type.html" target="_self">IPSR_Type</a></td><td class="desc">Union type to access the Interrupt Program Status Register (IPSR) </td></tr> +<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structITM__Type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM) </td></tr> +<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structMPU__Type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU) </td></tr> +<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structNVIC__Type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC) </td></tr> +<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCB__Type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB) </td></tr> +<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSCnSCB__Type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB </td></tr> +<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structSysTick__Type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick) </td></tr> +<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="structTPI__Type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI) </td></tr> +<tr id="row_14_" class="even"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionxPSR__Type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR) </td></tr> +</table> +</div><!-- directory --> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/annotated.js b/docs/Core/html/annotated.js new file mode 100644 index 0000000..323c6b9 --- /dev/null +++ b/docs/Core/html/annotated.js @@ -0,0 +1,18 @@ +var annotated = +[ + [ "APSR_Type", "unionAPSR__Type.html", "unionAPSR__Type" ], + [ "ARM_MPU_Region_t", "structARM__MPU__Region__t.html", "structARM__MPU__Region__t" ], + [ "CONTROL_Type", "unionCONTROL__Type.html", "unionCONTROL__Type" ], + [ "CoreDebug_Type", "structCoreDebug__Type.html", "structCoreDebug__Type" ], + [ "DWT_Type", "structDWT__Type.html", "structDWT__Type" ], + [ "FPU_Type", "structFPU__Type.html", "structFPU__Type" ], + [ "IPSR_Type", "unionIPSR__Type.html", "unionIPSR__Type" ], + [ "ITM_Type", "structITM__Type.html", "structITM__Type" ], + [ "MPU_Type", "structMPU__Type.html", "structMPU__Type" ], + [ "NVIC_Type", "structNVIC__Type.html", "structNVIC__Type" ], + [ "SCB_Type", "structSCB__Type.html", "structSCB__Type" ], + [ "SCnSCB_Type", "structSCnSCB__Type.html", "structSCnSCB__Type" ], + [ "SysTick_Type", "structSysTick__Type.html", "structSysTick__Type" ], + [ "TPI_Type", "structTPI__Type.html", "structTPI__Type" ], + [ "xPSR_Type", "unionxPSR__Type.html", "unionxPSR__Type" ] +];
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+ border-left: 2px solid #9AAED5; + margin: 0 24px 0 4px; + padding: 0 12px 0 16px; +} + +/* @end */ + +/* +.search { + color: #003399; + font-weight: bold; +} + +form.search { + margin-bottom: 0px; + margin-top: 0px; +} + +input.search { + font-size: 75%; + color: #000080; + font-weight: normal; + background-color: #e8eef2; +} +*/ + +td.tiny { + font-size: 75%; +} + +.dirtab { + padding: 4px; + border-collapse: collapse; + border: 1px solid #A2B4D8; +} + +th.dirtab { + background: #EBEFF6; + font-weight: bold; +} + +hr { + height: 0px; + border: none; + border-top: 1px solid #4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memItemLeft, .memItemRight, .memTemplParams { + border-top: 1px solid #C3CFE6; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; 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+ display:inline; + } +} + diff --git a/docs/Core/html/coreMISRA_Exceptions_pg.html b/docs/Core/html/coreMISRA_Exceptions_pg.html new file mode 100644 index 0000000..d6b95dc --- /dev/null +++ b/docs/Core/html/coreMISRA_Exceptions_pg.html @@ -0,0 +1,174 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>MISRA-C Deviations</title> +<title>CMSIS-Core (Cortex-M): MISRA-C Deviations</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">MISRA-C Deviations </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>CMSIS-Core (Cortex-M) uses the common coding rules for CMSIS components that are documented under <a href="../../General/html/index.html"><b>Introduction</b></a>.</p> +<p>CMSIS-Core (Cortex-M) violates the following MISRA-C:2004 rules:</p> +<ul> +<li>Required Rule 8.5, object/function definition in header file.<br/> + Violated since function definitions in header files are used for function inlining'.</li> +<li>Advisory Rule 12.4, Side effects on right hand side of logical operator.<br/> + Violated because volatile is used for core register definitions.</li> +<li>Advisory Rule 14.7, Return statement before end of function.<br/> + Violated to simplify code logic.</li> +<li>Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br/> + Violated since unions are used for effective representation of core registers.</li> +<li>Advisory Rule 19.4, Disallowed definition for macro.<br/> + Violated since macros are used for assembler keywords.</li> +<li>Advisory Rule 19.7, Function-like macro defined.<br/> + Violated since function-like macros are used to generate more efficient code.</li> +<li>Advisory Rule 19.16, all preprocessing directives must be valid.<br/> + Violated to set default settings for macros.</li> +</ul> +<p>CMSIS-Core (Cortex-M) violates the following MISRA-C:2012 rules:</p> +<ul> +<li>Directive 4.9, function-like macro defined.<br/> + Violated since function-like macros are used to generate more efficient code.</li> +<li>Rule 1.3, multiple use of '#/##' operators in macro definition.<br/> + Violated since function-like macros are used to generate more efficient code.</li> +<li>Rule 11.4, conversion between a pointer and integer type.<br/> + Violated because of core register access.</li> +<li>Rule 11.6, cast from unsigned long to pointer.<br/> + Violated because of core register access.</li> +<li>Rule 13.5, side effects on right hand side of logical operator.<br/> + Violated because of shift operand is used in macros and functions.</li> +<li>Rule 14.4, conditional expression should have essentially Boolean type.<br/> + Violated since macros with several instructions are used.</li> +<li>Rule 15.5, return statement before end of function.<br/> + Violated to simplify code logic.</li> +<li>Rule 20.10, '#/##' operators used.<br/> + Violated since function-like macros are used to generate more efficient code.</li> +<li>Rule 21.1, reserved to the compiler.<br/> + Violated since macros with leading underscores are used.</li> +</ul> +<p><device>.h files generated by <b>SVDConv.exe</b> violate the following MISRA-C:2004 rules:</p> +<ul> +<li>Advisory Rule 20.2, Re-use of C90 identifier pattern.<br/> + Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols.</li> +<li>Advisory Rule 19.1, Declaration before #include.<br/> + Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file. </li> +</ul> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/core_revisionHistory.html b/docs/Core/html/core_revisionHistory.html new file mode 100644 index 0000000..0016702 --- /dev/null +++ b/docs/Core/html/core_revisionHistory.html @@ -0,0 +1,274 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Revision History of CMSIS-Core (Cortex-M)</title> +<title>CMSIS-Core (Cortex-M): Revision History of CMSIS-Core (Cortex-M)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div 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get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.<br/> + Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.<br/> + Added support for Cortex-M1 (beta). <br/> + Removed usage of register keyword. <br/> + Added defines for EXC_RETURN, FNC_RETURN and integrity signature values. <br/> + Enhanced MPUv7 API with defines for memory access attributes.<br/> + </td></tr> +<tr> +<td>V5.1.1 </td><td>Aligned MSPLIM and PSPLIM access functions along supported compilers.<br/> + </td></tr> +<tr> +<td>V5.1.0 </td><td>Added MPU Functions for ARMv8-M for Cortex-M23/M33.<br/> + Moved __SSAT and __USAT intrinsics to CMSIS-Core.<br/> + Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.<br/> + </td></tr> +<tr> +<td>V5.0.2 </td><td>Added macros <a class="el" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a>.<br/> + Added macros <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a>.<br/> + Deprecated macro <a class="el" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a>.<br/> + Changed <a class="el" href="group__version__control__gr.html">Version Control</a> macros to be core agnostic. <br/> + Added <a class="el" href="group__mpu__functions.html">MPU Functions for Armv7-M</a> for Cortex-M0+/M3/M4/M7. </td></tr> +<tr> +<td>V5.0.1 </td><td>Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a>. <br/> + Added: uVisor support. <br/> + </td></tr> +<tr> +<td>V5.00 </td><td>Added: Cortex-M23, Cortex-M33 support.<br/> + Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br/> + Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT. <br/> + Reworked: SAU register and functions. <br/> + Added: macro <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>. <br/> + Updated: function <a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>. <br/> + Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions. <br/> + Added: macro <a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>. <br/> + Updated: compiler specific include files. <br/> + Updated: core dependant include files. <br/> + Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h. </td></tr> +<tr> +<td>V5.00<br/> +Beta 6 </td><td>Added: SCB_CFSR register bit definitions. <br/> + Added: function <a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a>. <br/> + Updated: core instruction macros <a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> for toolchain GCC. </td></tr> +<tr> +<td>V5.00<br/> +Beta 5 </td><td>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib. <br/> + Added: DSP libraries build projects to CMSIS pack. </td></tr> +<tr> +<td>V5.00<br/> +Beta 4 </td><td>Updated: ARMv8M device files. <br/> + Corrected: ARMv8MBL interrupts. <br/> + Reworked: NVIC functions. </td></tr> +<tr> +<td>V5.00<br/> +Beta 2 </td><td>Changed: ARMv8M SAU regions to 8. <br/> + Changed: moved function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> to file partition_<device>.h. <br/> + Changed: license under Apache-2.0. <br/> + Added: check if macro is defined before use. <br/> + Corrected: function <a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a>. <br/> + Corrected: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>. <br/> + Added: NVIC function virtualization with macros <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> and <a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a>. </td></tr> +<tr> +<td>V5.00<br/> +Beta 1 </td><td>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.<br/> + Renamed: core_*.h to lower case.<br/> + Added: function <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> to all CMSIS cores.<br/> + Added: ARMv8-M support. </td></tr> +<tr> +<td>V4.30 </td><td>Corrected: DoxyGen function parameter comments.<br/> + Corrected: IAR toolchain: removed for <a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> the attribute(noreturn).<br/> + Corrected: GCC toolchain: suppressed irrelevant compiler warnings.<br/> + Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h). </td></tr> +<tr> +<td>V4.20 </td><td>Corrected: MISRA-C:2004 violations. <br/> + Corrected: predefined macro for TI CCS Compiler. <br/> + Corrected: function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> in arm_math.h. <br/> + Updated: cache functions for Cortex-M7. <br/> + Added: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> to core_*.h. <br/> + Updated: functions <a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a>, <a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a>. <br/> + Corrected: potential bug in function <a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a>. </td></tr> +<tr> +<td>V4.10 </td><td>Corrected: MISRA-C:2004 violations. <br/> + Corrected: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. <br/> + Corrected: register definitions for ITCMCR register. <br/> + Corrected: register definitions for <a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a> register. <br/> + Added: functions <a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br/> + Added: register definitions for <a class="el" href="unionAPSR__Type.html">APSR_Type</a>, <a class="el" href="unionIPSR__Type.html">IPSR_Type</a>, <a class="el" href="unionxPSR__Type.html">xPSR_Type</a> register. <br/> + Added: <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. <br/> + Added: intrinsic functions <a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. <br/> + </td></tr> +<tr> +<td>V4.00 </td><td>Added: Cortex-M7 support.<br/> + Added: intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br/> + </td></tr> +<tr> +<td>V3.40 </td><td>Corrected: C++ include guard settings.<br/> + </td></tr> +<tr> +<td>V3.30 </td><td>Added: COSMIC tool chain support.<br/> + Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br/> + Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br/> + Corrected: GCC/CLang warnings.<br/> + </td></tr> +<tr> +<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br/> + Added: <a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br/> + Corrected: <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>.<br/> + Corrected: <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br/> + Corrected: <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. <br/> + Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br/> + </td></tr> +<tr> +<td>V3.01 </td><td>Added support for Cortex-M0+ processor.<br/> + </td></tr> +<tr> +<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/> + Added function <a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/> + Added <a class="el" href="regMap_pg.html">Register Mapping</a> for TPIU, DWT. <br/> + Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/> + Corrected <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/> + Corrected the functions <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/> + Documentation restructured. </td></tr> +<tr> +<td>V2.10 </td><td>Updated documentation.<br/> + Updated CMSIS core include files.<br/> + Changed CMSIS/Device folder structure.<br/> + Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/> + Reworked CMSIS DSP library examples. </td></tr> +<tr> +<td>V2.00 </td><td>Added support for Cortex-M4 processor. </td></tr> +<tr> +<td>V1.30 </td><td>Reworked Startup Concept.<br/> + Added additional Debug Functionality.<br/> + Changed folder structure.<br/> + Added doxygen comments.<br/> + Added definitions for bit. </td></tr> +<tr> +<td>V1.01 </td><td>Added support for Cortex-M0 processor. </td></tr> +<tr> +<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </td></tr> +<tr> +<td>V1.00 </td><td>Initial Release for Cortex-M3 processor. </td></tr> +</table> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/deprecated.html b/docs/Core/html/deprecated.html new file mode 100644 index 0000000..f8b5907 --- /dev/null +++ b/docs/Core/html/deprecated.html @@ -0,0 +1,140 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Deprecated List</title> +<title>CMSIS-Core (Cortex-M): Deprecated List</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('deprecated.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Deprecated List </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><dl class="reflist"> +<dt><a class="anchor" id="_deprecated000004"></a>Global <a class="el" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a> </dt> +<dd><p class="startdd">Do not use this macro. It has been superseded by <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a> and will be removed in the future.</p> +<p class="enddd"></p> +</dd> +<dt><a class="anchor" id="_deprecated000003"></a>Global <a class="el" href="group__version__control__depricated__gr.html#gabea7df329b150f620ee42f9d82516241">__XXX_CMSIS_VERSION</a> </dt> +<dd>Only rely on this define for CMSIS 5.0 and before. </dd> +<dt><a class="anchor" id="_deprecated000001"></a>Global <a class="el" href="group__version__control__depricated__gr.html#ga2ecc1658e18eb1a0be7959e33b836d05">__XXX_CMSIS_VERSION_MAIN</a> </dt> +<dd>Only rely on this define for CMSIS 5.0 and before. </dd> +<dt><a class="anchor" id="_deprecated000002"></a>Global <a class="el" href="group__version__control__depricated__gr.html#ga962096f43e0d194f0b79021964c57fbd">__XXX_CMSIS_VERSION_SUB</a> </dt> +<dd>Only rely on this define for CMSIS 5.0 and before. </dd> +</dl> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/device_h_pg.html b/docs/Core/html/device_h_pg.html new file mode 100644 index 0000000..d72aff3 --- /dev/null +++ b/docs/Core/html/device_h_pg.html @@ -0,0 +1,655 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Device Header File <device.h></title> +<title>CMSIS-Core (Cortex-M): Device Header File <device.h></title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('device_h_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Device Header File <device.h> </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p> +<ul> +<li><a class="el" href="device_h_pg.html#interrupt_number_sec">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li> +<li><a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li> +<li><a class="el" href="device_h_pg.html#device_access">Device Peripheral Access Layer</a> provides definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li> +<li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li> +</ul> +<p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</p> +<h1><a class="anchor" id="interrupt_number_sec"></a> +Interrupt Number Definition</h1> +<p><a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the enumeration <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device.</p> +<ul> +<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li> +<li>Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a>.</li> +</ul> +<p><b>Example:</b> </p> +<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p> +<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div> +<div class="line">{</div> +<div class="line"><span class="comment">/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/</span></div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, </div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a> = -13, </div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, </div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, </div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, </div> +<div class="line"><span class="comment">/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/</span></div> +<div class="line"> WAKEUP0_IRQn = 0, </div> +<div class="line"> WAKEUP1_IRQn = 1, </div> +<div class="line"> WAKEUP2_IRQn = 2,</div> +<div class="line"> : :</div> +<div class="line"> : :</div> +<div class="line"> EINT1_IRQn = 30, </div> +<div class="line"> EINT0_IRQn = 31, </div> +<div class="line">} <a class="code" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>;</div> +</div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a> +Configuration of the Processor and Core Peripherals</h1> +<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> configures the Cortex-M or SecurCore processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_<cpu>.h</b>.</p> +<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p> +<p><b>core_cm0.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm0plus.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM0PLUS_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm3.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM3_REV </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm4.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM4_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_cm7.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__CM7_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +<tr> +<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not. See <b>__FPU_DP</b> description below. </td></tr> +<tr> +<td>__FPU_DP </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <b>__FPU_PRESENT</b> and <b>__FPU_DP</b> determine the whether the FPU is with single or double precision as shown in the table below. <br/> +<br/> + <table class="cmtable"> +<tr bgcolor="cyan"> +<td><b>__FPU_PRESENT</b> </td><td><b>__FPU_DP</b> </td><td><b>Description</b> </td></tr> +<tr> +<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <b>__FPU_DP</b> has no influence. </td></tr> +<tr> +<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision. The file <b>ARMCM7_SP.h</b> has preconfigured settings for this combination. </td></tr> +<tr> +<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision. The file <b>ARMCM7_DP.h</b> has preconfigured settings for this combination. </td></tr> +</table> +</td></tr> +<tr> +<td>__ICACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not </td></tr> +<tr> +<td>__DCACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not </td></tr> +<tr> +<td>__DTCM_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Tightly Coupled Memory is present or not </td></tr> +</table> +<p><b>core_sc000.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__SC000_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_sc300.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__SC300_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_CM23.h</b> or <b>core_ARMv8MBL.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__ARMv8MBL_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not </td></tr> +<tr> +<td>__VTOR_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a VTOR register is present or not </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>core_CM33.h</b> or <b>core_ARMv8MML.h</b> </p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>__ARMv8MML_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr> +<tr> +<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr> +<tr> +<td>__SAUREGION_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if SAU regions are present or not </td></tr> +<tr> +<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr> +<tr> +<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>3 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr> +<tr> +<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr> +</table> +<p><b>Example</b> </p> +<p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV 0x0001 </span><span class="comment">/* Core revision r0p1 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __MPU_PRESENT 1 </span><span class="comment">/* MPU present or not */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __NVIC_PRIO_BITS 3 </span><span class="comment">/* Number of Bits used for Priority Levels */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __Vendor_SysTickConfig 0 </span><span class="comment">/* Set to 1 if different SysTick Config is used */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __FPU_PRESENT 1 </span><span class="comment">/* FPU present or not */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span>.</div> +<div class="line">.</div> +<div class="line"><span class="preprocessor">#include <core_cm4.h></span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span></div> +</div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a> +CMSIS Version and Processor Information</h1> +<p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-Core (Cortex-M) and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> to verify a minimum version or ensure that the right processor core is used.</p> +<p><b>core_cm0.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __CM0_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (0U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_cm0plus.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __CM0P_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (0U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_cm3.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __CM3_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (3U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_cm4.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __CM4_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (4U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_cm7.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __CM7_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (7U) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_sc000.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __SC000_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_SC (0U) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_sc300.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __SC300_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_SC (300U) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_ARMv8MBL.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __ARMv8MBL_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (tbd) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><p><b>core_ARMv8MML.h</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_MAIN (5U) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION_SUB (0U) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \</span></div> +<div class="line"><span class="preprocessor"> __ARMv8MML_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define __CORTEX_M (tbd) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div> +</div><!-- fragment --><h1><a class="anchor" id="device_access"></a> +Device Peripheral Access Layer</h1> +<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains for each peripheral:</p> +<ul> +<li>Register Layout Typedef</li> +<li>Base Address</li> +<li>Access Definitions</li> +</ul> +<p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p> +<h1><a class="anchor" id="device_h_sec"></a> +Device.h Template File</h1> +<p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p> +<pre class="fragment">/**************************************************************************//** + * @file <Device>.h + * @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for + * Device <Device> + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */ +#define <Device>_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* ToDo: replace '<Vendor>' with vendor name; add your doxyGen comment */ +/** @addtogroup <Vendor> + * @{ + */ + + +/* ToDo: replace '<Device>' with device name; add your doxyGen comment */ +/** @addtogroup <Device> + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum IRQn +{ +/* ======================================= ARM Cortex-M# Specific Interrupt Numbers ======================================== */ + +/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M0 / Cortex-M0+ device */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* ToDo: use this Cortex interrupt numbers if your device is a Cortex-M3 / Cortex-M4 / Cortex-M7 device */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== <Device> Specific Interrupt Numbers ========================================= */ +/* ToDo: add here your device specific external interrupt numbers + according the interrupt handlers defined in startup_Device.s + eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */ + <DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the Arm Cortex-M4 Processor and Core Peripherals =========================== */ +/* ToDo: set the defines according your Device */ +/* ToDo: define the correct core revision + __CM0_REV if your device is a Cortex-M0 device + __CM3_REV if your device is a Cortex-M3 device + __CM4_REV if your device is a Cortex-M4 device + __CM7_REV if your device is a Cortex-M7 device */ +#define __CM#_REV 0x0201 /*!< Core Revision r2p1 */ +/* ToDo: define the correct core features for the <Device> */ +#define __MPU_PRESENT 1 /*!< Set to 1 if MPU is present */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if VTOR is present */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0 /*!< Set to 1 if FPU is present */ +#define __FPU_DP 0 /*!< Set to 1 if FPU is double precision FPU (default is single precision FPU) */ +#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */ +#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */ +#define __DTCM_PRESENT 0 /*!< Set to 1 if DTCM is present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +/* ToDo: include the correct core_cm#.h file + core_cm0.h if your device is a CORTEX-M0 device + core_cm3.h if your device is a CORTEX-M3 device + core_cm4.h if your device is a CORTEX-M4 device + core_cm7.h if your device is a CORTEX-M4 device */ +#include <core_cm#.h> /*!< Arm Cortex-M# processor and core peripherals */ +/* ToDo: include your system_<Device>.h file + replace '<Device>' with your device name */ +#include "system_<Device>.h" /*!< <Device> System */ + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* ToDo: add here your device specific peripheral access structure typedefs + following is an example for a timer */ + +/* =========================================================================================================================== */ +/* ================ TMR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer (TMR) + */ + +typedef struct +{ /*!< (@ 0x40000000) TIM Structure */ + __IOM uint32_t TimerLoad; /*!< (@ 0x00000004) Timer Load */ + __IM uint32_t TimerValue; /*!< (@ 0x00000008) Timer Counter Current Value */ + __IOM uint32_t TimerControl; /*!< (@ 0x0000000C) Timer Control */ + __OM uint32_t TimerIntClr; /*!< (@ 0x00000010) Timer Interrupt Clear */ + __IM uint32_t TimerRIS; /*!< (@ 0x00000014) Timer Raw Interrupt Status */ + __IM uint32_t TimerMIS; /*!< (@ 0x00000018) Timer Masked Interrupt Status */ + __IM uint32_t RESERVED[1]; + __IOM uint32_t TimerBGLoad; /*!< (@ 0x00000020) Background Load Register */ +} <DeviceAbbreviation>_TMR_TypeDef; + +/*@}*/ /* end of group <Device>_Peripherals */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/* ToDo: add here your device peripherals base addresses + following is an example for timer */ +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +/* Peripheral and SRAM base address */ +#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ + +/* Peripheral memory map */ +#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */ +#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */ +#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */ + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/* ToDo: add here your device peripherals pointer definitions + following is an example for timer */ +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) +#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) +#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE) + + +/** @} */ /* End of group <Device> */ + +/** @} */ /* End of group <Vendor> */ + +#ifdef __cplusplus +} +#endif + +#endif /* <Device>_H */ +</pre> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/doxygen.css b/docs/Core/html/doxygen.css new file mode 100644 index 0000000..ce5dd28 --- /dev/null +++ b/docs/Core/html/doxygen.css @@ -0,0 +1,1366 @@ +/* The standard CSS for doxygen 1.8.6 */ + +body, table, div, p, dl { + font: 400 14px/22px Roboto,sans-serif; +} + +/* @group Heading Levels */ + +h1.groupheader { + font-size: 150%; +} + +.title { + font: 400 14px/28px Roboto,sans-serif; + font-size: 150%; + font-weight: bold; + margin: 10px 2px; +} + +h2.groupheader { + border-bottom: 1px solid #859DCD; + color: #334C7D; + font-size: 150%; + font-weight: normal; + margin-top: 1.75em; + padding-top: 8px; + padding-bottom: 4px; + width: 100%; +} + +h3.groupheader { + font-size: 100%; +} + +h1, h2, h3, h4, h5, h6 { + -webkit-transition: text-shadow 0.5s linear; + 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+ margin-right: 15px; +} + +/* @group Link Styling */ + +a { + color: #3A568E; + font-weight: normal; + text-decoration: none; +} + +.contents a:visited { + color: #4464A5; +} + +a:hover { + text-decoration: underline; +} + +a.qindex { + font-weight: bold; +} + +a.qindexHL { + font-weight: bold; + background-color: #9AAED5; + color: #ffffff; + border: 1px double #849CCC; +} + +.contents a.qindexHL:visited { + color: #ffffff; +} + +a.el { + font-weight: bold; +} + +a.elRef { +} + +a.code, a.code:visited, a.line, a.line:visited { + color: #4665A2; +} + +a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited { + color: #4665A2; +} + +/* @end */ + +dl.el { + margin-left: -1cm; +} + +pre.fragment { + border: 1px solid #C4CFE5; + background-color: #FBFCFD; + padding: 4px 6px; + margin: 4px 8px 4px 2px; + overflow: auto; + word-wrap: break-word; + font-size: 9pt; + line-height: 125%; + font-family: monospace, fixed; + font-size: 105%; +} + +div.fragment { + padding: 4px 6px; + margin: 4px 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background-color: white; + color: black; + margin: 0; +} + +div.contents { + margin-top: 10px; + margin-left: 12px; + margin-right: 8px; +} + +td.indexkey { + background-color: #EBEFF6; + font-weight: bold; + border: 1px solid #C3CFE6; + margin: 2px 0px 2px 0; + padding: 2px 10px; + white-space: nowrap; + vertical-align: top; +} + +td.indexvalue { + background-color: #EBEFF6; + border: 1px solid #C3CFE6; + padding: 2px 10px; + margin: 2px 0px; +} + +tr.memlist { + background-color: #EDF1F7; +} + +p.formulaDsp { + text-align: center; +} + +img.formulaDsp { + +} + +img.formulaInl { + vertical-align: middle; +} + +div.center { + text-align: center; + margin-top: 0px; + margin-bottom: 0px; + padding: 0px; +} + +div.center img { + border: 0px; +} + +address.footer { + text-align: right; + padding-right: 12px; +} + +img.footer { + border: 0px; + vertical-align: middle; +} + +/* @group Code Colorization */ + +span.keyword { + color: #008000 +} + +span.keywordtype { + color: #604020 +} + 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#4769AD; +} + +hr.footer { + height: 1px; +} + +/* @group Member Descriptions */ + +table.memberdecls { + border-spacing: 0px; + padding: 0px; +} + +.memberdecls td, .fieldtable tr { + -webkit-transition-property: background-color, box-shadow; + -webkit-transition-duration: 0.5s; + -moz-transition-property: background-color, box-shadow; + -moz-transition-duration: 0.5s; + -ms-transition-property: background-color, box-shadow; + -ms-transition-duration: 0.5s; + -o-transition-property: background-color, box-shadow; + -o-transition-duration: 0.5s; + transition-property: background-color, box-shadow; + transition-duration: 0.5s; +} + +.memberdecls td.glow, .fieldtable tr.glow { + background-color: cyan; + box-shadow: 0 0 15px cyan; +} + +.mdescLeft, .mdescRight, +.memItemLeft, .memItemRight, +.memTemplItemLeft, .memTemplItemRight, .memTemplParams { + background-color: #F9FAFC; + border: none; + margin: 4px; + padding: 1px 0 0 8px; +} + +.mdescLeft, .mdescRight { + padding: 0px 8px 4px 8px; + color: #555; +} + +.memSeparator { + border-bottom: 1px solid #DEE4F0; + line-height: 1px; + margin: 0px; + padding: 0px; +} + +.memItemLeft, .memTemplItemLeft { + white-space: nowrap; +} + +.memItemRight { + width: 100%; +} + +.memTemplParams { + color: #4464A5; + white-space: nowrap; + font-size: 80%; +} + +/* @end */ + +/* @group Member Details */ + +/* Styles for detailed member documentation */ + +.memtemplate { + font-size: 80%; + color: #4464A5; + font-weight: normal; + margin-left: 9px; +} + +.memnav { + background-color: #EBEFF6; + border: 1px solid #A2B4D8; + text-align: center; + margin: 2px; + margin-right: 15px; + padding: 2px; +} + +.mempage { + width: 100%; +} + +.memitem { + padding: 0; + margin-bottom: 10px; + margin-right: 5px; + -webkit-transition: box-shadow 0.5s linear; + -moz-transition: box-shadow 0.5s linear; + -ms-transition: box-shadow 0.5s linear; + -o-transition: box-shadow 0.5s linear; + transition: box-shadow 0.5s linear; + display: table !important; + width: 100%; +} + +.memitem.glow { + box-shadow: 0 0 15px cyan; +} + +.memname { + font-weight: bold; + margin-left: 6px; +} + +.memname td { + vertical-align: bottom; +} + +.memproto, dl.reflist dt { + border-top: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 0px 6px 0px; + color: #233456; + font-weight: bold; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + background-image:url('nav_f.png'); + background-repeat:repeat-x; + background-color: #E2E7F3; + /* opera specific markup */ + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + border-top-right-radius: 4px; + border-top-left-radius: 4px; + /* firefox specific markup */ + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + -moz-border-radius-topright: 4px; + -moz-border-radius-topleft: 4px; + /* webkit specific markup */ + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + -webkit-border-top-right-radius: 4px; + -webkit-border-top-left-radius: 4px; + +} + +.memdoc, dl.reflist dd { + border-bottom: 1px solid #A7B8DA; + border-left: 1px solid #A7B8DA; + border-right: 1px solid #A7B8DA; + padding: 6px 10px 2px 10px; + background-color: #FBFCFD; + border-top-width: 0; + background-image:url('nav_g.png'); + background-repeat:repeat-x; + background-color: #FFFFFF; + /* opera specific markup */ + border-bottom-left-radius: 4px; + border-bottom-right-radius: 4px; + box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); + /* firefox specific markup */ + -moz-border-radius-bottomleft: 4px; + -moz-border-radius-bottomright: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px; + /* webkit specific markup */ + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +dl.reflist dt { + padding: 5px; +} + +dl.reflist dd { + margin: 0px 0px 10px 0px; + padding: 5px; +} + +.paramkey { + text-align: right; +} + +.paramtype { + white-space: nowrap; +} + +.paramname { + color: #602020; + white-space: nowrap; +} +.paramname em { + font-style: normal; +} +.paramname code { + line-height: 14px; +} + +.params, .retval, .exception, .tparams { + margin-left: 0px; + padding-left: 0px; +} + +.params .paramname, .retval .paramname { + font-weight: bold; + vertical-align: top; +} + +.params .paramtype { + font-style: italic; + vertical-align: top; +} + +.params .paramdir { + font-family: "courier new",courier,monospace; + vertical-align: top; +} + +table.mlabels { + border-spacing: 0px; +} + +td.mlabels-left { + width: 100%; + padding: 0px; +} + +td.mlabels-right { + vertical-align: bottom; + padding: 0px; + white-space: nowrap; +} + +span.mlabels { + margin-left: 8px; +} + +span.mlabel { + background-color: #708CC4; + border-top:1px solid #5072B7; + border-left:1px solid #5072B7; + border-right:1px solid #C3CFE6; + border-bottom:1px solid #C3CFE6; + text-shadow: none; + color: white; + margin-right: 4px; + padding: 2px 3px; + border-radius: 3px; + font-size: 7pt; + white-space: nowrap; + vertical-align: middle; +} + + + +/* @end */ + +/* these are for tree view when not used as main index */ + +div.directory { + margin: 10px 0px; + border-top: 1px solid #A8B8D9; + border-bottom: 1px solid #A8B8D9; + width: 100%; +} + +.directory table { + border-collapse:collapse; +} + +.directory td { + margin: 0px; + padding: 0px; + vertical-align: top; +} + +.directory td.entry { + white-space: nowrap; + padding-right: 6px; + padding-top: 3px; +} + +.directory td.entry a { + outline:none; +} + +.directory td.entry a img { + border: none; +} + +.directory td.desc { + width: 100%; + padding-left: 6px; + padding-right: 6px; + padding-top: 3px; + border-left: 1px solid rgba(0,0,0,0.05); +} + +.directory tr.even { + padding-left: 6px; + background-color: #F7F8FB; +} + +.directory img { + vertical-align: -30%; +} + +.directory .levels { + white-space: nowrap; + width: 100%; + text-align: right; + font-size: 9pt; +} + +.directory .levels span { + cursor: pointer; + padding-left: 2px; + padding-right: 2px; + color: #3A568E; +} + +div.dynheader { + margin-top: 8px; + -webkit-touch-callout: none; + -webkit-user-select: none; + -khtml-user-select: none; + -moz-user-select: none; + -ms-user-select: none; + user-select: none; +} + +address { + font-style: normal; + color: #293C63; +} + +table.doxtable { + border-collapse:collapse; + margin-top: 4px; + margin-bottom: 4px; +} + +table.doxtable td, table.doxtable th { + border: 1px solid #2B4069; + padding: 3px 7px 2px; +} + +table.doxtable th { + background-color: #354E81; + color: #FFFFFF; + font-size: 110%; + padding-bottom: 4px; + padding-top: 5px; +} + +table.fieldtable { + /*width: 100%;*/ + margin-bottom: 10px; + border: 1px solid #A7B8DA; + border-spacing: 0px; + -moz-border-radius: 4px; + -webkit-border-radius: 4px; + border-radius: 4px; + -moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px; + -webkit-box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); + box-shadow: 2px 2px 2px rgba(0, 0, 0, 0.15); +} + +.fieldtable td, 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solid #A7B8DA; +} + + +.tabsearch { + top: 0px; + left: 10px; + height: 36px; + background-image: url('tab_b.png'); + z-index: 101; + overflow: hidden; + font-size: 13px; +} + +.navpath ul +{ + font-size: 11px; + background-image:url('tab_b.png'); + background-repeat:repeat-x; + background-position: 0 -5px; + height:30px; + line-height:30px; + color:#889FCE; + border:solid 1px #C1CDE5; + overflow:hidden; + margin:0px; + padding:0px; +} + +.navpath li +{ + list-style-type:none; + float:left; + padding-left:10px; + padding-right:15px; + background-image:url('bc_s.png'); + background-repeat:no-repeat; + background-position:right; + color:#344D7E; +} + +.navpath li.navelem a +{ + height:32px; + display:block; + text-decoration: none; + outline: none; + color: #27395E; + font-family: 'Lucida Grande',Geneva,Helvetica,Arial,sans-serif; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; +} + +.navpath li.navelem a:hover +{ + color:#6583BF; +} + +.navpath li.footer +{ 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border-left-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +#powerTip.w:after, #powerTip.w:before { + right: 100%; +} +#powerTip.w:after { + border-right-color: #ffffff; + border-width: 10px; + top: 50%; + margin-top: -10px; +} +#powerTip.w:before { + border-right-color: #808080; + border-width: 11px; + top: 50%; + margin-top: -11px; +} + +@media print +{ + #top { display: none; } + #side-nav { display: none; } + #nav-path { display: none; } + body { overflow:visible; } + h1, h2, h3, h4, h5, h6 { page-break-after: avoid; } + .summary { display: none; } + .memitem { page-break-inside: avoid; } + #doc-content + { + margin-left:0 !important; + height:auto !important; + width:auto !important; + overflow:inherit; + display:inline; + } +} + diff --git a/docs/Core/html/doxygen.png b/docs/Core/html/doxygen.png Binary files differnew file mode 100644 index 0000000..7765a33 --- /dev/null +++ b/docs/Core/html/doxygen.png diff --git a/docs/Core/html/dynsections.js b/docs/Core/html/dynsections.js new file mode 100644 index 0000000..ed092c7 --- /dev/null +++ b/docs/Core/html/dynsections.js @@ -0,0 +1,97 @@ +function toggleVisibility(linkObj) +{ + var base = $(linkObj).attr('id'); + var summary = $('#'+base+'-summary'); + var content = $('#'+base+'-content'); + var trigger = $('#'+base+'-trigger'); + var src=$(trigger).attr('src'); + if (content.is(':visible')===true) { + content.hide(); + summary.show(); + $(linkObj).addClass('closed').removeClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + content.show(); + summary.hide(); + $(linkObj).removeClass('closed').addClass('opened'); + $(trigger).attr('src',src.substring(0,src.length-10)+'open.png'); + } + return false; +} + +function updateStripes() +{ + $('table.directory tr'). + removeClass('even').filter(':visible:even').addClass('even'); +} +function toggleLevel(level) +{ + $('table.directory tr').each(function(){ + var l = this.id.split('_').length-1; + var i = $('#img'+this.id.substring(3)); + var a = $('#arr'+this.id.substring(3)); + if (l<level+1) { + i.attr('src','ftv2folderopen.png'); + a.attr('src','ftv2mnode.png'); + $(this).show(); + } else if (l==level+1) { + i.attr('src','ftv2folderclosed.png'); + a.attr('src','ftv2pnode.png'); + $(this).show(); + } else { + $(this).hide(); + } + }); + updateStripes(); +} + +function toggleFolder(id) +{ + //The clicked row + var currentRow = $('#row_'+id); + var currentRowImages = currentRow.find("img"); + + //All rows after the clicked row + var rows = currentRow.nextAll("tr"); + + //Only match elements AFTER this one (can't hide elements before) + var childRows = rows.filter(function() { + var re = new RegExp('^row_'+id+'\\d+_$', "i"); //only one sub + return this.id.match(re); + }); + + //First row is visible we are HIDING + if (childRows.filter(':first').is(':visible')===true) { + currentRowImages.filter("[id^=arr]").attr('src', 'ftv2pnode.png'); + currentRowImages.filter("[id^=img]").attr('src', 'ftv2folderclosed.png'); + rows.filter("[id^=row_"+id+"]").hide(); + } else { //We are SHOWING + //All sub images + var childImages = childRows.find("img"); + var childImg = childImages.filter("[id^=img]"); + var childArr = childImages.filter("[id^=arr]"); + + currentRow.find("[id^=arr]").attr('src', 'ftv2mnode.png'); //open row + currentRow.find("[id^=img]").attr('src', 'ftv2folderopen.png'); //open row + childImg.attr('src','ftv2folderclosed.png'); //children closed + childArr.attr('src','ftv2pnode.png'); //children closed + childRows.show(); //show all children + } + updateStripes(); +} + + +function toggleInherit(id) +{ + var rows = $('tr.inherit.'+id); + var img = $('tr.inherit_header.'+id+' img'); + var src = $(img).attr('src'); + if (rows.filter(':first').is(':visible')===true) { + rows.css('display','none'); + $(img).attr('src',src.substring(0,src.length-8)+'closed.png'); + } else { + rows.css('display','table-row'); // using show() causes jump in firefox + $(img).attr('src',src.substring(0,src.length-10)+'open.png'); + } +} + diff --git a/docs/Core/html/ftv2blank.png b/docs/Core/html/ftv2blank.png Binary files differnew file mode 100644 index 0000000..63c605b --- /dev/null +++ b/docs/Core/html/ftv2blank.png diff --git a/docs/Core/html/ftv2cl.png b/docs/Core/html/ftv2cl.png Binary files differnew file mode 100644 index 0000000..edd2ddc --- /dev/null +++ b/docs/Core/html/ftv2cl.png diff --git a/docs/Core/html/ftv2doc.png b/docs/Core/html/ftv2doc.png Binary files differnew file mode 100644 index 0000000..57fab09 --- /dev/null +++ b/docs/Core/html/ftv2doc.png diff --git a/docs/Core/html/ftv2folderclosed.png b/docs/Core/html/ftv2folderclosed.png Binary files differnew file mode 100644 index 0000000..23db980 --- /dev/null +++ b/docs/Core/html/ftv2folderclosed.png diff --git a/docs/Core/html/ftv2folderopen.png b/docs/Core/html/ftv2folderopen.png Binary files differnew file mode 100644 index 0000000..e9bd9eb --- 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b/docs/Core/html/ftv2vertline.png Binary files differnew file mode 100644 index 0000000..63c605b --- /dev/null +++ b/docs/Core/html/ftv2vertline.png diff --git a/docs/Core/html/functions.html b/docs/Core/html/functions.html new file mode 100644 index 0000000..e217893 --- /dev/null +++ b/docs/Core/html/functions.html @@ -0,0 +1,680 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Data Fields</title> +<title>CMSIS-Core (Cortex-M): Data Fields</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow2" class="tabs2"> + <ul class="tablist"> + <li><a href="annotated.html"><span>Data Structures</span></a></li> + <li class="current"><a href="functions.html"><span>Data Fields</span></a></li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="functions.html"><span>All</span></a></li> + <li><a href="functions_vars.html"><span>Variables</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li><a href="#index__"><span>_</span></a></li> + <li><a href="#index_a"><span>a</span></a></li> + <li><a href="#index_b"><span>b</span></a></li> + <li><a href="#index_c"><span>c</span></a></li> + <li><a href="#index_d"><span>d</span></a></li> + <li><a href="#index_e"><span>e</span></a></li> + <li><a href="#index_f"><span>f</span></a></li> + <li><a href="#index_h"><span>h</span></a></li> + <li><a href="#index_i"><span>i</span></a></li> + <li><a href="#index_l"><span>l</span></a></li> + <li><a href="#index_m"><span>m</span></a></li> + <li><a href="#index_n"><span>n</span></a></li> + <li><a href="#index_p"><span>p</span></a></li> + <li><a href="#index_q"><span>q</span></a></li> + <li><a href="#index_r"><span>r</span></a></li> + <li><a href="#index_s"><span>s</span></a></li> + <li><a href="#index_t"><span>t</span></a></li> + <li><a href="#index_u"><span>u</span></a></li> + <li><a href="#index_v"><span>v</span></a></li> + <li><a href="#index_w"><span>w</span></a></li> + <li class="current"><a href="#index_z"><span>z</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('functions.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div> + +<h3><a class="anchor" id="index__"></a>- _ -</h3><ul> +<li>_reserved0 +: <a class="el" href="unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_a"></a>- a -</h3><ul> +<li>ACPR +: <a class="el" href="structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">TPI_Type</a> +</li> +<li>ACTLR +: <a class="el" href="structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23">SCnSCB_Type</a> +</li> +<li>ADR +: <a class="el" href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">SCB_Type</a> +</li> +<li>AFSR +: <a class="el" href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">SCB_Type</a> +</li> +<li>AIRCR +: <a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_b"></a>- b -</h3><ul> +<li>b +: <a class="el" href="unionAPSR__Type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a> +</li> +<li>BFAR +: <a class="el" href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_c"></a>- c -</h3><ul> +<li>C +: <a class="el" href="unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a> +</li> +<li>CALIB +: <a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a> +</li> +<li>CCR +: <a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a> +</li> +<li>CFSR +: <a class="el" href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">SCB_Type</a> +</li> +<li>CID0 +: <a class="el" href="structITM__Type.html#a30bb2b166b1723867da4a708935677ba">ITM_Type</a> +</li> +<li>CID1 +: <a class="el" href="structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f">ITM_Type</a> +</li> +<li>CID2 +: <a class="el" href="structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d">ITM_Type</a> +</li> +<li>CID3 +: <a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">ITM_Type</a> +</li> +<li>CLAIMCLR +: <a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a> +</li> +<li>CLAIMSET +: <a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a> +</li> +<li>COMP0 +: <a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a> +</li> +<li>COMP1 +: <a class="el" href="structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type</a> +</li> +<li>COMP2 +: <a class="el" href="structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46">DWT_Type</a> +</li> +<li>COMP3 +: <a class="el" href="structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847">DWT_Type</a> +</li> +<li>CPACR +: <a class="el" href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">SCB_Type</a> +</li> +<li>CPICNT +: <a class="el" href="structDWT__Type.html#a2c08096c82abe245c0fa97badc458154">DWT_Type</a> +</li> +<li>CPUID +: <a class="el" href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">SCB_Type</a> +</li> +<li>CSPSR +: <a class="el" href="structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f">TPI_Type</a> +</li> +<li>CTRL +: <a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a> +, <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU_Type</a> +, <a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a> +</li> +<li>CYCCNT +: <a class="el" href="structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_d"></a>- d -</h3><ul> +<li>DCRDR +: <a class="el" href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">CoreDebug_Type</a> +</li> +<li>DCRSR +: <a class="el" href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">CoreDebug_Type</a> +</li> +<li>DEMCR +: <a class="el" href="structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee">CoreDebug_Type</a> +</li> +<li>DEVARCH +: <a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">ITM_Type</a> +</li> +<li>DEVID +: <a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a> +</li> +<li>DEVTYPE +: <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a> +</li> +<li>DFR +: <a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a> +</li> +<li>DFSR +: <a class="el" href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">SCB_Type</a> +</li> +<li>DHCSR +: <a class="el" href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">CoreDebug_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_e"></a>- e -</h3><ul> +<li>EXCCNT +: <a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_f"></a>- f -</h3><ul> +<li>FFCR +: <a class="el" href="structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2">TPI_Type</a> +</li> +<li>FFSR +: <a class="el" href="structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c">TPI_Type</a> +</li> +<li>FIFO0 +: <a class="el" href="structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">TPI_Type</a> +</li> +<li>FIFO1 +: <a class="el" href="structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc">TPI_Type</a> +</li> +<li>FOLDCNT +: <a class="el" href="structDWT__Type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">DWT_Type</a> +</li> +<li>FPCA +: <a class="el" href="unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type</a> +</li> +<li>FPCAR +: <a class="el" href="structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820">FPU_Type</a> +</li> +<li>FPCCR +: <a class="el" href="structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061">FPU_Type</a> +</li> +<li>FPDSCR +: <a class="el" href="structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a">FPU_Type</a> +</li> +<li>FSCR +: <a class="el" href="structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8">TPI_Type</a> +</li> +<li>FUNCTION0 +: <a class="el" href="structDWT__Type.html#a579ae082f58a0317b7ef029b20f52889">DWT_Type</a> +</li> +<li>FUNCTION1 +: <a class="el" href="structDWT__Type.html#a8dfcf25675f9606aa305c46e85182e4e">DWT_Type</a> +</li> +<li>FUNCTION2 +: <a class="el" href="structDWT__Type.html#ab1b60d6600c38abae515bab8e86a188f">DWT_Type</a> +</li> +<li>FUNCTION3 +: <a class="el" href="structDWT__Type.html#a52d4ff278fae6f9216c63b74ce328841">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_h"></a>- h -</h3><ul> +<li>HFSR +: <a class="el" href="structSCB__Type.html#a14ad254659362b9752c69afe3fd80934">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_i"></a>- i -</h3><ul> +<li>IABR +: <a class="el" href="structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af">NVIC_Type</a> +</li> +<li>ICER +: <a class="el" href="structNVIC__Type.html#a245df8bac1da05c39eadabede9323203">NVIC_Type</a> +</li> +<li>ICPR +: <a class="el" href="structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95">NVIC_Type</a> +</li> +<li>ICSR +: <a class="el" href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">SCB_Type</a> +</li> +<li>ICTR +: <a class="el" href="structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762">SCnSCB_Type</a> +</li> +<li>IMCR +: <a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">ITM_Type</a> +</li> +<li>IP +: <a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a> +</li> +<li>IRR +: <a class="el" href="structITM__Type.html#a66eb82a070953f09909f39b8e516fb91">ITM_Type</a> +</li> +<li>ISAR +: <a class="el" href="structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066">SCB_Type</a> +</li> +<li>ISER +: <a class="el" href="structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47">NVIC_Type</a> +</li> +<li>ISPR +: <a class="el" href="structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0">NVIC_Type</a> +</li> +<li>ISR +: <a class="el" href="unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a> +</li> +<li>IT +: <a class="el" href="unionxPSR__Type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a> +</li> +<li>ITATBCTR0 +: <a class="el" href="structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0">TPI_Type</a> +</li> +<li>ITATBCTR2 +: <a class="el" href="structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652">TPI_Type</a> +</li> +<li>ITCTRL +: <a class="el" href="structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d">TPI_Type</a> +</li> +<li>IWR +: <a class="el" href="structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94">ITM_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_l"></a>- l -</h3><ul> +<li>LAR +: <a class="el" href="structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5">ITM_Type</a> +</li> +<li>LOAD +: <a class="el" href="structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd">SysTick_Type</a> +</li> +<li>LSR +: <a class="el" href="structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8">ITM_Type</a> +</li> +<li>LSUCNT +: <a class="el" href="structDWT__Type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_m"></a>- m -</h3><ul> +<li>MASK0 +: <a class="el" href="structDWT__Type.html#a821eb5e71f340ec077efc064cfc567db">DWT_Type</a> +</li> +<li>MASK1 +: <a class="el" href="structDWT__Type.html#aabf94936c9340e62fed836dcfb152405">DWT_Type</a> +</li> +<li>MASK2 +: <a class="el" href="structDWT__Type.html#a00ac4d830dfe0070a656cda9baed170f">DWT_Type</a> +</li> +<li>MASK3 +: <a class="el" href="structDWT__Type.html#a2a509d8505c37a3b64f6b24993df5f3f">DWT_Type</a> +</li> +<li>MMFAR +: <a class="el" href="structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80">SCB_Type</a> +</li> +<li>MMFR +: <a class="el" href="structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c">SCB_Type</a> +</li> +<li>MVFR0 +: <a class="el" href="structFPU__Type.html#a4f19014defe6033d070b80af19ef627c">FPU_Type</a> +</li> +<li>MVFR1 +: <a class="el" href="structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d">FPU_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_n"></a>- n -</h3><ul> +<li>N +: <a class="el" href="unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a> +</li> +<li>nPRIV +: <a class="el" href="unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_p"></a>- p -</h3><ul> +<li>PCSR +: <a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a> +</li> +<li>PFR +: <a class="el" href="structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d">SCB_Type</a> +</li> +<li>PID0 +: <a class="el" href="structITM__Type.html#ab4a4cc97ad658e9c46cf17490daffb8a">ITM_Type</a> +</li> +<li>PID1 +: <a class="el" href="structITM__Type.html#a89ea1d805a668d6589b22d8e678eb6a4">ITM_Type</a> +</li> +<li>PID2 +: <a class="el" href="structITM__Type.html#a8471c4d77b7107cf580587509da69f38">ITM_Type</a> +</li> +<li>PID3 +: <a class="el" href="structITM__Type.html#af317d5e2d946d70e6fb67c02b92cc8a3">ITM_Type</a> +</li> +<li>PID4 +: <a class="el" href="structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158">ITM_Type</a> +</li> +<li>PID5 +: <a class="el" href="structITM__Type.html#af9085648bf18f69b5f9d1136d45e1d37">ITM_Type</a> +</li> +<li>PID6 +: <a class="el" href="structITM__Type.html#ad34dbe6b1072c77d36281049c8b169f6">ITM_Type</a> +</li> +<li>PID7 +: <a class="el" href="structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d">ITM_Type</a> +</li> +<li>PORT +: <a class="el" href="structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e">ITM_Type</a> +</li> +</ul> + + +<h3><a class="anchor" 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href="structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2">ITM_Type</a> +</li> +<li>TRIGGER +: <a class="el" href="structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd">TPI_Type</a> +</li> +<li>TYPE +: <a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">MPU_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_u"></a>- u -</h3><ul> +<li>u16 +: <a class="el" href="structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3">ITM_Type</a> +</li> +<li>u32 +: <a class="el" href="structITM__Type.html#a5834885903a557674f078f3b71fa8bc8">ITM_Type</a> +</li> +<li>u8 +: <a class="el" href="structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275">ITM_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_v"></a>- v -</h3><ul> +<li>V +: <a class="el" href="unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a> +</li> +<li>VAL +: <a class="el" href="structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93">SysTick_Type</a> +</li> +<li>VTOR +: <a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_w"></a>- w -</h3><ul> +<li>w +: <a class="el" href="unionAPSR__Type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_z"></a>- z -</h3><ul> +<li>Z +: <a class="el" href="unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/functions_vars.html b/docs/Core/html/functions_vars.html new file mode 100644 index 0000000..a5f74d8 --- /dev/null +++ b/docs/Core/html/functions_vars.html @@ -0,0 +1,680 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Data Fields - Variables</title> +<title>CMSIS-Core (Cortex-M): Data Fields - Variables</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" 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id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return 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href="#index__"><span>_</span></a></li> + <li><a href="#index_a"><span>a</span></a></li> + <li><a href="#index_b"><span>b</span></a></li> + <li><a href="#index_c"><span>c</span></a></li> + <li><a href="#index_d"><span>d</span></a></li> + <li><a href="#index_e"><span>e</span></a></li> + <li><a href="#index_f"><span>f</span></a></li> + <li><a href="#index_h"><span>h</span></a></li> + <li><a href="#index_i"><span>i</span></a></li> + <li><a href="#index_l"><span>l</span></a></li> + <li><a href="#index_m"><span>m</span></a></li> + <li><a href="#index_n"><span>n</span></a></li> + <li><a href="#index_p"><span>p</span></a></li> + <li><a href="#index_q"><span>q</span></a></li> + <li><a href="#index_r"><span>r</span></a></li> + <li><a href="#index_s"><span>s</span></a></li> + <li><a href="#index_t"><span>t</span></a></li> + <li><a href="#index_u"><span>u</span></a></li> + <li><a href="#index_v"><span>v</span></a></li> + <li><a href="#index_w"><span>w</span></a></li> + <li class="current"><a href="#index_z"><span>z</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('functions_vars.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a 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id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +  + +<h3><a class="anchor" id="index__"></a>- _ -</h3><ul> +<li>_reserved0 +: <a class="el" href="unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_a"></a>- a -</h3><ul> +<li>ACPR +: <a class="el" href="structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">TPI_Type</a> +</li> +<li>ACTLR +: <a class="el" href="structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23">SCnSCB_Type</a> +</li> +<li>ADR +: <a class="el" href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">SCB_Type</a> +</li> +<li>AFSR +: <a class="el" href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">SCB_Type</a> +</li> +<li>AIRCR +: <a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_b"></a>- b -</h3><ul> +<li>b +: <a class="el" href="unionAPSR__Type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a> +</li> +<li>BFAR +: <a class="el" href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_c"></a>- c -</h3><ul> +<li>C +: <a class="el" href="unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a> +</li> +<li>CALIB +: <a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a> +</li> +<li>CCR +: <a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a> +</li> +<li>CFSR +: <a class="el" href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">SCB_Type</a> +</li> +<li>CID0 +: <a class="el" href="structITM__Type.html#a30bb2b166b1723867da4a708935677ba">ITM_Type</a> +</li> +<li>CID1 +: <a class="el" href="structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f">ITM_Type</a> +</li> +<li>CID2 +: <a class="el" href="structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d">ITM_Type</a> +</li> +<li>CID3 +: <a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">ITM_Type</a> +</li> +<li>CLAIMCLR +: <a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a> +</li> +<li>CLAIMSET +: <a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a> +</li> +<li>COMP0 +: <a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a> +</li> +<li>COMP1 +: <a class="el" href="structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type</a> +</li> +<li>COMP2 +: <a class="el" href="structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46">DWT_Type</a> +</li> +<li>COMP3 +: <a class="el" href="structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847">DWT_Type</a> +</li> +<li>CPACR +: <a class="el" href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">SCB_Type</a> +</li> +<li>CPICNT +: <a class="el" href="structDWT__Type.html#a2c08096c82abe245c0fa97badc458154">DWT_Type</a> +</li> +<li>CPUID +: <a class="el" href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">SCB_Type</a> +</li> +<li>CSPSR +: <a class="el" href="structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f">TPI_Type</a> +</li> +<li>CTRL +: <a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a> +, <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU_Type</a> +, <a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a> +</li> +<li>CYCCNT +: <a class="el" href="structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_d"></a>- d -</h3><ul> +<li>DCRDR +: <a class="el" href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">CoreDebug_Type</a> +</li> +<li>DCRSR +: <a class="el" href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">CoreDebug_Type</a> +</li> +<li>DEMCR +: <a class="el" href="structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee">CoreDebug_Type</a> +</li> +<li>DEVARCH +: <a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">ITM_Type</a> +</li> +<li>DEVID +: <a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a> +</li> +<li>DEVTYPE +: <a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a> +</li> +<li>DFR +: <a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a> +</li> +<li>DFSR +: <a class="el" href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">SCB_Type</a> +</li> +<li>DHCSR +: <a class="el" href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">CoreDebug_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_e"></a>- e -</h3><ul> +<li>EXCCNT +: <a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_f"></a>- f -</h3><ul> +<li>FFCR +: <a class="el" href="structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2">TPI_Type</a> +</li> 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href="structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95">NVIC_Type</a> +</li> +<li>ICSR +: <a class="el" href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">SCB_Type</a> +</li> +<li>ICTR +: <a class="el" href="structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762">SCnSCB_Type</a> +</li> +<li>IMCR +: <a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">ITM_Type</a> +</li> +<li>IP +: <a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a> +</li> +<li>IRR +: <a class="el" href="structITM__Type.html#a66eb82a070953f09909f39b8e516fb91">ITM_Type</a> +</li> +<li>ISAR +: <a class="el" href="structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066">SCB_Type</a> +</li> +<li>ISER +: <a class="el" href="structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47">NVIC_Type</a> +</li> +<li>ISPR +: <a class="el" href="structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0">NVIC_Type</a> +</li> +<li>ISR +: <a class="el" href="unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a> +</li> +<li>IT +: <a class="el" href="unionxPSR__Type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a> +</li> +<li>ITATBCTR0 +: <a class="el" href="structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0">TPI_Type</a> +</li> +<li>ITATBCTR2 +: <a class="el" href="structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652">TPI_Type</a> +</li> +<li>ITCTRL +: <a class="el" href="structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d">TPI_Type</a> +</li> +<li>IWR +: <a class="el" href="structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94">ITM_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_l"></a>- l -</h3><ul> +<li>LAR +: <a class="el" href="structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5">ITM_Type</a> +</li> +<li>LOAD +: <a class="el" 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href="structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c">SCB_Type</a> +</li> +<li>MVFR0 +: <a class="el" href="structFPU__Type.html#a4f19014defe6033d070b80af19ef627c">FPU_Type</a> +</li> +<li>MVFR1 +: <a class="el" href="structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d">FPU_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_n"></a>- n -</h3><ul> +<li>N +: <a class="el" href="unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a> +</li> +<li>nPRIV +: <a class="el" href="unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_p"></a>- p -</h3><ul> +<li>PCSR +: <a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a> +</li> +<li>PFR +: <a class="el" href="structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d">SCB_Type</a> +</li> +<li>PID0 +: <a class="el" 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href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type</a> +</li> +<li>RBAR_A1 +: <a class="el" href="structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066">MPU_Type</a> +</li> +<li>RBAR_A2 +: <a class="el" href="structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2">MPU_Type</a> +</li> +<li>RBAR_A3 +: <a class="el" href="structMPU__Type.html#a207f6e9c3af753367554cc06df300a55">MPU_Type</a> +</li> +<li>RESERVED0 +: <a class="el" href="structDWT__Type.html#addd893d655ed90d40705b20170daac59">DWT_Type</a> +, <a class="el" href="structFPU__Type.html#a7b2967b069046c8544adbbc1db143a36">FPU_Type</a> +, <a class="el" href="structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80">NVIC_Type</a> +, <a class="el" href="structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type</a> +, <a class="el" href="structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type</a> +, <a class="el" href="structTPI__Type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">TPI_Type</a> +</li> +<li>RESERVED1 +: <a class="el" href="structDWT__Type.html#a069871233a8c1df03521e6d7094f1de4">DWT_Type</a> +, <a class="el" href="structTPI__Type.html#ac3956fe93987b725d89d3be32738da12">TPI_Type</a> +</li> +<li>RESERVED2 +: <a class="el" href="structDWT__Type.html#a8556ca1c32590517602d92fe0cd55738">DWT_Type</a> +, <a class="el" href="structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72">NVIC_Type</a> +, <a class="el" href="structTPI__Type.html#ac7bbb92e6231b9b38ac483f7d161a096">TPI_Type</a> +</li> +<li>RESERVED3 +: <a class="el" href="structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab">NVIC_Type</a> +, <a class="el" href="structTPI__Type.html#a31700c8cdd26e4c094db72af33d9f24c">TPI_Type</a> +</li> +<li>RESERVED4 +: <a class="el" href="structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">NVIC_Type</a> +, <a class="el" href="structTPI__Type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type</a> +</li> +<li>RESERVED5 +: <a class="el" href="structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type</a> +, <a class="el" href="structTPI__Type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type</a> +</li> +<li>RESERVED7 +: <a class="el" href="structTPI__Type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type</a> +</li> +<li>RNR +: <a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">MPU_Type</a> +</li> +<li>RSERVED1 +: <a class="el" href="structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_s"></a>- s -</h3><ul> +<li>SCR +: <a class="el" href="structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCB_Type</a> +</li> +<li>SHCSR +: <a class="el" href="structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4">SCB_Type</a> +</li> +<li>SHP +: <a class="el" href="structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162">SCB_Type</a> +</li> +<li>SLEEPCNT +: <a class="el" href="structDWT__Type.html#a416a54e2084ce66e5ca74f152a5ecc70">DWT_Type</a> +</li> +<li>SPPR +: <a class="el" href="structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5">TPI_Type</a> +</li> +<li>SPSEL +: <a class="el" href="unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a> +</li> +<li>SSPSR +: <a class="el" href="structTPI__Type.html#a7b72598e20066133e505bb781690dc22">TPI_Type</a> +</li> +<li>STIR +: <a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">NVIC_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_t"></a>- t -</h3><ul> +<li>T +: <a class="el" href="unionxPSR__Type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type</a> +</li> +<li>TCR +: <a class="el" href="structITM__Type.html#a04b9fbc83759cb818dfa161d39628426">ITM_Type</a> +</li> +<li>TER +: <a class="el" href="structITM__Type.html#acd03c6858f7b678dab6a6121462e7807">ITM_Type</a> +</li> +<li>TPR +: <a class="el" href="structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2">ITM_Type</a> +</li> +<li>TRIGGER +: <a class="el" href="structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd">TPI_Type</a> +</li> +<li>TYPE +: <a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">MPU_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_u"></a>- u -</h3><ul> +<li>u16 +: <a class="el" href="structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3">ITM_Type</a> +</li> +<li>u32 +: <a class="el" href="structITM__Type.html#a5834885903a557674f078f3b71fa8bc8">ITM_Type</a> +</li> +<li>u8 +: <a class="el" href="structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275">ITM_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_v"></a>- v -</h3><ul> +<li>V +: <a class="el" href="unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a> +</li> +<li>VAL +: <a class="el" href="structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93">SysTick_Type</a> +</li> +<li>VTOR +: <a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">SCB_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_w"></a>- w -</h3><ul> +<li>w +: <a class="el" href="unionAPSR__Type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a> +, <a class="el" href="unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a> +, <a class="el" href="unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a> +</li> +</ul> + + +<h3><a class="anchor" id="index_z"></a>- z -</h3><ul> +<li>Z +: <a class="el" href="unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a> +, <a class="el" href="unionxPSR__Type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/globals.html b/docs/Core/html/globals.html new file mode 100644 index 0000000..c6085ac --- /dev/null +++ b/docs/Core/html/globals.html @@ -0,0 +1,687 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Globals</title> +<title>CMSIS-Core (Cortex-M): Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="globals.html"><span>All</span></a></li> + <li><a href="globals_func.html"><span>Functions</span></a></li> + <li><a href="globals_vars.html"><span>Variables</span></a></li> + <li><a href="globals_enum.html"><span>Enumerations</span></a></li> + <li><a href="globals_eval.html"><span>Enumerator</span></a></li> + <li><a href="globals_defs.html"><span>Macros</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li class="current"><a href="globals.html#index__"><span>_</span></a></li> + <li><a href="globals_a.html#index_a"><span>a</span></a></li> + <li><a href="globals_b.html#index_b"><span>b</span></a></li> + <li><a href="globals_c.html#index_c"><span>c</span></a></li> + <li><a href="globals_d.html#index_d"><span>d</span></a></li> + <li><a href="globals_h.html#index_h"><span>h</span></a></li> + <li><a href="globals_i.html#index_i"><span>i</span></a></li> + <li><a href="globals_m.html#index_m"><span>m</span></a></li> + <li><a href="globals_n.html#index_n"><span>n</span></a></li> + <li><a href="globals_p.html#index_p"><span>p</span></a></li> + <li><a href="globals_s.html#index_s"><span>s</span></a></li> + <li><a href="globals_t.html#index_t"><span>t</span></a></li> + <li><a href="globals_u.html#index_u"><span>u</span></a></li> + <li><a href="globals_w.html#index_w"><span>w</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('globals.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index__"></a>- _ -</h3><ul> +<li>__ALIGNED +: <a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">Ref_CompilerControl.txt</a> +</li> +<li>__ARM_ARCH_6M__ +: <a class="el" href="group__compiler__conntrol__gr.html#ga8be4ebde5d4dd91b161d206545ce59aa">Ref_CompilerControl.txt</a> +</li> +<li>__ARM_ARCH_7EM__ +: <a class="el" href="group__compiler__conntrol__gr.html#ga43ab3e79ec5ecb615f1f2f6e83e7d48a">Ref_CompilerControl.txt</a> +</li> +<li>__ARM_ARCH_7M__ +: <a class="el" href="group__compiler__conntrol__gr.html#ga43e1af8bedda108dfc4f8584e6b278a2">Ref_CompilerControl.txt</a> +</li> +<li>__ARM_ARCH_8M_BASE__ +: <a class="el" href="group__compiler__conntrol__gr.html#gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a">Ref_CompilerControl.txt</a> +</li> +<li>__ARM_ARCH_8M_MAIN__ +: <a class="el" href="group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd">Ref_CompilerControl.txt</a> +</li> +<li>__ASM +: <a class="el" href="group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">Ref_CompilerControl.txt</a> +</li> +<li>__BKPT() +: <a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">Ref_cmInstr.txt</a> +</li> +<li>__CLREX() +: <a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">Ref_cmInstr.txt</a> +</li> +<li>__CLZ() +: <a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a> +</li> +<li>__CM_CMSIS_VERSION +: <a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">Ref_VersionControl.txt</a> +</li> +<li>__CM_CMSIS_VERSION_MAIN +: <a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">Ref_VersionControl.txt</a> +</li> +<li>__CM_CMSIS_VERSION_SUB +: <a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">Ref_VersionControl.txt</a> +</li> +<li>__CORTEX_M +: <a class="el" href="group__version__control__gr.html#ga63ea62503c88acab19fcf3d5743009e3">Ref_VersionControl.txt</a> +</li> +<li>__CORTEX_SC +: <a class="el" href="group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">Ref_VersionControl.txt</a> +</li> +<li>__disable_fault_irq() +: <a class="el" href="group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a> +</li> +<li>__disable_irq() +: <a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">Ref_CoreReg.txt</a> +</li> +<li>__DMB() +: <a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">Ref_cmInstr.txt</a> +</li> +<li>__DSB() +: <a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a> +</li> +<li>__enable_fault_irq() +: <a class="el" href="group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a> +</li> +<li>__enable_irq() +: <a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a> +</li> +<li>__get_APSR() +: <a class="el" href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a> +</li> +<li>__get_BASEPRI() +: <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667">Ref_CoreReg.txt</a> +</li> +<li>__get_CONTROL() +: <a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7">Ref_CoreReg.txt</a> +</li> +<li>__get_FAULTMASK() +: <a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">Ref_CoreReg.txt</a> +</li> +<li>__get_FPSCR() +: <a class="el" href="group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">Ref_CoreReg.txt</a> +</li> +<li>__get_IPSR() +: <a class="el" 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for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/globals_a.html b/docs/Core/html/globals_a.html new file mode 100644 index 0000000..16c8841 --- /dev/null +++ b/docs/Core/html/globals_a.html @@ -0,0 +1,195 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Globals</title> +<title>CMSIS-Core (Cortex-M): Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="globals.html"><span>All</span></a></li> + <li><a href="globals_func.html"><span>Functions</span></a></li> + <li><a href="globals_vars.html"><span>Variables</span></a></li> + <li><a href="globals_enum.html"><span>Enumerations</span></a></li> + <li><a href="globals_eval.html"><span>Enumerator</span></a></li> + <li><a href="globals_defs.html"><span>Macros</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li><a href="globals.html#index__"><span>_</span></a></li> + <li class="current"><a href="globals_a.html#index_a"><span>a</span></a></li> + <li><a href="globals_b.html#index_b"><span>b</span></a></li> + <li><a href="globals_c.html#index_c"><span>c</span></a></li> + <li><a href="globals_d.html#index_d"><span>d</span></a></li> + <li><a href="globals_h.html#index_h"><span>h</span></a></li> + <li><a href="globals_i.html#index_i"><span>i</span></a></li> + <li><a href="globals_m.html#index_m"><span>m</span></a></li> + <li><a href="globals_n.html#index_n"><span>n</span></a></li> + <li><a href="globals_p.html#index_p"><span>p</span></a></li> + <li><a href="globals_s.html#index_s"><span>s</span></a></li> + <li><a href="globals_t.html#index_t"><span>t</span></a></li> + <li><a href="globals_u.html#index_u"><span>u</span></a></li> + <li><a href="globals_w.html#index_w"><span>w</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('globals_a.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_a"></a>- a -</h3><ul> +<li>ARM_MPU_ACCESS_xxx +: <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_AP_xxx +: <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_CACHEP_xxx +: <a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_ClrRegion() +: <a class="el" href="group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_Disable() +: <a class="el" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_Enable() +: <a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_Load() +: <a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_RASR +: <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_RASR_EX +: <a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_RBAR +: <a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_REGION_SIZE_xxx +: <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_SetRegion() +: <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">Ref_MPU.txt</a> +</li> +<li>ARM_MPU_SetRegionEx() +: <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">Ref_MPU.txt</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/globals_b.html b/docs/Core/html/globals_b.html new file mode 100644 index 0000000..8bce3b2 --- /dev/null +++ b/docs/Core/html/globals_b.html @@ -0,0 +1,159 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Globals</title> +<title>CMSIS-Core (Cortex-M): Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="globals.html"><span>All</span></a></li> + <li><a href="globals_func.html"><span>Functions</span></a></li> + <li><a href="globals_vars.html"><span>Variables</span></a></li> + <li><a href="globals_enum.html"><span>Enumerations</span></a></li> + <li><a href="globals_eval.html"><span>Enumerator</span></a></li> + <li><a href="globals_defs.html"><span>Macros</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li><a href="globals.html#index__"><span>_</span></a></li> + <li><a href="globals_a.html#index_a"><span>a</span></a></li> + <li><a href="globals_b.html#index_b"><span>b</span></a></li> + <li><a href="globals_c.html#index_c"><span>c</span></a></li> + <li><a href="globals_d.html#index_d"><span>d</span></a></li> + <li class="current"><a href="globals_h.html#index_h"><span>h</span></a></li> + <li><a href="globals_i.html#index_i"><span>i</span></a></li> + <li><a href="globals_m.html#index_m"><span>m</span></a></li> + <li><a href="globals_n.html#index_n"><span>n</span></a></li> + <li><a href="globals_p.html#index_p"><span>p</span></a></li> + <li><a href="globals_s.html#index_s"><span>s</span></a></li> + <li><a href="globals_t.html#index_t"><span>t</span></a></li> + <li><a href="globals_u.html#index_u"><span>u</span></a></li> + <li><a href="globals_w.html#index_w"><span>w</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('globals_h.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_h"></a>- h -</h3><ul> +<li>HardFault_IRQn +: <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">Ref_NVIC.txt</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/globals_i.html b/docs/Core/html/globals_i.html new file mode 100644 index 0000000..d4fa5e8 --- /dev/null +++ b/docs/Core/html/globals_i.html @@ -0,0 +1,171 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Globals</title> +<title>CMSIS-Core (Cortex-M): Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow3" class="tabs2"> + <ul class="tablist"> + <li class="current"><a href="globals.html"><span>All</span></a></li> + <li><a href="globals_func.html"><span>Functions</span></a></li> + <li><a href="globals_vars.html"><span>Variables</span></a></li> + <li><a href="globals_enum.html"><span>Enumerations</span></a></li> + <li><a href="globals_eval.html"><span>Enumerator</span></a></li> + <li><a href="globals_defs.html"><span>Macros</span></a></li> + </ul> + </div> + <div id="navrow4" class="tabs3"> + <ul class="tablist"> + <li><a href="globals.html#index__"><span>_</span></a></li> + <li><a href="globals_a.html#index_a"><span>a</span></a></li> + <li><a href="globals_b.html#index_b"><span>b</span></a></li> + <li><a href="globals_c.html#index_c"><span>c</span></a></li> + <li><a href="globals_d.html#index_d"><span>d</span></a></li> + <li><a href="globals_h.html#index_h"><span>h</span></a></li> + <li class="current"><a href="globals_i.html#index_i"><span>i</span></a></li> + <li><a href="globals_m.html#index_m"><span>m</span></a></li> + <li><a href="globals_n.html#index_n"><span>n</span></a></li> + <li><a href="globals_p.html#index_p"><span>p</span></a></li> + <li><a href="globals_s.html#index_s"><span>s</span></a></li> + <li><a href="globals_t.html#index_t"><span>t</span></a></li> + <li><a href="globals_u.html#index_u"><span>u</span></a></li> + <li><a href="globals_w.html#index_w"><span>w</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('globals_i.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_i"></a>- i -</h3><ul> +<li>IRQn_Type +: <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">Ref_NVIC.txt</a> +</li> +<li>ITM_CheckChar() +: <a class="el" href="group__ITM__Debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">Ref_Debug.txt</a> +</li> +<li>ITM_ReceiveChar() +: <a class="el" href="group__ITM__Debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">Ref_Debug.txt</a> +</li> +<li>ITM_RxBuffer +: <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">Ref_Debug.txt</a> +</li> +<li>ITM_SendChar() +: <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">Ref_Debug.txt</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/globals_m.html b/docs/Core/html/globals_m.html new file mode 100644 index 0000000..687ebbe --- /dev/null +++ b/docs/Core/html/globals_m.html @@ -0,0 +1,159 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Globals</title> +<title>CMSIS-Core (Cortex-M): Globals</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_n"></a>- n -</h3><ul> +<li>NonMaskableInt_IRQn +: <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">Ref_NVIC.txt</a> +</li> +<li>NVIC_ClearPendingIRQ() +: <a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">Ref_NVIC.txt</a> +</li> +<li>NVIC_ClearTargetState() +: <a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">Ref_NVIC.txt</a> +</li> +<li>NVIC_DecodePriority() +: <a class="el" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">Ref_NVIC.txt</a> +</li> +<li>NVIC_DisableIRQ() +: <a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">Ref_NVIC.txt</a> +</li> +<li>NVIC_EnableIRQ() +: <a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">Ref_NVIC.txt</a> +</li> +<li>NVIC_EncodePriority() +: <a class="el" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetActive() +: <a class="el" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetEnableIRQ() +: <a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPendingIRQ() +: <a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPriority() +: <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetPriorityGrouping() +: <a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetTargetState() +: <a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">Ref_NVIC.txt</a> +</li> +<li>NVIC_GetVector() +: <a class="el" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetPendingIRQ() +: <a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetPriority() +: <a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetPriorityGrouping() +: <a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetTargetState() +: <a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a">Ref_NVIC.txt</a> +</li> +<li>NVIC_SetVector() +: <a class="el" href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">Ref_NVIC.txt</a> +</li> +<li>NVIC_SystemReset() +: <a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">Ref_NVIC.txt</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. 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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="contents"> +<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div> + +<h3><a class="anchor" id="index_w"></a>- w -</h3><ul> +<li>WWDG_STM_IRQn +: <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">Ref_NVIC.txt</a> +</li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__Core__Register__gr.html b/docs/Core/html/group__Core__Register__gr.html new file mode 100644 index 0000000..cad2c5d --- /dev/null +++ b/docs/Core/html/group__Core__Register__gr.html @@ -0,0 +1,1286 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Core Register Access</title> +<title>CMSIS-Core (Cortex-M): Core Register Access</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> 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(Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return 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onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">Core Register Access</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions to access the Cortex-M core registers. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga963cf236b73219ce78e965deb01b81a7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a> (void)</td></tr> +<tr class="memdesc:ga963cf236b73219ce78e965deb01b81a7"><td class="mdescLeft"> </td><td class="mdescRight">Read the CONTROL register. <a href="#ga963cf236b73219ce78e965deb01b81a7">More...</a><br/></td></tr> +<tr class="separator:ga963cf236b73219ce78e965deb01b81a7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac64d37e7ff9de06437f9fb94bbab8b6c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a> (uint32_t control)</td></tr> +<tr class="memdesc:gac64d37e7ff9de06437f9fb94bbab8b6c"><td class="mdescLeft"> </td><td class="mdescRight">Set the CONTROL Register. <a href="#gac64d37e7ff9de06437f9fb94bbab8b6c">More...</a><br/></td></tr> +<tr class="separator:gac64d37e7ff9de06437f9fb94bbab8b6c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">__get_IPSR</a> (void)</td></tr> +<tr class="memdesc:ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"><td class="mdescLeft"> </td><td class="mdescRight">Read the IPSR register. <a href="#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">More...</a><br/></td></tr> +<tr class="separator:ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga811c0012221ee918a75111ca84c4d5e7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a> (void)</td></tr> +<tr class="memdesc:ga811c0012221ee918a75111ca84c4d5e7"><td class="mdescLeft"> </td><td class="mdescRight">Read the APSR register. <a href="#ga811c0012221ee918a75111ca84c4d5e7">More...</a><br/></td></tr> +<tr class="separator:ga811c0012221ee918a75111ca84c4d5e7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga732e08184154f44a617963cc65ff95bd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a> (void)</td></tr> +<tr class="memdesc:ga732e08184154f44a617963cc65ff95bd"><td class="mdescLeft"> </td><td class="mdescRight">Read the xPSR register. <a href="#ga732e08184154f44a617963cc65ff95bd">More...</a><br/></td></tr> +<tr class="separator:ga732e08184154f44a617963cc65ff95bd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga914dfa8eff7ca53380dd54cf1d8bebd9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a> (void)</td></tr> +<tr class="memdesc:ga914dfa8eff7ca53380dd54cf1d8bebd9"><td class="mdescLeft"> </td><td class="mdescRight">Read the PSP register. <a href="#ga914dfa8eff7ca53380dd54cf1d8bebd9">More...</a><br/></td></tr> +<tr class="separator:ga914dfa8eff7ca53380dd54cf1d8bebd9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga48e5853f417e17a8a65080f6a605b743"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a> (uint32_t topOfProcStack)</td></tr> +<tr class="memdesc:ga48e5853f417e17a8a65080f6a605b743"><td class="mdescLeft"> </td><td class="mdescRight">Set the PSP register. <a href="#ga48e5853f417e17a8a65080f6a605b743">More...</a><br/></td></tr> +<tr class="separator:ga48e5853f417e17a8a65080f6a605b743"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab898559392ba027814e5bbb5a98b38d2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a> (void)</td></tr> +<tr class="memdesc:gab898559392ba027814e5bbb5a98b38d2"><td class="mdescLeft"> </td><td class="mdescRight">Read the MSP register. <a href="#gab898559392ba027814e5bbb5a98b38d2">More...</a><br/></td></tr> +<tr class="separator:gab898559392ba027814e5bbb5a98b38d2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga0bf9564ebc1613a8faba014275dac2a4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a> (uint32_t topOfMainStack)</td></tr> +<tr class="memdesc:ga0bf9564ebc1613a8faba014275dac2a4"><td class="mdescLeft"> </td><td class="mdescRight">Set the MSP register. <a href="#ga0bf9564ebc1613a8faba014275dac2a4">More...</a><br/></td></tr> +<tr class="separator:ga0bf9564ebc1613a8faba014275dac2a4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga799b5d9a2ae75e459264c8512c7c0e02"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a> (void)</td></tr> +<tr class="memdesc:ga799b5d9a2ae75e459264c8512c7c0e02"><td class="mdescLeft"> </td><td class="mdescRight">Read the PRIMASK register bit. <a href="#ga799b5d9a2ae75e459264c8512c7c0e02">More...</a><br/></td></tr> +<tr class="separator:ga799b5d9a2ae75e459264c8512c7c0e02"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga70b4e1a6c1c86eb913fb9d6e8400156f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a> (uint32_t priMask)</td></tr> +<tr class="memdesc:ga70b4e1a6c1c86eb913fb9d6e8400156f"><td class="mdescLeft"> </td><td class="mdescRight">Set the Priority Mask bit. <a href="#ga70b4e1a6c1c86eb913fb9d6e8400156f">More...</a><br/></td></tr> +<tr class="separator:ga70b4e1a6c1c86eb913fb9d6e8400156f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga32da759f46e52c95bcfbde5012260667"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a> (void)</td></tr> +<tr class="memdesc:ga32da759f46e52c95bcfbde5012260667"><td class="mdescLeft"> </td><td class="mdescRight">Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga32da759f46e52c95bcfbde5012260667">More...</a><br/></td></tr> +<tr class="separator:ga32da759f46e52c95bcfbde5012260667"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga360c73eb7ffb16088556f9278953b882"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a> (uint32_t basePri)</td></tr> +<tr class="memdesc:ga360c73eb7ffb16088556f9278953b882"><td class="mdescLeft"> </td><td class="mdescRight">Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga360c73eb7ffb16088556f9278953b882">More...</a><br/></td></tr> +<tr class="separator:ga360c73eb7ffb16088556f9278953b882"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga62fa63d39cf22df348857d5f44ab64d9"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> (uint32_t basePri)</td></tr> +<tr class="memdesc:ga62fa63d39cf22df348857d5f44ab64d9"><td class="mdescLeft"> </td><td class="mdescRight">Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga62fa63d39cf22df348857d5f44ab64d9">More...</a><br/></td></tr> +<tr class="separator:ga62fa63d39cf22df348857d5f44ab64d9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa78e4e6bf619a65e9f01b4af13fed3a8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a> (void)</td></tr> +<tr class="memdesc:gaa78e4e6bf619a65e9f01b4af13fed3a8"><td class="mdescLeft"> </td><td class="mdescRight">Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gaa78e4e6bf619a65e9f01b4af13fed3a8">More...</a><br/></td></tr> +<tr class="separator:gaa78e4e6bf619a65e9f01b4af13fed3a8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa5587cc09031053a40a35c14ec36078a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a> (uint32_t faultMask)</td></tr> +<tr class="memdesc:gaa5587cc09031053a40a35c14ec36078a"><td class="mdescLeft"> </td><td class="mdescRight">Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gaa5587cc09031053a40a35c14ec36078a">More...</a><br/></td></tr> +<tr class="separator:gaa5587cc09031053a40a35c14ec36078a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad6d7eca9ddd1d9072dd7b020cfe64905"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">__get_FPSCR</a> (void)</td></tr> +<tr class="memdesc:gad6d7eca9ddd1d9072dd7b020cfe64905"><td class="mdescLeft"> </td><td class="mdescRight">Read the FPSCR register [only Cortex-M4 and Cortex-M7]. <a href="#gad6d7eca9ddd1d9072dd7b020cfe64905">More...</a><br/></td></tr> +<tr class="separator:gad6d7eca9ddd1d9072dd7b020cfe64905"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6f26bd75ca7e3247f27b272acc10536b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">__set_FPSCR</a> (uint32_t fpscr)</td></tr> +<tr class="memdesc:ga6f26bd75ca7e3247f27b272acc10536b"><td class="mdescLeft"> </td><td class="mdescRight">Set the FPSC register [only for Cortex-M4 and Cortex-M7]. <a href="#ga6f26bd75ca7e3247f27b272acc10536b">More...</a><br/></td></tr> +<tr class="separator:ga6f26bd75ca7e3247f27b272acc10536b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga0f98dfbd252b89d12564472dbeba9c27"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a> (void)</td></tr> +<tr class="memdesc:ga0f98dfbd252b89d12564472dbeba9c27"><td class="mdescLeft"> </td><td class="mdescRight">Globally enables interrupts and configurable fault handlers. <a href="#ga0f98dfbd252b89d12564472dbeba9c27">More...</a><br/></td></tr> +<tr class="separator:ga0f98dfbd252b89d12564472dbeba9c27"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaeb8e5f7564a8ea23678fe3c987b04013"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> (void)</td></tr> +<tr class="memdesc:gaeb8e5f7564a8ea23678fe3c987b04013"><td class="mdescLeft"> </td><td class="mdescRight">Globally disables interrupts and configurable fault handlers. <a href="#gaeb8e5f7564a8ea23678fe3c987b04013">More...</a><br/></td></tr> +<tr class="separator:gaeb8e5f7564a8ea23678fe3c987b04013"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6575d37863cec5d334864f93b5b783bf"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf">__enable_fault_irq</a> (void)</td></tr> +<tr class="memdesc:ga6575d37863cec5d334864f93b5b783bf"><td class="mdescLeft"> </td><td class="mdescRight">Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga6575d37863cec5d334864f93b5b783bf">More...</a><br/></td></tr> +<tr class="separator:ga6575d37863cec5d334864f93b5b783bf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9d174f979b2f76fdb3228a9b338fd939"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">__disable_fault_irq</a> (void)</td></tr> +<tr class="memdesc:ga9d174f979b2f76fdb3228a9b338fd939"><td class="mdescLeft"> </td><td class="mdescRight">Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga9d174f979b2f76fdb3228a9b338fd939">More...</a><br/></td></tr> +<tr class="separator:ga9d174f979b2f76fdb3228a9b338fd939"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga8b226929264e903c7019e326b42bef47"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga8b226929264e903c7019e326b42bef47">__get_PSPLIM</a> (void)</td></tr> +<tr class="memdesc:ga8b226929264e903c7019e326b42bef47"><td class="mdescLeft"> </td><td class="mdescRight">Get Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. <a href="#ga8b226929264e903c7019e326b42bef47">More...</a><br/></td></tr> +<tr class="separator:ga8b226929264e903c7019e326b42bef47"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4348d14fc5eefbfd34ab8c51be44a81b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga4348d14fc5eefbfd34ab8c51be44a81b">__set_PSPLIM</a> (uint32_t ProcStackPtrLimit)</td></tr> +<tr class="memdesc:ga4348d14fc5eefbfd34ab8c51be44a81b"><td class="mdescLeft"> </td><td class="mdescRight">Set Process Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. <a href="#ga4348d14fc5eefbfd34ab8c51be44a81b">More...</a><br/></td></tr> +<tr class="separator:ga4348d14fc5eefbfd34ab8c51be44a81b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf39856ca50fc88cf459031b44eb2521c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#gaf39856ca50fc88cf459031b44eb2521c">__get_MSPLIM</a> (void)</td></tr> +<tr class="memdesc:gaf39856ca50fc88cf459031b44eb2521c"><td class="mdescLeft"> </td><td class="mdescRight">Get Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. <a href="#gaf39856ca50fc88cf459031b44eb2521c">More...</a><br/></td></tr> +<tr class="separator:gaf39856ca50fc88cf459031b44eb2521c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6809a07c5cb7410e361f3fba57f72172"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Core__Register__gr.html#ga6809a07c5cb7410e361f3fba57f72172">__set_MSPLIM</a> (uint32_t MainStackPtrLimit)</td></tr> +<tr class="memdesc:ga6809a07c5cb7410e361f3fba57f72172"><td class="mdescLeft"> </td><td class="mdescRight">Set Main Stack Pointer Limit Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. <a href="#ga6809a07c5cb7410e361f3fba57f72172">More...</a><br/></td></tr> +<tr class="separator:ga6809a07c5cb7410e361f3fba57f72172"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following functions provide access to Cortex-M core registers. </p> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga9d174f979b2f76fdb3228a9b338fd939"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __disable_fault_irq </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function disables interrupts and all fault handlers by setting FAULTMASK. The function uses the instruction <b>CPSID f</b>.</p> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Can be executed in privileged mode only.</li> +<li>An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf">__enable_fault_irq</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a>; <a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_FAULTMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaeb8e5f7564a8ea23678fe3c987b04013"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __disable_irq </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function disables interrupts and all configurable fault handlers by setting PRIMASK. The function uses the instruction <b>CPSID i</b>.</p> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Can be executed in privileged mode only.</li> +<li>An interrupt can enter pending state even if it is disabled. Disabling an interrupt only prevents the processor from taking that interrupt.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a>; <a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit. ">__set_PRIMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga6575d37863cec5d334864f93b5b783bf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __enable_fault_irq </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function enables interrupts and all fault handlers by clearing FAULTMASK. The function uses the instruction <b>CPSIE f</b>.</p> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Can be executed in privileged mode only.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">__disable_fault_irq</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a>; <a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_FAULTMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga0f98dfbd252b89d12564472dbeba9c27"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __enable_irq </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function enables interrupts and all configurable fault handlers by clearing PRIMASK. The function uses the instruction <b>CPSIE i</b>.</p> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Can be executed in privileged mode only.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a>; <a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit. ">__set_PRIMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga811c0012221ee918a75111ca84c4d5e7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_APSR </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Application Program Status Register (APSR) using the instruction <b>MRS</b>. <br/> +<br/> +The APSR contains the current state of the condition flags from instructions executed previously. The APSR is essential for controlling conditional branches. The following flags are used:</p> +<ul> +<li><b>N</b> (APSR[31]) (Negative flag)<ul> +<li>=1 The instruction result has a negative value (when interpreted as signed integer).</li> +<li>=0 The instruction result has a positive value or equal zero. <br/> +<br/> +</li> +</ul> +</li> +<li><b>Z</b> (APSR[30]) (Zero flag)<ul> +<li>=1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. <br/> +<br/> +</li> +</ul> +</li> +<li><b>C</b> (APSR[29]) (Carry or borrow flag)<ul> +<li>=1 For unsigned additions, if an unsigned overflow occurred.</li> +<li>=<em>inverse of borrow output status</em> For unsigned subtract operations. <br/> +<br/> +</li> +</ul> +</li> +<li><b>V</b> (APSR[28]) (Overflow flag)<ul> +<li>=1 A signed overflow occurred (for signed additions or subtractions). <br/> +<br/> +</li> +</ul> +</li> +<li><b>Q</b> (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]<ul> +<li>This flag is a <em>sticky</em> flag. Saturating and certain mutliplying instructions can set the flag, but cannot clear it.</li> +<li>=1 When saturation or an overflow occurred. <br/> +<br/> +</li> +</ul> +</li> +<li><b>GE</b> (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]<ul> +<li>Can be set by the parallel add and subtract instructions.</li> +<li>Are used by the <code>SEL</code> instruction to perform byte-based selection from two registers.</li> +</ul> +</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>APSR register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Some instructions update all flags; some instructions update a subset of the flags.</li> +<li>If a flag is not updated, the original value is preserved.</li> +<li>Conditional instructions that are not executed have no effect on the flags.</li> +<li>The CMSIS does not provide a function to update this register.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a>; <a class="el" href="unionAPSR__Type.html" title="Union type to access the Application Program Status Register (APSR). ">APSR_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga32da759f46e52c95bcfbde5012260667"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_BASEPRI </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function returns the Base Priority Mask register (BASEPRI) using the instruction <b>MRS</b>. <br/> +<br/> +BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p> +<dl class="section return"><dt>Returns</dt><dd>BASEPRI register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Not for Cortex-M0, Cortex-M0+, or SC000.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9" title="Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI_MAX</a>; <a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8" title="Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_FAULTMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02" title="Read the PRIMASK register bit. ">__get_PRIMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga963cf236b73219ce78e965deb01b81a7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_CONTROL </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the CONTROL register value using the instruction <b>MRS</b>. <br/> +<br/> +The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/> +</p> +<ul> +<li><b>CONTROL</b>[2] [only Cortex-M4 and Cortex-M7]<ul> +<li>=0 FPU not active</li> +<li>=1 FPU active <br/> +<br/> +</li> +</ul> +</li> +<li><b>CONTROL</b>[1]<ul> +<li>=0 In handler mode - MSP is selected. No alternate stack possible for handler mode.</li> +<li>=0 In thread mode - Default stack pointer MSP is used.</li> +<li>=1 In thread mode - Alternate stack pointer PSP is used. <br/> +<br/> +</li> +</ul> +</li> +<li><b>CONTROL</b>[0] [not Cortex-M0]<ul> +<li>=0 In thread mode and privileged state.</li> +<li>=1 In thread mode and user state.</li> +</ul> +</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>CONTROL register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>The processor can be in user state or privileged state when running in thread mode.</li> +<li>Exception handlers always run in privileged state.</li> +<li>On reset, the processor is in thread mode with privileged access rights.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a>; <a class="el" href="unionCONTROL__Type.html" title="Union type to access the Control Registers (CONTROL). ">CONTROL_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaa78e4e6bf619a65e9f01b4af13fed3a8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_FAULTMASK </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Fault Mask register (FAULTMASK) value using the instruction <b>MRS</b>. <br/> +<br/> +FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).</p> +<dl class="section return"><dt>Returns</dt><dd>FAULTMASK register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02" title="Read the PRIMASK register bit. ">__get_PRIMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gad6d7eca9ddd1d9072dd7b020cfe64905"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_FPSCR </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Floating-Point Status Control Register (FPSCR) value. <br/> +<br/> +FPSCR provides all necessary User level controls of the floating-point system.</p> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>FPSCR register value, when __FPU_PRESENT=1</li> +<li>=0, when __FPU_PRESENT=0</li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only for Cortex-M4 and Cortex-M7.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">__set_FPSCR</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_IPSR </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Interrupt Program Status Register (IPSR) using the instruction <b>MRS</b>. <br/> +<br/> +The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). Each exception has an assocciated unique IRQn number. The following bits are used:</p> +<ul> +<li><b>ISR_NUMBER</b> (IPSR[8:0])<ul> +<li>=0 Thread mode</li> +<li>=1 Reserved</li> +<li>=2 NMI</li> +<li>=3 HardFault</li> +<li>=4 MemManage</li> +<li>=5 BusFault</li> +<li>=6 UsageFault</li> +<li>=7-10 Reserved</li> +<li>=11 SVCall</li> +<li>=12 Reserved for Debug</li> +<li>=13 Reserved</li> +<li>=14 PendSV</li> +<li>=15 SysTick</li> +<li>=16 IRQ0</li> +<li>...</li> +<li>=n+15 IRQ(n-1)</li> +</ul> +</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>ISPR register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>This register is read-only.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd">__get_xPSR</a>; <a class="el" href="unionIPSR__Type.html" title="Union type to access the Interrupt Program Status Register (IPSR). ">IPSR_Type</a></li> +<li><a class="el" href="group__NVIC__gr.html">Interrupts and Exceptions (NVIC)</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gab898559392ba027814e5bbb5a98b38d2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_MSP </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Main Status Pointer (MSP) value using the instruction <b>MRS</b>. <br/> +<br/> +Physically two different stack pointers (SP) exist:</p> +<ul> +<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li> +<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li> +</ul> +<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p> +<ul> +<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li> +<li>=1 PSP is the current stack pointer. The initial value is undefined.</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>MSP Register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only one of the two SPs is visible at a time.</li> +<li>For many applications, the system can completely rely on the MSP.</li> +<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a>; <a class="el" href="group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9" title="Read the PSP register. ">__get_PSP</a>; <a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7" title="Read the CONTROL register. ">__get_CONTROL</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaf39856ca50fc88cf459031b44eb2521c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_MSPLIM </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the Main Stack Pointer Limit (MSPLIM). </p> +<dl class="section return"><dt>Returns</dt><dd>MSPLIM Register value </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga799b5d9a2ae75e459264c8512c7c0e02"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_PRIMASK </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Priority Mask register (PRIMASK) value using the instruction <b>MRS</b>. <br/> +<br/> +PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p> +<dl class="section return"><dt>Returns</dt><dd>PRIMASK register value<ul> +<li>=0 no effect</li> +<li>=1 prevents the activation of all exceptions with configurable priority</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8" title="Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_FAULTMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga914dfa8eff7ca53380dd54cf1d8bebd9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_PSP </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the Program Status Pointer (PSP) value using the instruction <b>MRS</b>. <br/> +<br/> +Physically two different stack pointers (SP) exist:</p> +<ul> +<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li> +<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li> +</ul> +<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p> +<ul> +<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li> +<li>=1 PSP is the current stack pointer. The initial value is undefined.</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>PSP register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only one of the two SPs is visible at a time.</li> +<li>For many applications, the system can completely rely on the MSP.</li> +<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a>; <a class="el" href="group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2" title="Read the MSP register. ">__get_MSP</a>; <a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7" title="Read the CONTROL register. ">__get_CONTROL</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga8b226929264e903c7019e326b42bef47"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_PSPLIM </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the Process Stack Pointer Limit (PSPLIM). </p> +<dl class="section return"><dt>Returns</dt><dd>PSPLIM Register value </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga732e08184154f44a617963cc65ff95bd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __get_xPSR </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function reads the combined Program Status Register (xPSR) using the instruction <b>MRS</b>. <br/> +<br/> +xPSR provides information about program execution and the APSR flags. It consists of the following PSRs: </p> +<ul> +<li>Application Program Status Register (APSR) </li> +<li>Interrupt Program Status Register (IPSR) </li> +<li>Execution Program Status Register (EPSR)</li> +</ul> +<p>In addition to the flags described in <a class="el" href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a> and <a class="el" href="group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">__get_IPSR</a>, the register provides the following flags:</p> +<ul> +<li><b>IT</b> (xPSR[26:25]) (If-Then condition instruction)<ul> +<li>Contains up to four instructions following an IT instruction.</li> +<li>Each instruction in the block is conditional.</li> +<li>The conditions for the instructions are either all the same, or some can be the inverse of others. <br/> +<br/> +</li> +</ul> +</li> +<li><b>T</b> (xPSR[24]) (Thumb bit)<ul> +<li>=1 Indicates that that the processor is in Thumb state.</li> +<li>=0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.</li> +<li>The conditions for the instructions are either all the same, or some can be the inverse of others.</li> +</ul> +</li> +</ul> +<dl class="section return"><dt>Returns</dt><dd>xPSR register value</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>The CMSIS does not provide functions that access EPSR.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">__get_APSR</a>; <a class="el" href="group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8" title="Read the IPSR register. ">__get_IPSR</a>; <a class="el" href="unionxPSR__Type.html" title="Union type to access the Special-Purpose Program Status Registers (xPSR). ">xPSR_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga360c73eb7ffb16088556f9278953b882"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_BASEPRI </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>basePri</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Base Priority Mask register (BASEPRI) value using the instruction <b>MSR</b>. <br/> +<br/> +BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">basePri</td><td>BASEPRI value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Cannot be set in user state.</li> +<li>Useful for changing the masking level or disabling the masking.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9" title="Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI_MAX</a>; <a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_FAULTMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit. ">__set_PRIMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga62fa63d39cf22df348857d5f44ab64d9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_BASEPRI_MAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>basePri</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function only increases the Base Priority Mask register (BASEPRI) value using the instruction <b>MSR</b>. The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level. <br/> +<br/> +BASEPRI defines the minimum priority for exception processing.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">basePri</td><td>BASEPRI value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Cannot be set in user state.</li> +<li>Useful for increasing the masking level.</li> +<li>Has no effect when <em>basePri</em> is lower than the current value of BASEPRI.</li> +<li>Use <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a> to lower the Base Priority Mask register.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_FAULTMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit. ">__set_PRIMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gac64d37e7ff9de06437f9fb94bbab8b6c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_CONTROL </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>control</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the CONTROL register value using the instruction <b>MSR</b>. <br/> +<br/> +The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode and, if implemented, indicates whether the FPU state is active. This register uses the following bits: <br/> +</p> +<ul> +<li><b>CONTROL</b>[2] [only Cortex-M4 and Cortex-M7]<ul> +<li>=0 FPU not active</li> +<li>=1 FPU active <br/> +<br/> +</li> +</ul> +</li> +<li><b>CONTROL</b>[1]<ul> +<li>Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).</li> +<li>=0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.</li> +<li>=0 In thread mode - Default stack pointer MSP is used.</li> +<li>=1 In thread mode - Alternate stack pointer PSP is used. <br/> +<br/> +</li> +</ul> +</li> +<li><b>CONTROL</b>[0] [not writeable for Cortex-M0]<ul> +<li>Writeable only when the processor is in privileged state.</li> +<li>Can be used to switch the processor to user state (thread mode).</li> +<li>Once in user state, trigger an interrupt and change the state to privileged in the exception handler (the only way).</li> +<li>=0 In thread mode and privileged state.</li> +<li>=1 In thread mode and user state.</li> +</ul> +</li> +</ul> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">control</td><td>CONTROL register value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>The processor can be in user state or privileged state when running in thread mode.</li> +<li>Exception handlers always run in privileged state.</li> +<li>On reset, the processor is in thread mode with privileged access rights.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a>; <a class="el" href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743" title="Set the PSP register. ">__set_PSP</a>; <a class="el" href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4" title="Set the MSP register. ">__set_MSP</a>; <a class="el" href="unionCONTROL__Type.html" title="Union type to access the Control Registers (CONTROL). ">CONTROL_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaa5587cc09031053a40a35c14ec36078a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_FAULTMASK </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>faultMask</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Fault Mask register (FAULTMASK) value using the instruction <b>MSR</b>. <br/> +<br/> +FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or memory management fault) to hard fault level without invoking a hard fault. This allows the fault handler to pretend to be the hard fault handler, whith the ability to:</p> +<ol type="1"> +<li><b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register. It can be used to test the bus system without causing a lockup.</li> +<li><b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without reprogramming the MPU to just carry out a few transfers for fixing faults.</li> +</ol> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">faultMask</td><td>FAULTMASK register value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>Is cleared automatically upon exiting the exception handler, except when returning from the NMI handler.</li> +<li>When set, it changes the effective current priority level to -1, so that even the hard fault handler is blocked.</li> +<li>Can be used by fault handlers to change their priority to -1 to have access to some features for hard fault exceptions (see above).</li> +<li>When set, lockups can still be caused by incorrect or undefined instructions, or by using SVC in the wrong priority level.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f" title="Set the Priority Mask bit. ">__set_PRIMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga6f26bd75ca7e3247f27b272acc10536b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_FPSCR </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>fpscr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Floating-Point Status Control Register (FPSCR) value. <br/> +<br/> +FPSCR provides all necessary User level control of the floating-point system. <br/> +</p> +<ul> +<li><b>N</b> (FPSC[31]) (Negative flag)<ul> +<li>=1 The instruction result has a negative value (when interpreted as signed integer).</li> +<li>=0 The instruction result has a positive value or equal zero. <br/> +<br/> +</li> +</ul> +</li> +<li><b>Z</b> (FPSC[30]) (Zero flag)<ul> +<li>=1 The instruction result is zero. Or, after a compare instruction, when the two values are the same. <br/> +<br/> +</li> +</ul> +</li> +<li><b>C</b> (FPSC[29]) (Carry or borrow flag)<ul> +<li>=1 For unsigned additions, if an unsigned overflow occurred.</li> +<li>=<em>inverse of borrow output status</em> For unsigned subtract operations. <br/> +<br/> +</li> +</ul> +</li> +<li><b>V</b> (FPSC[28]) (Overflow flag)<ul> +<li>=1 A signed overflow occurred (for signed additions or subtractions). <br/> +<br/> +</li> +</ul> +</li> +<li><b>AHP</b> (FPSC[26]) (Alternative half-precision flag)<ul> +<li>=1 Alternative half-precision format selected.</li> +<li>=0 IEEE half-precision format selected. <br/> +<br/> +</li> +</ul> +</li> +<li><b>DN</b> (FPSC[25]) (Default NaN mode control flag)<ul> +<li>=1 Any operation involving one or more NaNs returns the Default NaN.</li> +<li>=0 NaN operands propagate through to the output of a floating-point operation. <br/> +<br/> +</li> +</ul> +</li> +<li><b>FZ</b> (FPSC[24]) (Flush-to-zero mode control flag)<ul> +<li>=1 Flush-to-zero mode enabled.</li> +<li>=0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. <br/> +<br/> +</li> +</ul> +</li> +<li><b>RMode</b> (FPSC[23:22]) (Rounding Mode control flags)<ul> +<li>=0b00 Round to Nearest (RN) mode.</li> +<li>=0b01 Round towards Plus Infinity (RP) mode.</li> +<li>=0b10 Round towards Minus Infinity (RM) mode.</li> +<li>=0b11 Round towards Zero (RZ) mode.</li> +<li>The specified rounding mode is used by almost all floating-point instructions. <br/> +<br/> +</li> +</ul> +</li> +<li><b>IDC</b> (FPSC[7]) (Input Denormal cumulative exception flags)<ul> +<li>See Cumulative exception bits (FPSC[4:0]). <br/> +<br/> +</li> +</ul> +</li> +<li><b>IXC</b> (FPSC[4]) (Inexact cumulative exception flag)<ul> +<li>=1 Exception occurred.</li> +<li>=0 Value has to be set explicitly.</li> +<li>Flag is not cleared automatically. <br/> +<br/> +</li> +</ul> +</li> +<li><b>UFC</b> (FPSC[3]) (Underflow cumulative exception flag)<ul> +<li>=1 Exception occurred.</li> +<li>=0 Value has to be set explicitly.</li> +<li>Flag is not cleared automatically. <br/> +<br/> +</li> +</ul> +</li> +<li><b>OFC</b> (FPSC[2]) (Overflow cumulative exception flag)<ul> +<li>=1 Exception occurred.</li> +<li>=0 Value has to be set explicitly.</li> +<li>Flag is not cleared automatically. <br/> +<br/> +</li> +</ul> +</li> +<li><b>DZC</b> (FPSC[1]) (Division by Zero cumulative exception flag)<ul> +<li>=1 Exception occurred.</li> +<li>=0 Value has to be set explicitly.</li> +<li>Flag is not cleared automatically. <br/> +<br/> +</li> +</ul> +</li> +<li><b>IOC</b> (FPSC[0]) (Invalid Operation cumulative exception flag)<ul> +<li>=1 Exception occurred.</li> +<li>=0 Value has to be set explicitly.</li> +<li>Flag is not cleared automatically.</li> +</ul> +</li> +</ul> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">fpscr</td><td>FPSCR value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only for Cortex-M4 and Cortex-M7.</li> +<li>The variable <b>__FPU_PRESENT</b> has to be set to 1.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">__get_FPSCR</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga0bf9564ebc1613a8faba014275dac2a4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_MSP </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>topOfMainStack</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Main Status Pointer (MSP) value using the instruction <b>MSR</b>. <br/> +<br/> +Physically two different stack pointers (SP) exist:</p> +<ul> +<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li> +<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li> +</ul> +<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p> +<ul> +<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li> +<li>=1 PSP is the current stack pointer. The initial value is undefined.</li> +</ul> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">topOfMainStack</td><td>MSP value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only one of the two SPs is visible at a time.</li> +<li>For many applications, the system can completely rely on the MSP.</li> +<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a>; <a class="el" href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743" title="Set the PSP register. ">__set_PSP</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga6809a07c5cb7410e361f3fba57f72172"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__set_MSPLIM </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MainStackPtrLimit</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the Main Stack Pointer Limit (MSPLIM). </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">MainStackPtrLimit</td><td>Main Stack Pointer Limit value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga70b4e1a6c1c86eb913fb9d6e8400156f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_PRIMASK </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>priMask</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Priority Mask register (PRIMASK) value using the instruction <b>MSR</b>. <br/> +<br/> +PRIMASK is a 1-bit-wide interrupt mask register. When set, it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception. The PRIMASK prevents activation of all exceptions with configurable priority.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">priMask</td><td>Priority Mask<ul> +<li>=0 no effect</li> +<li>=1 prevents the activation of all exceptions with configurable priority</li> +</ul> +</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>When set, PRIMASK effectively changes the current priority level to 0. This is the highest programmable level.</li> +<li>When set and a fault occurs, the hard fault handler will be executed.</li> +<li>Useful for temprorarily disabling all interrupts for timing critical tasks.</li> +<li>Does not have the ability to mask BusFault or bypass MPU.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>; <a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a" title="Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_FAULTMASK</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga48e5853f417e17a8a65080f6a605b743"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_PSP </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>topOfProcStack</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the Program Status Pointer (PSP) value using the instruction <b>MSR</b>. <br/> +<br/> +Physically two different stack pointers (SP) exist:</p> +<ul> +<li>The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when running exception handlers (handler mode).</li> +<li>The Process Stack Pointer (PSP), which can be used only in thread mode.</li> +</ul> +<p>Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:</p> +<ul> +<li>=0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded from the first 32-bit word of the vector table from the program memory.</li> +<li>=1 PSP is the current stack pointer. The initial value is undefined.</li> +</ul> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">topOfProcStack</td><td>PSP value to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only one of the two SPs is visible at a time.</li> +<li>For many applications, the system can completely rely on the MSP.</li> +<li>The PSP is normally used in designs with an OS where the stack memory for OS Kernel must be separated from the application code.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a>; <a class="el" href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4" title="Set the MSP register. ">__set_MSP</a>; <a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c" title="Set the CONTROL Register. ">__set_CONTROL</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga4348d14fc5eefbfd34ab8c51be44a81b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __set_PSPLIM </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ProcStackPtrLimit</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the Process Stack Pointer Limit (PSPLIM). </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ProcStackPtrLimit</td><td>Process Stack Pointer Limit value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__Core__Register__gr.js b/docs/Core/html/group__Core__Register__gr.js new file mode 100644 index 0000000..b3641ea --- /dev/null +++ b/docs/Core/html/group__Core__Register__gr.js @@ -0,0 +1,29 @@ +var group__Core__Register__gr = +[ + [ "__disable_fault_irq", "group__Core__Register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939", null ], + [ "__disable_irq", "group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013", null ], + [ "__enable_fault_irq", "group__Core__Register__gr.html#ga6575d37863cec5d334864f93b5b783bf", null ], + [ "__enable_irq", "group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27", null ], + [ "__get_APSR", "group__Core__Register__gr.html#ga811c0012221ee918a75111ca84c4d5e7", null ], + [ "__get_BASEPRI", "group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667", null ], + [ "__get_CONTROL", "group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7", null ], + [ "__get_FAULTMASK", "group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8", null ], + [ "__get_FPSCR", "group__Core__Register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905", null ], + [ "__get_IPSR", "group__Core__Register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8", null ], + [ "__get_MSP", "group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2", null ], + [ "__get_MSPLIM", "group__Core__Register__gr.html#gaf39856ca50fc88cf459031b44eb2521c", null ], + [ "__get_PRIMASK", "group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02", null ], + [ "__get_PSP", "group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9", null ], + [ "__get_PSPLIM", "group__Core__Register__gr.html#ga8b226929264e903c7019e326b42bef47", null ], + [ "__get_xPSR", "group__Core__Register__gr.html#ga732e08184154f44a617963cc65ff95bd", null ], + [ "__set_BASEPRI", "group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882", null ], + [ "__set_BASEPRI_MAX", "group__Core__Register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9", null ], + [ "__set_CONTROL", "group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c", null ], + [ "__set_FAULTMASK", "group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a", null ], + [ "__set_FPSCR", "group__Core__Register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b", null ], + [ "__set_MSP", "group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4", null ], + [ "__set_MSPLIM", "group__Core__Register__gr.html#ga6809a07c5cb7410e361f3fba57f72172", null ], + [ "__set_PRIMASK", "group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f", null ], + [ "__set_PSP", "group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743", null ], + [ "__set_PSPLIM", "group__Core__Register__gr.html#ga4348d14fc5eefbfd34ab8c51be44a81b", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__Dcache__functions__m7.html b/docs/Core/html/group__Dcache__functions__m7.html new file mode 100644 index 0000000..619e877 --- /dev/null +++ b/docs/Core/html/group__Dcache__functions__m7.html @@ -0,0 +1,356 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>D-Cache Functions</title> +<title>CMSIS-Core (Cortex-M): D-Cache Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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+Functions</h2></td></tr> +<tr class="memitem:ga63aa640d9006021a796a5dcf9c7180b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a> (void)</td></tr> +<tr class="memdesc:ga63aa640d9006021a796a5dcf9c7180b6"><td class="mdescLeft"> </td><td class="mdescRight">Enable D-Cache. <a href="#ga63aa640d9006021a796a5dcf9c7180b6">More...</a><br/></td></tr> +<tr class="separator:ga63aa640d9006021a796a5dcf9c7180b6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6468170f90d270caab8116e7a4f0b5fe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">SCB_DisableDCache</a> (void)</td></tr> +<tr class="memdesc:ga6468170f90d270caab8116e7a4f0b5fe"><td class="mdescLeft"> </td><td class="mdescRight">Disable D-Cache. <a href="#ga6468170f90d270caab8116e7a4f0b5fe">More...</a><br/></td></tr> +<tr class="separator:ga6468170f90d270caab8116e7a4f0b5fe"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gace2d30db08887d0bdb818b8a785a5ce6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a> (void)</td></tr> +<tr class="memdesc:gace2d30db08887d0bdb818b8a785a5ce6"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate D-Cache. <a href="#gace2d30db08887d0bdb818b8a785a5ce6">More...</a><br/></td></tr> +<tr class="separator:gace2d30db08887d0bdb818b8a785a5ce6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga55583e3065c6eabca204b8b89b121c4c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">SCB_CleanDCache</a> (void)</td></tr> +<tr class="memdesc:ga55583e3065c6eabca204b8b89b121c4c"><td class="mdescLeft"> </td><td class="mdescRight">Clean D-Cache. <a href="#ga55583e3065c6eabca204b8b89b121c4c">More...</a><br/></td></tr> +<tr class="separator:ga55583e3065c6eabca204b8b89b121c4c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">SCB_CleanInvalidateDCache</a> (void)</td></tr> +<tr class="memdesc:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="mdescLeft"> </td><td class="mdescRight">Clean & Invalidate D-Cache. <a href="#ga1b741def9e3b2ca97dc9ea49b8ce505c">More...</a><br/></td></tr> +<tr class="separator:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga503ef7ef58c0773defd15a82f6336c09"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr> +<tr class="memdesc:ga503ef7ef58c0773defd15a82f6336c09"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Invalidate by address. <a href="#ga503ef7ef58c0773defd15a82f6336c09">More...</a><br/></td></tr> +<tr class="separator:ga503ef7ef58c0773defd15a82f6336c09"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga696fadbf7b9cc71dad42fab61873a40d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">SCB_CleanDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr> +<tr class="memdesc:ga696fadbf7b9cc71dad42fab61873a40d"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Clean by address. <a href="#ga696fadbf7b9cc71dad42fab61873a40d">More...</a><br/></td></tr> +<tr class="separator:ga696fadbf7b9cc71dad42fab61873a40d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga630131b2572eaa16b569ed364dfc895e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">SCB_CleanInvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr> +<tr class="memdesc:ga630131b2572eaa16b569ed364dfc895e"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Clean and Invalidate by address. <a href="#ga630131b2572eaa16b569ed364dfc895e">More...</a><br/></td></tr> +<tr class="separator:ga630131b2572eaa16b569ed364dfc895e"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>// close ICache functions </p> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga55583e3065c6eabca204b8b89b121c4c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_CleanDCache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function cleans the entire data cache. </p> + +</div> +</div> +<a class="anchor" id="ga696fadbf7b9cc71dad42fab61873a40d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_CleanDCache_by_Addr </td> + <td>(</td> + <td class="paramtype">uint32_t * </td> + <td class="paramname"><em>addr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>dsize</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr> + </table> + </dd> +</dl> +<p>The function cleans a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p> + +</div> +</div> +<a class="anchor" id="ga1b741def9e3b2ca97dc9ea49b8ce505c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_CleanInvalidateDCache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function cleans and invalidates the entire data cache. </p> + +</div> +</div> +<a class="anchor" id="ga630131b2572eaa16b569ed364dfc895e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_CleanInvalidateDCache_by_Addr </td> + <td>(</td> + <td class="paramtype">uint32_t * </td> + <td class="paramname"><em>addr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>dsize</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr> + </table> + </dd> +</dl> +<p>The function invalidates and cleans a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p> + +</div> +</div> +<a class="anchor" id="ga6468170f90d270caab8116e7a4f0b5fe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_DisableDCache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function turns off the entire data cache.</p> +<dl class="section note"><dt>Note</dt><dd>When disabling the data cache, you must clean (<a class="el" href="group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">SCB_CleanDCache</a>) the entire cache to ensure that any dirty data is flushed to external memory. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga63aa640d9006021a796a5dcf9c7180b6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_EnableDCache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function turns on the entire data cache. </p> +<dl class="section note"><dt>Note</dt><dd>Before enabling the data cache, you must invalidate the entire data cache (<a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>), because external memory might have changed from when the cache was disabled.</dd> +<dd> +After reset, you must invalidate (<a class="el" href="group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>) each cache before enabling it. </dd></dl> + +</div> +</div> +<a class="anchor" id="gace2d30db08887d0bdb818b8a785a5ce6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_InvalidateDCache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function invalidates the entire data cache.</p> +<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a>) it. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga503ef7ef58c0773defd15a82f6336c09"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_InvalidateDCache_by_Addr </td> + <td>(</td> + <td class="paramtype">uint32_t * </td> + <td class="paramname"><em>addr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>dsize</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr> + </table> + </dd> +</dl> +<p>The function invalidates a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__Dcache__functions__m7.js b/docs/Core/html/group__Dcache__functions__m7.js new file mode 100644 index 0000000..e05fce2 --- /dev/null +++ b/docs/Core/html/group__Dcache__functions__m7.js @@ -0,0 +1,11 @@ +var group__Dcache__functions__m7 = +[ + [ "SCB_CleanDCache", "group__Dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c", null ], + [ "SCB_CleanDCache_by_Addr", "group__Dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d", null ], + [ "SCB_CleanInvalidateDCache", "group__Dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c", null ], + [ "SCB_CleanInvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e", null ], + [ "SCB_DisableDCache", "group__Dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe", null ], + [ "SCB_EnableDCache", "group__Dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6", null ], + [ "SCB_InvalidateDCache", "group__Dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6", null ], + [ "SCB_InvalidateDCache_by_Addr", "group__Dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__ITM__Debug__gr.html b/docs/Core/html/group__ITM__Debug__gr.html new file mode 100644 index 0000000..be926f1 --- /dev/null +++ b/docs/Core/html/group__ITM__Debug__gr.html @@ -0,0 +1,278 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Debug Access</title> +<title>CMSIS-Core (Cortex-M): Debug Access</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__ITM__Debug__gr.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> | +<a href="#var-members">Variables</a> </div> + <div class="headertitle"> +<div class="title">Debug Access</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Debug Access to the Instrumented Trace Macrocell (ITM) +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> (uint32_t ch)</td></tr> +<tr class="memdesc:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="mdescLeft"> </td><td class="mdescRight">Transmits a character via channel 0. <a href="#gaaa7c716331f74d644bf6bf25cd3392d1">More...</a><br/></td></tr> +<tr class="separator:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga37b8f41cae703b5ff6947e271065558c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ITM__Debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">ITM_ReceiveChar</a> (void)</td></tr> +<tr class="memdesc:ga37b8f41cae703b5ff6947e271065558c"><td class="mdescLeft"> </td><td class="mdescRight">ITM Receive Character. <a href="#ga37b8f41cae703b5ff6947e271065558c">More...</a><br/></td></tr> +<tr class="separator:ga37b8f41cae703b5ff6947e271065558c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ITM__Debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">ITM_CheckChar</a> (void)</td></tr> +<tr class="memdesc:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="mdescLeft"> </td><td class="mdescRight">ITM Check Character. <a href="#ga7f9bbabd9756d1a7eafb2d9bf27e0535">More...</a><br/></td></tr> +<tr class="separator:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:ga12e68e55a7badc271b948d6c7230b2a8"><td class="memItemLeft" align="right" valign="top">volatile int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a></td></tr> +<tr class="memdesc:ga12e68e55a7badc271b948d6c7230b2a8"><td class="mdescLeft"> </td><td class="mdescRight">external variable to receive characters <a href="#ga12e68e55a7badc271b948d6c7230b2a8">More...</a><br/></td></tr> +<tr class="separator:ga12e68e55a7badc271b948d6c7230b2a8"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.</p> +<p>The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that provides together with the <b>Serial Viewer Output (SVO)</b> trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:</p> +<ul> +<li><b>ITM Channel 0</b>: implements the <a class="el" href="group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function which can be used for printf-style output via the debug interface.</li> +<li><b>ITM Channel 31</b>: is reserved for the RTOS kernel and can be used for kernel awareness debugging.</li> +</ul> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.</li> +<li>The ITM channel 0 can be enabled for the user task.</li> +<li>ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.</li> +</ul> +</dd></dl> +<hr/> + <h1><a class="anchor" id="ITM_debug_uv"></a> +ITM Debugger Support</h1> +<p>A debugger may support a <b>Debug (printf) Viewer</b> window to display data.</p> +<p><b>Direction: Microcontroller –> Debugger:</b></p> +<ul> +<li>Characters received via ITM communication channel 0 are written in a printf-style to the <b>Debug (printf) Viewer</b> window.</li> +</ul> +<p><b>Direction: Debugger –> Microcontroller:</b></p> +<ul> +<li>Check if <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> variable is available (only performed once).</li> +<li>Read the character from the <b>Debug (printf) Viewer</b> window.</li> +<li>If <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> is empty, write character to <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>.</li> +</ul> +<dl class="section note"><dt>Note</dt><dd>The current solution does not use a buffer mechanism for transmitting the characters.</dd></dl> +<hr/> + <h1><a class="anchor" id="itm_debug_ex"></a> +Example:</h1> +<p>Example for the usage of the ITM Channel 31 for RTOS Kernels:</p> +<div class="fragment"><div class="line"><span class="comment">// check if debugger connected and ITM channel enabled for tracing</span></div> +<div class="line"><span class="keywordflow">if</span> ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&</div> +<div class="line"> (ITM->TCR & ITM_TCR_ITMENA) &&</div> +<div class="line"> (ITM->TER & (1UL >> 31))) {</div> +<div class="line"> </div> +<div class="line"> <span class="comment">// transmit trace data</span></div> +<div class="line"> <span class="keywordflow">while</span> (ITM->PORT31_U32 == 0);</div> +<div class="line"> ITM->PORT[31].u8 = task_id; <span class="comment">// id of next task</span></div> +<div class="line"> <span class="keywordflow">while</span> (ITM->PORT[31].u32 == 0);</div> +<div class="line"> ITM->PORT[31].u32 = task_status; <span class="comment">// status information</span></div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga7f9bbabd9756d1a7eafb2d9bf27e0535"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t ITM_CheckChar </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function reads the external variable <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> and checks whether a character is available or not.</p> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>=0 - No character available</li> +<li>=1 - Character available </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga37b8f41cae703b5ff6947e271065558c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t ITM_ReceiveChar </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function inputs a character via the external variable <a class="el" href="group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>Received character</li> +<li>=1 - No character received </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaaa7c716331f74d644bf6bf25cd3392d1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t ITM_SendChar </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ch</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ch</td><td>Character to transmit</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Character to transmit </dd></dl> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a class="anchor" id="ga12e68e55a7badc271b948d6c7230b2a8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">volatile int32_t ITM_RxBuffer</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__ITM__Debug__gr.js b/docs/Core/html/group__ITM__Debug__gr.js new file mode 100644 index 0000000..fd96124 --- /dev/null +++ b/docs/Core/html/group__ITM__Debug__gr.js @@ -0,0 +1,7 @@ +var group__ITM__Debug__gr = +[ + [ "ITM_CheckChar", "group__ITM__Debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535", null ], + [ "ITM_ReceiveChar", "group__ITM__Debug__gr.html#ga37b8f41cae703b5ff6947e271065558c", null ], + [ "ITM_SendChar", "group__ITM__Debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1", null ], + [ "ITM_RxBuffer", "group__ITM__Debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__Icache__functions__m7.html b/docs/Core/html/group__Icache__functions__m7.html new file mode 100644 index 0000000..f1215a6 --- /dev/null +++ b/docs/Core/html/group__Icache__functions__m7.html @@ -0,0 +1,203 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>I-Cache Functions</title> +<title>CMSIS-Core (Cortex-M): I-Cache Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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</td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" 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+Functions</h2></td></tr> +<tr class="memitem:gaf9e7c6c8e16ada1f95e5bf5a03505b68"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a> (void)</td></tr> +<tr class="memdesc:gaf9e7c6c8e16ada1f95e5bf5a03505b68"><td class="mdescLeft"> </td><td class="mdescRight">Enable I-Cache. <a href="#gaf9e7c6c8e16ada1f95e5bf5a03505b68">More...</a><br/></td></tr> +<tr class="separator:gaf9e7c6c8e16ada1f95e5bf5a03505b68"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaba757390852f95b3ac2d8638c717d8d8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">SCB_DisableICache</a> (void)</td></tr> +<tr class="memdesc:gaba757390852f95b3ac2d8638c717d8d8"><td class="mdescLeft"> </td><td class="mdescRight">Disable I-Cache. <a href="#gaba757390852f95b3ac2d8638c717d8d8">More...</a><br/></td></tr> +<tr class="separator:gaba757390852f95b3ac2d8638c717d8d8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga50d373a785edd782c5de5a3b55e30ff3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a> (void)</td></tr> +<tr class="memdesc:ga50d373a785edd782c5de5a3b55e30ff3"><td class="mdescLeft"> </td><td class="mdescRight">Invalidate I-Cache. <a href="#ga50d373a785edd782c5de5a3b55e30ff3">More...</a><br/></td></tr> +<tr class="separator:ga50d373a785edd782c5de5a3b55e30ff3"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gaba757390852f95b3ac2d8638c717d8d8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_DisableICache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function turns off the instruction cache. </p> + +</div> +</div> +<a class="anchor" id="gaf9e7c6c8e16ada1f95e5bf5a03505b68"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_EnableICache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function turns on the instruction cache. </p> +<dl class="section note"><dt>Note</dt><dd>Before enabling the instruction cache, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a>) the entire instruction cache if external memory might have changed since the cache was disabled. </dd> +<dd> +After reset, you must invalidate (<a class="el" href="group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a>) each cache before enabling it. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga50d373a785edd782c5de5a3b55e30ff3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void SCB_InvalidateICache </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction. </p> +<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>) it. </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__Icache__functions__m7.js b/docs/Core/html/group__Icache__functions__m7.js new file mode 100644 index 0000000..3e654b0 --- /dev/null +++ b/docs/Core/html/group__Icache__functions__m7.js @@ -0,0 +1,6 @@ +var group__Icache__functions__m7 = +[ + [ "SCB_DisableICache", "group__Icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8", null ], + [ "SCB_EnableICache", "group__Icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68", null ], + [ "SCB_InvalidateICache", "group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__NVIC__gr.html b/docs/Core/html/group__NVIC__gr.html new file mode 100644 index 0000000..37b03e6 --- /dev/null +++ b/docs/Core/html/group__NVIC__gr.html @@ -0,0 +1,1425 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Interrupts and Exceptions (NVIC)</title> +<title>CMSIS-Core (Cortex-M): Interrupts and Exceptions (NVIC)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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+<tr class="memitem:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a></td></tr> +<tr class="memdesc:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="mdescLeft"> </td><td class="mdescRight">Virtualization of the NVIC API. <a href="#gadc48b4ed09386aab48fa6b9c96d9034c">More...</a><br/></td></tr> +<tr class="separator:gadc48b4ed09386aab48fa6b9c96d9034c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad01d3aa220b50ef141b06c93888b268d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a></td></tr> +<tr class="memdesc:gad01d3aa220b50ef141b06c93888b268d"><td class="mdescLeft"> </td><td class="mdescRight">Virtualization of interrupt vector table access functions. <a href="#gad01d3aa220b50ef141b06c93888b268d">More...</a><br/></td></tr> +<tr class="separator:gad01d3aa220b50ef141b06c93888b268d"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a> +Enumerations</h2></td></tr> +<tr class="memitem:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> { <br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">NonMaskableInt_IRQn</a> = -14, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">HardFault_IRQn</a> = -13, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">MemoryManagement_IRQn</a> = -12, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">BusFault_IRQn</a> = -11, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">UsageFault_IRQn</a> = -10, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da">SecureFault_IRQn</a> = -9, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">SVCall_IRQn</a> = -5, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">DebugMonitor_IRQn</a> = -4, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">PendSV_IRQn</a> = -2, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> = -1, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">WWDG_STM_IRQn</a> = 0, +<br/> +  <a class="el" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">PVD_STM_IRQn</a> = 1 +<br/> + }</td></tr> +<tr class="memdesc:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="mdescLeft"> </td><td class="mdescRight">Definition of IRQn numbers. <a href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">More...</a><br/></td></tr> +<tr class="separator:ga7e1129cd8a196f4284d41db3e82ad5c8"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gad78f447e891789b4d8f2e5b21eeda354"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a> (uint32_t PriorityGroup)</td></tr> +<tr class="memdesc:gad78f447e891789b4d8f2e5b21eeda354"><td class="mdescLeft"> </td><td class="mdescRight">Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gad78f447e891789b4d8f2e5b21eeda354">More...</a><br/></td></tr> +<tr class="separator:gad78f447e891789b4d8f2e5b21eeda354"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa81b19849367d3cdb95ac108c500fa78"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a> (void)</td></tr> +<tr class="memdesc:gaa81b19849367d3cdb95ac108c500fa78"><td class="mdescLeft"> </td><td class="mdescRight">Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gaa81b19849367d3cdb95ac108c500fa78">More...</a><br/></td></tr> +<tr class="separator:gaa81b19849367d3cdb95ac108c500fa78"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="mdescLeft"> </td><td class="mdescRight">Enable a device specific interrupt. <a href="#ga530ad9fda2ed1c8b70e439ecfe80591f">More...</a><br/></td></tr> +<tr class="separator:ga530ad9fda2ed1c8b70e439ecfe80591f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3">NVIC_GetEnableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="mdescLeft"> </td><td class="mdescRight">Get a device specific interrupt enable status. <a href="#ga72f102d31af0ee4aa7a6fb7a180840f3">More...</a><br/></td></tr> +<tr class="separator:ga72f102d31af0ee4aa7a6fb7a180840f3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="mdescLeft"> </td><td class="mdescRight">Disable a device specific interrupt. <a href="#ga736ba13a76eb37ef6e2c253be8b0331c">More...</a><br/></td></tr> +<tr class="separator:ga736ba13a76eb37ef6e2c253be8b0331c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga95a8329a680b051ecf3ee8f516acc662"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga95a8329a680b051ecf3ee8f516acc662"><td class="mdescLeft"> </td><td class="mdescRight">Get the pending device specific interrupt. <a href="#ga95a8329a680b051ecf3ee8f516acc662">More...</a><br/></td></tr> +<tr class="separator:ga95a8329a680b051ecf3ee8f516acc662"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3b885147ef9965ecede49614de8df9d2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga3b885147ef9965ecede49614de8df9d2"><td class="mdescLeft"> </td><td class="mdescRight">Set a device specific interrupt to pending. <a href="#ga3b885147ef9965ecede49614de8df9d2">More...</a><br/></td></tr> +<tr class="separator:ga3b885147ef9965ecede49614de8df9d2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="mdescLeft"> </td><td class="mdescRight">Clear a device specific interrupt from pending. <a href="#ga382ad6bedd6eecfdabd1b94dd128a01a">More...</a><br/></td></tr> +<tr class="separator:ga382ad6bedd6eecfdabd1b94dd128a01a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gadf4252e600661fd762cfc0d1a9f5b892"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gadf4252e600661fd762cfc0d1a9f5b892"><td class="mdescLeft"> </td><td class="mdescRight">Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gadf4252e600661fd762cfc0d1a9f5b892">More...</a><br/></td></tr> +<tr class="separator:gadf4252e600661fd762cfc0d1a9f5b892"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr> +<tr class="memdesc:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="mdescLeft"> </td><td class="mdescRight">Set the priority for an interrupt. <a href="#ga5bb7f43ad92937c039dee3d36c3c2798">More...</a><br/></td></tr> +<tr class="separator:ga5bb7f43ad92937c039dee3d36c3c2798"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="mdescLeft"> </td><td class="mdescRight">Get the priority of an interrupt. <a href="#gab18fb9f6c5f4c70fdd73047f0f7c8395">More...</a><br/></td></tr> +<tr class="separator:gab18fb9f6c5f4c70fdd73047f0f7c8395"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga0688c59605b119c53c71b2505ab23eb5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td></tr> +<tr class="memdesc:ga0688c59605b119c53c71b2505ab23eb5"><td class="mdescLeft"> </td><td class="mdescRight">Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga0688c59605b119c53c71b2505ab23eb5">More...</a><br/></td></tr> +<tr class="separator:ga0688c59605b119c53c71b2505ab23eb5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad3cbca1be7a4726afa9448a9acd89377"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)</td></tr> +<tr class="memdesc:gad3cbca1be7a4726afa9448a9acd89377"><td class="mdescLeft"> </td><td class="mdescRight">Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gad3cbca1be7a4726afa9448a9acd89377">More...</a><br/></td></tr> +<tr class="separator:gad3cbca1be7a4726afa9448a9acd89377"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaebee9cad6724a5bac1857f0f1fb6d6af"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gaebee9cad6724a5bac1857f0f1fb6d6af"><td class="mdescLeft"> </td><td class="mdescRight">Read Interrupt Vector [not for Cortex-M0, SC000]. <a href="#gaebee9cad6724a5bac1857f0f1fb6d6af">More...</a><br/></td></tr> +<tr class="separator:gaebee9cad6724a5bac1857f0f1fb6d6af"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab43c1c59d5c081f1bc725237f4b1f916"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">NVIC_SetVector</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t vector)</td></tr> +<tr class="memdesc:gab43c1c59d5c081f1bc725237f4b1f916"><td class="mdescLeft"> </td><td class="mdescRight">Modify Interrupt Vector [not for Cortex-M0, SC000]. <a href="#gab43c1c59d5c081f1bc725237f4b1f916">More...</a><br/></td></tr> +<tr class="separator:gab43c1c59d5c081f1bc725237f4b1f916"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> (void)</td></tr> +<tr class="memdesc:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="mdescLeft"> </td><td class="mdescRight">Reset the system. <a href="#ga1b47d17e90b6a03e7bd1ec6a0d549b46">More...</a><br/></td></tr> +<tr class="separator:ga1b47d17e90b6a03e7bd1ec6a0d549b46"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga62b37611e1ccbac47d747c98ef302746"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">NVIC_GetTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga62b37611e1ccbac47d747c98ef302746"><td class="mdescLeft"> </td><td class="mdescRight">Get Interrupt Target State. <a href="#ga62b37611e1ccbac47d747c98ef302746">More...</a><br/></td></tr> +<tr class="separator:ga62b37611e1ccbac47d747c98ef302746"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf46218d01a6a3b70666ad0492a7f950a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a">NVIC_SetTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gaf46218d01a6a3b70666ad0492a7f950a"><td class="mdescLeft"> </td><td class="mdescRight">Set Interrupt Target State. <a href="#gaf46218d01a6a3b70666ad0492a7f950a">More...</a><br/></td></tr> +<tr class="separator:gaf46218d01a6a3b70666ad0492a7f950a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga44b31316872e91bda1af7e17173de24b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga44b31316872e91bda1af7e17173de24b"><td class="mdescLeft"> </td><td class="mdescRight">Clear Interrupt Target State. <a href="#ga44b31316872e91bda1af7e17173de24b">More...</a><br/></td></tr> +<tr class="separator:ga44b31316872e91bda1af7e17173de24b"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).</p> +<p>Arm provides a template file <b>startup_<em>device</em></b> for each supported compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific interrupt handlers. Each interrupt handler is defined as a <b><em>weak</em></b> function to an dummy handler. These interrupt handlers can be used directly in application software without being adapted by the programmer.</p> +<p>The table below lists the core exception vectors of the various Cortex-M processors.</p> +<table class="cmtable" summary="Core Exception Name"> +<tr> +<th>Exception Vector </th><th>IRQn<br/> +Value </th><th>M0 </th><th>M0+ </th><th>M3 </th><th>M4 </th><th>M7 </th><th>SC000 </th><th>SC300 </th><th>Armv8-M<br/> +Baseline </th><th>Armv8-M<br/> +Mainline </th><th>Description </th></tr> +<tr> +<td><b>NonMaskableInt_IRQn</b> </td><td>-14 </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Non Maskable Interrupt </td></tr> +<tr> +<td><b>HardFault_IRQn</b> </td><td>-13 </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Hard Fault Interrupt </td></tr> +<tr> +<td><b>MemoryManagement_IRQn</b> </td><td>-12 </td><td>  </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Memory Management Interrupt </td></tr> +<tr> +<td><b>BusFault_IRQn</b> </td><td>-11 </td><td>  </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Bus Fault Interrupt </td></tr> +<tr> +<td><b>UsageFault_IRQn</b> </td><td>-10 </td><td>  </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Usage Fault Interrupt </td></tr> +<tr> +<td><b>SecureFault_IRQn</b> </td><td>-9 </td><td>  </td><td>  </td><td>  </td><td>  </td><td>  </td><td>  </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Secure Fault Interrupt </td></tr> +<tr> +<td><b>SVCall_IRQn</b> </td><td>-5 </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>SV Call Interrupt </td></tr> +<tr> +<td><b>DebugMonitor_IRQn</b> </td><td>-4 </td><td>  </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>  </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Debug Monitor Interrupt </td></tr> +<tr> +<td><b>PendSV_IRQn</b> </td><td>-2 </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>Pend SV Interrupt </td></tr> +<tr> +<td><b>SysTick_IRQn</b> </td><td>-1 </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td><div class="image"> +<img src="check.png" alt="available"/> +</div> + </td><td>System Tick Interrupt </td></tr> +</table> +<h1>Vector Table </h1> +<p>The Vector Table defines the entry addresses of the processor exceptions and the device specific interrupts. It is typically located at the beginning of the program memory, however <a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> it can be relocated to RAM. The symbol <b>__Vectors</b> is the address of the vector table in the startup code and the register <b>SCB->VTOR</b> holds the start address of the vector table.</p> +<p>An Armv8-M implementation with TrustZone provides two vector tables:</p> +<ul> +<li>vector table for Secure handlers</li> +<li>vector table for Non-Secure handlers</li> +</ul> +<p>Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p> +<h2>Processor Exceptions </h2> +<p>At the beginning of the vector table, the initial stack value and the exception vectors of the processor are defined. The vector table below shows the exception vectors of a Armv8-M Mainline processor. Other processor variants may have fewer vectors.</p> +<div class="fragment"><div class="line">__Vectors DCD __initial_sp ; Top of Stack initialization</div> +<div class="line"> DCD Reset_Handler ; Reset Handler</div> +<div class="line"> DCD NMI_Handler ; NMI Handler</div> +<div class="line"> DCD HardFault_Handler ; Hard Fault Handler</div> +<div class="line"> DCD MemManage_Handler ; MPU Fault Handler</div> +<div class="line"> DCD BusFault_Handler ; Bus Fault Handler</div> +<div class="line"> DCD UsageFault_Handler ; Usage Fault Handler</div> +<div class="line"> DCD SecureFault_Handler ; Secure Fault Handler</div> +<div class="line"> DCD 0 ; Reserved</div> +<div class="line"> DCD 0 ; Reserved</div> +<div class="line"> DCD 0 ; Reserved</div> +<div class="line"> DCD SVC_Handler ; SVCall Handler</div> +<div class="line"> DCD DebugMon_Handler ; Debug Monitor Handler</div> +<div class="line"> DCD 0 ; Reserved</div> +<div class="line"> DCD PendSV_Handler ; PendSV Handler</div> +<div class="line"> DCD SysTick_Handler ; SysTick Handler</div> +</div><!-- fragment --><h2>Device Specific Vectors </h2> +<p>Following the processor exception vectors, the vector table contains also the device specific interrupt vectors.</p> +<div class="fragment"><div class="line">; device specific interrupts</div> +<div class="line"> DCD WWDG_IRQHandler ; Window Watchdog</div> +<div class="line"> DCD PVD_IRQHandler ; PVD through EXTI Line detect</div> +<div class="line"> DCD TAMPER_IRQHandler ; Tamper</div> +</div><!-- fragment --><p>All device specific interrupts should have a default interrupt handler function that can be overwritten in user code. Below is an example for this default handler function.</p> +<div class="fragment"><div class="line">Default_Handler PROC</div> +<div class="line"> EXPORT WWDG_IRQHandler [WEAK]</div> +<div class="line"> EXPORT PVD_IRQHandler [WEAK]</div> +<div class="line"> EXPORT TAMPER_IRQHandler [WEAK]</div> +<div class="line"> :</div> +<div class="line"> :</div> +<div class="line"> WWDG_IRQHandler</div> +<div class="line"> PVD_IRQHandler</div> +<div class="line"> TAMPER_IRQHandler</div> +<div class="line"> :</div> +<div class="line"> :</div> +<div class="line"> B .</div> +<div class="line"> ENDP</div> +</div><!-- fragment --><p>The user application may simply define an interrupt handler function by using the handler name as shown below.</p> +<div class="fragment"><div class="line"><span class="keywordtype">void</span> WWDG_IRQHandler(<span class="keywordtype">void</span>)</div> +<div class="line">{</div> +<div class="line"> ...</div> +<div class="line">}</div> +</div><!-- fragment --><h1>NVIC Function Usage </h1> +<p>The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.</p> +<h2>Code Example 1 </h2> +<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div> +<div class="line"> </div> +<div class="line">uint32_t priorityGroup; <span class="comment">/* Variables to store priority group and priority */</span></div> +<div class="line">uint32_t priority;</div> +<div class="line">uint32_t preemptPriority;</div> +<div class="line">uint32_t subPriority;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a>(5); <span class="comment">/* Set priority group to 5:</span></div> +<div class="line"><span class="comment"> Bit[7..6] preempt priority Bits, </span></div> +<div class="line"><span class="comment"> Bit[5..3] subpriority Bits </span></div> +<div class="line"><span class="comment"> (valid for five priority bits) */</span></div> +<div class="line"> </div> +<div class="line"> priorityGroup = <a class="code" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a>(); <span class="comment">/* Get used priority grouping */</span></div> +<div class="line"> </div> +<div class="line"> priority = <a class="code" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a>(priorityGroup, 1, 6); <span class="comment">/* Encode priority with 6 for subpriority and 1 for preempt priority</span></div> +<div class="line"><span class="comment"> Note: priority depends on the used priority grouping */</span></div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a>(UART0_IRQn, priority); <span class="comment">/* Set new priority */</span></div> +<div class="line"> </div> +<div class="line"> priority = <a class="code" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a>(UART0_IRQn); <span class="comment">/* Retrieve priority again */</span> </div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a>(priority, priorityGroup, &preemptPriority, &subPriority);</div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">while</span>(1);</div> +<div class="line">}</div> +</div><!-- fragment --><h2>Code Example 2 </h2> +<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div> +<div class="line"> </div> +<div class="line">uint32_t active; <span class="comment">/* Variable to store interrupt active state */</span></div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> TIMER0_IRQHandler(<span class="keywordtype">void</span>) { <span class="comment">/* Timer 0 interrupt handler */</span></div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">if</span> (LPC_TIM0->IR & (1 << 0)) { <span class="comment">/* Check if interrupt for match channel 0 occured */</span> </div> +<div class="line"> LPC_TIM0->IR |= (1 << 0); <span class="comment">/* Acknowledge interrupt for match channel 0 occured */</span></div> +<div class="line"> }</div> +<div class="line"> active = <a class="code" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a>(TIMER0_IRQn); <span class="comment">/* Get interrupt active state of timer 0 */</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div> +<div class="line"> <span class="comment">/* Set match channel register MR0 to 1 millisecond */</span></div> +<div class="line"> LPC_TIM0->MR0 = (((<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000) / 4) - 1); <span class="comment">/* 1 ms? */</span></div> +<div class="line"> </div> +<div class="line"> LPC_TIM0->MCR = (3 << 0); <span class="comment">/* Enable interrupt and reset for match channel MR0 */</span></div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>(TIMER0_IRQn); <span class="comment">/* Enable NVIC interrupt for timer 0 */</span></div> +<div class="line"> LPC_TIM0->TCR = (1 << 0); <span class="comment">/* Enable timer 0 */</span></div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">while</span>(1);</div> +<div class="line">}</div> +</div><!-- fragment --><h1>NVIC API Virtualization </h1> +<p>The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing secure systems that control access to peripherals and related interrupts. These overrides allow an operating system to control the access privileges of application code to critical interrupts.</p> +<p>The NVIC function virtualization is enabled with the following #define symbols:</p> +<ul> +<li><a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> enables overriding the CMSIS-Core (Cortex-M) NVIC functions.</li> +<li><a class="el" href="group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d">CMSIS_VECTAB_VIRTUAL</a> enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions. </li> +</ul> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="gadc48b4ed09386aab48fa6b9c96d9034c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CMSIS_NVIC_VIRTUAL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the NVIC access functions in the table below must be implemented for virtualizing NVIC access. These functions should be implemented in a separate source module. The original CMSIS-Core __NVIC functions are always available independent of <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a>.</p> +<table class="doxtable"> +<tr> +<th>NVIC Access Functions </th><th>CMSIS-Core Functions </th></tr> +<tr> +<td>NVIC_EnableIRQ </td><td>__NVIC_EnableIRQ </td></tr> +<tr> +<td>NVIC_GetEnableIRQ </td><td>__NVIC_GetEnableIRQ </td></tr> +<tr> +<td>NVIC_DisableIRQ </td><td>__NVIC_DisableIRQ </td></tr> +<tr> +<td>NVIC_GetPendingIRQ </td><td>__NVIC_GetPendingIRQ </td></tr> +<tr> +<td>NVIC_SetPendingIRQ </td><td>__NVIC_SetPendingIRQ </td></tr> +<tr> +<td>NVIC_ClearPendingIRQ </td><td>__NVIC_ClearPendingIRQ </td></tr> +<tr> +<td>NVIC_GetActive </td><td>__NVIC_GetActive </td></tr> +<tr> +<td>NVIC_SetPriority </td><td>__NVIC_SetPriority </td></tr> +<tr> +<td>NVIC_GetPriority </td><td>__NVIC_GetPriority </td></tr> +<tr> +<td>NVIC_SetPriorityGrouping </td><td>__NVIC_SetPriorityGrouping </td></tr> +<tr> +<td>NVIC_GetPriorityGrouping </td><td>__NVIC_GetPriorityGrouping </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="gad01d3aa220b50ef141b06c93888b268d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define CMSIS_VECTAB_VIRTUAL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>When <a class="el" href="group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c">CMSIS_NVIC_VIRTUAL</a> is defined, the functions in the table below must be replaced to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.</p> +<p>The original CMSIS-Core functions are always available, but prefixed with __NVIC.</p> +<table class="doxtable"> +<tr> +<th>Interrupt Vector Table Access </th><th>CMSIS-Core Functions </th></tr> +<tr> +<td>NVIC_GetVector </td><td>__NVIC_GetVector </td></tr> +<tr> +<td>NVIC_SetVector </td><td>__NVIC_SetVector </td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Enumeration Type Documentation</h2> +<a class="anchor" id="ga7e1129cd8a196f4284d41db3e82ad5c8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">enum <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The core exception enumeration names for IRQn values are defined in the file <b>device.h</b>.</p> +<ul> +<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li> +<li>Positive IRQn values represent device-specific exceptions (external interrupts).</li> +<li>The first device-specific interrupt has the IRQn value 0.</li> +</ul> +<p>The table below describes the core exception names and their availability in various Cortex-M cores. </p> +<table class="fieldtable"> +<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30"></a>NonMaskableInt_IRQn</em> </td><td class="fielddoc"> +<p>Exception 2: Non Maskable Interrupt. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85"></a>HardFault_IRQn</em> </td><td class="fielddoc"> +<p>Exception 3: Hard Fault Interrupt. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa"></a>MemoryManagement_IRQn</em> </td><td class="fielddoc"> +<p>Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af"></a>BusFault_IRQn</em> </td><td class="fielddoc"> +<p>Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf"></a>UsageFault_IRQn</em> </td><td class="fielddoc"> +<p>Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da"></a>SecureFault_IRQn</em> </td><td class="fielddoc"> +<p>Exception 7: Secure Fault Interrupt [only on Armv8-M]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237"></a>SVCall_IRQn</em> </td><td class="fielddoc"> +<p>Exception 11: SV Call Interrupt. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c"></a>DebugMonitor_IRQn</em> </td><td class="fielddoc"> +<p>Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2"></a>PendSV_IRQn</em> </td><td class="fielddoc"> +<p>Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7"></a>SysTick_IRQn</em> </td><td class="fielddoc"> +<p>Exception 15: System Tick Interrupt. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2"></a>WWDG_STM_IRQn</em> </td><td class="fielddoc"> +<p>Device Interrupt 0: Window WatchDog Interrupt. </p> +</td></tr> +<tr><td class="fieldname"><em><a class="anchor" id="gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86"></a>PVD_STM_IRQn</em> </td><td class="fielddoc"> +<p>Device Interrupt 1: PVD through EXTI Line detection Interrupt. </p> +</td></tr> +</table> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga382ad6bedd6eecfdabd1b94dd128a01a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_ClearPendingIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function removes the pending state of the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative number.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li> +<li>An interrupt can have the status pending though it is not active.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662" title="Get the pending device specific interrupt. ">NVIC_GetPendingIRQ</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga44b31316872e91bda1af7e17173de24b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_ClearTargetState </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clears the interrupt target field in the non-secure NVIC when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 if interrupt is assigned to Secure</li> +<li>1 if interrupt is assigned to Non Secure </li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only available for Armv8-M in secure state.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746">NVIC_GetTargetState</a>; <a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a" title="Set Interrupt Target State. ">NVIC_SetTargetState</a>; </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gad3cbca1be7a4726afa9448a9acd89377"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_DecodePriority </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>Priority</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>PriorityGroup</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t * </td> + <td class="paramname"><em>pPreemptPriority</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t * </td> + <td class="paramname"><em>pSubPriority</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function decodes an interrupt priority value with the priority group <em>PriorityGroup</em> to preemptive priority value <em>pPreemptPriority</em> and subpriority value <em>pSubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">Priority</td><td>Priority </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr> + <tr><td class="paramdir">[out]</td><td class="paramname">*pPreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr> + <tr><td class="paramdir">[out]</td><td class="paramname">*pSubPriority</td><td>Subpriority value (starting from 0)</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5">NVIC_EncodePriority</a>; <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt. ">NVIC_GetPriority</a>; <a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_GetPriorityGrouping</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga736ba13a76eb37ef6e2c253be8b0331c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_DisableIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function disables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Number of the external interrupt to disable</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga530ad9fda2ed1c8b70e439ecfe80591f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_EnableIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li> +<li>The number of supported interrupts depends on the implementation of the chip designer and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32: <br/> + ICTR[4:0]<ul> +<li>0 - 32 interrupts supported</li> +<li>1 - 64 interrupts supported</li> +<li>...</li> +</ul> +</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a>; <a class="el" href="structSCnSCB__Type.html" title="Structure type to access the System Control and ID Register not in the SCB. ">SCnSCB_Type</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga0688c59605b119c53c71b2505ab23eb5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_EncodePriority </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>PriorityGroup</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>PreemptPriority</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>SubPriority</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function encodes the priority for an interrupt with the priority group <em>PriorityGroup</em>, preemptive priority value <em>PreemptPriority</em>, and subpriority value <em>SubPriority</em>. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">PreemptPriority</td><td>Preemptive priority value (starting from 0) </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">SubPriority</td><td>Subpriority value (starting from 0)</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Encoded priority for the interrupt</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377">NVIC_DecodePriority</a>; <a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt. ">NVIC_SetPriority</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gadf4252e600661fd762cfc0d1a9f5b892"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetActive </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and returns the active bit of the interrupt <em>IRQn</em>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 Interrupt is not active</li> +<li>1 Interrupt is active, or active and pending</li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>IRQn must not be negative.</li> +<li>Each external interrupt has an active status bit. When the processor starts the interrupt handler the bit is set to 1 and cleared when the interrupt return is executed.</li> +<li>When an ISR is preempted and the processor executes anohter interrupt handler, the previous interrupt is still defined as active.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga72f102d31af0ee4aa7a6fb7a180840f3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetEnableIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function returns the interrupt enable status for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 Interrupt is not enabled</li> +<li>1 Interrupt is pending</li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" title="Disable a device specific interrupt. ">NVIC_DisableIRQ</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga95a8329a680b051ecf3ee8f516acc662"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetPendingIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function returns the pending status of the specified device specific interrupt <em>IRQn</em>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 Interrupt is not pending</li> +<li>1 Interrupt is pending</li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear a device specific interrupt from pending. ">NVIC_ClearPendingIRQ</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gab18fb9f6c5f4c70fdd73047f0f7c8395"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetPriority </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function reads the priority for the specified interrupt <em>IRQn</em>. <em>IRQn</em> can can specify any device specific interrupt, or processor exception.</p> +<p>The returned priority value is automatically aligned to the implemented priority bits of the microcontroller.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Interrupt priority</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Each external interrupt has an associated priority-level register.</li> +<li>Unimplemented bits are read as zero.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a>; <a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78" title="Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_GetPriorityGrouping</a>; <a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667" title="Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__get_BASEPRI</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaa81b19849367d3cdb95ac108c500fa78"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetPriorityGrouping </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).</p> +<dl class="section return"><dt>Returns</dt><dd>Priority grouping field</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>By default, priority group setting is zero.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a>; <a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395" title="Get the priority of an interrupt. ">NVIC_GetPriority</a>; <a class="el" href="structSCB__Type.html" title="Structure type to access the System Control Block (SCB). ">SCB_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga62b37611e1ccbac47d747c98ef302746"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetTargetState </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reads the interrupt target field from the non-secure NVIC when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 if interrupt is assigned to Secure</li> +<li>1 if interrupt is assigned to Non Secure </li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only available for Armv8-M in secure state.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a>; <a class="el" href="group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a" title="Set Interrupt Target State. ">NVIC_SetTargetState</a>; </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaebee9cad6724a5bac1857f0f1fb6d6af"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_GetVector </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function allows to read the address of an interrupt handler function.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Address of interrupt handler function</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916">NVIC_SetVector</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga3b885147ef9965ecede49614de8df9d2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_SetPendingIRQ </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function sets the pending bit for the specified device specific interrupt <em>IRQn</em>. <em>IRQn</em> cannot be a negative value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>IRQn must not be negative.</li> +<li>The registers that control the status of interrupts are called SETPEND and CLRPEND.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a" title="Clear a device specific interrupt from pending. ">NVIC_ClearPendingIRQ</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga5bb7f43ad92937c039dee3d36c3c2798"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_SetPriority </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>priority</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sets the priority for the interrupt specified by <em>IRQn</em>.<em>IRQn</em> can can specify any device specific interrupt, or processor exception. The <em>priority</em> specifies the interrupt priority value, whereby lower values indicate a higher priority. The default priority is 0 for every interrupt. This is the highest possible priority.</p> +<p>The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative) priority that is higher than any configurable exception or interrupt.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt Number </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority to set</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>The number of priority levels is configurable and depends on the implementation of the chip designer. To determine the number of bits implemented for interrupt priority-level registers, write <em>0xFF</em> to one of the priority-level register, then read back the value. For example, if the minimum number of 3 bits have been implemented, the read-back value is <em>0xE0</em>.</li> +<li>Writes to unimplemented bits are ignored.</li> +<li><b>For Cortex-M0</b>:<ul> +<li>Dynamic switching of interrupt priority levels is not supported. The priority level of an interrupt should not be changed after it has been enabled.</li> +<li>Supports 0 to 192 priority levels.</li> +<li>Priority-level registers are 2 bit wide, occupying the two MSBs. Each Interrupt Priority Level Register is 1-byte wide.</li> +</ul> +</li> +<li><b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>:<ul> +<li>Dynamic switching of interrupt priority levels is supported.</li> +<li>Supports 0 to 255 priority levels.</li> +<li>Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits. Each register can be further devided into preempt priority level and subpriority level.</li> +</ul> +</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a>; <a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354" title="Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]. ">NVIC_SetPriorityGrouping</a>; <a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882" title="Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]. ">__set_BASEPRI</a>;</li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gad78f447e891789b4d8f2e5b21eeda354"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_SetPriorityGrouping </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>PriorityGroup</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function sets the priority grouping <em>PriorityGroup</em> using the required unlock sequence. <em>PriorityGroup</em> is assigned to the field PRIGROUP (register AIRCR[10:8]). This field determines the split of group priority from subpriority. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority group</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>not for Cortex-M0, Cortex-M0+, or SC000.</li> +<li>By default, priority group setting is zero.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a>; <a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt. ">NVIC_SetPriority</a>; <a class="el" href="structSCB__Type.html" title="Structure type to access the System Control Block (SCB). ">SCB_Type</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaf46218d01a6a3b70666ad0492a7f950a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_SetTargetState </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sets the interrupt target field in the non-secure NVIC when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>0 if interrupt is assigned to Secure</li> +<li>1 if interrupt is assigned to Non Secure </li> +</ul> +</dd></dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Only available for Armv8-M in secure state.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b">NVIC_ClearTargetState</a>; <a class="el" href="group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746" title="Get Interrupt Target State. ">NVIC_GetTargetState</a>; </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gab43c1c59d5c081f1bc725237f4b1f916"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_SetVector </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>vector</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function allows to change the address of an interrupt handler function.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">vector</td><td>Address of new interrupt handler function</td></tr> + </table> + </dd> +</dl> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>Usage of this function requires vector relocation to RAM. Refer to <a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> for more information.<ul> +<li>For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.</li> +</ul> +</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a></li> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga1b47d17e90b6a03e7bd1ec6a0d549b46"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void NVIC_SystemReset </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.</p> +<dl class="section remark"><dt>Remarks</dt><dd><ul> +<li>In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and most parts of the system, but should not affect the debug system.</li> +</ul> +</dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> </li> +</ul> +</dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__NVIC__gr.js b/docs/Core/html/group__NVIC__gr.js new file mode 100644 index 0000000..09a9dd1 --- /dev/null +++ b/docs/Core/html/group__NVIC__gr.js @@ -0,0 +1,38 @@ +var group__NVIC__gr = +[ + [ "CMSIS_NVIC_VIRTUAL", "group__NVIC__gr.html#gadc48b4ed09386aab48fa6b9c96d9034c", null ], + [ "CMSIS_VECTAB_VIRTUAL", "group__NVIC__gr.html#gad01d3aa220b50ef141b06c93888b268d", null ], + [ "IRQn_Type", "group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8", [ + [ "NonMaskableInt_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30", null ], + [ "HardFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85", null ], + [ "MemoryManagement_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa", null ], + [ "BusFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af", null ], + [ "UsageFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf", null ], + [ "SecureFault_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a9cda5594d898247bfa9d16ad966724da", null ], + [ "SVCall_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237", null ], + [ "DebugMonitor_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c", null ], + [ "PendSV_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2", null ], + [ "SysTick_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7", null ], + [ "WWDG_STM_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2", null ], + [ "PVD_STM_IRQn", "group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86", null ] + ] ], + [ "NVIC_ClearPendingIRQ", "group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a", null ], + [ "NVIC_ClearTargetState", "group__NVIC__gr.html#ga44b31316872e91bda1af7e17173de24b", null ], + [ "NVIC_DecodePriority", "group__NVIC__gr.html#gad3cbca1be7a4726afa9448a9acd89377", null ], + [ "NVIC_DisableIRQ", "group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c", null ], + [ "NVIC_EnableIRQ", "group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f", null ], + [ "NVIC_EncodePriority", "group__NVIC__gr.html#ga0688c59605b119c53c71b2505ab23eb5", null ], + [ "NVIC_GetActive", "group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892", null ], + [ "NVIC_GetEnableIRQ", "group__NVIC__gr.html#ga72f102d31af0ee4aa7a6fb7a180840f3", null ], + [ "NVIC_GetPendingIRQ", "group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662", null ], + [ "NVIC_GetPriority", "group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395", null ], + [ "NVIC_GetPriorityGrouping", "group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78", null ], + [ "NVIC_GetTargetState", "group__NVIC__gr.html#ga62b37611e1ccbac47d747c98ef302746", null ], + [ "NVIC_GetVector", "group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af", null ], + [ "NVIC_SetPendingIRQ", "group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2", null ], + [ "NVIC_SetPriority", "group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798", null ], + [ "NVIC_SetPriorityGrouping", "group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354", null ], + [ "NVIC_SetTargetState", "group__NVIC__gr.html#gaf46218d01a6a3b70666ad0492a7f950a", null ], + [ "NVIC_SetVector", "group__NVIC__gr.html#gab43c1c59d5c081f1bc725237f4b1f916", null ], + [ "NVIC_SystemReset", "group__NVIC__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__SysTick__gr.html b/docs/Core/html/group__SysTick__gr.html new file mode 100644 index 0000000..2bf6619 --- /dev/null +++ b/docs/Core/html/group__SysTick__gr.html @@ -0,0 +1,192 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Systick Timer (SYSTICK)</title> +<title>CMSIS-Core (Cortex-M): Systick Timer (SYSTICK)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">Systick Timer (SYSTICK)</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Initialize and start the SysTick timer. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gabe47de40e9b0ad465b752297a9d9f427"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> (uint32_t ticks)</td></tr> +<tr class="memdesc:gabe47de40e9b0ad465b752297a9d9f427"><td class="mdescLeft"> </td><td class="mdescRight">System Tick Timer Configuration. <a href="#gabe47de40e9b0ad465b752297a9d9f427">More...</a><br/></td></tr> +<tr class="separator:gabe47de40e9b0ad465b752297a9d9f427"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The System Tick Time (SysTick) generates interrupt requests on a regular basis. This allows an OS to carry out context switching to support multiple tasking. For applications that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an interrupt source for tasks that need to be executed regularly.</p> +<h1><a class="anchor" id="SysTick_code_ex_sec"></a> +Code Example</h1> +<p>The code below shows the usage of the function <a class="el" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration. ">SysTick_Config()</a> with an LPC1700.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div> +<div class="line"> </div> +<div class="line"><span class="keyword">volatile</span> uint32_t msTicks = 0; <span class="comment">/* Variable to store millisecond ticks */</span></div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>) { <span class="comment">/* SysTick interrupt Handler. */</span></div> +<div class="line"> msTicks++; <span class="comment">/* See startup file startup_LPC17xx.s for SysTick vector */</span> </div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div> +<div class="line"> uint32_t returnCode;</div> +<div class="line"> </div> +<div class="line"> returnCode = <a class="code" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000); <span class="comment">/* Configure SysTick to generate an interrupt every millisecond */</span></div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">if</span> (returnCode != 0) { <span class="comment">/* Check return code for errors */</span></div> +<div class="line"> <span class="comment">// Error Handling </span></div> +<div class="line"> }</div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">while</span>(1);</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gabe47de40e9b0ad465b752297a9d9f427"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t SysTick_Config </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ticks</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ticks</td><td>Number of ticks between two interrupts</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 - success </dd> +<dd> +1 - failure</dd></dl> +<dl class="section note"><dt>Note</dt><dd>When <b>#define __Vendor_SysTickConfig</b> is set to 1, the standard function <b>SysTick_Config</b> is excluded. In this case, the file <b><em>device</em>.h</b> must contain a vendor specific implementation of this function. </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__SysTick__gr.js b/docs/Core/html/group__SysTick__gr.js new file mode 100644 index 0000000..12d20c3 --- /dev/null +++ b/docs/Core/html/group__SysTick__gr.js @@ -0,0 +1,4 @@ +var group__SysTick__gr = +[ + [ "SysTick_Config", "group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__cache__functions__m7.html b/docs/Core/html/group__cache__functions__m7.html new file mode 100644 index 0000000..fb9cf3a --- /dev/null +++ b/docs/Core/html/group__cache__functions__m7.html @@ -0,0 +1,152 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Cache Functions (only Cortex-M7)</title> +<title>CMSIS-Core (Cortex-M): Cache Functions (only Cortex-M7)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#groups">Content</a> </div> + <div class="headertitle"> +<div class="title">Cache Functions (only Cortex-M7)</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions for Instruction and Data Cache. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a> +Content</h2></td></tr> +<tr class="memitem:group__Icache__functions__m7"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></td></tr> +<tr class="memdesc:group__Icache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the instruction cache. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__Dcache__functions__m7"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__Dcache__functions__m7.html">D-Cache Functions</a></td></tr> +<tr class="memdesc:group__Dcache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the data cache. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p> +<p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p> +<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling it.</dd></dl> +<p>The functions are grouped for:</p> +<ul> +<li><a class="el" href="group__Icache__functions__m7.html">I-Cache Functions</a></li> +<li><a class="el" href="group__Dcache__functions__m7.html">D-Cache Functions</a> </li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. 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searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" 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class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga8be4ebde5d4dd91b161d206545ce59aa">__ARM_ARCH_6M__</a></td></tr> +<tr class="memdesc:ga8be4ebde5d4dd91b161d206545ce59aa"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1) <a href="#ga8be4ebde5d4dd91b161d206545ce59aa">More...</a><br/></td></tr> +<tr class="separator:ga8be4ebde5d4dd91b161d206545ce59aa"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga43e1af8bedda108dfc4f8584e6b278a2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga43e1af8bedda108dfc4f8584e6b278a2">__ARM_ARCH_7M__</a></td></tr> +<tr class="memdesc:ga43e1af8bedda108dfc4f8584e6b278a2"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv7-M (Cortex-M3) <a href="#ga43e1af8bedda108dfc4f8584e6b278a2">More...</a><br/></td></tr> +<tr class="separator:ga43e1af8bedda108dfc4f8584e6b278a2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga43ab3e79ec5ecb615f1f2f6e83e7d48a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga43ab3e79ec5ecb615f1f2f6e83e7d48a">__ARM_ARCH_7EM__</a></td></tr> +<tr class="memdesc:ga43ab3e79ec5ecb615f1f2f6e83e7d48a"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU. <a href="#ga43ab3e79ec5ecb615f1f2f6e83e7d48a">More...</a><br/></td></tr> +<tr class="separator:ga43ab3e79ec5ecb615f1f2f6e83e7d48a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a">__ARM_ARCH_8M_BASE__</a></td></tr> +<tr class="memdesc:gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv8-M Baseline. <a href="#gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a">More...</a><br/></td></tr> +<tr class="separator:gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad424c7143edd08c982dddad0ff65f4cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd">__ARM_ARCH_8M_MAIN__</a></td></tr> +<tr class="memdesc:gad424c7143edd08c982dddad0ff65f4cd"><td class="mdescLeft"> </td><td class="mdescRight">Set to 1 when generating code for Armv8-M Mainline. <a href="#gad424c7143edd08c982dddad0ff65f4cd">More...</a><br/></td></tr> +<tr class="separator:gad424c7143edd08c982dddad0ff65f4cd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1378040bcf22428955c6e3ce9c2053cd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a></td></tr> +<tr class="memdesc:ga1378040bcf22428955c6e3ce9c2053cd"><td class="mdescLeft"> </td><td class="mdescRight">Pass information from the compiler to the assembler. <a href="#ga1378040bcf22428955c6e3ce9c2053cd">More...</a><br/></td></tr> +<tr class="separator:ga1378040bcf22428955c6e3ce9c2053cd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">__INLINE</a></td></tr> +<tr class="memdesc:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="mdescLeft"> </td><td class="mdescRight">Recommend that function should be inlined by the compiler. <a href="#gade2d8d7118f8ff49547f60aa0c3382bb">More...</a><br/></td></tr> +<tr class="separator:gade2d8d7118f8ff49547f60aa0c3382bb"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a></td></tr> +<tr class="memdesc:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="mdescLeft"> </td><td class="mdescRight">Define a static function should be inlined by the compiler. <a href="#gaba87361bfad2ae52cfe2f40c1a1dbf9c">More...</a><br/></td></tr> +<tr class="separator:gaba87361bfad2ae52cfe2f40c1a1dbf9c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga153a4a31b276a9758959580538720a51"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51">__NO_RETURN</a></td></tr> +<tr class="memdesc:ga153a4a31b276a9758959580538720a51"><td class="mdescLeft"> </td><td class="mdescRight">Inform the compiler that a function does not return. <a href="#ga153a4a31b276a9758959580538720a51">More...</a><br/></td></tr> +<tr class="separator:ga153a4a31b276a9758959580538720a51"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a></td></tr> +<tr class="memdesc:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="mdescLeft"> </td><td class="mdescRight">Inform that a variable shall be retained in executable image. <a href="#ga3e40e4c553fc11588f7a4c2a19e789e0">More...</a><br/></td></tr> +<tr class="separator:ga3e40e4c553fc11588f7a4c2a19e789e0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac607bf387b29162be6a9b77fc7999539"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gac607bf387b29162be6a9b77fc7999539">__WEAK</a></td></tr> +<tr class="memdesc:gac607bf387b29162be6a9b77fc7999539"><td class="mdescLeft"> </td><td class="mdescRight">Export a function or variable weakly to allow overwrites. <a href="#gac607bf387b29162be6a9b77fc7999539">More...</a><br/></td></tr> +<tr class="separator:gac607bf387b29162be6a9b77fc7999539"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabe8996d3d985ee1529475443cc635bf1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a></td></tr> +<tr class="memdesc:gabe8996d3d985ee1529475443cc635bf1"><td class="mdescLeft"> </td><td class="mdescRight">Request smallest possible alignment. <a href="#gabe8996d3d985ee1529475443cc635bf1">More...</a><br/></td></tr> +<tr class="separator:gabe8996d3d985ee1529475443cc635bf1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4dbb70fab85207c27b581ecb6532b314"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a></td></tr> +<tr class="memdesc:ga4dbb70fab85207c27b581ecb6532b314"><td class="mdescLeft"> </td><td class="mdescRight">Request smallest possible alignment for a structure. <a href="#ga4dbb70fab85207c27b581ecb6532b314">More...</a><br/></td></tr> +<tr class="separator:ga4dbb70fab85207c27b581ecb6532b314"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a></td></tr> +<tr class="memdesc:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned access of a uint32_t variable. <a href="#ga27fd2ec6767ca1ab66d36b5cc0103268">More...</a><br/></td></tr> +<tr class="separator:ga27fd2ec6767ca1ab66d36b5cc0103268"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabe8693a7200e573101551d49a1772fb9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a></td></tr> +<tr class="memdesc:gabe8693a7200e573101551d49a1772fb9"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned read of a uint16_t variable. <a href="#gabe8693a7200e573101551d49a1772fb9">More...</a><br/></td></tr> +<tr class="separator:gabe8693a7200e573101551d49a1772fb9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gadb9cd73446f7e11e92383cd327a23407"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a></td></tr> +<tr class="memdesc:gadb9cd73446f7e11e92383cd327a23407"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned write of a uint16_t variable. <a href="#gadb9cd73446f7e11e92383cd327a23407">More...</a><br/></td></tr> +<tr class="separator:gadb9cd73446f7e11e92383cd327a23407"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga254322c344d954c9f829719a50a88e87"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a></td></tr> +<tr class="memdesc:ga254322c344d954c9f829719a50a88e87"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned read of a uint32_t variable. <a href="#ga254322c344d954c9f829719a50a88e87">More...</a><br/></td></tr> +<tr class="separator:ga254322c344d954c9f829719a50a88e87"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabb2180285c417aa9120a360c51f64b4b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a></td></tr> +<tr class="memdesc:gabb2180285c417aa9120a360c51f64b4b"><td class="mdescLeft"> </td><td class="mdescRight">Pointer for unaligned write of a uint32_t variable. <a href="#gabb2180285c417aa9120a360c51f64b4b">More...</a><br/></td></tr> +<tr class="separator:gabb2180285c417aa9120a360c51f64b4b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga0c58caa5a273e2c21924509a45f8b849"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a></td></tr> +<tr class="memdesc:ga0c58caa5a273e2c21924509a45f8b849"><td class="mdescLeft"> </td><td class="mdescRight">Minimum alignment for a variable. <a href="#ga0c58caa5a273e2c21924509a45f8b849">More...</a><br/></td></tr> +<tr class="separator:ga0c58caa5a273e2c21924509a45f8b849"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The CMSIS-Core provides the header file <b>cmsis_compiler.h</b> with consistent #define symbols for generate C or C++ source files that should be compiler agnostic. Each CMSIS compliant compiler should support the functionality described in this section.</p> +<p>The header file <b>cmsis_compiler.h</b> is also included by each <a class="el" href="device_h_pg.html">Device Header File <device.h></a> so that these definitions are available. </p> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga0c58caa5a273e2c21924509a45f8b849"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ALIGNED</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Specifies a minimum alignment for a variable or structure field, measured in bytes.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint32_t stack_space[0x100] <a class="code" href="group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849">__ALIGNED</a>(8); <span class="comment">// 8-byte alignment required</span></div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga8be4ebde5d4dd91b161d206545ce59aa"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ARM_ARCH_6M__</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>#define <b>ARM_ARCH_6M</b></b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor. </p> + +</div> +</div> +<a class="anchor" id="ga43ab3e79ec5ecb615f1f2f6e83e7d48a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ARM_ARCH_7EM__</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>#define <b>ARM_ARCH_7EM</b></b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU </p> + +</div> +</div> +<a class="anchor" id="ga43e1af8bedda108dfc4f8584e6b278a2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ARM_ARCH_7M__</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>#define <b>ARM_ARCH_7M</b></b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor. </p> + +</div> +</div> +<a class="anchor" id="gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ARM_ARCH_8M_BASE__</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>#define <b>ARM_ARCH_8M_BASE</b></b> is set to 1 when generating code for the Armv8-M architecture baseline variant. </p> + +</div> +</div> +<a class="anchor" id="gad424c7143edd08c982dddad0ff65f4cd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ARM_ARCH_8M_MAIN__</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>#define <b>ARM_ARCH_8M_MAIN</b></b> is set to 1 when generating code for the Armv8-M architecture mainline variant. </p> + +</div> +</div> +<a class="anchor" id="ga1378040bcf22428955c6e3ce9c2053cd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __ASM</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The <b>__ASM</b> keyword can declare or define an embedded assembly function or incorporate inline assembly into a function (shown in the code example below).</p> +<p><b>Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="comment">// Reverse bit order of value</span></div> +<div class="line"> </div> +<div class="line">__attribute__( ( always_inline ) ) <a class="code" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>(uint32_t value)</div> +<div class="line">{</div> +<div class="line"> uint32_t result;</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd">__ASM</a> <span class="keyword">volatile</span> (<span class="stringliteral">"rbit %0, %1"</span> : <span class="stringliteral">"=r"</span> (result) : <span class="stringliteral">"r"</span> (value) );</div> +<div class="line"> <span class="keywordflow">return</span>(result);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gade2d8d7118f8ff49547f60aa0c3382bb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __INLINE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to inline code or not. The <b>__INLINE</b> attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline the function. As the function is global an callable function is also generated.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="keyword">const</span> uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};</div> +<div class="line"> </div> +<div class="line"><span class="comment">/*------------------------------------------------------------------------------</span></div> +<div class="line"><span class="comment"> Switch on LEDs</span></div> +<div class="line"><span class="comment"> *------------------------------------------------------------------------------*/</span></div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb">__INLINE</a> <span class="keyword">static</span> <span class="keywordtype">void</span> LED_On (uint32_t led) {</div> +<div class="line"> </div> +<div class="line"> PTD->PCOR = led_mask[led];</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga153a4a31b276a9758959580538720a51"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __NO_RETURN</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Informs the compiler that the function does not return. The compiler can then perform optimizations by removing code that is never reached.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="comment">// OS idle demon (running when no other thread is ready to run).</span></div> +<div class="line"> </div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51">__NO_RETURN</a> <span class="keywordtype">void</span> os_idle_demon (<span class="keywordtype">void</span>);</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gabe8996d3d985ee1529475443cc635bf1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __PACKED</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Specifies that a type must have the smallest possible alignment.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="keyword">struct </span>foo {</div> +<div class="line"> uint8_t u8;</div> +<div class="line"> uint32_t u32[2] <a class="code" href="group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1">__PACKED</a>;</div> +<div class="line">};</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga4dbb70fab85207c27b581ecb6532b314"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __PACKED_STRUCT</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Specifies that a structure must have the smallest possible alignment.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314">__PACKED_STRUCT</a> foo {</div> +<div class="line"> uint8_t u8;</div> +<div class="line"> uint32_t u32;</div> +<div class="line"> uint16_t u16;</div> +<div class="line">};</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gaba87361bfad2ae52cfe2f40c1a1dbf9c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __STATIC_INLINE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines a static function that may be inlined by the compiler. If the compiler generates inline code for all calls to this functions, no additional function implementation is generated which may further optimize space.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">\\ Get Interrupt Vector</div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t <a class="code" href="group__NVIC__gr.html#gaebee9cad6724a5bac1857f0f1fb6d6af">NVIC_GetVector</a>(<a class="code" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</div> +<div class="line">{</div> +<div class="line"> uint32_t *vectors = (uint32_t *)SCB->VTOR;</div> +<div class="line"> <span class="keywordflow">return</span> vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gabe8693a7200e573101551d49a1772fb9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __UNALIGNED_UINT16_READ</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint16_t val16;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div> +<div class="line"> val16 = <a class="code" href="group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9">__UNALIGNED_UINT16_READ</a>(ptr);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gadb9cd73446f7e11e92383cd327a23407"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __UNALIGNED_UINT16_WRITE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint16_t val16 = 0U;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div> +<div class="line"> <a class="code" href="group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407">__UNALIGNED_UINT16_WRITE</a>(ptr, val16);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga27fd2ec6767ca1ab66d36b5cc0103268"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __UNALIGNED_UINT32</td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000004">Deprecated:</a></b></dt><dd>Do not use this macro. It has been superseded by <a class="el" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>, <a class="el" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a> and will be removed in the future.</dd></dl> +<p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint32_t val32;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div> +<div class="line"> <a class="code" href="group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268">__UNALIGNED_UINT32</a>(ptr) = val32;</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga254322c344d954c9f829719a50a88e87"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __UNALIGNED_UINT32_READ</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint32_t val32;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div> +<div class="line"> val32 = <a class="code" href="group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87">__UNALIGNED_UINT32_READ</a>(ptr);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gabb2180285c417aa9120a360c51f64b4b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __UNALIGNED_UINT32_WRITE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm processor core and compiler settings.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line">uint32_t val32 = 0U;</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> test (uint8_t *ptr) {</div> +<div class="line"> <a class="code" href="group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b">__UNALIGNED_UINT32_WRITE</a>(ptr, val32);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga3e40e4c553fc11588f7a4c2a19e789e0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __USED</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Definitions tagged with <b>__USED</b> in the source code should be not removed by the linker when detected as unused.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="comment">/* Export following variables for debugging */</span></div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a> uint32_t <span class="keyword">const</span> CMSIS_RTOS_API_Version = osCMSIS;</div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a> uint32_t <span class="keyword">const</span> CMSIS_RTOS_RTX_Version = osCMSIS_RTX;</div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a> uint32_t <span class="keyword">const</span> os_clockrate = OS_TICK;</div> +<div class="line"><a class="code" href="group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0">__USED</a> uint32_t <span class="keyword">const</span> os_timernum = 0;</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gac607bf387b29162be6a9b77fc7999539"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __WEAK</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Functions defined with <b>__WEAK</b> export their symbols weakly. A weakly defined function behaves like a normally defined function unless a non-weakly defined function of the same name is linked into the same image. If both a non-weakly defined function and a weakly defined function exist in the same image then all calls to the function resolve to call the non-weak function.</p> +<p>Functions declared with <b>__WEAK</b> and then defined without <b>__WEAK</b> behave as non-weak functions.</p> +<p><b> Code Example:</b> </p> +<div class="fragment"><div class="line"><a class="code" href="group__compiler__conntrol__gr.html#gac607bf387b29162be6a9b77fc7999539">__WEAK</a> <span class="keywordtype">void</span> <a class="code" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>(<span class="keywordtype">void</span>)</div> +<div class="line">{</div> +<div class="line"> SystemCoreSetup();</div> +<div class="line"> SystemCoreClockSetup(); </div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__compiler__conntrol__gr.js b/docs/Core/html/group__compiler__conntrol__gr.js new file mode 100644 index 0000000..87193e4 --- /dev/null +++ b/docs/Core/html/group__compiler__conntrol__gr.js @@ -0,0 +1,22 @@ +var group__compiler__conntrol__gr = +[ + [ "__ALIGNED", "group__compiler__conntrol__gr.html#ga0c58caa5a273e2c21924509a45f8b849", null ], + [ "__ARM_ARCH_6M__", "group__compiler__conntrol__gr.html#ga8be4ebde5d4dd91b161d206545ce59aa", null ], + [ "__ARM_ARCH_7EM__", "group__compiler__conntrol__gr.html#ga43ab3e79ec5ecb615f1f2f6e83e7d48a", null ], + [ "__ARM_ARCH_7M__", "group__compiler__conntrol__gr.html#ga43e1af8bedda108dfc4f8584e6b278a2", null ], + [ "__ARM_ARCH_8M_BASE__", "group__compiler__conntrol__gr.html#gab3f1284f4cdc6c5e5c9c9d4b8ec29b2a", null ], + [ "__ARM_ARCH_8M_MAIN__", "group__compiler__conntrol__gr.html#gad424c7143edd08c982dddad0ff65f4cd", null ], + [ "__ASM", "group__compiler__conntrol__gr.html#ga1378040bcf22428955c6e3ce9c2053cd", null ], + [ "__INLINE", "group__compiler__conntrol__gr.html#gade2d8d7118f8ff49547f60aa0c3382bb", null ], + [ "__NO_RETURN", "group__compiler__conntrol__gr.html#ga153a4a31b276a9758959580538720a51", null ], + [ "__PACKED", "group__compiler__conntrol__gr.html#gabe8996d3d985ee1529475443cc635bf1", null ], + [ "__PACKED_STRUCT", "group__compiler__conntrol__gr.html#ga4dbb70fab85207c27b581ecb6532b314", null ], + [ "__STATIC_INLINE", "group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c", null ], + [ "__UNALIGNED_UINT16_READ", "group__compiler__conntrol__gr.html#gabe8693a7200e573101551d49a1772fb9", null ], + [ "__UNALIGNED_UINT16_WRITE", "group__compiler__conntrol__gr.html#gadb9cd73446f7e11e92383cd327a23407", null ], + [ "__UNALIGNED_UINT32", "group__compiler__conntrol__gr.html#ga27fd2ec6767ca1ab66d36b5cc0103268", null ], + [ "__UNALIGNED_UINT32_READ", "group__compiler__conntrol__gr.html#ga254322c344d954c9f829719a50a88e87", null ], + [ "__UNALIGNED_UINT32_WRITE", "group__compiler__conntrol__gr.html#gabb2180285c417aa9120a360c51f64b4b", null ], + [ "__USED", "group__compiler__conntrol__gr.html#ga3e40e4c553fc11588f7a4c2a19e789e0", null ], + [ "__WEAK", "group__compiler__conntrol__gr.html#gac607bf387b29162be6a9b77fc7999539", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__context__trustzone__functions.html b/docs/Core/html/group__context__trustzone__functions.html new file mode 100644 index 0000000..3bcaf37 --- /dev/null +++ b/docs/Core/html/group__context__trustzone__functions.html @@ -0,0 +1,271 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>RTOS Context Management</title> +<title>CMSIS-Core (Cortex-M): RTOS Context Management</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" 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id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" 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onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span 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class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga926e2ec472535a6d2b8125be1a79e3c0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html#ga926e2ec472535a6d2b8125be1a79e3c0">TZ_InitContextSystem_S</a> (void)</td></tr> +<tr class="memdesc:ga926e2ec472535a6d2b8125be1a79e3c0"><td class="mdescLeft"> </td><td class="mdescRight">Initialize secure context memory system. <a href="#ga926e2ec472535a6d2b8125be1a79e3c0">More...</a><br/></td></tr> +<tr class="separator:ga926e2ec472535a6d2b8125be1a79e3c0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gacd016f166bee549a0d3e970132e64a90"><td class="memItemLeft" align="right" valign="top">TZ_MemoryId_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a> (TZ_ModuleId_t module)</td></tr> +<tr class="memdesc:gacd016f166bee549a0d3e970132e64a90"><td class="mdescLeft"> </td><td class="mdescRight">Allocate context memory for calling secure software modules in TrustZone. <a href="#gacd016f166bee549a0d3e970132e64a90">More...</a><br/></td></tr> +<tr class="separator:gacd016f166bee549a0d3e970132e64a90"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac84f678fbe974f8b02c683e0b8046524"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html#gac84f678fbe974f8b02c683e0b8046524">TZ_FreeModuleContext_S</a> (TZ_MemoryId_t id)</td></tr> +<tr class="memdesc:gac84f678fbe974f8b02c683e0b8046524"><td class="mdescLeft"> </td><td class="mdescRight">Free context memory that was previously allocated with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a>. <a href="#gac84f678fbe974f8b02c683e0b8046524">More...</a><br/></td></tr> +<tr class="separator:gac84f678fbe974f8b02c683e0b8046524"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4748f6bcdd5fed279ac5a6cd7eca2689"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689">TZ_LoadContext_S</a> (TZ_MemoryId_t id)</td></tr> +<tr class="memdesc:ga4748f6bcdd5fed279ac5a6cd7eca2689"><td class="mdescLeft"> </td><td class="mdescRight">Load secure context (called on RTOS thread context switch) <a href="#ga4748f6bcdd5fed279ac5a6cd7eca2689">More...</a><br/></td></tr> +<tr class="separator:ga4748f6bcdd5fed279ac5a6cd7eca2689"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac106570f4905f82922fd335aeb08a1bf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html#gac106570f4905f82922fd335aeb08a1bf">TZ_StoreContext_S</a> (TZ_MemoryId_t id)</td></tr> +<tr class="memdesc:gac106570f4905f82922fd335aeb08a1bf"><td class="mdescLeft"> </td><td class="mdescRight">Store secure context (called on RTOS thread context switch) <a href="#gac106570f4905f82922fd335aeb08a1bf">More...</a><br/></td></tr> +<tr class="separator:gac106570f4905f82922fd335aeb08a1bf"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to <a class="el" href="using_TrustZone_pg.html#RTOS_TrustZone">RTOS Thread Context Management</a>. </p> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gacd016f166bee549a0d3e970132e64a90"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">TZ_MemoryId_t TZ_AllocModuleContext_S </td> + <td>(</td> + <td class="paramtype">TZ_ModuleId_t </td> + <td class="paramname"><em>module</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Allocates the secure memory regions for thread execution. The parameter <em>module</em> describes the set of secure functions that are called by the non-secure thread. Set <em>module</em> to zero if no secure calls are used/allowed. This leads to no secure memory to be assigned which results in zero being returned as memory id as well. This function should be called by an RTOS kernel at the start of a thread. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">module</td><td>A non-zero value identifies software modules called from non-secure mode. zero is used if no secure calls are used/allowed. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value != 0 id TrustZone memory slot identify </dd> +<dd> +value 0 no memory available or internal error </dd></dl> + +</div> +</div> +<a class="anchor" id="gac84f678fbe974f8b02c683e0b8046524"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_FreeModuleContext_S </td> + <td>(</td> + <td class="paramtype">TZ_MemoryId_t </td> + <td class="paramname"><em>id</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>De-allocates the secure memory regions. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a>. This function should be called by an RTOS kernel at the termination of a thread. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>TrustZone memory slot identifier </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>execution status (1: success, 0: error) </dd></dl> + +</div> +</div> +<a class="anchor" id="ga926e2ec472535a6d2b8125be1a79e3c0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_InitContextSystem_S </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initializes the memory allocation management for the secure memory regions. As a minimum the secure thread mode stack will be provided. </p> +<dl class="section return"><dt>Returns</dt><dd>execution status (1: success, 0: error) </dd></dl> + +</div> +</div> +<a class="anchor" id="ga4748f6bcdd5fed279ac5a6cd7eca2689"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_LoadContext_S </td> + <td>(</td> + <td class="paramtype">TZ_MemoryId_t </td> + <td class="paramname"><em>id</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Prepare the secure context for execution so that a thread in the non-secure state can call secure library modules. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a> which might be zero if not used. This function should be called by an RTOS kernel at thread context switch before running a thread. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>TrustZone memory slot identifier </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>execution status (1: success, 0: error) </dd></dl> + +</div> +</div> +<a class="anchor" id="gac106570f4905f82922fd335aeb08a1bf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_StoreContext_S </td> + <td>(</td> + <td class="paramtype">TZ_MemoryId_t </td> + <td class="paramname"><em>id</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Free the secure context that has been previously loaded with <a class="el" href="group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689">TZ_LoadContext_S</a>. The parameter <em>id</em> refers to a TrustZone memory slot that has been obtained with <a class="el" href="group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90">TZ_AllocModuleContext_S</a> which might be zero if not used. This function should be called by an RTOS kernel at thread context switch after running a thread. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">id</td><td>TrustZone memory slot identifier </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>execution status (1: success, 0: error) </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__context__trustzone__functions.js b/docs/Core/html/group__context__trustzone__functions.js new file mode 100644 index 0000000..fa603e0 --- /dev/null +++ b/docs/Core/html/group__context__trustzone__functions.js @@ -0,0 +1,8 @@ +var group__context__trustzone__functions = +[ + [ "TZ_AllocModuleContext_S", "group__context__trustzone__functions.html#gacd016f166bee549a0d3e970132e64a90", null ], + [ "TZ_FreeModuleContext_S", "group__context__trustzone__functions.html#gac84f678fbe974f8b02c683e0b8046524", null ], + [ "TZ_InitContextSystem_S", "group__context__trustzone__functions.html#ga926e2ec472535a6d2b8125be1a79e3c0", null ], + [ "TZ_LoadContext_S", "group__context__trustzone__functions.html#ga4748f6bcdd5fed279ac5a6cd7eca2689", null ], + [ "TZ_StoreContext_S", "group__context__trustzone__functions.html#gac106570f4905f82922fd335aeb08a1bf", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__coreregister__trustzone__functions.html b/docs/Core/html/group__coreregister__trustzone__functions.html new file mode 100644 index 0000000..84584ac --- /dev/null +++ b/docs/Core/html/group__coreregister__trustzone__functions.html @@ -0,0 +1,610 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Core Register Access Functions</title> +<title>CMSIS-Core (Cortex-M): Core Register Access Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" 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id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" 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+ onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span 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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga27bf1f88e794c30808ee73a29d46e358"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga27bf1f88e794c30808ee73a29d46e358">__TZ_get_CONTROL_NS</a> (void)</td></tr> +<tr class="memdesc:ga27bf1f88e794c30808ee73a29d46e358"><td class="mdescLeft"> </td><td class="mdescRight">Get Control register (non-secure) <a href="#ga27bf1f88e794c30808ee73a29d46e358">More...</a><br/></td></tr> +<tr class="separator:ga27bf1f88e794c30808ee73a29d46e358"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3eb150204e6d389d5b49065179b9cde5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga3eb150204e6d389d5b49065179b9cde5">__TZ_set_CONTROL_NS</a> (uint32_t control)</td></tr> +<tr class="memdesc:ga3eb150204e6d389d5b49065179b9cde5"><td class="mdescLeft"> </td><td class="mdescRight">Set Control register (non-secure) <a href="#ga3eb150204e6d389d5b49065179b9cde5">More...</a><br/></td></tr> +<tr class="separator:ga3eb150204e6d389d5b49065179b9cde5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga40ff8336c6d09af6da1081d4e4adc126"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga40ff8336c6d09af6da1081d4e4adc126">__TZ_get_PSP_NS</a> (void)</td></tr> +<tr class="memdesc:ga40ff8336c6d09af6da1081d4e4adc126"><td class="mdescLeft"> </td><td class="mdescRight">Get Process Stack Pointer (non-secure) <a href="#ga40ff8336c6d09af6da1081d4e4adc126">More...</a><br/></td></tr> +<tr class="separator:ga40ff8336c6d09af6da1081d4e4adc126"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaea8db21c00cfa4144ee74dc65dbd7580"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gaea8db21c00cfa4144ee74dc65dbd7580">__TZ_set_PSP_NS</a> (uint32_t topOfProcStack)</td></tr> +<tr class="memdesc:gaea8db21c00cfa4144ee74dc65dbd7580"><td class="mdescLeft"> </td><td class="mdescRight">Set Process Stack Pointer (non-secure) <a href="#gaea8db21c00cfa4144ee74dc65dbd7580">More...</a><br/></td></tr> +<tr class="separator:gaea8db21c00cfa4144ee74dc65dbd7580"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab3aa15eb4f352e230b9f7a3e8856a9e9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gab3aa15eb4f352e230b9f7a3e8856a9e9">__TZ_get_MSP_NS</a> (void)</td></tr> +<tr class="memdesc:gab3aa15eb4f352e230b9f7a3e8856a9e9"><td class="mdescLeft"> </td><td class="mdescRight">Get Main Stack Pointer (non-secure) <a href="#gab3aa15eb4f352e230b9f7a3e8856a9e9">More...</a><br/></td></tr> +<tr class="separator:gab3aa15eb4f352e230b9f7a3e8856a9e9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga41c3ac2d9af23c40647c053ad7d564e7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga41c3ac2d9af23c40647c053ad7d564e7">__TZ_set_MSP_NS</a> (uint32_t topOfMainStack)</td></tr> +<tr class="memdesc:ga41c3ac2d9af23c40647c053ad7d564e7"><td class="mdescLeft"> </td><td class="mdescRight">Set Main Stack Pointer (non-secure) <a href="#ga41c3ac2d9af23c40647c053ad7d564e7">More...</a><br/></td></tr> +<tr class="separator:ga41c3ac2d9af23c40647c053ad7d564e7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaaaf2aaf904b25ed17fd3e5e63f8e029b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gaaaf2aaf904b25ed17fd3e5e63f8e029b">__TZ_get_SP_NS</a> (void)</td></tr> +<tr class="memdesc:gaaaf2aaf904b25ed17fd3e5e63f8e029b"><td class="mdescLeft"> </td><td class="mdescRight">Get Stack Pointer (non-secure) <a href="#gaaaf2aaf904b25ed17fd3e5e63f8e029b">More...</a><br/></td></tr> +<tr class="separator:gaaaf2aaf904b25ed17fd3e5e63f8e029b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab7263167cb006aeeb04b68e579dae015"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gab7263167cb006aeeb04b68e579dae015">__TZ_set_SP_NS</a> (uint32_t topOfStack)</td></tr> +<tr class="memdesc:gab7263167cb006aeeb04b68e579dae015"><td class="mdescLeft"> </td><td class="mdescRight">Set Stack Pointer (non-secure) <a href="#gab7263167cb006aeeb04b68e579dae015">More...</a><br/></td></tr> +<tr class="separator:gab7263167cb006aeeb04b68e579dae015"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7cc3271c79e619f8838e8767df3cb509"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga7cc3271c79e619f8838e8767df3cb509">__TZ_get_PRIMASK_NS</a> (void)</td></tr> +<tr class="memdesc:ga7cc3271c79e619f8838e8767df3cb509"><td class="mdescLeft"> </td><td class="mdescRight">Get Priority Mask (non-secure) <a href="#ga7cc3271c79e619f8838e8767df3cb509">More...</a><br/></td></tr> +<tr class="separator:ga7cc3271c79e619f8838e8767df3cb509"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga6686c2ab5756b5049fad1644e89b3340"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga6686c2ab5756b5049fad1644e89b3340">__TZ_set_PRIMASK_NS</a> (uint32_t priMask)</td></tr> +<tr class="memdesc:ga6686c2ab5756b5049fad1644e89b3340"><td class="mdescLeft"> </td><td class="mdescRight">Set Priority Mask (non-secure) <a href="#ga6686c2ab5756b5049fad1644e89b3340">More...</a><br/></td></tr> +<tr class="separator:ga6686c2ab5756b5049fad1644e89b3340"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga624509c924d2583f0d4dca6ab270f051"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051">__TZ_get_BASEPRI_NS</a> (void)</td></tr> +<tr class="memdesc:ga624509c924d2583f0d4dca6ab270f051"><td class="mdescLeft"> </td><td class="mdescRight">Get Base Priority (non-secure) <a href="#ga624509c924d2583f0d4dca6ab270f051">More...</a><br/></td></tr> +<tr class="separator:ga624509c924d2583f0d4dca6ab270f051"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga92c187f0b4d53627b59e0fd0bda0b0df"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga92c187f0b4d53627b59e0fd0bda0b0df">__TZ_set_BASEPRI_NS</a> (uint32_t basePri)</td></tr> +<tr class="memdesc:ga92c187f0b4d53627b59e0fd0bda0b0df"><td class="mdescLeft"> </td><td class="mdescRight">Set Base Priority (non-secure) <a href="#ga92c187f0b4d53627b59e0fd0bda0b0df">More...</a><br/></td></tr> +<tr class="separator:ga92c187f0b4d53627b59e0fd0bda0b0df"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga578b41087f207e1a475daae6cc8a28dc"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga578b41087f207e1a475daae6cc8a28dc">__TZ_get_FAULTMASK_NS</a> (void)</td></tr> +<tr class="memdesc:ga578b41087f207e1a475daae6cc8a28dc"><td class="mdescLeft"> </td><td class="mdescRight">Get Fault Mask (non-secure) <a href="#ga578b41087f207e1a475daae6cc8a28dc">More...</a><br/></td></tr> +<tr class="separator:ga578b41087f207e1a475daae6cc8a28dc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4f0912db7bc65439d23817c1d372a7a4"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga4f0912db7bc65439d23817c1d372a7a4">__TZ_set_FAULTMASK_NS</a> (uint32_t faultMask)</td></tr> +<tr class="memdesc:ga4f0912db7bc65439d23817c1d372a7a4"><td class="mdescLeft"> </td><td class="mdescRight">Set Fault Mask (non-secure) <a href="#ga4f0912db7bc65439d23817c1d372a7a4">More...</a><br/></td></tr> +<tr class="separator:ga4f0912db7bc65439d23817c1d372a7a4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5da646ec291b6a183f38497ce92be51c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga5da646ec291b6a183f38497ce92be51c">__TZ_get_PSPLIM_NS</a> (void)</td></tr> +<tr class="memdesc:ga5da646ec291b6a183f38497ce92be51c"><td class="mdescLeft"> </td><td class="mdescRight">Get Process Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. <a href="#ga5da646ec291b6a183f38497ce92be51c">More...</a><br/></td></tr> +<tr class="separator:ga5da646ec291b6a183f38497ce92be51c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga81e0995ee0fd2a9dcd9e9681bc22c76f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#ga81e0995ee0fd2a9dcd9e9681bc22c76f">__TZ_set_PSPLIM_NS</a> (uint32_t ProcStackPtrLimit)</td></tr> +<tr class="memdesc:ga81e0995ee0fd2a9dcd9e9681bc22c76f"><td class="mdescLeft"> </td><td class="mdescRight">Set Process Stack Pointer (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. <a href="#ga81e0995ee0fd2a9dcd9e9681bc22c76f">More...</a><br/></td></tr> +<tr class="separator:ga81e0995ee0fd2a9dcd9e9681bc22c76f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gada00853d3e49fa8d21f375c53d28fa51"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gada00853d3e49fa8d21f375c53d28fa51">__TZ_get_MSPLIM_NS</a> (void)</td></tr> +<tr class="memdesc:gada00853d3e49fa8d21f375c53d28fa51"><td class="mdescLeft"> </td><td class="mdescRight">Get Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. <a href="#gada00853d3e49fa8d21f375c53d28fa51">More...</a><br/></td></tr> +<tr class="separator:gada00853d3e49fa8d21f375c53d28fa51"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad2013f4d4311d6db253594a12d192617"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html#gad2013f4d4311d6db253594a12d192617">__TZ_set_MSPLIM_NS</a> (uint32_t MainStackPtrLimit)</td></tr> +<tr class="memdesc:gad2013f4d4311d6db253594a12d192617"><td class="mdescLeft"> </td><td class="mdescRight">Set Main Stack Pointer Limit (non-secure) Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always. <a href="#gad2013f4d4311d6db253594a12d192617">More...</a><br/></td></tr> +<tr class="separator:gad2013f4d4311d6db253594a12d192617"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga624509c924d2583f0d4dca6ab270f051"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_BASEPRI_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Base Priority register when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>Base Priority register value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga32da759f46e52c95bcfbde5012260667">__get_BASEPRI</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga27bf1f88e794c30808ee73a29d46e358"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_CONTROL_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the content of the non-secure Control register when in secure mode. </p> +<dl class="section return"><dt>Returns</dt><dd>non-secure Control register value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga963cf236b73219ce78e965deb01b81a7">__get_CONTROL</a>; <a class="el" href="unionCONTROL__Type.html" title="Union type to access the Control Registers (CONTROL). ">CONTROL_Type</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga578b41087f207e1a475daae6cc8a28dc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_FAULTMASK_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Fault Mask register when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>Fault Mask register value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">__get_FAULTMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gab3aa15eb4f352e230b9f7a3e8856a9e9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_MSP_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>MSP register value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gab898559392ba027814e5bbb5a98b38d2">__get_MSP</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gada00853d3e49fa8d21f375c53d28fa51"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_MSPLIM_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>MSPLIM register value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga7cc3271c79e619f8838e8767df3cb509"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_PRIMASK_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current state of the non-secure priority mask bit from the Priority Mask register when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>Priority Mask value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">__get_PRIMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga40ff8336c6d09af6da1081d4e4adc126"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_PSP_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>PSP register value </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">__get_PSP</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga5da646ec291b6a183f38497ce92be51c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_PSPLIM_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>PSPLIM register value </dd></dl> + +</div> +</div> +<a class="anchor" id="gaaaf2aaf904b25ed17fd3e5e63f8e029b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __TZ_get_SP_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns the current value of the non-secure Stack Pointer (SP) when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>SP register value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga92c187f0b4d53627b59e0fd0bda0b0df"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_BASEPRI_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>basePri</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Base Priority register when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">basePri</td><td>Base Priority value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga360c73eb7ffb16088556f9278953b882">__set_BASEPRI</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga3eb150204e6d389d5b49065179b9cde5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_CONTROL_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>control</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Writes the given value to the non-secure Control register when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">control</td><td>Control register value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">__set_CONTROL</a>; <a class="el" href="unionCONTROL__Type.html" title="Union type to access the Control Registers (CONTROL). ">CONTROL_Type</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga4f0912db7bc65439d23817c1d372a7a4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_FAULTMASK_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>faultMask</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Fault Mask register when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">faultMask</td><td>Fault Mask value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#gaa5587cc09031053a40a35c14ec36078a">__set_FAULTMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga41c3ac2d9af23c40647c053ad7d564e7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_MSP_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>topOfMainStack</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">topOfMainStack</td><td>Main Stack Pointer value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">__set_MSP</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gad2013f4d4311d6db253594a12d192617"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_MSPLIM_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MainStackPtrLimit</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">MainStackPtrLimit</td><td>Main Stack Pointer value to set </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga6686c2ab5756b5049fad1644e89b3340"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_PRIMASK_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>priMask</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Priority Mask register when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">priMask</td><td>Priority Mask </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">__set_PRIMASK</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaea8db21c00cfa4144ee74dc65dbd7580"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_PSP_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>topOfProcStack</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">topOfProcStack</td><td>Process Stack Pointer value to set </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__Core__Register__gr.html#ga48e5853f417e17a8a65080f6a605b743">__set_PSP</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga81e0995ee0fd2a9dcd9e9681bc22c76f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_PSPLIM_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ProcStackPtrLimit</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ProcStackPtrLimit</td><td>Process Stack Pointer Limit value to set </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gab7263167cb006aeeb04b68e579dae015"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __TZ_set_SP_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>topOfStack</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">topOfStack</td><td>Stack Pointer value to set </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__coreregister__trustzone__functions.js b/docs/Core/html/group__coreregister__trustzone__functions.js new file mode 100644 index 0000000..fb1bbd3 --- /dev/null +++ b/docs/Core/html/group__coreregister__trustzone__functions.js @@ -0,0 +1,21 @@ +var group__coreregister__trustzone__functions = +[ + [ "__TZ_get_BASEPRI_NS", "group__coreregister__trustzone__functions.html#ga624509c924d2583f0d4dca6ab270f051", null ], + [ "__TZ_get_CONTROL_NS", "group__coreregister__trustzone__functions.html#ga27bf1f88e794c30808ee73a29d46e358", null ], + [ "__TZ_get_FAULTMASK_NS", "group__coreregister__trustzone__functions.html#ga578b41087f207e1a475daae6cc8a28dc", null ], + [ "__TZ_get_MSP_NS", "group__coreregister__trustzone__functions.html#gab3aa15eb4f352e230b9f7a3e8856a9e9", null ], + [ "__TZ_get_MSPLIM_NS", "group__coreregister__trustzone__functions.html#gada00853d3e49fa8d21f375c53d28fa51", null ], + [ "__TZ_get_PRIMASK_NS", "group__coreregister__trustzone__functions.html#ga7cc3271c79e619f8838e8767df3cb509", null ], + [ "__TZ_get_PSP_NS", "group__coreregister__trustzone__functions.html#ga40ff8336c6d09af6da1081d4e4adc126", null ], + [ "__TZ_get_PSPLIM_NS", "group__coreregister__trustzone__functions.html#ga5da646ec291b6a183f38497ce92be51c", null ], + [ "__TZ_get_SP_NS", "group__coreregister__trustzone__functions.html#gaaaf2aaf904b25ed17fd3e5e63f8e029b", null ], + [ "__TZ_set_BASEPRI_NS", "group__coreregister__trustzone__functions.html#ga92c187f0b4d53627b59e0fd0bda0b0df", null ], + [ "__TZ_set_CONTROL_NS", "group__coreregister__trustzone__functions.html#ga3eb150204e6d389d5b49065179b9cde5", null ], + [ "__TZ_set_FAULTMASK_NS", "group__coreregister__trustzone__functions.html#ga4f0912db7bc65439d23817c1d372a7a4", null ], + [ "__TZ_set_MSP_NS", "group__coreregister__trustzone__functions.html#ga41c3ac2d9af23c40647c053ad7d564e7", null ], + [ "__TZ_set_MSPLIM_NS", "group__coreregister__trustzone__functions.html#gad2013f4d4311d6db253594a12d192617", null ], + [ "__TZ_set_PRIMASK_NS", "group__coreregister__trustzone__functions.html#ga6686c2ab5756b5049fad1644e89b3340", null ], + [ "__TZ_set_PSP_NS", "group__coreregister__trustzone__functions.html#gaea8db21c00cfa4144ee74dc65dbd7580", null ], + [ "__TZ_set_PSPLIM_NS", "group__coreregister__trustzone__functions.html#ga81e0995ee0fd2a9dcd9e9681bc22c76f", null ], + [ "__TZ_set_SP_NS", "group__coreregister__trustzone__functions.html#gab7263167cb006aeeb04b68e579dae015", null ] +];
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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">FPU Functions</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions that relate to the Floating-Point Arithmetic Unit. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga6bcad99ce80a0e7e4ddc6f2379081756"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__fpu__functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> (void)</td></tr> +<tr class="memdesc:ga6bcad99ce80a0e7e4ddc6f2379081756"><td class="mdescLeft"> </td><td class="mdescRight">Get the FPU type. <a href="#ga6bcad99ce80a0e7e4ddc6f2379081756">More...</a><br/></td></tr> +<tr class="separator:ga6bcad99ce80a0e7e4ddc6f2379081756"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>Some Cortex-M processors include optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. The Cortex-M processor with FPU is an implementation of the single-precision and double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5). </p> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga6bcad99ce80a0e7e4ddc6f2379081756"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> uint32_t SCB_GetFPUType </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li><b>0</b>: No FPU</li> +<li><b>1</b>: Single precision FPU</li> +<li><b>2</b>: Double + Single precision FPU</li> +</ul> +</dd></dl> +<p>The function returns the implemented FPU type. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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\ No newline at end of file diff --git a/docs/Core/html/group__intrinsic__CPU__gr.html b/docs/Core/html/group__intrinsic__CPU__gr.html new file mode 100644 index 0000000..b11dac6 --- /dev/null +++ b/docs/Core/html/group__intrinsic__CPU__gr.html @@ -0,0 +1,1423 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Intrinsic Functions for CPU Instructions</title> +<title>CMSIS-Core (Cortex-M): Intrinsic Functions for CPU Instructions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" 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id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" 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onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">Intrinsic Functions for CPU Instructions</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions that generate specific Cortex-M CPU Instructions. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">__NOP</a> (void)</td></tr> +<tr class="memdesc:gac71fad9f0a91980fecafcb450ee0a63e"><td class="mdescLeft"> </td><td class="mdescRight">No Operation. <a href="#gac71fad9f0a91980fecafcb450ee0a63e">More...</a><br/></td></tr> +<tr class="separator:gac71fad9f0a91980fecafcb450ee0a63e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">__WFI</a> (void)</td></tr> +<tr class="memdesc:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Interrupt. <a href="#gaed91dfbf3d7d7b7fba8d912fcbeaad88">More...</a><br/></td></tr> +<tr class="separator:gaed91dfbf3d7d7b7fba8d912fcbeaad88"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad3efec76c3bfa2b8528ded530386c563"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (void)</td></tr> +<tr class="memdesc:gad3efec76c3bfa2b8528ded530386c563"><td class="mdescLeft"> </td><td class="mdescRight">Wait For Event. <a href="#gad3efec76c3bfa2b8528ded530386c563">More...</a><br/></td></tr> +<tr class="separator:gad3efec76c3bfa2b8528ded530386c563"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">__SEV</a> (void)</td></tr> +<tr class="memdesc:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="mdescLeft"> </td><td class="mdescRight">Send Event. <a href="#ga3c34da7eb16496ae2668a5b95fa441e7">More...</a><br/></td></tr> +<tr class="separator:ga3c34da7eb16496ae2668a5b95fa441e7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga92f5621626711931da71eaa8bf301af7"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> (uint8_t value)</td></tr> +<tr class="memdesc:ga92f5621626711931da71eaa8bf301af7"><td class="mdescLeft"> </td><td class="mdescRight">Set Breakpoint. <a href="#ga92f5621626711931da71eaa8bf301af7">More...</a><br/></td></tr> +<tr class="separator:ga92f5621626711931da71eaa8bf301af7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga93c09b4709394d81977300d5f84950e5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a> (void)</td></tr> +<tr class="memdesc:ga93c09b4709394d81977300d5f84950e5"><td class="mdescLeft"> </td><td class="mdescRight">Instruction Synchronization Barrier. <a href="#ga93c09b4709394d81977300d5f84950e5">More...</a><br/></td></tr> +<tr class="separator:ga93c09b4709394d81977300d5f84950e5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a> (void)</td></tr> +<tr class="memdesc:gacb2a8ca6eae1ba4b31161578b720c199"><td class="mdescLeft"> </td><td class="mdescRight">Data Synchronization Barrier. <a href="#gacb2a8ca6eae1ba4b31161578b720c199">More...</a><br/></td></tr> +<tr class="separator:gacb2a8ca6eae1ba4b31161578b720c199"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a> (void)</td></tr> +<tr class="memdesc:gab1c9b393641dc2d397b3408fdbe72b96"><td class="mdescLeft"> </td><td class="mdescRight">Data Memory Barrier. <a href="#gab1c9b393641dc2d397b3408fdbe72b96">More...</a><br/></td></tr> +<tr class="separator:gab1c9b393641dc2d397b3408fdbe72b96"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">__REV</a> (uint32_t value)</td></tr> +<tr class="memdesc:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (32 bit) <a href="#ga4717abc17af5ba29b1e4c055e0a0d9b8">More...</a><br/></td></tr> +<tr class="separator:ga4717abc17af5ba29b1e4c055e0a0d9b8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a> (uint32_t value)</td></tr> +<tr class="memdesc:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <a href="#gaeef6f853b6df3a365c838ee5b49a7a26">More...</a><br/></td></tr> +<tr class="separator:gaeef6f853b6df3a365c838ee5b49a7a26"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">__REVSH</a> (int32_t value)</td></tr> +<tr class="memdesc:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="mdescLeft"> </td><td class="mdescRight">Reverse byte order (16 bit) <a href="#ga1ec006e6d79063363cb0c2a2e0b3adbe">More...</a><br/></td></tr> +<tr class="separator:ga1ec006e6d79063363cb0c2a2e0b3adbe"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad6f9f297f6b91a995ee199fbc796b863"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a> (uint32_t value)</td></tr> +<tr class="memdesc:gad6f9f297f6b91a995ee199fbc796b863"><td class="mdescLeft"> </td><td class="mdescRight">Reverse bit order of value. <a href="#gad6f9f297f6b91a995ee199fbc796b863">More...</a><br/></td></tr> +<tr class="separator:gad6f9f297f6b91a995ee199fbc796b863"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a> (uint32_t value, uint32_t shift)</td></tr> +<tr class="memdesc:gaf66beb577bb9d90424c3d1d7f684c024"><td class="mdescLeft"> </td><td class="mdescRight">Rotate a value right by a number of bits. <a href="#gaf66beb577bb9d90424c3d1d7f684c024">More...</a><br/></td></tr> +<tr class="separator:gaf66beb577bb9d90424c3d1d7f684c024"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a> (volatile uint8_t *addr)</td></tr> +<tr class="memdesc:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga9e3ac13d8dcf4331176b624cf6234a7e">More...</a><br/></td></tr> +<tr class="separator:ga9e3ac13d8dcf4331176b624cf6234a7e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a> (volatile uint16_t *addr)</td></tr> +<tr class="memdesc:ga9feffc093d6f68b120d592a7a0d45a15"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga9feffc093d6f68b120d592a7a0d45a15">More...</a><br/></td></tr> +<tr class="separator:ga9feffc093d6f68b120d592a7a0d45a15"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a> (volatile uint32_t *addr)</td></tr> +<tr class="memdesc:gabd78840a0f2464905b7cec791ebc6a4c"><td class="mdescLeft"> </td><td class="mdescRight">LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gabd78840a0f2464905b7cec791ebc6a4c">More...</a><br/></td></tr> +<tr class="separator:gabd78840a0f2464905b7cec791ebc6a4c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a> (uint8_t value, volatile uint8_t *addr)</td></tr> +<tr class="memdesc:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#gaab6482d1f59f59e2b6b7efc1af391c99">More...</a><br/></td></tr> +<tr class="separator:gaab6482d1f59f59e2b6b7efc1af391c99"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a> (uint16_t value, volatile uint16_t *addr)</td></tr> +<tr class="memdesc:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga0a354bdf71caa52f081a4a54e84c8d2a">More...</a><br/></td></tr> +<tr class="separator:ga0a354bdf71caa52f081a4a54e84c8d2a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> (uint32_t value, volatile uint32_t *addr)</td></tr> +<tr class="memdesc:ga335deaaa7991490e1450cb7d1e4c5197"><td class="mdescLeft"> </td><td class="mdescRight">STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga335deaaa7991490e1450cb7d1e4c5197">More...</a><br/></td></tr> +<tr class="separator:ga335deaaa7991490e1450cb7d1e4c5197"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> (void)</td></tr> +<tr class="memdesc:ga354c5ac8870cc3dfb823367af9c4b412"><td class="mdescLeft"> </td><td class="mdescRight">Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga354c5ac8870cc3dfb823367af9c4b412">More...</a><br/></td></tr> +<tr class="separator:ga354c5ac8870cc3dfb823367af9c4b412"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga8cfeb5ffe0e49ec6b29dafdde92e5118">__SSAT</a> (int32_t value, uint32_t sat)</td></tr> +<tr class="memdesc:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="mdescLeft"> </td><td class="mdescRight">Signed Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga8cfeb5ffe0e49ec6b29dafdde92e5118">More...</a><br/></td></tr> +<tr class="separator:ga8cfeb5ffe0e49ec6b29dafdde92e5118"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga76bbe4374a5912362866cdc1ded4064a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga76bbe4374a5912362866cdc1ded4064a">__USAT</a> (uint32_t value, uint32_t sat)</td></tr> +<tr class="memdesc:ga76bbe4374a5912362866cdc1ded4064a"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned Saturate [not for Cortex-M0, Cortex-M0+, or SC000]. <a href="#ga76bbe4374a5912362866cdc1ded4064a">More...</a><br/></td></tr> +<tr class="separator:ga76bbe4374a5912362866cdc1ded4064a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga90884c591ac5d73d6069334eba9d6c02"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> (uint32_t value)</td></tr> +<tr class="memdesc:ga90884c591ac5d73d6069334eba9d6c02"><td class="mdescLeft"> </td><td class="mdescRight">Count leading zeros. <a href="#ga90884c591ac5d73d6069334eba9d6c02">More...</a><br/></td></tr> +<tr class="separator:ga90884c591ac5d73d6069334eba9d6c02"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac09134f1bf9c49db07282001afcc9380"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> (uint32_t value)</td></tr> +<tr class="memdesc:gac09134f1bf9c49db07282001afcc9380"><td class="mdescLeft"> </td><td class="mdescRight">Rotate Right with Extend (32 bit) <a href="#gac09134f1bf9c49db07282001afcc9380">More...</a><br/></td></tr> +<tr class="separator:gac09134f1bf9c49db07282001afcc9380"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9464d75db32846aa8295c3c3adfacb41"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a> (uint8_t ptr)</td></tr> +<tr class="memdesc:ga9464d75db32846aa8295c3c3adfacb41"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (8 bit) <a href="#ga9464d75db32846aa8295c3c3adfacb41">More...</a><br/></td></tr> +<tr class="separator:ga9464d75db32846aa8295c3c3adfacb41"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a> (uint16_t ptr)</td></tr> +<tr class="memdesc:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (16 bit) <a href="#gaa762b8bc5634ce38cb14d62a6b2aee32">More...</a><br/></td></tr> +<tr class="separator:gaa762b8bc5634ce38cb14d62a6b2aee32"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a> (uint32_t ptr)</td></tr> +<tr class="memdesc:ga616504f5da979ba8a073d428d6e8d5c7"><td class="mdescLeft"> </td><td class="mdescRight">LDRT Unprivileged (32 bit) <a href="#ga616504f5da979ba8a073d428d6e8d5c7">More...</a><br/></td></tr> +<tr class="separator:ga616504f5da979ba8a073d428d6e8d5c7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a> (uint8_t value, uint8_t ptr)</td></tr> +<tr class="memdesc:gad41aa59c92c0a165b7f98428d3320cd5"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (8 bit) <a href="#gad41aa59c92c0a165b7f98428d3320cd5">More...</a><br/></td></tr> +<tr class="separator:gad41aa59c92c0a165b7f98428d3320cd5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a> (uint16_t value, uint16_t ptr)</td></tr> +<tr class="memdesc:ga2b5d93b8e461755b1072a03df3f1722e"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (16 bit) <a href="#ga2b5d93b8e461755b1072a03df3f1722e">More...</a><br/></td></tr> +<tr class="separator:ga2b5d93b8e461755b1072a03df3f1722e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> (uint32_t value, uint32_t ptr)</td></tr> +<tr class="memdesc:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="mdescLeft"> </td><td class="mdescRight">STRT Unprivileged (32 bit) <a href="#ga625bc4ac0b1d50de9bcd13d9f050030e">More...</a><br/></td></tr> +<tr class="separator:ga625bc4ac0b1d50de9bcd13d9f050030e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga263b9b2d9c06d731022873acddb6aa3f">__LDAB</a> (volatile uint8_t *ptr)</td></tr> +<tr class="memdesc:ga263b9b2d9c06d731022873acddb6aa3f"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (8 bit) <a href="#ga263b9b2d9c06d731022873acddb6aa3f">More...</a><br/></td></tr> +<tr class="separator:ga263b9b2d9c06d731022873acddb6aa3f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5810ac0b87a37e321c2f909cd3860499"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5810ac0b87a37e321c2f909cd3860499">__LDAH</a> (volatile uint16_t *ptr)</td></tr> +<tr class="memdesc:ga5810ac0b87a37e321c2f909cd3860499"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (16 bit) <a href="#ga5810ac0b87a37e321c2f909cd3860499">More...</a><br/></td></tr> +<tr class="separator:ga5810ac0b87a37e321c2f909cd3860499"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga22a24f416b65c2f5a82d9f1162d9394d">__LDA</a> (volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire (32 bit) <a href="#ga22a24f416b65c2f5a82d9f1162d9394d">More...</a><br/></td></tr> +<tr class="separator:ga22a24f416b65c2f5a82d9f1162d9394d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gace025d3a1f85d2ab9bae7288838d6bc8">__STLB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr> +<tr class="memdesc:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (8 bit) <a href="#gace025d3a1f85d2ab9bae7288838d6bc8">More...</a><br/></td></tr> +<tr class="separator:gace025d3a1f85d2ab9bae7288838d6bc8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga25691650de536f9b248b15f6dc4a3e70"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga25691650de536f9b248b15f6dc4a3e70">__STLH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr> +<tr class="memdesc:ga25691650de536f9b248b15f6dc4a3e70"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (16 bit) <a href="#ga25691650de536f9b248b15f6dc4a3e70">More...</a><br/></td></tr> +<tr class="separator:ga25691650de536f9b248b15f6dc4a3e70"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga5429d7083fb8d30c43cecd3a861e1672">__STL</a> (uint32_t value, volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:ga5429d7083fb8d30c43cecd3a861e1672"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release (32 bit) <a href="#ga5429d7083fb8d30c43cecd3a861e1672">More...</a><br/></td></tr> +<tr class="separator:ga5429d7083fb8d30c43cecd3a861e1672"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga513beada40cdd7123281f22482603bcc"><td class="memItemLeft" align="right" valign="top">uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga513beada40cdd7123281f22482603bcc">__LDAEXB</a> (volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:ga513beada40cdd7123281f22482603bcc"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (8 bit) <a href="#ga513beada40cdd7123281f22482603bcc">More...</a><br/></td></tr> +<tr class="separator:ga513beada40cdd7123281f22482603bcc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memItemLeft" align="right" valign="top">uint16_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga426b61640fc68f21b21ae4dc2726f3b4">__LDAEXH</a> (volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (16 bit) <a href="#ga426b61640fc68f21b21ae4dc2726f3b4">More...</a><br/></td></tr> +<tr class="separator:ga426b61640fc68f21b21ae4dc2726f3b4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3c74d923529f664eda099d1b2668b3c1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga3c74d923529f664eda099d1b2668b3c1">__LDAEX</a> (volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:ga3c74d923529f664eda099d1b2668b3c1"><td class="mdescLeft"> </td><td class="mdescRight">Load-Acquire Exclusive (32 bit) <a href="#ga3c74d923529f664eda099d1b2668b3c1">More...</a><br/></td></tr> +<tr class="separator:ga3c74d923529f664eda099d1b2668b3c1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga590724a32a229978536fbbbd6cc82536"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga590724a32a229978536fbbbd6cc82536">__STLEXB</a> (uint8_t value, volatile uint8_t *ptr)</td></tr> +<tr class="memdesc:ga590724a32a229978536fbbbd6cc82536"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (8 bit) <a href="#ga590724a32a229978536fbbbd6cc82536">More...</a><br/></td></tr> +<tr class="separator:ga590724a32a229978536fbbbd6cc82536"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga047c3bebca3d0ae348ab8370a046301d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#ga047c3bebca3d0ae348ab8370a046301d">__STLEXH</a> (uint16_t value, volatile uint16_t *ptr)</td></tr> +<tr class="memdesc:ga047c3bebca3d0ae348ab8370a046301d"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (16 bit) <a href="#ga047c3bebca3d0ae348ab8370a046301d">More...</a><br/></td></tr> +<tr class="separator:ga047c3bebca3d0ae348ab8370a046301d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae7f955b91595cfd82a03e4b437c59afe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__CPU__gr.html#gae7f955b91595cfd82a03e4b437c59afe">__STLEX</a> (uint32_t value, volatile uint32_t *ptr)</td></tr> +<tr class="memdesc:gae7f955b91595cfd82a03e4b437c59afe"><td class="mdescLeft"> </td><td class="mdescRight">Store-Release Exclusive (32 bit) <a href="#gae7f955b91595cfd82a03e4b437c59afe">More...</a><br/></td></tr> +<tr class="separator:gae7f955b91595cfd82a03e4b437c59afe"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler. Refer to the <a class="el" href="index.html#ref_man_sec">Cortex-M Reference Manuals</a> for detailed information about these Cortex-M instructions.</p> +<dl class="section note"><dt>Note</dt><dd>When using the <b>Arm Compiler Version 5 Toolchain</b> the following <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> are implemented using the Embedded Assembler. As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information) it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><em>define __NO_EMBEDDED_ASM</em></b>:<ul> +<li><a class="el" href="group__intrinsic__CPU__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">__REV16</a></li> +<li><a class="el" href="group__intrinsic__CPU__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">__REVSH</a></li> +<li><a class="el" href="group__intrinsic__CPU__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a> </li> +</ul> +</dd></dl> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga92f5621626711931da71eaa8bf301af7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __BKPT </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga354c5ac8870cc3dfb823367af9c4b412"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __CLREX </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000]. </p> + +</div> +</div> +<a class="anchor" id="ga90884c591ac5d73d6069334eba9d6c02"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t __CLZ </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function counts the number of leading zeros of a data value.</p> +<p>On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction instruction and thus __CLZ is implemented in software.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to count the leading zeros </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>number of leading zeros in value </dd></dl> + +</div> +</div> +<a class="anchor" id="gab1c9b393641dc2d397b3408fdbe72b96"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __DMB </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. </p> + +</div> +</div> +<a class="anchor" id="gacb2a8ca6eae1ba4b31161578b720c199"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __DSB </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. </p> + +</div> +</div> +<a class="anchor" id="ga93c09b4709394d81977300d5f84950e5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __ISB </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. </p> + +</div> +</div> +<a class="anchor" id="ga22a24f416b65c2f5a82d9f1162d9394d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __LDA </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDA instruction for 32 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga263b9b2d9c06d731022873acddb6aa3f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t __LDAB </td> + <td>(</td> + <td class="paramtype">volatile uint8_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDAB instruction for 8 bit value. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3c74d923529f664eda099d1b2668b3c1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __LDAEX </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDA exclusive instruction for 32 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga513beada40cdd7123281f22482603bcc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t __LDAEXB </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDAB exclusive instruction for 8 bit value. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga426b61640fc68f21b21ae4dc2726f3b4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint16_t __LDAEXH </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDAH exclusive instruction for 16 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5810ac0b87a37e321c2f909cd3860499"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint16_t __LDAH </td> + <td>(</td> + <td class="paramtype">volatile uint16_t * </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a LDAH instruction for 16 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9464d75db32846aa8295c3c3adfacb41"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t __LDRBT </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged LDRT command for 8 bit value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*ptr) </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9e3ac13d8dcf4331176b624cf6234a7e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint8_t __LDREXB </td> + <td>(</td> + <td class="paramtype">volatile uint8_t * </td> + <td class="paramname"><em>addr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint8_t at (*addr) </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9feffc093d6f68b120d592a7a0d45a15"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint16_t __LDREXH </td> + <td>(</td> + <td class="paramtype">volatile uint16_t * </td> + <td class="paramname"><em>addr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*addr) </dd></dl> + +</div> +</div> +<a class="anchor" id="gabd78840a0f2464905b7cec791ebc6a4c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __LDREXW </td> + <td>(</td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>addr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*addr) </dd></dl> + +</div> +</div> +<a class="anchor" id="gaa762b8bc5634ce38cb14d62a6b2aee32"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint16_t __LDRHT </td> + <td>(</td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged LDRT command for 16 bit values.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint16_t at (*ptr) </dd></dl> + +</div> +</div> +<a class="anchor" id="ga616504f5da979ba8a073d428d6e8d5c7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __LDRT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ptr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged LDRT command for 32 bit values.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to data </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>value of type uint32_t at (*ptr) </dd></dl> + +</div> +</div> +<a class="anchor" id="gac71fad9f0a91980fecafcb450ee0a63e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __NOP </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function does nothing. This instruction can be used for code alignment purposes. </p> + +</div> +</div> +<a class="anchor" id="gad6f9f297f6b91a995ee199fbc796b863"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __RBIT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga4717abc17af5ba29b1e4c055e0a0d9b8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __REV </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl> + +</div> +</div> +<a class="anchor" id="gaeef6f853b6df3a365c838ee5b49a7a26"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __REV16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga1ec006e6d79063363cb0c2a2e0b3adbe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t __REVSH </td> + <td>(</td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to reverse </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Reversed value </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf66beb577bb9d90424c3d1d7f684c024"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __ROR </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>shift</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function rotates a value right by a specified number of bits.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be shifted right </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">shift</td><td>Number of bits in the range [1..31] </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl> + +</div> +</div> +<a class="anchor" id="gac09134f1bf9c49db07282001afcc9380"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __RRX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to rotate </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Rotated value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3c34da7eb16496ae2668a5b95fa441e7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __SEV </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Send Event is a hint instruction. It causes an event to be signaled to the CPU. </p> + +</div> +</div> +<a class="anchor" id="ga8cfeb5ffe0e49ec6b29dafdde92e5118"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">int32_t __SSAT </td> + <td>(</td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>sat</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function saturates a signed value [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [1..32] </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5429d7083fb8d30c43cecd3a861e1672"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STL </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STL instruction for 32 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="gace025d3a1f85d2ab9bae7288838d6bc8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STLB </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint8_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STLB instruction for 8 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="gae7f955b91595cfd82a03e4b437c59afe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STLEX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STL exclusive instruction for 32 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga590724a32a229978536fbbbd6cc82536"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STLEXB </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint8_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STLB exclusive instruction for 8 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga047c3bebca3d0ae348ab8370a046301d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STLEXH </td> + <td>(</td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint16_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STLH exclusive instruction for 16 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga25691650de536f9b248b15f6dc4a3e70"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STLH </td> + <td>(</td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint16_t * </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Executes a STLH instruction for 16 bit values. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only availabe for Armv8-M Architecture. </dd></dl> + +</div> +</div> +<a class="anchor" id="gad41aa59c92c0a165b7f98428d3320cd5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STRBT </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged STRT command for 8 bit values.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="gaab6482d1f59f59e2b6b7efc1af391c99"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STREXB </td> + <td>(</td> + <td class="paramtype">uint8_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint8_t * </td> + <td class="paramname"><em>addr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> + +</div> +</div> +<a class="anchor" id="ga0a354bdf71caa52f081a4a54e84c8d2a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STREXH </td> + <td>(</td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint16_t * </td> + <td class="paramname"><em>addr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> + +</div> +</div> +<a class="anchor" id="ga335deaaa7991490e1450cb7d1e4c5197"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __STREXW </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">volatile uint32_t * </td> + <td class="paramname"><em>addr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">*addr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded </dd> +<dd> +1 Function failed </dd></dl> + +</div> +</div> +<a class="anchor" id="ga2b5d93b8e461755b1072a03df3f1722e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STRHT </td> + <td>(</td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint16_t </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged STRT command for 16 bit values.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga625bc4ac0b1d50de9bcd13d9f050030e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __STRT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ptr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function executed an Unprivileged STRT command for 32 bit values.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to store </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">ptr</td><td>Pointer to location </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga76bbe4374a5912362866cdc1ded4064a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>value</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>sat</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function saturates an unsigned value [not for Cortex-M0, Cortex-M0+, or SC000].</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">value</td><td>Value to be saturated </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">sat</td><td>Bit position to saturate to [0..31] </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Saturated value </dd></dl> + +</div> +</div> +<a class="anchor" id="gad3efec76c3bfa2b8528ded530386c563"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __WFE </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Wait For Event is a hint instruction that permits the processor to enter a low-power state until an events occurs: </p> +<ul> +<li>If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:<ul> +<li>An exception, unless masked by the exception mask registers or the current priority level.</li> +<li>An exception enters the Pending state, if SEVONPEND in the System Control Register is set.</li> +<li>A Debug Entry request, if Debug is enabled.</li> +<li>An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction.</li> +</ul> +</li> +</ul> +<ul> +<li>If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately. </li> +</ul> + +</div> +</div> +<a class="anchor" id="gaed91dfbf3d7d7b7fba8d912fcbeaad88"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void __WFI </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>WFI is a hint instruction that suspends execution until one of the following events occurs:</p> +<ul> +<li>A non-masked interrupt occurs and is taken.</li> +<li>An interrupt masked by PRIMASK becomes pending.</li> +<li>A Debug Entry request. </li> +</ul> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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\ No newline at end of file diff --git a/docs/Core/html/group__intrinsic__SIMD__gr.html b/docs/Core/html/group__intrinsic__SIMD__gr.html new file mode 100644 index 0000000..0e323e2 --- /dev/null +++ b/docs/Core/html/group__intrinsic__SIMD__gr.html @@ -0,0 +1,3126 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</title> +<title>CMSIS-Core (Cortex-M): Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" 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onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" 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colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gac20aa0f741d0a1494d58c531e38d5785"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac20aa0f741d0a1494d58c531e38d5785">__SADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gac20aa0f741d0a1494d58c531e38d5785"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit signed addition. <a href="#gac20aa0f741d0a1494d58c531e38d5785">More...</a><br/></td></tr> +<tr class="separator:gac20aa0f741d0a1494d58c531e38d5785"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">__QADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating addition. <a href="#gaf2f5a9132dcfc6d01d34cd971c425713">More...</a><br/></td></tr> +<tr class="separator:gaf2f5a9132dcfc6d01d34cd971c425713"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga524575b442ea01aec10c762bf4d85fea"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga524575b442ea01aec10c762bf4d85fea">__SHADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga524575b442ea01aec10c762bf4d85fea"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed addition with halved results. <a href="#ga524575b442ea01aec10c762bf4d85fea">More...</a><br/></td></tr> +<tr class="separator:ga524575b442ea01aec10c762bf4d85fea"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab3d7fd00d113b20fb3741a17394da762"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab3d7fd00d113b20fb3741a17394da762">__UADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gab3d7fd00d113b20fb3741a17394da762"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned addition. <a href="#gab3d7fd00d113b20fb3741a17394da762">More...</a><br/></td></tr> +<tr class="separator:gab3d7fd00d113b20fb3741a17394da762"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafa9af218db3934a692fb06fa728d8031"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafa9af218db3934a692fb06fa728d8031">__UQADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gafa9af218db3934a692fb06fa728d8031"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating addition. <a href="#gafa9af218db3934a692fb06fa728d8031">More...</a><br/></td></tr> +<tr class="separator:gafa9af218db3934a692fb06fa728d8031"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">__UHADD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned addition with halved results. <a href="#ga3a14e5485e59bf0f23595b7c2a94eb0b">More...</a><br/></td></tr> +<tr class="separator:ga3a14e5485e59bf0f23595b7c2a94eb0b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaba63bb52e1e93fb527e26f3d474da12e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">__SSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gaba63bb52e1e93fb527e26f3d474da12e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit signed subtraction. <a href="#gaba63bb52e1e93fb527e26f3d474da12e">More...</a><br/></td></tr> +<tr class="separator:gaba63bb52e1e93fb527e26f3d474da12e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga753493a65493880c28baa82c151a0d61"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga753493a65493880c28baa82c151a0d61">__QSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga753493a65493880c28baa82c151a0d61"><td class="mdescLeft"> </td><td class="mdescRight">Q setting quad 8-bit saturating subtract. <a href="#ga753493a65493880c28baa82c151a0d61">More...</a><br/></td></tr> +<tr class="separator:ga753493a65493880c28baa82c151a0d61"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac3ec7215b354d925a239f3b31df2b77b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac3ec7215b354d925a239f3b31df2b77b">__SHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gac3ec7215b354d925a239f3b31df2b77b"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit signed subtraction with halved results. <a href="#gac3ec7215b354d925a239f3b31df2b77b">More...</a><br/></td></tr> +<tr class="separator:gac3ec7215b354d925a239f3b31df2b77b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">__USUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="mdescLeft"> </td><td class="mdescRight">GE setting quad 8-bit unsigned subtract. <a href="#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">More...</a><br/></td></tr> +<tr class="separator:gacb7257dc3b8e9acbd0ef0e31ff87d4b8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9736fe816aec74fe886e7fb949734eab"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9736fe816aec74fe886e7fb949734eab">__UQSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga9736fe816aec74fe886e7fb949734eab"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned saturating subtraction. <a href="#ga9736fe816aec74fe886e7fb949734eab">More...</a><br/></td></tr> +<tr class="separator:ga9736fe816aec74fe886e7fb949734eab"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga48a55df1c3e73923b73819d7c19b392d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga48a55df1c3e73923b73819d7c19b392d">__UHSUB8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga48a55df1c3e73923b73819d7c19b392d"><td class="mdescLeft"> </td><td class="mdescRight">Quad 8-bit unsigned subtraction with halved results. <a href="#ga48a55df1c3e73923b73819d7c19b392d">More...</a><br/></td></tr> +<tr class="separator:ga48a55df1c3e73923b73819d7c19b392d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad0bf46373a1c05aabf64517e84be5984"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gad0bf46373a1c05aabf64517e84be5984"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed addition. <a href="#gad0bf46373a1c05aabf64517e84be5984">More...</a><br/></td></tr> +<tr class="separator:gad0bf46373a1c05aabf64517e84be5984"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae83a53ec04b496304bed6d9fe8f7461b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">__QADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gae83a53ec04b496304bed6d9fe8f7461b"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating addition. <a href="#gae83a53ec04b496304bed6d9fe8f7461b">More...</a><br/></td></tr> +<tr class="separator:gae83a53ec04b496304bed6d9fe8f7461b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga15d8899a173effb8ad8c7268da32b60e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga15d8899a173effb8ad8c7268da32b60e"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition with halved results. <a href="#ga15d8899a173effb8ad8c7268da32b60e">More...</a><br/></td></tr> +<tr class="separator:ga15d8899a173effb8ad8c7268da32b60e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">__UADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition. <a href="#gaa1160f0cf76d6aa292fbad54a1aa6b74">More...</a><br/></td></tr> +<tr class="separator:gaa1160f0cf76d6aa292fbad54a1aa6b74"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9e2cc5117e79578a08b25f1e89022966"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9e2cc5117e79578a08b25f1e89022966">__UQADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga9e2cc5117e79578a08b25f1e89022966"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition. <a href="#ga9e2cc5117e79578a08b25f1e89022966">More...</a><br/></td></tr> +<tr class="separator:ga9e2cc5117e79578a08b25f1e89022966"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabd0b0e2da2e6364e176d051687702b86"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gabd0b0e2da2e6364e176d051687702b86">__UHADD16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gabd0b0e2da2e6364e176d051687702b86"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition with halved results. <a href="#gabd0b0e2da2e6364e176d051687702b86">More...</a><br/></td></tr> +<tr class="separator:gabd0b0e2da2e6364e176d051687702b86"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction. <a href="#ga4262f73be75efbac6b46ab7c71aa6cbc">More...</a><br/></td></tr> +<tr class="separator:ga4262f73be75efbac6b46ab7c71aa6cbc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad089605c16df9823a2c8aaa37777aae5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad089605c16df9823a2c8aaa37777aae5">__QSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gad089605c16df9823a2c8aaa37777aae5"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturating subtract. <a href="#gad089605c16df9823a2c8aaa37777aae5">More...</a><br/></td></tr> +<tr class="separator:gad089605c16df9823a2c8aaa37777aae5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">__SHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction with halved results. <a href="#ga31328467f0f91b8ff9ae9a01682ad3bf">More...</a><br/></td></tr> +<tr class="separator:ga31328467f0f91b8ff9ae9a01682ad3bf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">__USUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract. <a href="#ga9f2b77e11fc4a77b26c36c423ed45b4e">More...</a><br/></td></tr> +<tr class="separator:ga9f2b77e11fc4a77b26c36c423ed45b4e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5ec4e2e231d15e5c692233feb3806187"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5ec4e2e231d15e5c692233feb3806187">__UQSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga5ec4e2e231d15e5c692233feb3806187"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction. <a href="#ga5ec4e2e231d15e5c692233feb3806187">More...</a><br/></td></tr> +<tr class="separator:ga5ec4e2e231d15e5c692233feb3806187"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1f7545b8dc33bb97982731cb9d427a69"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">__UHSUB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga1f7545b8dc33bb97982731cb9d427a69"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction with halved results. <a href="#ga1f7545b8dc33bb97982731cb9d427a69">More...</a><br/></td></tr> +<tr class="separator:ga1f7545b8dc33bb97982731cb9d427a69"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5845084fd99c872e98cf5553d554de2a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5845084fd99c872e98cf5553d554de2a">__SASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga5845084fd99c872e98cf5553d554de2a"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit addition and subtraction with exchange. <a href="#ga5845084fd99c872e98cf5553d554de2a">More...</a><br/></td></tr> +<tr class="separator:ga5845084fd99c872e98cf5553d554de2a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga87618799672e1511e33964bc71467eb3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga87618799672e1511e33964bc71467eb3"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit add and subtract with exchange. <a href="#ga87618799672e1511e33964bc71467eb3">More...</a><br/></td></tr> +<tr class="separator:ga87618799672e1511e33964bc71467eb3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae0a649035f67627464fd80e7218c89d5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gae0a649035f67627464fd80e7218c89d5"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed addition and subtraction with halved results. <a href="#gae0a649035f67627464fd80e7218c89d5">More...</a><br/></td></tr> +<tr class="separator:gae0a649035f67627464fd80e7218c89d5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga980353d2c72ebb879282e49f592fddc0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga980353d2c72ebb879282e49f592fddc0">__UASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga980353d2c72ebb879282e49f592fddc0"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned addition and subtraction with exchange. <a href="#ga980353d2c72ebb879282e49f592fddc0">More...</a><br/></td></tr> +<tr class="separator:ga980353d2c72ebb879282e49f592fddc0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5eff3ae5eabcd73f3049996ca391becb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">__UQASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga5eff3ae5eabcd73f3049996ca391becb"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating addition and subtraction with exchange. <a href="#ga5eff3ae5eabcd73f3049996ca391becb">More...</a><br/></td></tr> +<tr class="separator:ga5eff3ae5eabcd73f3049996ca391becb"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga028f0732b961fb6e5209326fb3855261"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga028f0732b961fb6e5209326fb3855261">__UHASX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga028f0732b961fb6e5209326fb3855261"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned addition and subtraction with halved results and exchange. <a href="#ga028f0732b961fb6e5209326fb3855261">More...</a><br/></td></tr> +<tr class="separator:ga028f0732b961fb6e5209326fb3855261"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">__SSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit signed subtraction and addition with exchange. <a href="#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">More...</a><br/></td></tr> +<tr class="separator:ga9d3bc5c539f9bd50f7d59ffa37ac6a65"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab41eb2b17512ab01d476fc9d5bd19520"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gab41eb2b17512ab01d476fc9d5bd19520"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit subtract and add with exchange. <a href="#gab41eb2b17512ab01d476fc9d5bd19520">More...</a><br/></td></tr> +<tr class="separator:gab41eb2b17512ab01d476fc9d5bd19520"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed subtraction and addition with halved results. <a href="#gafadbd89c36b5addcf1ca10dd392db3e9">More...</a><br/></td></tr> +<tr class="separator:gafadbd89c36b5addcf1ca10dd392db3e9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga578a082747436772c482c96d7a58e45e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga578a082747436772c482c96d7a58e45e">__USAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga578a082747436772c482c96d7a58e45e"><td class="mdescLeft"> </td><td class="mdescRight">GE setting dual 16-bit unsigned subtract and add with exchange. <a href="#ga578a082747436772c482c96d7a58e45e">More...</a><br/></td></tr> +<tr class="separator:ga578a082747436772c482c96d7a58e45e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gadecfdfabc328d8939d49d996f2fd4482"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gadecfdfabc328d8939d49d996f2fd4482">__UQSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gadecfdfabc328d8939d49d996f2fd4482"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned saturating subtraction and addition with exchange. <a href="#gadecfdfabc328d8939d49d996f2fd4482">More...</a><br/></td></tr> +<tr class="separator:gadecfdfabc328d8939d49d996f2fd4482"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga09e129e6613329aab87c89f1108b7ed7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga09e129e6613329aab87c89f1108b7ed7">__UHSAX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga09e129e6613329aab87c89f1108b7ed7"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit unsigned subtraction and addition with halved results and exchange. <a href="#ga09e129e6613329aab87c89f1108b7ed7">More...</a><br/></td></tr> +<tr class="separator:ga09e129e6613329aab87c89f1108b7ed7"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac8855c07044239ea775c8128013204f0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac8855c07044239ea775c8128013204f0">__USAD8</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gac8855c07044239ea775c8128013204f0"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference. <a href="#gac8855c07044239ea775c8128013204f0">More...</a><br/></td></tr> +<tr class="separator:gac8855c07044239ea775c8128013204f0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">__USADA8</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="mdescLeft"> </td><td class="mdescRight">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate. <a href="#gad032bd21f013c5d29f5fcb6b0f02bc3f">More...</a><br/></td></tr> +<tr class="separator:gad032bd21f013c5d29f5fcb6b0f02bc3f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga95e666b82216066bf6064d1244e6883c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga95e666b82216066bf6064d1244e6883c">__SSAT16</a> (uint32_t val1, const uint32_t val2)</td></tr> +<tr class="memdesc:ga95e666b82216066bf6064d1244e6883c"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit saturate. <a href="#ga95e666b82216066bf6064d1244e6883c">More...</a><br/></td></tr> +<tr class="separator:ga95e666b82216066bf6064d1244e6883c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga967f516afff5900cf30f1a81907cdd89"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga967f516afff5900cf30f1a81907cdd89">__USAT16</a> (uint32_t val1, const uint32_t val2)</td></tr> +<tr class="memdesc:ga967f516afff5900cf30f1a81907cdd89"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit unsigned saturate. <a href="#ga967f516afff5900cf30f1a81907cdd89">More...</a><br/></td></tr> +<tr class="separator:ga967f516afff5900cf30f1a81907cdd89"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab41d713653b16f8d9fef44d14e397228"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gab41d713653b16f8d9fef44d14e397228">__UXTB16</a> (uint32_t val)</td></tr> +<tr class="memdesc:gab41d713653b16f8d9fef44d14e397228"><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and zero-extend to 16-bits. <a href="#gab41d713653b16f8d9fef44d14e397228">More...</a><br/></td></tr> +<tr class="separator:gab41d713653b16f8d9fef44d14e397228"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad25ce96db0f17096bbd815f4817faf09"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad25ce96db0f17096bbd815f4817faf09">__UXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gad25ce96db0f17096bbd815f4817faf09"><td class="mdescLeft"> </td><td class="mdescRight">Extracted 16-bit to 32-bit unsigned addition. <a href="#gad25ce96db0f17096bbd815f4817faf09">More...</a><br/></td></tr> +<tr class="separator:gad25ce96db0f17096bbd815f4817faf09"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">__SXTB16</a> (uint32_t val)</td></tr> +<tr class="memdesc:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="mdescLeft"> </td><td class="mdescRight">Dual extract 8-bits and sign extend each to 16-bits. <a href="#ga38dce3dd13ba212e80ec3cff4abeb11a">More...</a><br/></td></tr> +<tr class="separator:ga38dce3dd13ba212e80ec3cff4abeb11a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gac540b4fc41d30778ba102d2a65db5589"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gac540b4fc41d30778ba102d2a65db5589">__SXTAB16</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gac540b4fc41d30778ba102d2a65db5589"><td class="mdescLeft"> </td><td class="mdescRight">Dual extracted 8-bit to 16-bit signed addition. <a href="#gac540b4fc41d30778ba102d2a65db5589">More...</a><br/></td></tr> +<tr class="separator:gac540b4fc41d30778ba102d2a65db5589"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae326e368a1624d2dfb4b97c626939257"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gae326e368a1624d2dfb4b97c626939257"><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply. <a href="#gae326e368a1624d2dfb4b97c626939257">More...</a><br/></td></tr> +<tr class="separator:gae326e368a1624d2dfb4b97c626939257"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaee6390f86965cb662500f690b0012092"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaee6390f86965cb662500f690b0012092">__SMUADX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gaee6390f86965cb662500f690b0012092"><td class="mdescLeft"> </td><td class="mdescRight">Q setting sum of dual 16-bit signed multiply with exchange. <a href="#gaee6390f86965cb662500f690b0012092">More...</a><br/></td></tr> +<tr class="separator:gaee6390f86965cb662500f690b0012092"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaea60757232f740ec6b09980eebb614ff"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> (int32_t val1, int32_t val2, int32_t val3)</td></tr> +<tr class="memdesc:gaea60757232f740ec6b09980eebb614ff"><td class="mdescLeft"> </td><td class="mdescRight">32-bit signed multiply with 32-bit truncated accumulator. <a href="#gaea60757232f740ec6b09980eebb614ff">More...</a><br/></td></tr> +<tr class="separator:gaea60757232f740ec6b09980eebb614ff"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae0c86f3298532183f3a29f5bb454d354"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gae0c86f3298532183f3a29f5bb454d354">__SMLAD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:gae0c86f3298532183f3a29f5bb454d354"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with single 32-bit accumulator. <a href="#gae0c86f3298532183f3a29f5bb454d354">More...</a><br/></td></tr> +<tr class="separator:gae0c86f3298532183f3a29f5bb454d354"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9c286d330f4fb29b256335add91eec9f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga9c286d330f4fb29b256335add91eec9f">__SMLADX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:ga9c286d330f4fb29b256335add91eec9f"><td class="mdescLeft"> </td><td class="mdescRight">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator. <a href="#ga9c286d330f4fb29b256335add91eec9f">More...</a><br/></td></tr> +<tr class="separator:ga9c286d330f4fb29b256335add91eec9f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad80e9b20c1736fd798f897362273a146"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad80e9b20c1736fd798f897362273a146">__SMLALD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr> +<tr class="memdesc:gad80e9b20c1736fd798f897362273a146"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with single 64-bit accumulator. <a href="#gad80e9b20c1736fd798f897362273a146">More...</a><br/></td></tr> +<tr class="separator:gad80e9b20c1736fd798f897362273a146"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">__SMLALDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr> +<tr class="memdesc:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange with single 64-bit accumulator. <a href="#gad1adad1b3f2667328cc0db6c6b4f41cf">More...</a><br/></td></tr> +<tr class="separator:gad1adad1b3f2667328cc0db6c6b4f41cf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga039142a5368840683cf329cb55b73f84"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga039142a5368840683cf329cb55b73f84">__SMUSD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga039142a5368840683cf329cb55b73f84"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply returning difference. <a href="#ga039142a5368840683cf329cb55b73f84">More...</a><br/></td></tr> +<tr class="separator:ga039142a5368840683cf329cb55b73f84"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabb5bcba694bf17b141c32e6a8474f60e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">__SMUSDX</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gabb5bcba694bf17b141c32e6a8474f60e"><td class="mdescLeft"> </td><td class="mdescRight">Dual 16-bit signed multiply with exchange returning difference. <a href="#gabb5bcba694bf17b141c32e6a8474f60e">More...</a><br/></td></tr> +<tr class="separator:gabb5bcba694bf17b141c32e6a8474f60e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf4350af7f2030c36f43b2c104a9d16cd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">__SMLSD</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:gaf4350af7f2030c36f43b2c104a9d16cd"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate. <a href="#gaf4350af7f2030c36f43b2c104a9d16cd">More...</a><br/></td></tr> +<tr class="separator:gaf4350af7f2030c36f43b2c104a9d16cd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5290ce5564770ad124910d2583dc0a9e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5290ce5564770ad124910d2583dc0a9e">__SMLSDX</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:ga5290ce5564770ad124910d2583dc0a9e"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate. <a href="#ga5290ce5564770ad124910d2583dc0a9e">More...</a><br/></td></tr> +<tr class="separator:ga5290ce5564770ad124910d2583dc0a9e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga5611f7314e0c8f53da377918dfbf42ee"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">__SMLSLD</a> (uint32_t val1, uint32_t val2, uint64_t val3)</td></tr> +<tr class="memdesc:ga5611f7314e0c8f53da377918dfbf42ee"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate. <a href="#ga5611f7314e0c8f53da377918dfbf42ee">More...</a><br/></td></tr> +<tr class="separator:ga5611f7314e0c8f53da377918dfbf42ee"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga83e69ef81057d3cbd06863d729385187"><td class="memItemLeft" align="right" valign="top">unsigned long long </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga83e69ef81057d3cbd06863d729385187">__SMLSLDX</a> (uint32_t val1, uint32_t val2, unsigned long long val3)</td></tr> +<tr class="memdesc:ga83e69ef81057d3cbd06863d729385187"><td class="mdescLeft"> </td><td class="mdescRight">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate. <a href="#ga83e69ef81057d3cbd06863d729385187">More...</a><br/></td></tr> +<tr class="separator:ga83e69ef81057d3cbd06863d729385187"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf5448e591fe49161b6759b48aecb08fe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaf5448e591fe49161b6759b48aecb08fe">__SEL</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:gaf5448e591fe49161b6759b48aecb08fe"><td class="mdescLeft"> </td><td class="mdescRight">Select bytes based on GE bits. <a href="#gaf5448e591fe49161b6759b48aecb08fe">More...</a><br/></td></tr> +<tr class="separator:gaf5448e591fe49161b6759b48aecb08fe"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga17b873f246c9f5e9355760ffef3dad4a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">__QADD</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga17b873f246c9f5e9355760ffef3dad4a"><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating add. <a href="#ga17b873f246c9f5e9355760ffef3dad4a">More...</a><br/></td></tr> +<tr class="separator:ga17b873f246c9f5e9355760ffef3dad4a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3ba259f8f05a36f7b88b469a71ffc096"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">__QSUB</a> (uint32_t val1, uint32_t val2)</td></tr> +<tr class="memdesc:ga3ba259f8f05a36f7b88b469a71ffc096"><td class="mdescLeft"> </td><td class="mdescRight">Q setting saturating subtract. <a href="#ga3ba259f8f05a36f7b88b469a71ffc096">More...</a><br/></td></tr> +<tr class="separator:ga3ba259f8f05a36f7b88b469a71ffc096"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">__PKHBT</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[15:0] of <em>val1</em> with bits[31:16] of <em>val2</em> levitated with the <em>val3</em>. <a href="#gaefb8ebf3a54e197464da1ff69a44f4b5">More...</a><br/></td></tr> +<tr class="separator:gaefb8ebf3a54e197464da1ff69a44f4b5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__intrinsic__SIMD__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">__PKHTB</a> (uint32_t val1, uint32_t val2, uint32_t val3)</td></tr> +<tr class="memdesc:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="mdescLeft"> </td><td class="mdescRight">Halfword packing instruction. Combines bits[31:16] of <em>val1</em> with bits[15:0] of <em>val2</em> right-shifted with the <em>val3</em>. <a href="#gafd8fe4a6d87e947caa81a69ec36c1666">More...</a><br/></td></tr> +<tr class="separator:gafd8fe4a6d87e947caa81a69ec36c1666"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p><b>Single Instruction Multiple Data (SIMD)</b> extensions are provided <b>only for Cortex-M4 and Cortex-M7 cores</b> to simplify development of application software. SIMD extensions increase the processing capability without materially increasing the power consumption. The SIMD extensions are completely transparent to the operating system (OS), allowing existing OS ports to be used.</p> +<p><b>SIMD Features:</b></p> +<ul> +<li>Simultaneous computation of 2x16-bit or 4x8-bit operands</li> +<li>Fractional arithmetic</li> +<li>User definable saturation modes (arbitrary word-width)</li> +<li>Dual 16x16 multiply-add/subtract 32x32 fractional MAC</li> +<li>Simultaneous 8/16-bit select operations</li> +<li>Performance up to 3.2 GOPS at 800MHz</li> +<li>Performance is achieved with a "near zero" increase in power consumption on a typical implementation</li> +</ul> +<p><b>Examples:</b> </p> +<p><b>Addition:</b> Add two values using SIMD function</p> +<div class="fragment"><div class="line">uint32_t add_halfwords(uint32_t val1, uint32_t val2)</div> +<div class="line">{</div> +<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#gad0bf46373a1c05aabf64517e84be5984">__SADD16</a>(val1, val2);</div> +<div class="line">}</div> +</div><!-- fragment --><p><b>Subtraction:</b> Subtract two values using SIMD function</p> +<div class="fragment"><div class="line">uint32_t sub_halfwords(uint32_t val1, uint32_t val2)</div> +<div class="line">{</div> +<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">__SSUB16</a>(val1, val2);</div> +<div class="line">}</div> +</div><!-- fragment --><p><b>Multiplication:</b> Performing a multiplication using SIMD function</p> +<div class="fragment"><div class="line">uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)</div> +<div class="line">{</div> +<div class="line"> <span class="keywordflow">return</span> <a class="code" href="group__intrinsic__SIMD__gr.html#gae326e368a1624d2dfb4b97c626939257">__SMUAD</a>(val1, val2);</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gaefb8ebf3a54e197464da1ff69a44f4b5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __PKHBT </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Combine a halfword from one register with a halfword from another register. The second argument can be left-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands </td></tr> + <tr><td class="paramname">val3</td><td>value for left-shifting <em>val2</em>. Value range [0..31].</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the combination of halfwords.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0]</div> +<div class="line">res[31:16] = val2[31:16]<<val3 </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafd8fe4a6d87e947caa81a69ec36c1666"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __PKHTB </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Combines a halfword from one register with a halfword from another register. The second argument can be right-shifted before extraction of the halfword. The registers PC and SP are not allowed as arguments. This instruction does not change the flags.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>second 16-bit operands </td></tr> + <tr><td class="paramname">val2</td><td>first 16-bit operands </td></tr> + <tr><td class="paramname">val3</td><td>value for right-shifting <em>val2</em>. Value range [1..32].</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the combination of halfwords.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val2[15:0]>>val3</div> +<div class="line">res[31:16] = val1[31:16] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga17b873f246c9f5e9355760ffef3dad4a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to obtain the saturating add of two integers.<br/> + The Q bit is set if the operation saturates.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first summand of the saturating add operation. </td></tr> + <tr><td class="paramname">val2</td><td>second summand of the saturating add operation.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the saturating addition of val1 and val2.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[31:0] = SAT(val1 + SAT(val2))</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae83a53ec04b496304bed6d9fe8f7461b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit integer arithmetic additions in parallel, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the saturated addition of the low halfwords, in the low halfword of the return value. </li> +<li>the saturated addition of the high halfwords, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0]</div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf2f5a9132dcfc6d01d34cd971c425713"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four 8-bit integer additions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the saturated addition of the first byte of each operand in the first byte of the return value. </li> +<li>the saturated addition of the second byte of each operand in the second byte of the return value. </li> +<li>the saturated addition of the third byte of each operand in the third byte of the return value. </li> +<li>the saturated addition of the fourth byte of each operand in the fourth byte of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8] </div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16] </div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga87618799672e1511e33964bc71467eb3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the one operand, then add the high halfwords and subtract the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the saturated subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the saturated addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16] </div> +<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab41eb2b17512ab01d476fc9d5bd19520"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of one operand, then subtract the high halfwords and add the low halfwords, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the saturated addition of the low halfword of the first operand and the high halfword of the second operand, in the low halfword of the return value. </li> +<li>the saturated subtraction of the low halfword of the second operand from the high halfword of the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3ba259f8f05a36f7b88b469a71ffc096"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to obtain the saturating subtraction of two integers.<br/> + The Q bit is set if the operation saturates.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>minuend of the saturating subtraction operation. </td></tr> + <tr><td class="paramname">val2</td><td>subtrahend of the saturating subtraction operation.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the saturating subtraction of val1 and val2.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[31:0] = SAT(val1 - SAT(val2))</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad089605c16df9823a2c8aaa37777aae5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit integer subtractions, saturating the results to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the saturated subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li> +<li>the saturated subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 16-bit signed integer range -2<sup>15</sup> <= x <= 2<sup>15</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0]</div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga753493a65493880c28baa82c151a0d61"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __QSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four 8-bit integer subtractions, saturating the results to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> <= x <= 2<sup>7</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad0bf46373a1c05aabf64517e84be5984"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed integer additions.<br/> + The GE bits in the APSR are set according to the results of the additions.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfwords in the low halfword of the return value. </li> +<li>the addition of the high halfwords in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0]</div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac20aa0f741d0a1494d58c531e38d5785"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function performs four 8-bit signed integer additions. The GE bits of the APSR are set according to the results of the additions. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the addition of the second bytes of each operand, in the second byte of the return value. </li> +<li>the addition of the third bytes of each operand, in the third byte of the return value. </li> +<li>the addition of the fourth bytes of each operand, in the fourth byte of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[7:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8] </div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16] </div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5845084fd99c872e98cf5553d554de2a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function inserts an SASX instruction into the instruction stream generated by the compiler. It enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/> + The GE bits in the APRS are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16] </div> +<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf5448e591fe49161b6759b48aecb08fe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SEL </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function inserts a SEL instruction into the instruction stream generated by the compiler. It enables you to select bytes from the input parameters, whereby the bytes that are selected depend upon the results of previous SIMD instruction function. The results of previous SIMD instruction function are represented by the Greater than or Equal flags in the Application Program Status Register (APSR). The __SEL function works equally well on both halfword and byte operand function results. This is because halfword operand operations set two (duplicate) GE bits per value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>four selectable 8-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>four selectable 8-bit values.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>The function selects bytes from the input parameters and returns them in the return value, res, according to the following criteria: <ul> +<li>if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0] </li> +<li>if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8] </li> +<li>if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16] </li> +<li>if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24] </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga15d8899a173effb8ad8c7268da32b60e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two signed 16-bit integer additions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the low halfwords, in the low halfword of the return value. </li> +<li>the halved addition of the high halfwords, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] >> 1</div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga524575b442ea01aec10c762bf4d85fea"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four signed 8-bit integer additions, halving the results. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] >> 1</div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8] >> 1</div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16] >> 1</div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24] >> 1 </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae0a649035f67627464fd80e7218c89d5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] - val2[31:16]) >> 1 </div> +<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafadbd89c36b5addcf1ca10dd392db3e9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand, perform one signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] + val2[31:16]) >> 1</div> +<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga31328467f0f91b8ff9ae9a01682ad3bf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two signed 16-bit integer subtractions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the returned result. </li> +<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the returned result.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] >> 1</div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac3ec7215b354d925a239f3b31df2b77b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SHSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four signed 8-bit integer subtractions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] >> 1</div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8] >> 1</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16] >> 1</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae0c86f3298532183f3a29f5bb454d354"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLAD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value, as a 32-bit integer.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">res[31:0] = p1 + p2 + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9c286d330f4fb29b256335add91eec9f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLADX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications with exchanged halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication with exchanged halfwords of the second operand added to the accumulate value, as a 32-bit integer.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">res[31:0] = p1 + p2 + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad80e9b20c1736fd798f897362273a146"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t __SMLALD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">sum = p1 + p2 + val3[63:32][31:0]</div> +<div class="line">res[63:32] = sum[63:32]</div> +<div class="line">res[31:0] = sum[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad1adad1b3f2667328cc0db6c6b4f41cf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">unsigned long long __SMLALDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned long long </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, and perform two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the product of each multiplication added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">sum = p1 + p2 + val3[63:32][31:0]</div> +<div class="line">res[63:32] = sum[63:32]</div> +<div class="line">res[31:0] = sum[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaf4350af7f2030c36f43b2c104a9d16cd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLSD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 32-bit accumulate operand.<br/> + The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the subtraction.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">res[31:0] = p1 - p2 + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5290ce5564770ad124910d2583dc0a9e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMLSDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords in the second operand, then perform two 16-bit signed multiplications. The difference of the products is added to a 32-bit accumulate operand.<br/> + The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">res[31:0] = p1 - p2 + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5611f7314e0c8f53da377918dfbf42ee"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint64_t __SMLSLD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint64_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function It enables you to perform two 16-bit signed multiplications, take the difference of the products, subtracting the high halfword product from the low halfword product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">res[63:0] = p1 - p2 + val3[63:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga83e69ef81057d3cbd06863d729385187"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">unsigned long long __SMLSLDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">unsigned long long </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, perform two 16-bit multiplications, adding the difference of the products to a 64-bit accumulate operand. Overflow cannot occur during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit addition, and this overflow is not detected. Instead, the result wraps round to modulo2<sup>64</sup>.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the product of each multiplication, added to the accumulate value.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">res[63:0] = p1 - p2 + val3[63:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaea60757232f740ec6b09980eebb614ff"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMMLA </td> + <td>(</td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">int32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform a signed 32-bit multiplications, adding the most significant 32 bits of the 64-bit result to a 32-bit accumulate operand.<br/> +</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for multiplication. </td></tr> + <tr><td class="paramname">val3</td><td>accumulate value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the product of multiplication (most significant 32 bits) is added to the accumulate value, as a 32-bit integer.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p = val1 * val2</div> +<div class="line">res[31:0] = p[61:32] + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gae326e368a1624d2dfb4b97c626939257"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUAD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, adding the products together.<br/> + The Q bit is set if the addition overflows.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the sum of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">res[31:0] = p1 + p2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaee6390f86965cb662500f690b0012092"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUADX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications with exchanged halfwords of the second operand, adding the products together.<br/> + The Q bit is set if the addition overflows.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the sum of the products of the two 16-bit signed multiplications with exchanged halfwords of the second operand.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">res[31:0] = p1 + p2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga039142a5368840683cf329cb55b73f84"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUSD </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, taking the difference of the products by subtracting the high halfword product from the low halfword product.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[15:0]</div> +<div class="line">p2 = val1[31:16] * val2[31:16]</div> +<div class="line">res[31:0] = p1 - p2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gabb5bcba694bf17b141c32e6a8474f60e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SMUSDX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed multiplications, subtracting one of the products from the other. The halfwords of the second operand are exchanged before performing the arithmetic. This produces top * bottom and bottom * top multiplication.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operands for each multiplication. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit operands for each multiplication.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the difference of the products of the two 16-bit signed multiplications.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">p1 = val1[15:0] * val2[31:16]</div> +<div class="line">p2 = val1[31:16] * val2[15:0]</div> +<div class="line">res[31:0] = p1 - p2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga95e666b82216066bf6064d1244e6883c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSAT16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to saturate two signed 16-bit values to a selected signed range.<br/> + The Q bit is set if either operation saturates.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>two signed 16-bit values to be saturated. </td></tr> + <tr><td class="paramname">val2</td><td>bit position for saturation, an integral constant expression in the range 1 to 16.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul> +<li>the signed saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li> +<li>the signed saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">Saturate halfwords in val1 to the <span class="keywordtype">signed</span> range specified by the bit position in val2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9d3bc5c539f9bd50f7d59ffa37ac6a65"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the two halfwords of one operand and perform one 16-bit integer subtraction and one 16-bit addition.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga4262f73be75efbac6b46ab7c71aa6cbc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit signed integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands of each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands of each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <ul> +<li>res is the return value, then: </li> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0]</div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaba63bb52e1e93fb527e26f3d474da12e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four 8-bit signed integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands of each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands of each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on </dt><dd>the results of the operation.</dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac540b4fc41d30778ba102d2a65db5589"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SXTAB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to extract two 8-bit values from the second operand (at bit positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the first operand.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>values added to the zero-extended to 16-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the addition of <em>val1</em> and <em>val2</em>, where the 8-bit values in val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + SignExtended(val2[7:0])</div> +<div class="line">res[31:16] = val1[31:16] + SignExtended(val2[23:16])</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga38dce3dd13ba212e80ec3cff4abeb11a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __SXTB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to extract two 8-bit values from an operand and sign-extend them to 16 bits each.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the 8-bit values sign-extended to 16-bit values. <ul> +<li>sign-extended value of val[7:0] in the low halfword of the return value. </li> +<li>sign-extended value of val[23:16] in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = SignExtended(val[7:0]</div> +<div class="line">res[31:16] = SignExtended(val[23:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gaa1160f0cf76d6aa292fbad54a1aa6b74"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit unsigned integer additions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands for each addition. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands for each addition.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfwords in each operand, in the low halfword of the return value. </li> +<li>the addition of the high halfwords in each operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0x10000 then APSR.GE[0] = 11 else 00 </li> +<li>if res[31:16] >= 0x10000 then APSR.GE[1] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] </div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab3d7fd00d113b20fb3741a17394da762"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions. The GE bits of the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands for each addition. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands for each addition.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the first bytes from each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes from each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes from each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[7:0] >= 0x100 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0x100 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0x100 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0x100 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga980353d2c72ebb879282e49f592fddc0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the two halfwords of the second operand, add the high halfwords and subtract the low halfwords.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the low halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="section user"><dt>If <em>res</em> is the return value, then:</dt><dd><ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0x10000 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gabd0b0e2da2e6364e176d051687702b86"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer additions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the low halfwords in each operand, in the low halfword of the return value. </li> +<li>the halved addition of the high halfwords in each operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] >> 1</div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga3a14e5485e59bf0f23595b7c2a94eb0b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] >> 1</div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8] >> 1</div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16] >> 1</div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga028f0732b961fb6e5209326fb3855261"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, add the high halfwords and subtract the low halfwords, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the subtraction in the low halfword, and the first operand for the addition in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the subtraction in the high halfword, and the second operand for the addition in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the high halfword in the second operand from the low halfword in the first operand. </li> +<li>the halved addition of the high halfword in the first operand and the low halfword in the second operand.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] - val2[31:16]) >> 1</div> +<div class="line">res[31:16] = (val1[31:16] + val2[15:0] ) >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga09e129e6613329aab87c89f1108b7ed7"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the high halfword in the second operand and the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = (val1[15:0] + val2[31:16]) >> 1</div> +<div class="line">res[31:16] = (val1[31:16] - val2[15:0] ) >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga1f7545b8dc33bb97982731cb9d427a69"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer subtractions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the halved subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] >> 1</div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga48a55df1c3e73923b73819d7c19b392d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UHSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer subtractions, halving the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the halved subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the halved subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the halved subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0] >> 1</div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8] >> 1</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16] >> 1</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24] >> 1</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9e2cc5117e79578a08b25f1e89022966"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQADD16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer additions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfword in the first operand and the low halfword in the second operand, in the low halfword of the return value. </li> +<li>the addition of the high halfword in the first operand and the high halfword in the second operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[15:0] </div> +<div class="line">res[31:16] = val1[31:16] + val2[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gafa9af218db3934a692fb06fa728d8031"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQADD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer additions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit summands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit summands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the halved addition of the first bytes in each operand, in the first byte of the return value. </li> +<li>the halved addition of the second bytes in each operand, in the second byte of the return value. </li> +<li>the halved addition of the third bytes in each operand, in the third byte of the return value. </li> +<li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] + val2[7:0] </div> +<div class="line">res[15:8] = val1[15:8] + val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] + val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] + val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5eff3ae5eabcd73f3049996ca391becb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQASX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the high halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] + val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gadecfdfabc328d8939d49d996f2fd4482"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand and perform one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the results to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first 16-bit operand for the addition in the low halfword, and the first 16-bit operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second 16-bit halfword for the addition in the high halfword, and the second 16-bit halfword for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 <= x <= 2<sup>16</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga5ec4e2e231d15e5c692233feb3806187"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two unsigned 16-bit integer subtractions, saturating the results to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands for each subtraction. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands for each subtraction.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 16-bit unsigned integer range 0 < x < 2<sup>16</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] </div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9736fe816aec74fe886e7fb949734eab"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UQSUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit integer subtractions, saturating the results to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The results are saturated to the 8-bit unsigned integer range 0 < x < 2<sup>8</sup> - 1.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0]</div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gac8855c07044239ea775c8128013204f0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAD8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences together, returning the result as a single unsigned integer.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>The sum is returned as a single unsigned integer.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">absdiff1 = val1[7:0] - val2[7:0]</div> +<div class="line">absdiff2 = val1[15:8] - val2[15:8]</div> +<div class="line">absdiff3 = val1[23:16] - val2[23:16]</div> +<div class="line">absdiff4 = val1[31:24] - val2[31:24]</div> +<div class="line">res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad032bd21f013c5d29f5fcb6b0f02bc3f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USADA8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val3</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four unsigned 8-bit subtractions, and add the absolute values of the differences to a 32-bit accumulate operand.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands for the subtractions. </td></tr> + <tr><td class="paramname">val3</td><td>accumulation value.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the sum of the absolute differences of the following bytes, added to the accumulation value: <ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">absdiff1 = val1[7:0] - val2[7:0]</div> +<div class="line">absdiff2 = val1[15:8] - val2[15:8]</div> +<div class="line">absdiff3 = val1[23:16] - val2[23:16]</div> +<div class="line">absdiff4 = val1[31:24] - val2[31:24]</div> +<div class="line">sum = absdiff1 + absdiff2 + absdiff3 + absdiff4</div> +<div class="line">res[31:0] = sum[31:0] + val3[31:0]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga967f516afff5900cf30f1a81907cdd89"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAT16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">const uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to saturate two signed 16-bit values to a selected unsigned range.<br/> + The Q bit is set if either operation saturates.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>two 16-bit values that are to be saturated. </td></tr> + <tr><td class="paramname">val2</td><td>bit position for saturation, and must be an integral constant expression in the range 0 to 15.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the saturation of the two signed 16-bit values, as non-negative values. <ul> +<li>the saturation of the low halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the low halfword of the return value. </li> +<li>the saturation of the high halfword in <em>val1</em>, saturated to the bit position specified in <em>val2</em> and returned in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">Saturate halfwords in val1 to the <span class="keywordtype">unsigned</span> range specified by the bit position in val2</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga578a082747436772c482c96d7a58e45e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USAX </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to exchange the halfwords of the second operand, subtract the high halfwords and add the low halfwords.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first operand for the addition in the low halfword, and the first operand for the subtraction in the high halfword. </td></tr> + <tr><td class="paramname">val2</td><td>second operand for the addition in the high halfword, and the second operand for the subtraction in the low halfword.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the addition of the low halfword in the first operand and the high halfword in the second operand, in the low halfword of the return value. </li> +<li>the subtraction of the low halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value. </li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation. </dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0x10000 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] + val2[31:16]</div> +<div class="line">res[31:16] = val1[31:16] - val2[15:0] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="ga9f2b77e11fc4a77b26c36c423ed45b4e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USUB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform two 16-bit unsigned integer subtractions.<br/> + The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first two 16-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second two 16-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the low halfword in the second operand from the low halfword in the first operand, in the low halfword of the return value. </li> +<li>the subtraction of the high halfword in the second operand from the high halfword in the first operand, in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[15:0] >= 0 then APSR.GE[1:0] = 11 else 00 </li> +<li>if res[31:16] >= 0 then APSR.GE[3:2] = 11 else 00</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = val1[15:0] - val2[15:0] </div> +<div class="line">res[31:16] = val1[31:16] - val2[31:16] </div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gacb7257dc3b8e9acbd0ef0e31ff87d4b8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __USUB8 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to perform four 8-bit unsigned integer subtractions. The GE bits in the APSR are set according to the results.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>first four 8-bit operands. </td></tr> + <tr><td class="paramname">val2</td><td>second four 8-bit operands.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd><ul> +<li>the subtraction of the first byte in the second operand from the first byte in the first operand, in the first bytes of the return value. </li> +<li>the subtraction of the second byte in the second operand from the second byte in the first operand, in the second byte of the return value. </li> +<li>the subtraction of the third byte in the second operand from the third byte in the first operand, in the third byte of the return value. </li> +<li>the subtraction of the fourth byte in the second operand from the fourth byte in the first operand, in the fourth byte of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt></dt><dd>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on the results of the operation.</dd></dl> +<dl class="section user"><dt></dt><dd>If <em>res</em> is the return value, then: <ul> +<li>if res[8:0] >= 0 then APSR.GE[0] = 1 else 0 </li> +<li>if res[15:8] >= 0 then APSR.GE[1] = 1 else 0 </li> +<li>if res[23:16] >= 0 then APSR.GE[2] = 1 else 0 </li> +<li>if res[31:24] >= 0 then APSR.GE[3] = 1 else 0</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[7:0] = val1[7:0] - val2[7:0]</div> +<div class="line">res[15:8] = val1[15:8] - val2[15:8]</div> +<div class="line">res[23:16] = val1[23:16] - val2[23:16]</div> +<div class="line">res[31:24] = val1[31:24] - val2[31:24]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gad25ce96db0f17096bbd815f4817faf09"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UXTAB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val1</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val2</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to extract two 8-bit values from one operand, zero-extend them to 16 bits each, and add the results to two 16-bit values from another operand.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val1</td><td>value added to the zero-extended to 16-bit values. </td></tr> + <tr><td class="paramname">val2</td><td>two 8-bit values to be extracted and zero-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the 8-bit values in <em>val2</em>, zero-extended to 16-bit values and added to <em>val1</em>.</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]</div> +<div class="line">res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +<a class="anchor" id="gab41d713653b16f8d9fef44d14e397228"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t __UXTB16 </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>val</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This function enables you to extract two 8-bit values from an operand and zero-extend them to 16 bits each.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">val</td><td>two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>the 8-bit values zero-extended to 16-bit values. <ul> +<li>zero-extended value of val[7:0] in the low halfword of the return value. </li> +<li>zero-extended value of val[23:16] in the high halfword of the return value.</li> +</ul> +</dd></dl> +<dl class="section user"><dt>Operation:</dt><dd><div class="fragment"><div class="line">res[15:0] = ZeroExtended(val[7:0] )</div> +<div class="line">res[31:16] = ZeroExtended(val[23:16])</div> +</div><!-- fragment --> </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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\ No newline at end of file diff --git a/docs/Core/html/group__mpu__defines.html b/docs/Core/html/group__mpu__defines.html new file mode 100644 index 0000000..ba7ee01 --- /dev/null +++ b/docs/Core/html/group__mpu__defines.html @@ -0,0 +1,303 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Define values</title> +<title>CMSIS-Core (Cortex-M): Define values</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> 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class="memitem:gadb0a92c0928c113120567e85ff1ba05c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a></td></tr> +<tr class="memdesc:gadb0a92c0928c113120567e85ff1ba05c"><td class="mdescLeft"> </td><td class="mdescRight">Size values of a MPU region (in RASR field) <a href="#gadb0a92c0928c113120567e85ff1ba05c">More...</a><br/></td></tr> +<tr class="separator:gadb0a92c0928c113120567e85ff1ba05c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabc4788126d7798469cb862a08d3050cc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a></td></tr> +<tr class="memdesc:gabc4788126d7798469cb862a08d3050cc"><td class="mdescLeft"> </td><td class="mdescRight">Values for MPU region access permissions (in RASR field) <a href="#gabc4788126d7798469cb862a08d3050cc">More...</a><br/></td></tr> +<tr class="separator:gabc4788126d7798469cb862a08d3050cc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga71d41084e984be70a23cb640fd89d1e2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a></td></tr> +<tr class="memdesc:ga71d41084e984be70a23cb640fd89d1e2"><td class="mdescLeft"> </td><td class="mdescRight">Values for MPU region access attributes (in RASR field) <a href="#ga71d41084e984be70a23cb640fd89d1e2">More...</a><br/></td></tr> +<tr class="separator:ga71d41084e984be70a23cb640fd89d1e2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab23596306119e7831847bd9683de3934"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a></td></tr> +<tr class="memdesc:gab23596306119e7831847bd9683de3934"><td class="mdescLeft"> </td><td class="mdescRight">Cache policy values for MPU region access attributes (in RASR field) <a href="#gab23596306119e7831847bd9683de3934">More...</a><br/></td></tr> +<tr class="separator:gab23596306119e7831847bd9683de3934"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following define values are used with <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> to setup the <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value field in the MPU region.</p> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structARM__MPU__Region__t.html" title="Setup information of a single MPU Region. ">ARM_MPU_Region_t</a>, <a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a>, <a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>. </dd></dl> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga71d41084e984be70a23cb640fd89d1e2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_ACCESS_xxx</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The following define values are used to compose the access attributes for an MPU region: </p> +<table class="doxtable"> +<tr> +<th align="left">#define </th><th align="left">TEX </th><th align="left">Shareable </th><th align="left">Cacheable </th><th align="left">Bufferable </th><th align="left">Description </th></tr> +<tr> +<td align="left">ARM_MPU_ACCESS_ORDERED </td><td align="left">000b </td><td align="left">1 </td><td align="left">0 </td><td align="left">0 </td><td align="left">Strongly ordered memory </td></tr> +<tr> +<td align="left">ARM_MPU_ACCESS_DEVICE(S) </td><td align="left">0s0b </td><td align="left">S </td><td align="left">0 </td><td align="left">S </td><td align="left">Memory mapped peripheral device, shared (S=1) or non-shared (S=0) </td></tr> +<tr> +<td align="left">ARM_MPU_ACCESS_NORMAL(O,I,S) </td><td align="left">1BBb </td><td align="left">S </td><td align="left">A </td><td align="left">A </td><td align="left">Normal memory, with outer/inner cache policy (O/I=<a class="el" href="group__mpu__defines.html#gab23596306119e7831847bd9683de3934">ARM_MPU_CACHEP_xxx</a>, shared (S=1) or non-share (S=0) </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="gabc4788126d7798469cb862a08d3050cc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_AP_xxx</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The following define values are used to compose the access permission for an MPU region: </p> +<table class="doxtable"> +<tr> +<th align="left">#define </th><th align="left">Value </th><th align="left">Access permissions </th></tr> +<tr> +<td align="left">ARM_MPU_AP_NONE </td><td align="left">0x0U </td><td align="left">None: any access generates a permission fault. </td></tr> +<tr> +<td align="left">ARM_MPU_AP_PRIV </td><td align="left">0x1U </td><td align="left">Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault. </td></tr> +<tr> +<td align="left">ARM_MPU_AP_URO </td><td align="left">0x2U </td><td align="left">Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault. </td></tr> +<tr> +<td align="left">ARM_MPU_AP_FULL </td><td align="left">0x3U </td><td align="left">Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated. </td></tr> +<tr> +<td align="left">ARM_MPU_AP_PRO </td><td align="left">0x5U </td><td align="left">Privileged Read-only: any unprivileged access or privileged write generates a permission fault. </td></tr> +<tr> +<td align="left">ARM_MPU_AP_RO </td><td align="left">0x6U </td><td align="left">Privileged and Unprivileged Read-only: any write generates a permission fault. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="gab23596306119e7831847bd9683de3934"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_CACHEP_xxx</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The following define values are used to compose the cacheability flags within the access attributes for an MPU region: </p> +<table class="doxtable"> +<tr> +<th align="left">#define </th><th align="left">Value </th><th align="left">Cacheability policy </th></tr> +<tr> +<td align="left">ARM_MPU_CACHEP_NOCACHE </td><td align="left">00b </td><td align="left">Non-cacheable </td></tr> +<tr> +<td align="left">ARM_MPU_CACHEP_WB_WRA </td><td align="left">01b </td><td align="left">Write-back, write and read allocate </td></tr> +<tr> +<td align="left">ARM_MPU_CACHEP_WT_NWA </td><td align="left">10b </td><td align="left">Write-through, no write allocate </td></tr> +<tr> +<td align="left">ARM_MPU_CACHEP_WB_NWA </td><td align="left">11b </td><td align="left">Write-back, no write allocate </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="gadb0a92c0928c113120567e85ff1ba05c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_REGION_SIZE_xxx</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The following define values are used to compose the size information for an MPU region:</p> +<table class="doxtable"> +<tr> +<th align="left">#define </th><th align="left">Value </th><th align="left">Description </th></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_32B </td><td align="left">0x04U </td><td align="left">Region size 32 Bytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_64B </td><td align="left">0x05U </td><td align="left">Region size 64 Bytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_128B </td><td align="left">0x06U </td><td align="left">Region size 128 Bytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_256B </td><td align="left">0x07U </td><td align="left">Region size 256 Bytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_512B </td><td align="left">0x08U </td><td align="left">Region size 512 Bytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_1KB </td><td align="left">0x09U </td><td align="left">Region size 1 KByte </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_2KB </td><td align="left">0x0AU </td><td align="left">Region size 2 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_4KB </td><td align="left">0x0BU </td><td align="left">Region size 4 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_8KB </td><td align="left">0x0CU </td><td align="left">Region size 8 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_16KB </td><td align="left">0x0DU </td><td align="left">Region size 16 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_32KB </td><td align="left">0x0EU </td><td align="left">Region size 32 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_64KB </td><td align="left">0x0FU </td><td align="left">Region size 64 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_128KB </td><td align="left">0x10U </td><td align="left">Region size 128 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_256KB </td><td align="left">0x11U </td><td align="left">Region size 256 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_512KB </td><td align="left">0x12U </td><td align="left">Region size 512 KBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_1MB </td><td align="left">0x13U </td><td align="left">Region size 1 MByte </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_2MB </td><td align="left">0x14U </td><td align="left">Region size 2 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_4MB </td><td align="left">0x15U </td><td align="left">Region size 4 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_8MB </td><td align="left">0x16U </td><td align="left">Region size 8 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_16MB </td><td align="left">0x17U </td><td align="left">Region size 16 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_32MB </td><td align="left">0x18U </td><td align="left">Region size 32 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_64MB </td><td align="left">0x19U </td><td align="left">Region size 64 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_128MB </td><td align="left">0x1AU </td><td align="left">Region size 128 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_256MB </td><td align="left">0x1BU </td><td align="left">Region size 256 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_512MB </td><td align="left">0x1CU </td><td align="left">Region size 512 MBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_1GB </td><td align="left">0x1DU </td><td align="left">Region size 1 GByte </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_2GB </td><td align="left">0x1EU </td><td align="left">Region size 2 GBytes </td></tr> +<tr> +<td align="left">ARM_MPU_REGION_SIZE_4GB </td><td align="left">0x1FU </td><td align="left">Region size 4 GBytes </td></tr> +</table> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li 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+Content</h2></td></tr> +<tr class="memitem:group__mpu__defines"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__defines.html">Define values</a></td></tr> +<tr class="memdesc:group__mpu__defines"><td class="mdescLeft"> </td><td class="mdescRight">Define values for MPU region setup. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a> +Data Structures</h2></td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html">MPU_Type</a></td></tr> +<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure type to access the Memory Protection Unit (MPU). <a href="structMPU__Type.html#details">More...</a><br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></td></tr> +<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Setup information of a single MPU Region. <a href="structARM__MPU__Region__t.html#details">More...</a><br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ga3fead12dc24a6d00ad53f55a042486ca"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(Region, BaseAddress)</td></tr> +<tr class="memdesc:ga3fead12dc24a6d00ad53f55a042486ca"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Base Address Register Value. <a href="#ga3fead12dc24a6d00ad53f55a042486ca">More...</a><br/></td></tr> +<tr class="separator:ga3fead12dc24a6d00ad53f55a042486ca"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)</td></tr> +<tr class="memdesc:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga96b93785c92e2dbcb3a2356c25bf2adc">More...</a><br/></td></tr> +<tr class="separator:ga96b93785c92e2dbcb3a2356c25bf2adc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc">ARM_MPU_RASR_EX</a>(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)</td></tr> +<tr class="memdesc:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="mdescLeft"> </td><td class="mdescRight">MPU Region Attribute and Size Register Value. <a href="#ga332ed5f8969dd4df6b61c6ae32ec36dc">More...</a><br/></td></tr> +<tr class="separator:ga332ed5f8969dd4df6b61c6ae32ec36dc"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a> (uint32_t MPU_CTRL)</td></tr> +<tr class="memdesc:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="mdescLeft"> </td><td class="mdescRight">Enable the memory protection unit (MPU) and. <a href="#ga31406efd492ec9a091a70ffa2d8a42fb">More...</a><br/></td></tr> +<tr class="separator:ga31406efd492ec9a091a70ffa2d8a42fb"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga7cbc0a4a066ed90e85c8176228235d57"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a> ()</td></tr> +<tr class="separator:ga7cbc0a4a066ed90e85c8176228235d57"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c">ARM_MPU_ClrRegion</a> (uint32_t rnr)</td></tr> +<tr class="separator:ga9dcb0afddf4ac351f33f3c7a5169c62c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d">ARM_MPU_SetRegion</a> (uint32_t rbar, uint32_t rasr)</td></tr> +<tr class="separator:ga16931f9ad84d7289e8218e169ae6db5d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga042ba1a6a1a58795231459ac0410b809"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a> (uint32_t rnr, uint32_t rbar, uint32_t rasr)</td></tr> +<tr class="separator:ga042ba1a6a1a58795231459ac0410b809"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gafa27b26d5847fa8e465584e376b6078a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> (MPU_Region_t const *table, uint32_t cnt)</td></tr> +<tr class="separator:gafa27b26d5847fa8e465584e376b6078a"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.</p> +<p>The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.</p> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keywordtype">void</span> main() </div> +<div class="line">{</div> +<div class="line"> <span class="comment">// Set Region 0</span></div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809">ARM_MPU_SetRegionEx</a>(0UL, 0x08000000UL, MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a>(0);</div> +<div class="line"> </div> +<div class="line"> <span class="comment">// Execute application code that is access protected by the MPU</span></div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57">ARM_MPU_Disable</a>();</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga96b93785c92e2dbcb3a2356c25bf2adc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RASR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">DisableExec, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessPermission, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">TypeExtField, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsShareable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsCacheable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">IsBufferable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">SubRegionDisable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">Size </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">DisableExec</td><td>Instruction access disable bit. 1 = disable instruction fetches. </td></tr> + <tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr> + <tr><td class="paramname">TypeExtField</td><td>Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. </td></tr> + <tr><td class="paramname">IsShareable</td><td>1 = region is shareable between multiple bus masters. </td></tr> + <tr><td class="paramname">IsCacheable</td><td>1 = region is cacheable (values may be kept in cache). </td></tr> + <tr><td class="paramname">IsBufferable</td><td>1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy. </td></tr> + <tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr> + <tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga332ed5f8969dd4df6b61c6ae32ec36dc"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RASR_EX</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">DisableExec, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessPermission, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">AccessAttributes, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">SubRegionDisable, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">Size </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This macro is used to construct a valid <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> value. The ENABLE bit of the RASR value is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">DisableExec</td><td>Instruction access disable bit, 1= disable instruction fetches. </td></tr> + <tr><td class="paramname">AccessPermission</td><td>Data access permission configures read/write access for User and Privileged mode. Possible values see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr> + <tr><td class="paramname">AccessAttributes</td><td>Memory access attribution, see <a class="el" href="group__mpu__defines.html#ga71d41084e984be70a23cb640fd89d1e2">ARM_MPU_ACCESS_xxx</a>. </td></tr> + <tr><td class="paramname">SubRegionDisable</td><td>Sub-region disable field (8 bits). </td></tr> + <tr><td class="paramname">Size</td><td>Region size with values defined under <a class="el" href="group__mpu__defines.html#gadb0a92c0928c113120567e85ff1ba05c">ARM_MPU_REGION_SIZE_xxx</a>. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga3fead12dc24a6d00ad53f55a042486ca"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define ARM_MPU_RBAR</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">Region, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">BaseAddress </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>This preprocessor function can be used to construct a valid <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> value. The VALID bit is implicitly set to 1.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">Region</td><td>The region to be configured, number 0 to 15. </td></tr> + <tr><td class="paramname">BaseAddress</td><td>The base address for the region. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga9dcb0afddf4ac351f33f3c7a5169c62c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_ClrRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clear and disable the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be cleared. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga7cbc0a4a066ed90e85c8176228235d57"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Disable </td> + <td>(</td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disable the MPU. </p> + +</div> +</div> +<a class="anchor" id="ga31406efd492ec9a091a70ffa2d8a42fb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Enable </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>MPU_CTRL</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">MPU_CTRL</td><td>Additional control settings that configure MPU behaviour</td></tr> + </table> + </dd> +</dl> +<p>The function <a class="el" href="group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb">ARM_MPU_Enable</a> writes to the register <a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">MPU->CTRL</a> and sets bit ENABLE. The parameter <em>MPU_CTRL</em> provides additional bit values (see table below) that configure the MPU behaviour. For processors that implement an <b>MPU Fault Handler</b> the <a class="el" href="group__NVIC__gr.html">MemoryManagement_IRQn</a> exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.</p> +<p>The following table contains possible values for the parameter <em>MPU_CTRL</em> that set specific bits in register MPU->CTRL. </p> +<table class="doxtable"> +<tr> +<th align="left">Bit </th><th align="left">MPU_CTRL value </th><th align="left">When applied </th><th align="left">When not applied </th></tr> +<tr> +<td align="left">1 </td><td align="left">MPU_CTRL_HFNMIENA_Msk </td><td align="left">Enable MPU during hard fault, NMI, and FAULTMASK handlers execution </td><td align="left">Disable MPU during hard fault, NMI, and FAULTMASK handler execution </td></tr> +<tr> +<td align="left">2 </td><td align="left">MPU_CTRL_PRIVDEFENA_Msk </td><td align="left">Enable default memory map as a background region for privileged access </td><td align="left">Use only MPU region settings </td></tr> +</table> +<p><b>Example:</b></p> +<div class="fragment"><div class="line"><span class="comment">// enable MPU with all region definitions. Exceptions are not protected by MPU.</span></div> +<div class="line"> MPU_Enable (0);</div> +<div class="line"> </div> +<div class="line"><span class="comment">// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.</span></div> +<div class="line"> MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gafa27b26d5847fa8e465584e376b6078a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_Load </td> + <td>(</td> + <td class="paramtype">MPU_Region_t const * </td> + <td class="paramname"><em>table</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>cnt</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Load the given number of MPU regions from a table. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">table</td><td>Pointer to the MPU configuration table. </td></tr> + <tr><td class="paramname">cnt</td><td>Number of regions to be configured.</td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>only up to 16 regions can be handled as the function <a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> uses the REGION field in <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU->RBAR</a>.</dd></dl> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keyword">const</span> <a class="code" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> mpuTable[3][4] = {</div> +<div class="line"> {</div> +<div class="line"> { .<a class="code" href="structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22">RBAR</a> = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(0UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(1UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(2UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(3UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> },</div> +<div class="line"> {</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x08000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x20000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x40020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x40022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> },</div> +<div class="line"> {</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(4UL, 0x18000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(5UL, 0x30000000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },</div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(6UL, 0x50020000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) }, </div> +<div class="line"> { .RBAR = <a class="code" href="group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca">ARM_MPU_RBAR</a>(7UL, 0x50022000UL), .RASR = <a class="code" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }</div> +<div class="line"> }</div> +<div class="line">};</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> UpdateMpu(uint32_t idx)</div> +<div class="line">{</div> +<div class="line"> <a class="code" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>(mpuTable[idx], 4);</div> +<div class="line">}</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga16931f9ad84d7289e8218e169ae6db5d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegion </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rasr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure an MPU region.</p> +<p>The region number should be contained in the rbar value.</p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr> + <tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +<a class="anchor" id="ga042ba1a6a1a58795231459ac0410b809"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="group__compiler__conntrol__gr.html#gaba87361bfad2ae52cfe2f40c1a1dbf9c">__STATIC_INLINE</a> void ARM_MPU_SetRegionEx </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rnr</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rbar</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>rasr</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Configure the given MPU region. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">rnr</td><td>Region number to be configured. </td></tr> + <tr><td class="paramname">rbar</td><td>Value for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a> register. </td></tr> + <tr><td class="paramname">rasr</td><td>Value for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a> register. </td></tr> + </table> + </dd> +</dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__mpu__functions.js b/docs/Core/html/group__mpu__functions.js new file mode 100644 index 0000000..a7f207f --- /dev/null +++ b/docs/Core/html/group__mpu__functions.js @@ -0,0 +1,30 @@ +var group__mpu__functions = +[ + [ "Define values", "group__mpu__defines.html", "group__mpu__defines" ], + [ "MPU_Type", "structMPU__Type.html", [ + [ "CTRL", "structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f", null ], + [ "RASR", "structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3", null ], + [ "RASR_A1", "structMPU__Type.html#a1658326c6762637eeef8a79bb467445e", null ], + [ "RASR_A2", "structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205", null ], + [ "RASR_A3", "structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd", null ], + [ "RBAR", "structMPU__Type.html#a990c609b26d990b8ba832b110adfd353", null ], + [ "RBAR_A1", "structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066", null ], + [ "RBAR_A2", "structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2", null ], + [ "RBAR_A3", "structMPU__Type.html#a207f6e9c3af753367554cc06df300a55", null ], + [ "RNR", "structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c", null ], + [ "TYPE", "structMPU__Type.html#aba02af87f77577c725cf73879cabb609", null ] + ] ], + [ "ARM_MPU_Region_t", "structARM__MPU__Region__t.html", [ + [ "RASR", "structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d", null ], + [ "RBAR", "structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22", null ] + ] ], + [ "ARM_MPU_RASR", "group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc", null ], + [ "ARM_MPU_RASR_EX", "group__mpu__functions.html#ga332ed5f8969dd4df6b61c6ae32ec36dc", null ], + [ "ARM_MPU_RBAR", "group__mpu__functions.html#ga3fead12dc24a6d00ad53f55a042486ca", null ], + [ "ARM_MPU_ClrRegion", "group__mpu__functions.html#ga9dcb0afddf4ac351f33f3c7a5169c62c", null ], + [ "ARM_MPU_Disable", "group__mpu__functions.html#ga7cbc0a4a066ed90e85c8176228235d57", null ], + [ "ARM_MPU_Enable", "group__mpu__functions.html#ga31406efd492ec9a091a70ffa2d8a42fb", null ], + [ "ARM_MPU_Load", "group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a", null ], + [ "ARM_MPU_SetRegion", "group__mpu__functions.html#ga16931f9ad84d7289e8218e169ae6db5d", null ], + [ "ARM_MPU_SetRegionEx", "group__mpu__functions.html#ga042ba1a6a1a58795231459ac0410b809", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__nvic__trustzone__functions.html b/docs/Core/html/group__nvic__trustzone__functions.html new file mode 100644 index 0000000..8d56623 --- /dev/null +++ b/docs/Core/html/group__nvic__trustzone__functions.html @@ -0,0 +1,488 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>NVIC Functions</title> +<title>CMSIS-Core (Cortex-M): NVIC Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link 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onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a 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class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga0d3b5db0685bd95cc8bd2f7ad0891d39">TZ_NVIC_SetPriorityGrouping_NS</a> (uint32_t PriorityGroup)</td></tr> +<tr class="memdesc:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="mdescLeft"> </td><td class="mdescRight">Set Priority Grouping (non-secure) <a href="#ga0d3b5db0685bd95cc8bd2f7ad0891d39">More...</a><br/></td></tr> +<tr class="separator:ga0d3b5db0685bd95cc8bd2f7ad0891d39"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaf5f578628bc8b7154b29577f6f6a87fd">TZ_NVIC_GetPriorityGrouping_NS</a> (void)</td></tr> +<tr class="memdesc:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="mdescLeft"> </td><td class="mdescRight">Get Priority Grouping (non-secure) <a href="#gaf5f578628bc8b7154b29577f6f6a87fd">More...</a><br/></td></tr> +<tr class="separator:gaf5f578628bc8b7154b29577f6f6a87fd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaedea4c16dd4a0b792c7e9d1da4c49295">TZ_NVIC_EnableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="mdescLeft"> </td><td class="mdescRight">Enable External Interrupt (non-secure) <a href="#gaedea4c16dd4a0b792c7e9d1da4c49295">More...</a><br/></td></tr> +<tr class="separator:gaedea4c16dd4a0b792c7e9d1da4c49295"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga57d2a6736704c4a39421ed1a2e7b689b">TZ_NVIC_GetEnableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="mdescLeft"> </td><td class="mdescRight">Get Interrupt Enable status (non-secure) <a href="#ga57d2a6736704c4a39421ed1a2e7b689b">More...</a><br/></td></tr> +<tr class="separator:ga57d2a6736704c4a39421ed1a2e7b689b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabc58593dea7803c1f1e1ed3b098f497c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gabc58593dea7803c1f1e1ed3b098f497c">TZ_NVIC_DisableIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gabc58593dea7803c1f1e1ed3b098f497c"><td class="mdescLeft"> </td><td class="mdescRight">Disable External Interrupt (non-secure) <a href="#gabc58593dea7803c1f1e1ed3b098f497c">More...</a><br/></td></tr> +<tr class="separator:gabc58593dea7803c1f1e1ed3b098f497c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gab85bd0d55d746caf0e414be5284afe24"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gab85bd0d55d746caf0e414be5284afe24">TZ_NVIC_GetPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gab85bd0d55d746caf0e414be5284afe24"><td class="mdescLeft"> </td><td class="mdescRight">Get Pending Interrupt (non-secure) <a href="#gab85bd0d55d746caf0e414be5284afe24">More...</a><br/></td></tr> +<tr class="separator:gab85bd0d55d746caf0e414be5284afe24"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gaccbc9aa0eacf4d4c3d3046edb9e02edd">TZ_NVIC_SetPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="mdescLeft"> </td><td class="mdescRight">Set Pending Interrupt (non-secure) <a href="#gaccbc9aa0eacf4d4c3d3046edb9e02edd">More...</a><br/></td></tr> +<tr class="separator:gaccbc9aa0eacf4d4c3d3046edb9e02edd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga3b30f8b602b593a806617b671a50731a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga3b30f8b602b593a806617b671a50731a">TZ_NVIC_ClearPendingIRQ_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga3b30f8b602b593a806617b671a50731a"><td class="mdescLeft"> </td><td class="mdescRight">Clear Pending Interrupt (non-secure) <a href="#ga3b30f8b602b593a806617b671a50731a">More...</a><br/></td></tr> +<tr class="separator:ga3b30f8b602b593a806617b671a50731a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga1bffd79bd6365d83281883b6c4b0f218"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga1bffd79bd6365d83281883b6c4b0f218">TZ_NVIC_GetActive_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:ga1bffd79bd6365d83281883b6c4b0f218"><td class="mdescLeft"> </td><td class="mdescRight">Get Active Interrupt (non-secure) <a href="#ga1bffd79bd6365d83281883b6c4b0f218">More...</a><br/></td></tr> +<tr class="separator:ga1bffd79bd6365d83281883b6c4b0f218"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga2caf0df3603378c436c838138e42059a"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#ga2caf0df3603378c436c838138e42059a">TZ_NVIC_SetPriority_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr> +<tr class="memdesc:ga2caf0df3603378c436c838138e42059a"><td class="mdescLeft"> </td><td class="mdescRight">Set Interrupt Priority (non-secure) <a href="#ga2caf0df3603378c436c838138e42059a">More...</a><br/></td></tr> +<tr class="separator:ga2caf0df3603378c436c838138e42059a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gade6a8784339946fdd50575d7e65a3268"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html#gade6a8784339946fdd50575d7e65a3268">TZ_NVIC_GetPriority_NS</a> (<a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr> +<tr class="memdesc:gade6a8784339946fdd50575d7e65a3268"><td class="mdescLeft"> </td><td class="mdescRight">Get Interrupt Priority (non-secure) <a href="#gade6a8784339946fdd50575d7e65a3268">More...</a><br/></td></tr> +<tr class="separator:gade6a8784339946fdd50575d7e65a3268"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga3b30f8b602b593a806617b671a50731a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_ClearPendingIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Clears the pending bit of an non-secure external interrupt when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">NVIC_ClearPendingIRQ</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gabc58593dea7803c1f1e1ed3b098f497c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_DisableIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disables a device-specific interrupt in the non-secure NVIC when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">NVIC_DisableIRQ</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaedea4c16dd4a0b792c7e9d1da4c49295"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_EnableIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enables a device-specific interrupt in the non-secure NVIC when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>External interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga1bffd79bd6365d83281883b6c4b0f218"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_NVIC_GetActive_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reads the active register in non-secure NVIC when in secure state and returns the active bit. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Interrupt status is not active. </dd> +<dd> +1 Interrupt status is active. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">NVIC_GetActive</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga57d2a6736704c4a39421ed1a2e7b689b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_NVIC_GetEnableIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Interrupt is not enabled. </dd> +<dd> +1 Interrupt is enabled. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a>; <a class="el" href="group__NVIC__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c" title="Disable a device specific interrupt. ">NVIC_DisableIRQ</a>; </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gab85bd0d55d746caf0e414be5284afe24"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_NVIC_GetPendingIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Interrupt status is not pending. </dd> +<dd> +1 Interrupt status is pending. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga95a8329a680b051ecf3ee8f516acc662">NVIC_GetPendingIRQ</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gade6a8784339946fdd50575d7e65a3268"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_NVIC_GetPriority_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reads the priority of an non-secure interrupt when in secure state. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaf5f578628bc8b7154b29577f6f6a87fd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_NVIC_GetPriorityGrouping_NS </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Reads the priority grouping field from the non-secure NVIC when in secure state. </p> +<dl class="section return"><dt>Returns</dt><dd>Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). </dd></dl> +<dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Mainline. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gaa81b19849367d3cdb95ac108c500fa78">NVIC_GetPriorityGrouping</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="gaccbc9aa0eacf4d4c3d3046edb9e02edd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_SetPendingIRQ_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sets the pending bit of an non-secure external interrupt when in secure state. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. Value cannot be negative. </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga3b885147ef9965ecede49614de8df9d2">NVIC_SetPendingIRQ</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga2caf0df3603378c436c838138e42059a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_SetPriority_NS </td> + <td>(</td> + <td class="paramtype"><a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> </td> + <td class="paramname"><em>IRQn</em>, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>priority</em> </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sets the priority of an non-secure interrupt when in secure state. </p> +<dl class="section note"><dt>Note</dt><dd>The priority cannot be set for every core interrupt. </dd></dl> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt number. </td></tr> + <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority to set. </td></tr> + </table> + </dd> +</dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> </li> +</ul> +</dd></dl> + +</div> +</div> +<a class="anchor" id="ga0d3b5db0685bd95cc8bd2f7ad0891d39"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_NVIC_SetPriorityGrouping_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>PriorityGroup</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Sets the non-secure priority grouping field when in secure state using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">PriorityGroup</td><td>Priority grouping field. </td></tr> + </table> + </dd> +</dl> +<dl class="section note"><dt>Note</dt><dd>Only available for Armv8-M Mainline. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__NVIC__gr.html#gad78f447e891789b4d8f2e5b21eeda354">NVIC_SetPriorityGrouping</a> </li> +</ul> +</dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__nvic__trustzone__functions.js b/docs/Core/html/group__nvic__trustzone__functions.js new file mode 100644 index 0000000..a5a4bc0 --- /dev/null +++ b/docs/Core/html/group__nvic__trustzone__functions.js @@ -0,0 +1,14 @@ +var group__nvic__trustzone__functions = +[ + [ "TZ_NVIC_ClearPendingIRQ_NS", "group__nvic__trustzone__functions.html#ga3b30f8b602b593a806617b671a50731a", null ], + [ "TZ_NVIC_DisableIRQ_NS", "group__nvic__trustzone__functions.html#gabc58593dea7803c1f1e1ed3b098f497c", null ], + [ "TZ_NVIC_EnableIRQ_NS", "group__nvic__trustzone__functions.html#gaedea4c16dd4a0b792c7e9d1da4c49295", null ], + [ "TZ_NVIC_GetActive_NS", "group__nvic__trustzone__functions.html#ga1bffd79bd6365d83281883b6c4b0f218", null ], + [ "TZ_NVIC_GetEnableIRQ_NS", "group__nvic__trustzone__functions.html#ga57d2a6736704c4a39421ed1a2e7b689b", null ], + [ "TZ_NVIC_GetPendingIRQ_NS", "group__nvic__trustzone__functions.html#gab85bd0d55d746caf0e414be5284afe24", null ], + [ "TZ_NVIC_GetPriority_NS", "group__nvic__trustzone__functions.html#gade6a8784339946fdd50575d7e65a3268", null ], + [ "TZ_NVIC_GetPriorityGrouping_NS", "group__nvic__trustzone__functions.html#gaf5f578628bc8b7154b29577f6f6a87fd", null ], + [ "TZ_NVIC_SetPendingIRQ_NS", "group__nvic__trustzone__functions.html#gaccbc9aa0eacf4d4c3d3046edb9e02edd", null ], + [ "TZ_NVIC_SetPriority_NS", "group__nvic__trustzone__functions.html#ga2caf0df3603378c436c838138e42059a", null ], + [ "TZ_NVIC_SetPriorityGrouping_NS", "group__nvic__trustzone__functions.html#ga0d3b5db0685bd95cc8bd2f7ad0891d39", null ] +];
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Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains typically these definition and also includes the core specific header files.</p> +<p>The definitions for <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.</p> +<p>Each peripheral provides a data type definition with a name that is composed of:</p> +<ul> +<li>an optional prefix <b><<em>device abbreviation></em>_</b></li> +<li><b><<em>peripheral name</em>></b></li> +<li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li> +</ul> +<p>Examples:</p> +<ul> +<li><b>UART_TypeDef</b> for the peripheral <b>UART</b>.</li> +<li><b>LPC_UART_TypeDef</b> for the device family <b>LPC</b> and the peripheral <b>UART</b>.</li> +</ul> +<p>The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.</p> +<ul> +<li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="doxtable"> +<tr> +<th align="left">IO Type Qualifier </th><th align="left">Type </th><th align="left">Description </th></tr> +<tr> +<td align="left"><b>__IM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read only' permissions </td></tr> +<tr> +<td align="left"><b>__OM</b> </td><td align="left">Struct member </td><td align="left">Defines 'write only' permissions </td></tr> +<tr> +<td align="left"><b>__IOM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read / write' permissions </td></tr> +<tr> +<td align="left"><b>__I</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read only' permissions </td></tr> +<tr> +<td align="left"><b>__O</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'write only' permissions </td></tr> +<tr> +<td align="left"><b>__IO</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read / write' permissions </td></tr> +</table> +<dl class="section note"><dt>Note</dt><dd><b>__IM</b>, <b>__OM</b>, <b>__IOM</b> are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used <b>__I</b>, <b>__O</b>, <b>__IO</b> also for struct member definitions.</dd></dl> +The typedef <b><<em>device abbreviation</em>>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</li> +</ul> +<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div> +<div class="line">{</div> +<div class="line"> <span class="keyword">union </span>{</div> +<div class="line"> __IM uint8_t RBR; <span class="comment">/* Offset: 0x000 (R/ ) Receiver Buffer Register */</span></div> +<div class="line"> __OM uint8_t THR; <span class="comment">/* Offset: 0x000 ( /W) Transmit Holding Register */</span></div> +<div class="line"> __IOM uint8_t DLL; <span class="comment">/* Offset: 0x000 (R/W) Divisor Latch LSB */</span></div> +<div class="line"> uint32_t RESERVED0;</div> +<div class="line"> };</div> +<div class="line"> <span class="keyword">union </span>{</div> +<div class="line"> __IOM uint8_t DLM; <span class="comment">/* Offset: 0x004 (R/W) Divisor Latch MSB */</span></div> +<div class="line"> __IOM uint32_t IER; <span class="comment">/* Offset: 0x004 (R/W) Interrupt Enable Register */</span></div> +<div class="line"> };</div> +<div class="line"> <span class="keyword">union </span>{</div> +<div class="line"> __IM uint32_t IIR; <span class="comment">/* Offset: 0x008 (R/ ) Interrupt ID Register */</span></div> +<div class="line"> __OM uint8_t FCR; <span class="comment">/* Offset: 0x008 ( /W) FIFO Control Register */</span></div> +<div class="line"> };</div> +<div class="line"> __IOM uint8_t LCR; <span class="comment">/* Offset: 0x00C (R/W) Line Control Register */</span></div> +<div class="line"> uint8_t RESERVED1[7];</div> +<div class="line"> __IM uint8_t LSR; <span class="comment">/* Offset: 0x014 (R/ ) Line Status Register */</span></div> +<div class="line"> uint8_t RESERVED2[7];</div> +<div class="line"> __IOM uint8_t SCR; <span class="comment">/* Offset: 0x01C (R/W) Scratch Pad Register */</span></div> +<div class="line"> uint8_t RESERVED3[3];</div> +<div class="line"> __IOM uint32_t ACR; <span class="comment">/* Offset: 0x020 (R/W) Autobaud Control Register */</span></div> +<div class="line"> __IOM uint8_t ICR; <span class="comment">/* Offset: 0x024 (R/W) IrDA Control Register */</span></div> +<div class="line"> uint8_t RESERVED4[3];</div> +<div class="line"> __IOM uint8_t FDR; <span class="comment">/* Offset: 0x028 (R/W) Fractional Divider Register */</span></div> +<div class="line"> uint8_t RESERVED5[7];</div> +<div class="line"> __IOM uint8_t TER; <span class="comment">/* Offset: 0x030 (R/W) Transmit Enable Register */</span></div> +<div class="line"> uint8_t RESERVED6[39];</div> +<div class="line"> __IM uint8_t FIFOLVL; <span class="comment">/* Offset: 0x058 (R/ ) FIFO Level Register */</span></div> +<div class="line">} LPC_UART_TypeDef;</div> +</div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p> +<p><b>Example:</b> In this example <b>LPC_UART2</b> and <b>LPC_UART3</b> are two pointers to UARTs defined with above register structure. <br/> +</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )</span></div> +<div class="line"><span class="preprocessor">#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</span></div> +</div><!-- fragment --><dl class="section note"><dt>Note</dt><dd><ul> +<li>The prefix <b>LPC</b> is optional.</li> +</ul> +</dd></dl> +<p>The registers in the various UARTs can now be referred in the user code as shown below:<br/> +</p> +<div class="fragment"><div class="line">val = LPC_UART2->DR <span class="comment">// is the data register of UART1.</span></div> +</div><!-- fragment --><hr/> +<h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a> +Minimal Requirements</h1> +<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/> +<br/> +</p> +<ul> +<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/> +<br/> +<b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div> +<div class="line">{</div> +<div class="line"> __IOM uint32_t CTRL; <span class="comment">/* Offset: 0x000 (R/W) SysTick Control and Status Register */</span></div> +<div class="line"> __IOM uint32_t LOAD; <span class="comment">/* Offset: 0x004 (R/W) SysTick Reload Value Register */</span></div> +<div class="line"> __IOM uint32_t VAL; <span class="comment">/* Offset: 0x008 (R/W) SysTick Current Value Register */</span></div> +<div class="line"> __IM uint32_t CALIB; <span class="comment">/* Offset: 0x00C (R/ ) SysTick Calibration Register */</span></div> +<div class="line">} <a class="code" href="structSysTick__Type.html">SysTick_Type</a>;</div> +</div><!-- fragment --></li> +<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/> +<br/> +<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010) </span><span class="comment">/* SysTick Base Address */</span><span class="preprocessor"></span></div> +</div><!-- fragment --></li> +<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/> +<br/> +<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE) </span><span class="comment">/* SysTick access definition */</span><span class="preprocessor"></span></div> +</div><!-- fragment --></li> +</ul> +<p>These definitions allow accessing peripheral registers with simple assignments.</p> +<ul> +<li><b>Example:</b> <br/> +<div class="fragment"><div class="line">SysTick->CTRL = 0;</div> +</div><!-- fragment --></li> +</ul> +<hr/> +<h1><a class="anchor" id="core_cmsis_pal_opts"></a> +Optional Features</h1> +<p>Optionally, the file <b><em>device</em>.h</b> may define:</p> +<ul> +<li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>. It is recommended to use CAPITAL letters for #define constants.</li> +<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>.</li> +</ul> +<hr/> +<h1><a class="anchor" id="core_cmsis_pal_bitfields"></a> +Register Bit Fields</h1> +<p>For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.</p> +<p><b>Example:</b></p> +<p>Bit field definitions for register CPUID in SCB (System Control Block).</p> +<div class="fragment"><div class="line"><span class="comment">/* SCB CPUID Register Definitions */</span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos 24U </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Pos 20U </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos 16U </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Pos 4U </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Pos 0U </span></div> +<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Msk (0xFUL </span><span class="comment">/*<< SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">) </span></div> +</div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning the result to a peripheral register. ">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value. ">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p> +<h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga139b6e261c981f014f386927ca4a8444"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define _FLD2VAL</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">field, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">value </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">field</td><td>name of bit field. </td></tr> + <tr><td class="paramname">value</td><td>value of the register. This parameter is interpreted as an uint32_t type.</td></tr> + </table> + </dd> +</dl> +<p>The macro <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line"><span class="keywordtype">id</span> = <a class="code" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(SCB_CPUID_REVISION, SCB->CPUID);</div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="ga286e3b913dbd236c7f48ea70c8821f4e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define _VAL2FLD</td> + <td>(</td> + <td class="paramtype"> </td> + <td class="paramname">field, </td> + </tr> + <tr> + <td class="paramkey"></td> + <td></td> + <td class="paramtype"> </td> + <td class="paramname">value </td> + </tr> + <tr> + <td></td> + <td>)</td> + <td></td><td></td> + </tr> + </table> +</div><div class="memdoc"> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramname">field</td><td>name of bit field. </td></tr> + <tr><td class="paramname">value</td><td>value for the bit field. This parameter is interpreted as an uint32_t type.</td></tr> + </table> + </dd> +</dl> +<p>The macro <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p> +<p><b>Example:</b> </p> +<div class="fragment"><div class="line">SCB->CPUID = <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_REVISION, 0x3) | <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(SCB_CPUID_VARIANT, 0x3);</div> +</div><!-- fragment --> +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__peripheral__gr.js b/docs/Core/html/group__peripheral__gr.js new file mode 100644 index 0000000..39b83c7 --- /dev/null +++ b/docs/Core/html/group__peripheral__gr.js @@ -0,0 +1,5 @@ +var group__peripheral__gr = +[ + [ "_FLD2VAL", "group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444", null ], + [ "_VAL2FLD", "group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__sau__trustzone__functions.html b/docs/Core/html/group__sau__trustzone__functions.html new file mode 100644 index 0000000..c1cb706 --- /dev/null +++ b/docs/Core/html/group__sau__trustzone__functions.html @@ -0,0 +1,201 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SAU Functions</title> +<title>CMSIS-Core (Cortex-M): SAU Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__sau__trustzone__functions.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">SAU Functions<div class="ingroups"><a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> (void)</td></tr> +<tr class="memdesc:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="mdescLeft"> </td><td class="mdescRight">Setup Secure Attribute Unit (SAU) and non-secure interrupts. <a href="#ga6093bc5939ea8924fbcfdffb8f0553f1">More...</a><br/></td></tr> +<tr class="separator:ga6093bc5939ea8924fbcfdffb8f0553f1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga187377409289e34838225ce801fb102c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga187377409289e34838225ce801fb102c">TZ_SAU_Enable</a> (void)</td></tr> +<tr class="memdesc:ga187377409289e34838225ce801fb102c"><td class="mdescLeft"> </td><td class="mdescRight">Enable Security Attribution Unit (SAU) <a href="#ga187377409289e34838225ce801fb102c">More...</a><br/></td></tr> +<tr class="separator:ga187377409289e34838225ce801fb102c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga42e201cea0a4b09f588a28b751f726fb"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html#ga42e201cea0a4b09f588a28b751f726fb">TZ_SAU_Disable</a> (void)</td></tr> +<tr class="memdesc:ga42e201cea0a4b09f588a28b751f726fb"><td class="mdescLeft"> </td><td class="mdescRight">Disable Security Attribution Unit (SAU) <a href="#ga42e201cea0a4b09f588a28b751f726fb">More...</a><br/></td></tr> +<tr class="separator:ga42e201cea0a4b09f588a28b751f726fb"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The Secure Attribution Unit (SAU) functions SAU</p> +<dl class="section note"><dt>Note</dt><dd>A SAU is always present if the security extension is available. The functionality differs if the SAU contains SAU regions. If SAU regions are available is configured with the macro __SAUREGION_PRESENT (see <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a>). </dd></dl> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="ga42e201cea0a4b09f588a28b751f726fb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_SAU_Disable </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Disables the Security Attribution Unit (SAU). </p> + +</div> +</div> +<a class="anchor" id="ga187377409289e34838225ce801fb102c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_SAU_Enable </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enables the Security Attribution Unit (SAU). </p> + +</div> +</div> +<a class="anchor" id="ga6093bc5939ea8924fbcfdffb8f0553f1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void TZ_SAU_Setup </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> uses the settings in the <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts. It is called from the function <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__sau__trustzone__functions.js b/docs/Core/html/group__sau__trustzone__functions.js new file mode 100644 index 0000000..12263bf --- /dev/null +++ b/docs/Core/html/group__sau__trustzone__functions.js @@ -0,0 +1,6 @@ +var group__sau__trustzone__functions = +[ + [ "TZ_SAU_Disable", "group__sau__trustzone__functions.html#ga42e201cea0a4b09f588a28b751f726fb", null ], + [ "TZ_SAU_Enable", "group__sau__trustzone__functions.html#ga187377409289e34838225ce801fb102c", null ], + [ "TZ_SAU_Setup", "group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__system__init__gr.html b/docs/Core/html/group__system__init__gr.html new file mode 100644 index 0000000..96bf4fe --- /dev/null +++ b/docs/Core/html/group__system__init__gr.html @@ -0,0 +1,231 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>System and Clock Configuration</title> +<title>CMSIS-Core (Cortex-M): System and Clock Configuration</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> | +<a href="#var-members">Variables</a> </div> + <div class="headertitle"> +<div class="title">System and Clock Configuration</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions for system and clock setup available in system_<em>device</em>.c. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> (void)</td></tr> +<tr class="memdesc:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="mdescLeft"> </td><td class="mdescRight">Function to Initialize the system. <a href="#ga93f514700ccf00d08dbdcff7f1224eb2">More...</a><br/></td></tr> +<tr class="separator:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> (void)</td></tr> +<tr class="memdesc:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="mdescLeft"> </td><td class="mdescRight">Function to update the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. <a href="#gae0c36a9591fe6e9c45ecb21a794f0f0f">More...</a><br/></td></tr> +<tr class="separator:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a> +Variables</h2></td></tr> +<tr class="memitem:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr> +<tr class="memdesc:gaa3cd3e43291e81e795d642b79b6088e6"><td class="mdescLeft"> </td><td class="mdescRight">Variable to hold the system core clock value. <a href="#gaa3cd3e43291e81e795d642b79b6088e6">More...</a><br/></td></tr> +<tr class="separator:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>Arm provides a template file <b>system_<em>device</em>.c</b> that must be adapted by the silicon vendor to match their actual device. As a <b>minimum requirement</b>, this file must provide:</p> +<ul> +<li>A device-specific system configuration function, <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit()</a>.</li> +<li>A global variable that contains the system frequency, <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>.</li> +</ul> +<p>The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.</p> +<dl class="section note"><dt>Note</dt><dd>Please pay special attention to the static variable <code>SystemCoreClock</code>. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed. Be aware that a value stored to <code>SystemCoreClock</code> during low level initializaton (i.e. <code><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a></code>) might get overwritten by C libray startup code. Thus its highly recommended to call <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> at the beginning of the user <code>main()</code> routine.</dd></dl> +<h1><a class="anchor" id="system_init_code_ex_sec"></a> +Code Example</h1> +<p>The code below shows the usage of the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and the functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> and <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock. ">SystemCoreClockUpdate()</a> with an LPC1700.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div> +<div class="line"></div> +<div class="line">uint32_t coreClock_1 = 0; <span class="comment">/* Variables to store core clock values */</span></div> +<div class="line">uint32_t coreClock_2 = 0;</div> +<div class="line"></div> +<div class="line"></div> +<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div> +<div class="line"></div> +<div class="line"> coreClock_1 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>; <span class="comment">/* Store value of predefined SystemCoreClock */</span></div> +<div class="line"></div> +<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a>(); <span class="comment">/* Update SystemCoreClock according to register settings */</span></div> +<div class="line"></div> +<div class="line"> coreClock_2 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>; <span class="comment">/* Store value of calculated SystemCoreClock */</span></div> +<div class="line"></div> +<div class="line"> <span class="keywordflow">if</span> (coreClock_2 != coreClock_1) { <span class="comment">/* Without changing the clock setting both core clock values should be the same */</span> </div> +<div class="line"> <span class="comment">// Error Handling</span></div> +<div class="line"> }</div> +<div class="line"></div> +<div class="line"> <span class="keywordflow">while</span>(1);</div> +<div class="line">}</div> +</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gae0c36a9591fe6e9c45ecb21a794f0f0f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void SystemCoreClockUpdate </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. </p> + +</div> +</div> +<a class="anchor" id="ga93f514700ccf00d08dbdcff7f1224eb2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">void SystemInit </td> + <td>(</td> + <td class="paramtype">void </td> + <td class="paramname"></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. SystemInit is called from the file <b>startup<em>_device</em></b>. </p> + +</div> +</div> +<h2 class="groupheader">Variable Documentation</h2> +<a class="anchor" id="gaa3cd3e43291e81e795d642b79b6088e6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t SystemCoreClock</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.</p> +<dl class="section attention"><dt>Attention</dt><dd>Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__system__init__gr.js b/docs/Core/html/group__system__init__gr.js new file mode 100644 index 0000000..1ed21ea --- /dev/null +++ b/docs/Core/html/group__system__init__gr.js @@ -0,0 +1,6 @@ +var group__system__init__gr = +[ + [ "SystemCoreClockUpdate", "group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f", null ], + [ "SystemInit", "group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2", null ], + [ "SystemCoreClock", "group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__systick__trustzone__functions.html b/docs/Core/html/group__systick__trustzone__functions.html new file mode 100644 index 0000000..240eb3f --- /dev/null +++ b/docs/Core/html/group__systick__trustzone__functions.html @@ -0,0 +1,173 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SysTick Functions</title> +<title>CMSIS-Core (Cortex-M): SysTick Functions</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#func-members">Functions</a> </div> + <div class="headertitle"> +<div class="title">SysTick Functions<div class="ingroups"><a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>SysTick functions related to TrustZone for Armv8-M. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a> +Functions</h2></td></tr> +<tr class="memitem:gad18a1b1a6796c652f2b35e728f2e2670"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__systick__trustzone__functions.html#gad18a1b1a6796c652f2b35e728f2e2670">TZ_SysTick_Config_NS</a> (uint32_t ticks)</td></tr> +<tr class="memdesc:gad18a1b1a6796c652f2b35e728f2e2670"><td class="mdescLeft"> </td><td class="mdescRight">System Tick Configuration (non-secure) <a href="#gad18a1b1a6796c652f2b35e728f2e2670">More...</a><br/></td></tr> +<tr class="separator:gad18a1b1a6796c652f2b35e728f2e2670"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<h2 class="groupheader">Function Documentation</h2> +<a class="anchor" id="gad18a1b1a6796c652f2b35e728f2e2670"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TZ_SysTick_Config_NS </td> + <td>(</td> + <td class="paramtype">uint32_t </td> + <td class="paramname"><em>ticks</em></td><td>)</td> + <td></td> + </tr> + </table> +</div><div class="memdoc"> +<p>Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. </p> +<dl class="params"><dt>Parameters</dt><dd> + <table class="params"> + <tr><td class="paramdir">[in]</td><td class="paramname">ticks</td><td>Number of ticks between two interrupts. </td></tr> + </table> + </dd> +</dl> +<dl class="section return"><dt>Returns</dt><dd>0 Function succeeded. </dd> +<dd> +1 Function failed. </dd></dl> +<dl class="section note"><dt>Note</dt><dd>When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><em>device</em>.h</b> must contain a vendor-specific implementation of this function. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><ul> +<li><a class="el" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> </li> +</ul> +</dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__systick__trustzone__functions.js b/docs/Core/html/group__systick__trustzone__functions.js new file mode 100644 index 0000000..803de1e --- /dev/null +++ b/docs/Core/html/group__systick__trustzone__functions.js @@ -0,0 +1,4 @@ +var group__systick__trustzone__functions = +[ + [ "TZ_SysTick_Config_NS", "group__systick__trustzone__functions.html#gad18a1b1a6796c652f2b35e728f2e2670", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__trustzone__functions.html b/docs/Core/html/group__trustzone__functions.html new file mode 100644 index 0000000..aadc6ba --- /dev/null +++ b/docs/Core/html/group__trustzone__functions.html @@ -0,0 +1,161 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>TrustZone for Armv8-M</title> +<title>CMSIS-Core (Cortex-M): TrustZone for Armv8-M</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__trustzone__functions.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#groups">Content</a> </div> + <div class="headertitle"> +<div class="title">TrustZone for Armv8-M</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Functions that related to optional Armv8-M security extension. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a> +Content</h2></td></tr> +<tr class="memitem:group__coreregister__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a></td></tr> +<tr class="memdesc:group__coreregister__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Core register Access functions related to TrustZone for Armv8-M. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__nvic__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__nvic__trustzone__functions.html">NVIC Functions</a></td></tr> +<tr class="memdesc:group__nvic__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__systick__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__systick__trustzone__functions.html">SysTick Functions</a></td></tr> +<tr class="memdesc:group__systick__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">SysTick functions related to TrustZone for Armv8-M. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__sau__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__sau__trustzone__functions.html">SAU Functions</a></td></tr> +<tr class="memdesc:group__sau__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:group__context__trustzone__functions"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__context__trustzone__functions.html">RTOS Context Management</a></td></tr> +<tr class="memdesc:group__context__trustzone__functions"><td class="mdescLeft"> </td><td class="mdescRight">RTOS Thread Context Management for Armv8-M TrustZone. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology. To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:</p> +<ul> +<li><a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a></li> +<li><a class="el" href="group__nvic__trustzone__functions.html">NVIC Functions</a></li> +<li><a class="el" href="group__systick__trustzone__functions.html">SysTick Functions</a></li> +<li><a class="el" href="group__sau__trustzone__functions.html">SAU Functions</a></li> +<li><a class="el" href="group__context__trustzone__functions.html">RTOS Context Management</a> </li> +</ul> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__trustzone__functions.js b/docs/Core/html/group__trustzone__functions.js new file mode 100644 index 0000000..d6d489c --- /dev/null +++ b/docs/Core/html/group__trustzone__functions.js @@ -0,0 +1,8 @@ +var group__trustzone__functions = +[ + [ "Core Register Access Functions", "group__coreregister__trustzone__functions.html", "group__coreregister__trustzone__functions" ], + [ "NVIC Functions", "group__nvic__trustzone__functions.html", "group__nvic__trustzone__functions" ], + [ "SysTick Functions", "group__systick__trustzone__functions.html", "group__systick__trustzone__functions" ], + [ "SAU Functions", "group__sau__trustzone__functions.html", "group__sau__trustzone__functions" ], + [ "RTOS Context Management", "group__context__trustzone__functions.html", "group__context__trustzone__functions" ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__version__control__depricated__gr.html b/docs/Core/html/group__version__control__depricated__gr.html new file mode 100644 index 0000000..afbeb0c --- /dev/null +++ b/docs/Core/html/group__version__control__depricated__gr.html @@ -0,0 +1,204 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Version Control per Core (Depricated)</title> +<title>CMSIS-Core (Cortex-M): Version Control per Core (Depricated)</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__version__control__depricated__gr.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#define-members">Macros</a> </div> + <div class="headertitle"> +<div class="title">Version Control per Core (Depricated)<div class="ingroups"><a class="el" href="group__version__control__gr.html">Version Control</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>Version #define symbols for CMSIS release specific C/C++ source code. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ga2ecc1658e18eb1a0be7959e33b836d05"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__depricated__gr.html#ga2ecc1658e18eb1a0be7959e33b836d05">__XXX_CMSIS_VERSION_MAIN</a></td></tr> +<tr class="memdesc:ga2ecc1658e18eb1a0be7959e33b836d05"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS major version for core of type XXX, i.e. CM0 or SC300. <a href="#ga2ecc1658e18eb1a0be7959e33b836d05">More...</a><br/></td></tr> +<tr class="separator:ga2ecc1658e18eb1a0be7959e33b836d05"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga962096f43e0d194f0b79021964c57fbd"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__depricated__gr.html#ga962096f43e0d194f0b79021964c57fbd">__XXX_CMSIS_VERSION_SUB</a></td></tr> +<tr class="memdesc:ga962096f43e0d194f0b79021964c57fbd"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS minor version for core of type XXX, i.e. CM0 or SC300. <a href="#ga962096f43e0d194f0b79021964c57fbd">More...</a><br/></td></tr> +<tr class="separator:ga962096f43e0d194f0b79021964c57fbd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gabea7df329b150f620ee42f9d82516241"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__depricated__gr.html#gabea7df329b150f620ee42f9d82516241">__XXX_CMSIS_VERSION</a></td></tr> +<tr class="memdesc:gabea7df329b150f620ee42f9d82516241"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS version for core of type XXX, i.e. CM0 or SC300. <a href="#gabea7df329b150f620ee42f9d82516241">More...</a><br/></td></tr> +<tr class="separator:gabea7df329b150f620ee42f9d82516241"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>Prior CMSIS release 5.1.0 the version information was core specific.</p> +<p><b>Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#if !defined(__CM_CMSIS_VERSION) && defined(__CORTEX_M)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#if ((__CORTEX_M == 0) && (__CM0_CMSIS_VERSION >= 0x00050000)) || \</span></div> +<div class="line"><span class="preprocessor"> ((__CORTEX_M == 3) && (__CM3_CMSIS_VERSION >= 0x00050000)) || \</span></div> +<div class="line"><span class="preprocessor"> ((__CORTEX_M == 4) && (__CM4_CMSIS_VERSION >= 0x00050000)) || \</span></div> +<div class="line"><span class="preprocessor"> ((__CORTEX_M == 7) && (__CM7_CMSIS_VERSION >= 0x00050000))</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have CMSIS 5!</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need CMSIS 5!</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#endif</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need a Cortex-M controller!</span></div> +<div class="line"><span class="preprocessor">#endif</span></div> +</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="gabea7df329b150f620ee42f9d82516241"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __XXX_CMSIS_VERSION</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS version is a combination of the <a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a> (bits 31..15) and <a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a> (bits 14..0). </p> +<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000003">Deprecated:</a></b></dt><dd>Only rely on this define for CMSIS 5.0 and before. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga2ecc1658e18eb1a0be7959e33b836d05"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __XXX_CMSIS_VERSION_MAIN</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS major version can be used to differentiate between CMSIS major releases. </p> +<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000001">Deprecated:</a></b></dt><dd>Only rely on this define for CMSIS 5.0 and before. </dd></dl> + +</div> +</div> +<a class="anchor" id="ga962096f43e0d194f0b79021964c57fbd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __XXX_CMSIS_VERSION_SUB</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS minor version can be used to query a CMSIS release update level. </p> +<dl class="deprecated"><dt><b><a class="el" href="deprecated.html#_deprecated000002">Deprecated:</a></b></dt><dd>Only rely on this define for CMSIS 5.0 and before. </dd></dl> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__version__control__depricated__gr.js b/docs/Core/html/group__version__control__depricated__gr.js new file mode 100644 index 0000000..02d3c83 --- /dev/null +++ b/docs/Core/html/group__version__control__depricated__gr.js @@ -0,0 +1,6 @@ +var group__version__control__depricated__gr = +[ + [ "__XXX_CMSIS_VERSION", "group__version__control__depricated__gr.html#gabea7df329b150f620ee42f9d82516241", null ], + [ "__XXX_CMSIS_VERSION_MAIN", "group__version__control__depricated__gr.html#ga2ecc1658e18eb1a0be7959e33b836d05", null ], + [ "__XXX_CMSIS_VERSION_SUB", "group__version__control__depricated__gr.html#ga962096f43e0d194f0b79021964c57fbd", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/group__version__control__gr.html b/docs/Core/html/group__version__control__gr.html new file mode 100644 index 0000000..3ac128f --- /dev/null +++ b/docs/Core/html/group__version__control__gr.html @@ -0,0 +1,258 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Version Control</title> +<title>CMSIS-Core (Cortex-M): Version Control</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('group__version__control__gr.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#groups">Content</a> | +<a href="#define-members">Macros</a> </div> + <div class="headertitle"> +<div class="title">Version Control</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Version #define symbols for CMSIS release specific C/C++ source code. +<a href="#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a> +Content</h2></td></tr> +<tr class="memitem:group__version__control__depricated__gr"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__depricated__gr.html">Version Control per Core (Depricated)</a></td></tr> +<tr class="memdesc:group__version__control__depricated__gr"><td class="mdescLeft"> </td><td class="mdescRight">Version #define symbols for CMSIS release specific C/C++ source code. <br/></td></tr> +<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr> +</table><table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a> +Macros</h2></td></tr> +<tr class="memitem:ga85987c5fcc1e012d7ac01369ee6ca2b5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a></td></tr> +<tr class="memdesc:ga85987c5fcc1e012d7ac01369ee6ca2b5"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS major version. <a href="#ga85987c5fcc1e012d7ac01369ee6ca2b5">More...</a><br/></td></tr> +<tr class="separator:ga85987c5fcc1e012d7ac01369ee6ca2b5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga22083cbe7f0606cfd538ec12b2e41608"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a></td></tr> +<tr class="memdesc:ga22083cbe7f0606cfd538ec12b2e41608"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS minor version. <a href="#ga22083cbe7f0606cfd538ec12b2e41608">More...</a><br/></td></tr> +<tr class="separator:ga22083cbe7f0606cfd538ec12b2e41608"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga39f3d64ff95fb58feccc7639e537ff89"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89">__CM_CMSIS_VERSION</a></td></tr> +<tr class="memdesc:ga39f3d64ff95fb58feccc7639e537ff89"><td class="mdescLeft"> </td><td class="mdescRight">Contains the CMSIS version. <a href="#ga39f3d64ff95fb58feccc7639e537ff89">More...</a><br/></td></tr> +<tr class="separator:ga39f3d64ff95fb58feccc7639e537ff89"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ga63ea62503c88acab19fcf3d5743009e3"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#ga63ea62503c88acab19fcf3d5743009e3">__CORTEX_M</a></td></tr> +<tr class="memdesc:ga63ea62503c88acab19fcf3d5743009e3"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core version for a Cortex-M class controller. <a href="#ga63ea62503c88acab19fcf3d5743009e3">More...</a><br/></td></tr> +<tr class="separator:ga63ea62503c88acab19fcf3d5743009e3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">__CORTEX_SC</a></td></tr> +<tr class="memdesc:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="mdescLeft"> </td><td class="mdescRight">Contains the core version for a Cortex Secure Core controller. <a href="#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c">More...</a><br/></td></tr> +<tr class="separator:gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<p>The header file <b>cmsis_version.h</b> is included by each core header so that these definitions are available.</p> +<p><b>Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CM_CMSIS_VERSION) && \</span></div> +<div class="line"><span class="preprocessor"> (__CM_CMSIS_VERSION >= 0x00050001)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have CMSIS 5.1 or later</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need CMSIS 5.1 or later!</span></div> +<div class="line"><span class="preprocessor">#endif</span></div> +</div><!-- fragment --> <h2 class="groupheader">Macro Definition Documentation</h2> +<a class="anchor" id="ga39f3d64ff95fb58feccc7639e537ff89"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __CM_CMSIS_VERSION</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS version is a combination of the <a class="el" href="group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5">__CM_CMSIS_VERSION_MAIN</a> (bits 31..15) and <a class="el" href="group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608">__CM_CMSIS_VERSION_SUB</a> (bits 14..0). </p> + +</div> +</div> +<a class="anchor" id="ga85987c5fcc1e012d7ac01369ee6ca2b5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __CM_CMSIS_VERSION_MAIN</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS major version can be used to differentiate between CMSIS major releases. </p> + +</div> +</div> +<a class="anchor" id="ga22083cbe7f0606cfd538ec12b2e41608"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __CM_CMSIS_VERSION_SUB</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The CMSIS minor version can be used to query a CMSIS release update level. </p> + +</div> +</div> +<a class="anchor" id="ga63ea62503c88acab19fcf3d5743009e3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __CORTEX_M</td> + </tr> + </table> +</div><div class="memdoc"> +<p>This define can be used to differentiate between the various available Cortex-M controllers. Possible values are:</p> +<ul> +<li>0 for a Cortex-M0 or Cortex-M0+</li> +<li>3 for a Cortex-M3</li> +<li>4 for a Cortex-M4</li> +<li>7 for a Cortex-M7</li> +<li>23 for a Cortex-M23</li> +<li>33 for a Cortex-M33</li> +</ul> +<p>This define is only available for Cortex-M class controllers. <b>Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CORTEX_M) && (__CORTEX_M == 4)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have an Cortex-M4 controller.</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need a Cortex-M4 controller!</span></div> +<div class="line"><span class="preprocessor">#endif</span></div> +</div><!-- fragment --> +</div> +</div> +<a class="anchor" id="gaeaaf66c86e5ae02a0e1fe542cb7f4d8c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">#define __CORTEX_SC</td> + </tr> + </table> +</div><div class="memdoc"> +<p>This define can be used to differentiate between the various available Cortex Secure Core controllers. Possible values are:</p> +<ul> +<li>000 for a Cortex-SC000</li> +<li>300 for a Cortex-SC300</li> +</ul> +<p>This define is only available for Cortex Secure Core controllers. <b>Code Example:</b> </p> +<div class="fragment"><div class="line"><span class="preprocessor">#if defined(__CORTEX_SC) && (__CORTEX_SC == 300U)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error Yes, we have an Cortex SC300 controller.</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#error We need a Cortex SC300 controller!</span></div> +<div class="line"><span class="preprocessor">#endif</span></div> +</div><!-- fragment --> +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/group__version__control__gr.js b/docs/Core/html/group__version__control__gr.js new file mode 100644 index 0000000..32b6209 --- /dev/null +++ b/docs/Core/html/group__version__control__gr.js @@ -0,0 +1,9 @@ +var group__version__control__gr = +[ + [ "Version Control per Core (Depricated)", "group__version__control__depricated__gr.html", "group__version__control__depricated__gr" ], + [ "__CM_CMSIS_VERSION", "group__version__control__gr.html#ga39f3d64ff95fb58feccc7639e537ff89", null ], + [ "__CM_CMSIS_VERSION_MAIN", "group__version__control__gr.html#ga85987c5fcc1e012d7ac01369ee6ca2b5", null ], + [ "__CM_CMSIS_VERSION_SUB", "group__version__control__gr.html#ga22083cbe7f0606cfd538ec12b2e41608", null ], + [ "__CORTEX_M", "group__version__control__gr.html#ga63ea62503c88acab19fcf3d5743009e3", null ], + [ "__CORTEX_SC", "group__version__control__gr.html#gaeaaf66c86e5ae02a0e1fe542cb7f4d8c", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/index.html b/docs/Core/html/index.html new file mode 100644 index 0000000..24643bb --- /dev/null +++ b/docs/Core/html/index.html @@ -0,0 +1,196 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Overview</title> +<title>CMSIS-Core (Cortex-M): Overview</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li class="current"><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('index.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Overview </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p> +<ul> +<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li> +<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li> +<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li> +<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system. ">SystemInit()</a> function is essential for configuring the clock system of the device.</li> +<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li> +<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li> +</ul> +<p>The following sections provide details about the CMSIS-Core (Cortex-M):</p> +<ul> +<li><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li> +<li><a class="el" href="using_TrustZone_pg.html">Using TrustZone® for Armv8-M</a> describes how to use the security extensions available in the Armv8-M architecture.</li> +<li><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.</li> +<li><a class="el" href="coreMISRA_Exceptions_pg.html">MISRA-C Deviations</a> describes the violations to the MISRA standard.</li> +<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li> +<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li> +</ul> +<hr/> +<h2>CMSIS-Core (Cortex-M) in ARM::CMSIS Pack </h2> +<p>Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories: </p> +<table class="doxtable"> +<tr> +<th>File/Folder </th><th>Content </th></tr> +<tr> +<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr> +<tr> +<td><b>CMSIS\Core\Include</b> </td><td>CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr> +<tr> +<td><b>Device</b> </td><td><a class="el" href="using_ARM_pg.html">Arm reference implementations</a> of Cortex-M devices </td></tr> +<tr> +<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> for extension by silicon vendors </td></tr> +</table> +<hr/> +<h1><a class="anchor" id="ref_v6-v8M"></a> +Processor Support</h1> +<p>CMSIS supports the complete range of <a href="http://www.arm.com/products/processors/cortex-m/index.php" target="_blank"><b>Cortex-M processors</b></a> (with exception of Cortex-M1) and the <a href="http://www.arm.com/products/processors/instruction-set-architectures/armv8-m-architecture.php" target="_blank"><b>Armv8-M architecture</b></a> including security extensions.</p> +<h2><a class="anchor" id="ref_man_sec"></a> +Cortex-M Reference Manuals</h2> +<p>The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:</p> +<ul> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)</li> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)</li> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)</li> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (ARMv7-M architecture)</li> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)</li> +</ul> +<p>The <b>Cortex-M23</b> and <b>Cortex-M33</b> are described with Technical Reference Manuals that are available here:</p> +<ul> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0550c/cortex_m23_r1p0_technical_reference_manual_DDI0550C_en.pdf" target="_blank"><b>Cortex-M23 Technical Reference Manual</b></a> (Armv8-M baseline architecture)</li> +<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.100230_0002_00_en/cortex_m33_trm_100230_0002_00_en.pdf" target="_blank"><b>Cortex-M33 Technical Reference Manual</b></a> (Armv8-M mainline architecture)</li> +</ul> +<h2><a class="anchor" id="ARMv8M"></a> +Armv8-M Architecture</h2> +<p>Armv8-M introduces two profiles <b>baseline</b> (for power and area constrained applications) and <b>mainline</b> (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.</p> +<p>The Armv8-M Architecture is described in the <a href="http://developer.arm.com/products/architecture/m-profile/docs/ddi0553/latest/armv8-m-architecture-reference-manual" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.</p> +<hr/> +<h1><a class="anchor" id="tested_tools_sec"></a> +Tested and Verified Toolchains</h1> +<p>The <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> supplied by Arm have been tested and verified with the following toolchains:</p> +<ul> +<li>Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)</li> +<li>Arm: Arm Compiler 6.9</li> +<li>Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)</li> +<li>GNU: GNU Tools for Arm Embedded 6.3.1 20170620</li> +<li>IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183</li> +</ul> +<hr/> + </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. 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aP=/[\n\t\r]/g,af=/\s+/,aU=/\r/g,g=/^(?:button|input)$/i,D=/^(?:button|input|object|select|textarea)$/i,l=/^a(?:rea)?$/i,ao=/^(?:autofocus|autoplay|async|checked|controls|defer|disabled|hidden|loop|multiple|open|readonly|required|scoped|selected)$/i,F=b.support.getSetAttribute,be,aY,aF;b.fn.extend({attr:function(e,bv){return b.access(this,e,bv,true,b.attr)},removeAttr:function(e){return this.each(function(){b.removeAttr(this,e)})},prop:function(e,bv){return b.access(this,e,bv,true,b.prop)},removeProp:function(e){e=b.propFix[e]||e;return this.each(function(){try{this[e]=L;delete this[e]}catch(bv){}})},addClass:function(by){var bA,bw,bv,bx,bz,bB,e;if(b.isFunction(by)){return this.each(function(bC){b(this).addClass(by.call(this,bC,this.className))})}if(by&&typeof by==="string"){bA=by.split(af);for(bw=0,bv=this.length;bw<bv;bw++){bx=this[bw];if(bx.nodeType===1){if(!bx.className&&bA.length===1){bx.className=by}else{bz=" "+bx.className+" ";for(bB=0,e=bA.length;bB<e;bB++){if(!~bz.indexOf(" "+bA[bB]+" ")){bz+=bA[bB]+" "}}bx.className=b.trim(bz)}}}}return this},removeClass:function(bz){var bA,bw,bv,by,bx,bB,e;if(b.isFunction(bz)){return this.each(function(bC){b(this).removeClass(bz.call(this,bC,this.className))})}if((bz&&typeof bz==="string")||bz===L){bA=(bz||"").split(af);for(bw=0,bv=this.length;bw<bv;bw++){by=this[bw];if(by.nodeType===1&&by.className){if(bz){bx=(" "+by.className+" ").replace(aP," ");for(bB=0,e=bA.length;bB<e;bB++){bx=bx.replace(" "+bA[bB]+" "," ")}by.className=b.trim(bx)}else{by.className=""}}}}return this},toggleClass:function(bx,bv){var bw=typeof bx,e=typeof bv==="boolean";if(b.isFunction(bx)){return this.each(function(by){b(this).toggleClass(bx.call(this,by,this.className,bv),bv)})}return this.each(function(){if(bw==="string"){var bA,bz=0,by=b(this),bB=bv,bC=bx.split(af);while((bA=bC[bz++])){bB=e?bB:!by.hasClass(bA);by[bB?"addClass":"removeClass"](bA)}}else{if(bw==="undefined"||bw==="boolean"){if(this.className){b._data(this,"__className__",this.className)}this.className=this.className||bx===false?"":b._data(this,"__className__")||""}}})},hasClass:function(e){var bx=" "+e+" ",bw=0,bv=this.length;for(;bw<bv;bw++){if(this[bw].nodeType===1&&(" "+this[bw].className+" ").replace(aP," ").indexOf(bx)>-1){return true}}return false},val:function(bx){var e,bv,by,bw=this[0];if(!arguments.length){if(bw){e=b.valHooks[bw.nodeName.toLowerCase()]||b.valHooks[bw.type];if(e&&"get" in e&&(bv=e.get(bw,"value"))!==L){return bv}bv=bw.value;return typeof bv==="string"?bv.replace(aU,""):bv==null?"":bv}return}by=b.isFunction(bx);return this.each(function(bA){var bz=b(this),bB;if(this.nodeType!==1){return}if(by){bB=bx.call(this,bA,bz.val())}else{bB=bx}if(bB==null){bB=""}else{if(typeof bB==="number"){bB+=""}else{if(b.isArray(bB)){bB=b.map(bB,function(bC){return bC==null?"":bC+""})}}}e=b.valHooks[this.nodeName.toLowerCase()]||b.valHooks[this.type];if(!e||!("set" in e)||e.set(this,bB,"value")===L){this.value=bB}})}});b.extend({valHooks:{option:{get:function(e){var bv=e.attributes.value;return !bv||bv.specified?e.value:e.text}},select:{get:function(e){var bA,bv,bz,bx,by=e.selectedIndex,bB=[],bC=e.options,bw=e.type==="select-one";if(by<0){return null}bv=bw?by:0;bz=bw?by+1:bC.length;for(;bv<bz;bv++){bx=bC[bv];if(bx.selected&&(b.support.optDisabled?!bx.disabled:bx.getAttribute("disabled")===null)&&(!bx.parentNode.disabled||!b.nodeName(bx.parentNode,"optgroup"))){bA=b(bx).val();if(bw){return bA}bB.push(bA)}}if(bw&&!bB.length&&bC.length){return b(bC[by]).val()}return bB},set:function(bv,bw){var e=b.makeArray(bw);b(bv).find("option").each(function(){this.selected=b.inArray(b(this).val(),e)>=0});if(!e.length){bv.selectedIndex=-1}return e}}},attrFn:{val:true,css:true,html:true,text:true,data:true,width:true,height:true,offset:true},attr:function(bA,bx,bB,bz){var bw,e,by,bv=bA.nodeType; +if(!bA||bv===3||bv===8||bv===2){return}if(bz&&bx in b.attrFn){return b(bA)[bx](bB)}if(typeof bA.getAttribute==="undefined"){return b.prop(bA,bx,bB)}by=bv!==1||!b.isXMLDoc(bA);if(by){bx=bx.toLowerCase();e=b.attrHooks[bx]||(ao.test(bx)?aY:be)}if(bB!==L){if(bB===null){b.removeAttr(bA,bx);return}else{if(e&&"set" in e&&by&&(bw=e.set(bA,bB,bx))!==L){return bw}else{bA.setAttribute(bx,""+bB);return bB}}}else{if(e&&"get" in e&&by&&(bw=e.get(bA,bx))!==null){return bw}else{bw=bA.getAttribute(bx);return bw===null?L:bw}}},removeAttr:function(bx,bz){var by,bA,bv,e,bw=0;if(bz&&bx.nodeType===1){bA=bz.toLowerCase().split(af);e=bA.length;for(;bw<e;bw++){bv=bA[bw];if(bv){by=b.propFix[bv]||bv;b.attr(bx,bv,"");bx.removeAttribute(F?bv:by);if(ao.test(bv)&&by in bx){bx[by]=false}}}}},attrHooks:{type:{set:function(e,bv){if(g.test(e.nodeName)&&e.parentNode){b.error("type property can't be changed")}else{if(!b.support.radioValue&&bv==="radio"&&b.nodeName(e,"input")){var bw=e.value;e.setAttribute("type",bv);if(bw){e.value=bw}return bv}}}},value:{get:function(bv,e){if(be&&b.nodeName(bv,"button")){return be.get(bv,e)}return e in bv?bv.value:null},set:function(bv,bw,e){if(be&&b.nodeName(bv,"button")){return be.set(bv,bw,e)}bv.value=bw}}},propFix:{tabindex:"tabIndex",readonly:"readOnly","for":"htmlFor","class":"className",maxlength:"maxLength",cellspacing:"cellSpacing",cellpadding:"cellPadding",rowspan:"rowSpan",colspan:"colSpan",usemap:"useMap",frameborder:"frameBorder",contenteditable:"contentEditable"},prop:function(bz,bx,bA){var bw,e,by,bv=bz.nodeType;if(!bz||bv===3||bv===8||bv===2){return}by=bv!==1||!b.isXMLDoc(bz);if(by){bx=b.propFix[bx]||bx;e=b.propHooks[bx]}if(bA!==L){if(e&&"set" in e&&(bw=e.set(bz,bA,bx))!==L){return bw}else{return(bz[bx]=bA)}}else{if(e&&"get" in e&&(bw=e.get(bz,bx))!==null){return bw}else{return bz[bx]}}},propHooks:{tabIndex:{get:function(bv){var e=bv.getAttributeNode("tabindex");return e&&e.specified?parseInt(e.value,10):D.test(bv.nodeName)||l.test(bv.nodeName)&&bv.href?0:L}}}});b.attrHooks.tabindex=b.propHooks.tabIndex;aY={get:function(bv,e){var bx,bw=b.prop(bv,e);return bw===true||typeof bw!=="boolean"&&(bx=bv.getAttributeNode(e))&&bx.nodeValue!==false?e.toLowerCase():L},set:function(bv,bx,e){var bw;if(bx===false){b.removeAttr(bv,e)}else{bw=b.propFix[e]||e;if(bw in bv){bv[bw]=true}bv.setAttribute(e,e.toLowerCase())}return e}};if(!F){aF={name:true,id:true};be=b.valHooks.button={get:function(bw,bv){var e;e=bw.getAttributeNode(bv);return e&&(aF[bv]?e.nodeValue!=="":e.specified)?e.nodeValue:L},set:function(bw,bx,bv){var e=bw.getAttributeNode(bv);if(!e){e=av.createAttribute(bv);bw.setAttributeNode(e)}return(e.nodeValue=bx+"")}};b.attrHooks.tabindex.set=be.set;b.each(["width","height"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{set:function(bw,bx){if(bx===""){bw.setAttribute(e,"auto");return bx}}})});b.attrHooks.contenteditable={get:be.get,set:function(bv,bw,e){if(bw===""){bw="false"}be.set(bv,bw,e)}}}if(!b.support.hrefNormalized){b.each(["href","src","width","height"],function(bv,e){b.attrHooks[e]=b.extend(b.attrHooks[e],{get:function(bx){var bw=bx.getAttribute(e,2);return bw===null?L:bw}})})}if(!b.support.style){b.attrHooks.style={get:function(e){return e.style.cssText.toLowerCase()||L},set:function(e,bv){return(e.style.cssText=""+bv)}}}if(!b.support.optSelected){b.propHooks.selected=b.extend(b.propHooks.selected,{get:function(bv){var e=bv.parentNode;if(e){e.selectedIndex;if(e.parentNode){e.parentNode.selectedIndex}}return null}})}if(!b.support.enctype){b.propFix.enctype="encoding"}if(!b.support.checkOn){b.each(["radio","checkbox"],function(){b.valHooks[this]={get:function(e){return e.getAttribute("value")===null?"on":e.value}}})}b.each(["radio","checkbox"],function(){b.valHooks[this]=b.extend(b.valHooks[this],{set:function(e,bv){if(b.isArray(bv)){return(e.checked=b.inArray(b(e).val(),bv)>=0)}}})});var bd=/^(?:textarea|input|select)$/i,n=/^([^\.]*)?(?:\.(.+))?$/,J=/\bhover(\.\S+)?\b/,aO=/^key/,bf=/^(?:mouse|contextmenu)|click/,T=/^(?:focusinfocus|focusoutblur)$/,U=/^(\w*)(?:#([\w\-]+))?(?:\.([\w\-]+))?$/,Y=function(e){var bv=U.exec(e);if(bv){bv[1]=(bv[1]||"").toLowerCase();bv[3]=bv[3]&&new RegExp("(?:^|\\s)"+bv[3]+"(?:\\s|$)")}return bv},j=function(bw,e){var bv=bw.attributes||{};return((!e[1]||bw.nodeName.toLowerCase()===e[1])&&(!e[2]||(bv.id||{}).value===e[2])&&(!e[3]||e[3].test((bv["class"]||{}).value)))},bt=function(e){return b.event.special.hover?e:e.replace(J,"mouseenter$1 mouseleave$1")};b.event={add:function(bx,bC,bJ,bA,by){var bD,bB,bK,bI,bH,bF,e,bG,bv,bz,bw,bE;if(bx.nodeType===3||bx.nodeType===8||!bC||!bJ||!(bD=b._data(bx))){return}if(bJ.handler){bv=bJ;bJ=bv.handler}if(!bJ.guid){bJ.guid=b.guid++}bK=bD.events;if(!bK){bD.events=bK={}}bB=bD.handle;if(!bB){bD.handle=bB=function(bL){return typeof b!=="undefined"&&(!bL||b.event.triggered!==bL.type)?b.event.dispatch.apply(bB.elem,arguments):L};bB.elem=bx}bC=b.trim(bt(bC)).split(" ");for(bI=0;bI<bC.length;bI++){bH=n.exec(bC[bI])||[];bF=bH[1];e=(bH[2]||"").split(".").sort();bE=b.event.special[bF]||{};bF=(by?bE.delegateType:bE.bindType)||bF;bE=b.event.special[bF]||{};bG=b.extend({type:bF,origType:bH[1],data:bA,handler:bJ,guid:bJ.guid,selector:by,quick:Y(by),namespace:e.join(".")},bv);bw=bK[bF];if(!bw){bw=bK[bF]=[];bw.delegateCount=0;if(!bE.setup||bE.setup.call(bx,bA,e,bB)===false){if(bx.addEventListener){bx.addEventListener(bF,bB,false)}else{if(bx.attachEvent){bx.attachEvent("on"+bF,bB)}}}}if(bE.add){bE.add.call(bx,bG);if(!bG.handler.guid){bG.handler.guid=bJ.guid}}if(by){bw.splice(bw.delegateCount++,0,bG)}else{bw.push(bG)}b.event.global[bF]=true}bx=null},global:{},remove:function(bJ,bE,bv,bH,bB){var bI=b.hasData(bJ)&&b._data(bJ),bF,bx,bz,bL,bC,bA,bG,bw,by,bK,bD,e;if(!bI||!(bw=bI.events)){return}bE=b.trim(bt(bE||"")).split(" ");for(bF=0;bF<bE.length;bF++){bx=n.exec(bE[bF])||[];bz=bL=bx[1];bC=bx[2];if(!bz){for(bz in bw){b.event.remove(bJ,bz+bE[bF],bv,bH,true)}continue}by=b.event.special[bz]||{};bz=(bH?by.delegateType:by.bindType)||bz;bD=bw[bz]||[];bA=bD.length;bC=bC?new RegExp("(^|\\.)"+bC.split(".").sort().join("\\.(?:.*\\.)?")+"(\\.|$)"):null;for(bG=0;bG<bD.length;bG++){e=bD[bG];if((bB||bL===e.origType)&&(!bv||bv.guid===e.guid)&&(!bC||bC.test(e.namespace))&&(!bH||bH===e.selector||bH==="**"&&e.selector)){bD.splice(bG--,1);if(e.selector){bD.delegateCount--}if(by.remove){by.remove.call(bJ,e)}}}if(bD.length===0&&bA!==bD.length){if(!by.teardown||by.teardown.call(bJ,bC)===false){b.removeEvent(bJ,bz,bI.handle)}delete bw[bz]}}if(b.isEmptyObject(bw)){bK=bI.handle;if(bK){bK.elem=null}b.removeData(bJ,["events","handle"],true)}},customEvent:{getData:true,setData:true,changeData:true},trigger:function(bv,bD,bA,bJ){if(bA&&(bA.nodeType===3||bA.nodeType===8)){return}var bG=bv.type||bv,bx=[],e,bw,bC,bH,bz,by,bF,bE,bB,bI;if(T.test(bG+b.event.triggered)){return}if(bG.indexOf("!")>=0){bG=bG.slice(0,-1);bw=true}if(bG.indexOf(".")>=0){bx=bG.split(".");bG=bx.shift();bx.sort()}if((!bA||b.event.customEvent[bG])&&!b.event.global[bG]){return}bv=typeof bv==="object"?bv[b.expando]?bv:new b.Event(bG,bv):new b.Event(bG);bv.type=bG;bv.isTrigger=true;bv.exclusive=bw;bv.namespace=bx.join(".");bv.namespace_re=bv.namespace?new RegExp("(^|\\.)"+bx.join("\\.(?:.*\\.)?")+"(\\.|$)"):null;by=bG.indexOf(":")<0?"on"+bG:"";if(!bA){e=b.cache;for(bC in e){if(e[bC].events&&e[bC].events[bG]){b.event.trigger(bv,bD,e[bC].handle.elem,true)}}return}bv.result=L;if(!bv.target){bv.target=bA}bD=bD!=null?b.makeArray(bD):[];bD.unshift(bv);bF=b.event.special[bG]||{};if(bF.trigger&&bF.trigger.apply(bA,bD)===false){return}bB=[[bA,bF.bindType||bG]];if(!bJ&&!bF.noBubble&&!b.isWindow(bA)){bI=bF.delegateType||bG;bH=T.test(bI+bG)?bA:bA.parentNode;bz=null;for(;bH;bH=bH.parentNode){bB.push([bH,bI]);bz=bH}if(bz&&bz===bA.ownerDocument){bB.push([bz.defaultView||bz.parentWindow||bb,bI])}}for(bC=0;bC<bB.length&&!bv.isPropagationStopped();bC++){bH=bB[bC][0];bv.type=bB[bC][1];bE=(b._data(bH,"events")||{})[bv.type]&&b._data(bH,"handle");if(bE){bE.apply(bH,bD)}bE=by&&bH[by];if(bE&&b.acceptData(bH)&&bE.apply(bH,bD)===false){bv.preventDefault()}}bv.type=bG;if(!bJ&&!bv.isDefaultPrevented()){if((!bF._default||bF._default.apply(bA.ownerDocument,bD)===false)&&!(bG==="click"&&b.nodeName(bA,"a"))&&b.acceptData(bA)){if(by&&bA[bG]&&((bG!=="focus"&&bG!=="blur")||bv.target.offsetWidth!==0)&&!b.isWindow(bA)){bz=bA[by];if(bz){bA[by]=null}b.event.triggered=bG;bA[bG]();b.event.triggered=L;if(bz){bA[by]=bz}}}}return bv.result},dispatch:function(e){e=b.event.fix(e||bb.event);var bz=((b._data(this,"events")||{})[e.type]||[]),bA=bz.delegateCount,bG=[].slice.call(arguments,0),by=!e.exclusive&&!e.namespace,bH=[],bC,bB,bK,bx,bF,bE,bv,bD,bI,bw,bJ;bG[0]=e;e.delegateTarget=this;if(bA&&!e.target.disabled&&!(e.button&&e.type==="click")){bx=b(this);bx.context=this.ownerDocument||this;for(bK=e.target;bK!=this;bK=bK.parentNode||this){bE={};bD=[];bx[0]=bK;for(bC=0;bC<bA;bC++){bI=bz[bC];bw=bI.selector;if(bE[bw]===L){bE[bw]=(bI.quick?j(bK,bI.quick):bx.is(bw))}if(bE[bw]){bD.push(bI)}}if(bD.length){bH.push({elem:bK,matches:bD})}}}if(bz.length>bA){bH.push({elem:this,matches:bz.slice(bA)})}for(bC=0;bC<bH.length&&!e.isPropagationStopped();bC++){bv=bH[bC];e.currentTarget=bv.elem;for(bB=0;bB<bv.matches.length&&!e.isImmediatePropagationStopped();bB++){bI=bv.matches[bB];if(by||(!e.namespace&&!bI.namespace)||e.namespace_re&&e.namespace_re.test(bI.namespace)){e.data=bI.data;e.handleObj=bI;bF=((b.event.special[bI.origType]||{}).handle||bI.handler).apply(bv.elem,bG);if(bF!==L){e.result=bF;if(bF===false){e.preventDefault();e.stopPropagation()}}}}}return e.result},props:"attrChange attrName relatedNode srcElement altKey bubbles cancelable ctrlKey currentTarget eventPhase metaKey relatedTarget shiftKey target timeStamp view which".split(" "),fixHooks:{},keyHooks:{props:"char charCode key keyCode".split(" "),filter:function(bv,e){if(bv.which==null){bv.which=e.charCode!=null?e.charCode:e.keyCode}return bv}},mouseHooks:{props:"button buttons clientX clientY fromElement offsetX offsetY pageX pageY screenX screenY toElement".split(" "),filter:function(bx,bw){var by,bz,e,bv=bw.button,bA=bw.fromElement;if(bx.pageX==null&&bw.clientX!=null){by=bx.target.ownerDocument||av;bz=by.documentElement;e=by.body;bx.pageX=bw.clientX+(bz&&bz.scrollLeft||e&&e.scrollLeft||0)-(bz&&bz.clientLeft||e&&e.clientLeft||0);bx.pageY=bw.clientY+(bz&&bz.scrollTop||e&&e.scrollTop||0)-(bz&&bz.clientTop||e&&e.clientTop||0)}if(!bx.relatedTarget&&bA){bx.relatedTarget=bA===bx.target?bw.toElement:bA}if(!bx.which&&bv!==L){bx.which=(bv&1?1:(bv&2?3:(bv&4?2:0)))}return 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0},disableSelection:function(){return this.bind((a.support.selectstart?"selectstart":"mousedown")+".ui-disableSelection",function(e){e.preventDefault()})},enableSelection:function(){return this.unbind(".ui-disableSelection")}});a.each(["Width","Height"],function(g,e){var f=e==="Width"?["Left","Right"]:["Top","Bottom"],h=e.toLowerCase(),k={innerWidth:a.fn.innerWidth,innerHeight:a.fn.innerHeight,outerWidth:a.fn.outerWidth,outerHeight:a.fn.outerHeight};function j(m,l,i,n){a.each(f,function(){l-=parseFloat(a.curCSS(m,"padding"+this,true))||0;if(i){l-=parseFloat(a.curCSS(m,"border"+this+"Width",true))||0}if(n){l-=parseFloat(a.curCSS(m,"margin"+this,true))||0}});return l}a.fn["inner"+e]=function(i){if(i===d){return k["inner"+e].call(this)}return this.each(function(){a(this).css(h,j(this,i)+"px")})};a.fn["outer"+e]=function(i,l){if(typeof i!=="number"){return k["outer"+e].call(this,i)}return this.each(function(){a(this).css(h,j(this,i,true,l)+"px")})}});function c(g,e){var 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c=b.cleanData;b.cleanData=function(f){for(var g=0,h;(h=f[g])!=null;g++){try{b(h).triggerHandler("remove")}catch(j){}}c(f)}}else{var a=b.fn.remove;b.fn.remove=function(e,f){return this.each(function(){if(!f){if(!e||b.filter(e,[this]).length){b("*",this).add([this]).each(function(){try{b(this).triggerHandler("remove")}catch(g){}})}}return a.call(b(this),e,f)})}}b.widget=function(f,h,e){var g=f.split(".")[0],j;f=f.split(".")[1];j=g+"-"+f;if(!e){e=h;h=b.Widget}b.expr[":"][j]=function(k){return !!b.data(k,f)};b[g]=b[g]||{};b[g][f]=function(k,l){if(arguments.length){this._createWidget(k,l)}};var i=new h();i.options=b.extend(true,{},i.options);b[g][f].prototype=b.extend(true,i,{namespace:g,widgetName:f,widgetEventPrefix:b[g][f].prototype.widgetEventPrefix||f,widgetBaseClass:j},e);b.widget.bridge(f,b[g][f])};b.widget.bridge=function(f,e){b.fn[f]=function(i){var g=typeof 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j,i,h=this.options[e];g=g||{};f=b.Event(f);f.type=(e===this.widgetEventPrefix?e:this.widgetEventPrefix+e).toLowerCase();f.target=this.element[0];i=f.originalEvent;if(i){for(j in i){if(!(j in f)){f[j]=i[j]}}}this.element.trigger(f,g);return !(b.isFunction(h)&&h.call(this.element[0],f,g)===false||f.isDefaultPrevented())}}})(jQuery);/*! + * jQuery UI Mouse 1.8.18 + * + * Copyright 2011, AUTHORS.txt (http://jqueryui.com/about) + * Dual licensed under the MIT or GPL Version 2 licenses. + * http://jquery.org/license + * + * http://docs.jquery.com/UI/Mouse + * + * Depends: + * jquery.ui.widget.js + */ +(function(b,c){var a=false;b(document).mouseup(function(d){a=false});b.widget("ui.mouse",{options:{cancel:":input,option",distance:1,delay:0},_mouseInit:function(){var d=this;this.element.bind("mousedown."+this.widgetName,function(e){return d._mouseDown(e)}).bind("click."+this.widgetName,function(e){if(true===b.data(e.target,d.widgetName+".preventClickEvent")){b.removeData(e.target,d.widgetName+".preventClickEvent");e.stopImmediatePropagation();return false}});this.started=false},_mouseDestroy:function(){this.element.unbind("."+this.widgetName)},_mouseDown:function(f){if(a){return}(this._mouseStarted&&this._mouseUp(f));this._mouseDownEvent=f;var e=this,g=(f.which==1),d=(typeof this.options.cancel=="string"&&f.target.nodeName?b(f.target).closest(this.options.cancel).length:false);if(!g||d||!this._mouseCapture(f)){return true}this.mouseDelayMet=!this.options.delay;if(!this.mouseDelayMet){this._mouseDelayTimer=setTimeout(function(){e.mouseDelayMet=true},this.options.delay)}if(this._mouseDistanceMet(f)&&this._mouseDelayMet(f)){this._mouseStarted=(this._mouseStart(f)!==false);if(!this._mouseStarted){f.preventDefault();return true}}if(true===b.data(f.target,this.widgetName+".preventClickEvent")){b.removeData(f.target,this.widgetName+".preventClickEvent")}this._mouseMoveDelegate=function(h){return e._mouseMove(h)};this._mouseUpDelegate=function(h){return e._mouseUp(h)};b(document).bind("mousemove."+this.widgetName,this._mouseMoveDelegate).bind("mouseup."+this.widgetName,this._mouseUpDelegate);f.preventDefault();a=true;return true},_mouseMove:function(d){if(b.browser.msie&&!(document.documentMode>=9)&&!d.button){return this._mouseUp(d)}if(this._mouseStarted){this._mouseDrag(d);return d.preventDefault()}if(this._mouseDistanceMet(d)&&this._mouseDelayMet(d)){this._mouseStarted=(this._mouseStart(this._mouseDownEvent,d)!==false);(this._mouseStarted?this._mouseDrag(d):this._mouseUp(d))}return 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l=this.handles.split(",");this.handles={};for(var g=0;g<l.length;g++){var j=c.trim(l[g]),e="ui-resizable-"+j;var h=c('<div class="ui-resizable-handle '+e+'"></div>');if(/sw|se|ne|nw/.test(j)){h.css({zIndex:++k.zIndex})}if("se"==j){h.addClass("ui-icon ui-icon-gripsmall-diagonal-se")}this.handles[j]=".ui-resizable-"+j;this.element.append(h)}}this._renderAxis=function(q){q=q||this.element;for(var n in this.handles){if(this.handles[n].constructor==String){this.handles[n]=c(this.handles[n],this.element).show()}if(this.elementIsWrapper&&this.originalElement[0].nodeName.match(/textarea|input|select|button/i)){var o=c(this.handles[n],this.element),p=0;p=/sw|ne|nw|se|n|s/.test(n)?o.outerHeight():o.outerWidth();var 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g="client"+h,f=j.ownerDocument.documentElement,d=j.ownerDocument.body;return Math.max(f[e],d[e])-Math.min(f[g],d[g])};function b(d){return typeof d=="object"?d:{top:d,left:d}}})(jQuery); diff --git a/docs/Core/html/modules.html b/docs/Core/html/modules.html new file mode 100644 index 0000000..d6f059c --- /dev/null +++ b/docs/Core/html/modules.html @@ -0,0 +1,155 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Reference</title> +<title>CMSIS-Core (Cortex-M): Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script 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<div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li class="current"><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('modules.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Reference</div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock">Here is a list of all modules:</div><div class="directory"> +<div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span>]</div><table class="directory"> +<tr id="row_0_" class="even"><td class="entry"><img id="arr_0_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('0_')"/><a class="el" href="group__version__control__gr.html" target="_self">Version Control</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr> +<tr id="row_0_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__version__control__depricated__gr.html" target="_self">Version Control per Core (Depricated)</a></td><td class="desc">Version #define symbols for CMSIS release specific C/C++ source code </td></tr> +<tr id="row_1_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__compiler__conntrol__gr.html" target="_self">Compiler Control</a></td><td class="desc">Compiler agnostic #define symbols for generic C/C++ source code </td></tr> +<tr id="row_2_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Naming conventions and optional features for accessing peripherals </td></tr> +<tr id="row_3_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Functions for system and clock setup available in system_<em>device</em>.c </td></tr> +<tr id="row_4_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__NVIC__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Functions to access the Nested Vector Interrupt Controller (NVIC) </td></tr> +<tr id="row_5_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Core__Register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers </td></tr> +<tr id="row_6_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__CPU__gr.html" target="_self">Intrinsic Functions for CPU Instructions</a></td><td class="desc">Functions that generate specific Cortex-M CPU Instructions </td></tr> +<tr id="row_7_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__intrinsic__SIMD__gr.html" target="_self">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a></td><td class="desc">Access to dedicated SIMD instructions </td></tr> +<tr id="row_8_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__fpu__functions.html" target="_self">FPU Functions</a></td><td class="desc">Functions that relate to the Floating-Point Arithmetic Unit </td></tr> +<tr id="row_9_" class="even"><td class="entry"><img id="arr_9_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('9_')"/><a class="el" href="group__mpu__functions.html" target="_self">MPU Functions for Armv7-M</a></td><td class="desc">Functions that relate to the Memory Protection Unit </td></tr> +<tr id="row_9_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__mpu__defines.html" target="_self">Define values</a></td><td class="desc">Define values for MPU region setup </td></tr> +<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__SysTick__gr.html" target="_self">Systick Timer (SYSTICK)</a></td><td class="desc">Initialize and start the SysTick timer </td></tr> +<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__ITM__Debug__gr.html" target="_self">Debug Access</a></td><td class="desc">Debug Access to the Instrumented Trace Macrocell (ITM) </td></tr> +<tr id="row_12_" class="even"><td class="entry"><img id="arr_12_" src="ftv2mnode.png" alt="o" width="16" height="22" onclick="toggleFolder('12_')"/><a class="el" href="group__trustzone__functions.html" target="_self">TrustZone for Armv8-M</a></td><td class="desc">Functions that related to optional Armv8-M security extension </td></tr> +<tr id="row_12_0_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__coreregister__trustzone__functions.html" target="_self">Core Register Access Functions</a></td><td class="desc">Core register Access functions related to TrustZone for Armv8-M </td></tr> +<tr id="row_12_1_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__nvic__trustzone__functions.html" target="_self">NVIC Functions</a></td><td class="desc">Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M </td></tr> +<tr id="row_12_2_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__systick__trustzone__functions.html" target="_self">SysTick Functions</a></td><td class="desc">SysTick functions related to TrustZone for Armv8-M </td></tr> +<tr id="row_12_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__sau__trustzone__functions.html" target="_self">SAU Functions</a></td><td class="desc">Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M </td></tr> +<tr id="row_12_4_"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__context__trustzone__functions.html" target="_self">RTOS Context Management</a></td><td class="desc">RTOS Thread Context Management for Armv8-M TrustZone </td></tr> +<tr id="row_13_" class="even"><td class="entry"><img id="arr_13_" src="ftv2mlastnode.png" alt="\" width="16" height="22" onclick="toggleFolder('13_')"/><a class="el" href="group__cache__functions__m7.html" target="_self">Cache Functions (only Cortex-M7)</a></td><td class="desc">Functions for Instruction and Data Cache </td></tr> +<tr id="row_13_0_"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__Icache__functions__m7.html" target="_self">I-Cache Functions</a></td><td class="desc">Functions for the instruction cache </td></tr> +<tr id="row_13_1_" class="even"><td class="entry"><img src="ftv2blank.png" alt=" " width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="group__Dcache__functions__m7.html" target="_self">D-Cache Functions</a></td><td class="desc">Functions for the data cache </td></tr> +</table> +</div><!-- directory --> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/modules.js b/docs/Core/html/modules.js new file mode 100644 index 0000000..da3f440 --- /dev/null +++ b/docs/Core/html/modules.js @@ -0,0 +1,17 @@ +var modules = +[ + [ "Version Control", "group__version__control__gr.html", "group__version__control__gr" ], + [ "Compiler Control", "group__compiler__conntrol__gr.html", "group__compiler__conntrol__gr" ], + [ "Peripheral Access", "group__peripheral__gr.html", "group__peripheral__gr" ], + [ "System and Clock Configuration", "group__system__init__gr.html", "group__system__init__gr" ], + [ "Interrupts and Exceptions (NVIC)", "group__NVIC__gr.html", "group__NVIC__gr" ], + [ "Core Register Access", "group__Core__Register__gr.html", "group__Core__Register__gr" ], + [ "Intrinsic Functions for CPU Instructions", "group__intrinsic__CPU__gr.html", "group__intrinsic__CPU__gr" ], + [ "Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]", "group__intrinsic__SIMD__gr.html", "group__intrinsic__SIMD__gr" ], + [ "FPU Functions", "group__fpu__functions.html", "group__fpu__functions" ], + [ "MPU Functions for Armv7-M", "group__mpu__functions.html", "group__mpu__functions" ], + [ "Systick Timer (SYSTICK)", "group__SysTick__gr.html", "group__SysTick__gr" ], + [ "Debug Access", "group__ITM__Debug__gr.html", "group__ITM__Debug__gr" ], + [ "TrustZone for Armv8-M", "group__trustzone__functions.html", "group__trustzone__functions" ], + [ "Cache Functions (only Cortex-M7)", "group__cache__functions__m7.html", "group__cache__functions__m7" ] +];
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getData(varName) +{ + var i = varName.lastIndexOf('/'); + var n = i>=0 ? varName.substring(i+1) : varName; + return eval(n.replace(/\-/g,'_')); +} + +function stripPath(uri) +{ + return uri.substring(uri.lastIndexOf('/')+1); +} + +function stripPath2(uri) +{ + var i = uri.lastIndexOf('/'); + var s = uri.substring(i+1); + var m = uri.substring(0,i+1).match(/\/d\w\/d\w\w\/$/); + return m ? uri.substring(i-6) : s; +} + +function localStorageSupported() +{ + try { + return 'localStorage' in window && window['localStorage'] !== null && window.localStorage.getItem; + } + catch(e) { + return false; + } +} + + +function storeLink(link) +{ + if (!$("#nav-sync").hasClass('sync') && localStorageSupported()) { + window.localStorage.setItem('navpath',link); + } +} + +function deleteLink() +{ + if (localStorageSupported()) { + window.localStorage.setItem('navpath',''); + } +} + +function cachedLink() +{ + if (localStorageSupported()) { + return window.localStorage.getItem('navpath'); + } else { + return ''; + } +} + +function getScript(scriptName,func,show) +{ + var head = document.getElementsByTagName("head")[0]; + var script = document.createElement('script'); + script.id = scriptName; + script.type = 'text/javascript'; + script.onload = func; + script.src = scriptName+'.js'; + if ($.browser.msie && $.browser.version<=8) { + // script.onload does not work with older versions of IE + script.onreadystatechange = function() { + if (script.readyState=='complete' || script.readyState=='loaded') { + func(); if (show) showRoot(); + } + } + } + head.appendChild(script); +} + +function createIndent(o,domNode,node,level) +{ + var level=-1; + var n = node; + while (n.parentNode) { level++; n=n.parentNode; } + if (node.childrenData) { + var imgNode = document.createElement("img"); + imgNode.style.paddingLeft=(16*level).toString()+'px'; + imgNode.width = 16; + imgNode.height = 22; + imgNode.border = 0; + node.plus_img = imgNode; + node.expandToggle = document.createElement("a"); + node.expandToggle.href = "javascript:void(0)"; + node.expandToggle.onclick = function() { + if (node.expanded) { + $(node.getChildrenUL()).slideUp("fast"); + node.plus_img.src = node.relpath+"ftv2pnode.png"; + node.expanded = false; + } else { + expandNode(o, node, false, false); + } + } + node.expandToggle.appendChild(imgNode); + domNode.appendChild(node.expandToggle); + imgNode.src = node.relpath+"ftv2pnode.png"; + } else { + var span = document.createElement("span"); + span.style.display = 'inline-block'; + span.style.width = 16*(level+1)+'px'; + span.style.height = '22px'; + span.innerHTML = ' '; + domNode.appendChild(span); + } +} + +var animationInProgress = false; + +function gotoAnchor(anchor,aname,updateLocation) +{ + var pos, docContent = $('#doc-content'); + if (anchor.parent().attr('class')=='memItemLeft' || + anchor.parent().attr('class')=='fieldtype' || + anchor.parent().is(':header')) + { + pos = anchor.parent().position().top; + } else if (anchor.position()) { + pos = anchor.position().top; + } + if (pos) { + var dist = Math.abs(Math.min( + pos-docContent.offset().top, + docContent[0].scrollHeight- + docContent.height()-docContent.scrollTop())); + animationInProgress=true; + docContent.animate({ + scrollTop: pos + docContent.scrollTop() - docContent.offset().top + },Math.max(50,Math.min(500,dist)),function(){ + if (updateLocation) window.location.href=aname; + animationInProgress=false; + }); + } +} + +function newNode(o, po, text, link, childrenData, lastNode) +{ + var node = new Object(); + node.children = Array(); + node.childrenData = childrenData; + node.depth = po.depth + 1; + node.relpath = po.relpath; + node.isLast = lastNode; + + node.li = document.createElement("li"); + po.getChildrenUL().appendChild(node.li); + node.parentNode = po; + + node.itemDiv = document.createElement("div"); + node.itemDiv.className = "item"; + + node.labelSpan = document.createElement("span"); + node.labelSpan.className = "label"; + + createIndent(o,node.itemDiv,node,0); + node.itemDiv.appendChild(node.labelSpan); + node.li.appendChild(node.itemDiv); + + var a = document.createElement("a"); + node.labelSpan.appendChild(a); + node.label = document.createTextNode(text); + node.expanded = false; + a.appendChild(node.label); + if (link) { + var url; + if (link.substring(0,1)=='^') { + url = link.substring(1); + link = url; + } else { + url = node.relpath+link; + } + a.className = stripPath(link.replace('#',':')); + if (link.indexOf('#')!=-1) { + var aname = '#'+link.split('#')[1]; + var srcPage = stripPath($(location).attr('pathname')); + var targetPage = stripPath(link.split('#')[0]); + a.href = srcPage!=targetPage ? url : "javascript:void(0)"; + a.onclick = function(){ + storeLink(link); + if (!$(a).parent().parent().hasClass('selected')) + { + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + $(a).parent().parent().addClass('selected'); + $(a).parent().parent().attr('id','selected'); + } + var anchor = $(aname); + gotoAnchor(anchor,aname,true); + }; + } else { + a.href = url; + a.onclick = function() { storeLink(link); } + } + } else { + if (childrenData != null) + { + a.className = "nolink"; + a.href = "javascript:void(0)"; + a.onclick = node.expandToggle.onclick; + } + } + + node.childrenUL = null; + node.getChildrenUL = function() { + if (!node.childrenUL) { + node.childrenUL = document.createElement("ul"); + node.childrenUL.className = "children_ul"; + node.childrenUL.style.display = "none"; + node.li.appendChild(node.childrenUL); + } + return node.childrenUL; + }; + + return node; +} + +function showRoot() +{ + var headerHeight = $("#top").height(); + var footerHeight = $("#nav-path").height(); + var windowHeight = $(window).height() - headerHeight - footerHeight; + (function (){ // retry until we can scroll to the selected item + try { + var navtree=$('#nav-tree'); + navtree.scrollTo('#selected',0,{offset:-windowHeight/2}); + } catch (err) { + setTimeout(arguments.callee, 0); + } + })(); +} + +function expandNode(o, node, imm, showRoot) +{ + if (node.childrenData && !node.expanded) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + expandNode(o, node, imm, showRoot); + }, showRoot); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } if (imm || ($.browser.msie && $.browser.version>8)) { + // somehow slideDown jumps to the start of tree for IE9 :-( + $(node.getChildrenUL()).show(); + } else { + $(node.getChildrenUL()).slideDown("fast"); + } + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + } + } +} + +function glowEffect(n,duration) +{ + n.addClass('glow').delay(duration).queue(function(next){ + $(this).removeClass('glow');next(); + }); +} + +function highlightAnchor() +{ + var aname = $(location).attr('hash'); + var anchor = $(aname); + if (anchor.parent().attr('class')=='memItemLeft'){ + var rows = $('.memberdecls tr[class$="'+ + window.location.hash.substring(1)+'"]'); + glowEffect(rows.children(),300); // member without details + } else if (anchor.parents().slice(2).prop('tagName')=='TR') { + glowEffect(anchor.parents('div.memitem'),1000); // enum value + } else if (anchor.parent().attr('class')=='fieldtype'){ + glowEffect(anchor.parent().parent(),1000); // struct field + } else if (anchor.parent().is(":header")) { + glowEffect(anchor.parent(),1000); // section header + } else { + glowEffect(anchor.next(),1000); // normal member + } + gotoAnchor(anchor,aname,false); +} + +function selectAndHighlight(hash,n) +{ + var a; + if (hash) { + var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1); + a=$('.item a[class$="'+link+'"]'); + } + if (a && a.length) { + a.parent().parent().addClass('selected'); + a.parent().parent().attr('id','selected'); + highlightAnchor(); + } else if (n) { + $(n.itemDiv).addClass('selected'); + $(n.itemDiv).attr('id','selected'); + } + if ($('#nav-tree-contents .item:first').hasClass('selected')) { + $('#nav-sync').css('top','30px'); + } else { + $('#nav-sync').css('top','5px'); + } + showRoot(); +} + +function showNode(o, node, index, hash) +{ + if (node && node.childrenData) { + if (typeof(node.childrenData)==='string') { + var varName = node.childrenData; + getScript(node.relpath+varName,function(){ + node.childrenData = getData(varName); + showNode(o,node,index,hash); + },true); + } else { + if (!node.childrenVisited) { + getNode(o, node); + } + $(node.getChildrenUL()).css({'display':'block'}); + if (node.isLast) { + node.plus_img.src = node.relpath+"ftv2mlastnode.png"; + } else { + node.plus_img.src = node.relpath+"ftv2mnode.png"; + } + node.expanded = true; + var n = node.children[o.breadcrumbs[index]]; + if (index+1<o.breadcrumbs.length) { + showNode(o,n,index+1,hash); + } else { + if (typeof(n.childrenData)==='string') { + var varName = n.childrenData; + getScript(n.relpath+varName,function(){ + n.childrenData = getData(varName); + node.expanded=false; + showNode(o,node,index,hash); // retry with child node expanded + },true); + } else { + var rootBase = stripPath(o.toroot.replace(/\..+$/, '')); + if (rootBase=="index" || rootBase=="pages" || rootBase=="search") { + expandNode(o, n, true, true); + } + selectAndHighlight(hash,n); + } + } + } + } else { + selectAndHighlight(hash); + } +} + +function removeToInsertLater(element) { + var parentNode = element.parentNode; + var nextSibling = element.nextSibling; + parentNode.removeChild(element); + return function() { + if (nextSibling) { + parentNode.insertBefore(element, nextSibling); + } else { + parentNode.appendChild(element); + } + }; +} + +function getNode(o, po) +{ + var insertFunction = removeToInsertLater(po.li); + po.childrenVisited = true; + var l = po.childrenData.length-1; + for (var i in po.childrenData) { + var nodeData = po.childrenData[i]; + po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2], + i==l); + } + insertFunction(); +} + +function gotoNode(o,subIndex,root,hash,relpath) +{ + var nti = navTreeSubIndices[subIndex][root+hash]; + o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]); + if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index + navTo(o,NAVTREE[0][1],"",relpath); + $('.item').removeClass('selected'); + $('.item').removeAttr('id'); + } + if (o.breadcrumbs) { + o.breadcrumbs.unshift(0); // add 0 for root node + showNode(o, o.node, 0, hash); + } +} + +function navTo(o,root,hash,relpath) +{ + var link = cachedLink(); + if (link) { + var parts = link.split('#'); + root = parts[0]; + if (parts.length>1) hash = '#'+parts[1]; + else hash=''; + } + if (hash.match(/^#l\d+$/)) { + var anchor=$('a[name='+hash.substring(1)+']'); + glowEffect(anchor.parent(),1000); // line number + hash=''; // strip line number anchors + //root=root.replace(/_source\./,'.'); // source link to doc link + } + var url=root+hash; + var i=-1; + while (NAVTREEINDEX[i+1]<=url) i++; + if (i==-1) { i=0; root=NAVTREE[0][1]; } // fallback: show index + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath) + } else { + getScript(relpath+'navtreeindex'+i,function(){ + navTreeSubIndices[i] = eval('NAVTREEINDEX'+i); + if (navTreeSubIndices[i]) { + gotoNode(o,i,root,hash,relpath); + } + },true); + } +} + +function showSyncOff(n,relpath) +{ + n.html('<img src="'+relpath+'sync_off.png" title="'+SYNCOFFMSG+'"/>'); +} + +function showSyncOn(n,relpath) +{ + n.html('<img src="'+relpath+'sync_on.png" title="'+SYNCONMSG+'"/>'); +} + +function toggleSyncButton(relpath) +{ + var navSync = $('#nav-sync'); + if (navSync.hasClass('sync')) { + navSync.removeClass('sync'); + showSyncOff(navSync,relpath); + storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash')); + } else { + navSync.addClass('sync'); + showSyncOn(navSync,relpath); + deleteLink(); + } +} + +function initNavTree(toroot,relpath) +{ + var o = new Object(); + o.toroot = toroot; + o.node = new Object(); + o.node.li = document.getElementById("nav-tree-contents"); + o.node.childrenData = NAVTREE; + o.node.children = new Array(); + o.node.childrenUL = document.createElement("ul"); + o.node.getChildrenUL = function() { return o.node.childrenUL; }; + o.node.li.appendChild(o.node.childrenUL); + o.node.depth = 0; + o.node.relpath = relpath; + o.node.expanded = false; + o.node.isLast = true; + o.node.plus_img = document.createElement("img"); + o.node.plus_img.src = relpath+"ftv2pnode.png"; + o.node.plus_img.width = 16; + o.node.plus_img.height = 22; + + if (localStorageSupported()) { + var navSync = $('#nav-sync'); + if (cachedLink()) { + showSyncOff(navSync,relpath); + navSync.removeClass('sync'); + } else { + showSyncOn(navSync,relpath); + } + navSync.click(function(){ toggleSyncButton(relpath); }); + } + + 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id="row_3_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="partition_h_pg.html" target="_self">System Partition Header File partition_<device>.h</a></td><td class="desc"></td></tr> +<tr id="row_4_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="coreMISRA_Exceptions_pg.html" target="_self">MISRA-C Deviations</a></td><td class="desc"></td></tr> +<tr id="row_5_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="regMap_pg.html" target="_self">Register Mapping</a></td><td class="desc"></td></tr> +<tr id="row_6_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="deprecated.html" target="_self">Deprecated List</a></td><td class="desc"></td></tr> +</table> +</div><!-- directory --> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/partition_h_pg.html b/docs/Core/html/partition_h_pg.html new file mode 100644 index 0000000..f41a311 --- /dev/null +++ b/docs/Core/html/partition_h_pg.html @@ -0,0 +1,277 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>System Partition Header File partition_<device>.h</title> +<title>CMSIS-Core (Cortex-M): System Partition Header File partition_<device>.h</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('partition_h_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">System Partition Header File partition_<device>.h </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> contains the initial setup of the TrustZone hardware in an Armv8-M system. The function <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a> is call from <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and uses the settings in this file to initialize the Secure Attribute Unit (SAU) and define non-secure interrupts (register NVIC_INIT_ITNS). The following initializations are performed:</p> +<ul> +<li><a class="el" href="partition_h_pg.html#sau_ctrlregister_sec">SAU CTRL register settings</a> provides settings for the SAU CTRL register.</li> +<li><a class="el" href="partition_h_pg.html#sau_regions_sect">Configuration of the SAU Address Regions</a> provides configuration of the SAU Address Regions.</li> +<li><a class="el" href="partition_h_pg.html#sau_sleepexception_sec">Configuration of Sleep and Exception behaviour</a> provides device-specific deepsleep and exception settings.</li> +<li><a class="el" href="partition_h_pg.html#sau_interrupttarget_sec">Configuration of Interrupt Target settings</a> provides device-specific interrupt target settings.</li> +</ul> +<h1><a class="anchor" id="sau_ctrlregister_sec"></a> +SAU CTRL register settings</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>SAU_INIT_CTRL </td><td>0 .. 1 </td><td>0 </td><td>Initialize SAU CTRL register or not<ul> +<li>0: do not initialize SAU CTRL register</li> +<li>1: initialize SAU CTRL register </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_CTRL_ENABLE </td><td>0 .. 1 </td><td>0 </td><td>enable/disable the SAU<ul> +<li>0: disable SAU</li> +<li>1: enable SAU </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_CTRL_ALLNS </td><td>0 .. 1 </td><td>0 </td><td>value for SAU_CTRL register bit ALLNS<ul> +<li>0: all Memory is Secure</li> +<li>1: all Memory is Non-Secure </li> +</ul> +</td></tr> +</table> +<h1><a class="anchor" id="sau_regions_sect"></a> +Configuration of the SAU Address Regions</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>SAU_REGIONS_MAX </td><td>0 .. tbd </td><td>8 </td><td>maximum number of SAU regions </td></tr> +<tr> +<td>SAU_INIT_REGION<number> </td><td>0 .. 1 </td><td>0 </td><td>initialize SAU region or not<ul> +<li>0: do not initialize SAU region</li> +<li>1: initialize SAU region </li> +</ul> +</td></tr> +<tr> +<td>SAU_INIT_START<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/> + [in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr> +<tr> +<td>SAU_INIT_END<number> </td><td>0x00000000 .. 0xFFFFFFE0<br/> + [in steps of 32] </td><td>0x00000000 </td><td>region start address </td></tr> +<tr> +<td>SAU_INIT_NSC<number> </td><td>0 .. 1 </td><td>0 </td><td>SAU region attribute<ul> +<li>0: Non-Secure</li> +<li>1: Secure, Non-Secure callable </li> +</ul> +</td></tr> +</table> +<p>The range of <number> is from 0 .. SAU_REGIONS_MAX. A set of these macros must exist for each <number>.</p> +<p>The following example shows a set of SAU region macros.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define SAU_REGIONS_MAX 8 </span><span class="comment">/* Max. number of SAU regions */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION0 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START0 0x00000000 </span><span class="comment">/* start address of SAU region 0 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END0 0x001FFFE0 </span><span class="comment">/* end address of SAU region 0 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC0 1</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION1 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START1 0x00200000 </span><span class="comment">/* start address of SAU region 1 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END1 0x003FFFE0 </span><span class="comment">/* end address of SAU region 1 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC1 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION2 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START2 0x20200000 </span><span class="comment">/* start address of SAU region 2 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END2 0x203FFFE0 </span><span class="comment">/* end address of SAU region 2 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC2 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION3 1</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START3 0x40000000 </span><span class="comment">/* start address of SAU region 3 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END3 0x40040000 </span><span class="comment">/* end address of SAU region 3 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC3 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION4 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START4 0x00000000 </span><span class="comment">/* start address of SAU region 4 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END4 0x00000000 </span><span class="comment">/* end address of SAU region 4 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC4 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION5 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START5 0x00000000 </span><span class="comment">/* start address of SAU region 5 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END5 0x00000000 </span><span class="comment">/* end address of SAU region 5 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC5 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION6 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START6 0x00000000 </span><span class="comment">/* start address of SAU region 6 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END6 0x00000000 </span><span class="comment">/* end address of SAU region 6 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_NSC6 0</span></div> +<div class="line"><span class="preprocessor"></span> </div> +<div class="line"><span class="preprocessor">#define SAU_INIT_REGION7 0</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_START7 0x00000000 </span><span class="comment">/* start address of SAU region 7 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define SAU_INIT_END7 0x00000000 </span><span class="comment">/* end address of SAU region 7 */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor">#define SAU_INIT_NSC7 0</span></div> +</div><!-- fragment --><h1><a class="anchor" id="sau_sleepexception_sec"></a> +Configuration of Sleep and Exception behaviour</h1> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>CSR_INIT_DEEPSLEEPS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_CSR register bit DEEPSLEEPS<ul> +<li>0: Deep Sleep can be enabled by Secure and Non-Secure state</li> +<li>1: Deep Sleep can be enabled by Secure state only </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_SYSRESETREQS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit SYSRESETREQS<ul> +<li>0: System reset request accessible from Secure and Non-Secure state</li> +<li>1: System reset request accessible from Secure state only </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_PRIS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit PRIS<ul> +<li>0: Priority of Non-Secure exceptions is Not altered</li> +<li>1: Priority of Non-Secure exceptions is Lowered to 0x80-0xFF </li> +</ul> +</td></tr> +<tr> +<td>AIRCR_INIT_BFHFNMINS </td><td>0 .. 1 </td><td>0 </td><td>value for SCB_AIRCR register bit BFHFNMINS<ul> +<li>0: BusFault, HardFault, and NMI target are Secure state</li> +<li>1: BusFault, HardFault, and NMI target are Non-Secure state </li> +</ul> +</td></tr> +</table> +<h1><a class="anchor" id="sau_interrupttarget_sec"></a> +Configuration of Interrupt Target settings</h1> +<p>Each interrupt has a configuration bit that defines the execution in Secure or Non-secure state. The Non-Secure interrupts have a separate vector table. Refer to <a class="el" href="using_TrustZone_pg.html#Model_TrustZone">Programmers Model with TrustZone</a> for more information.</p> +<table class="cmtable"> +<tr> +<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr> +<tr> +<td>NVIC_INIT_ITNS<number> </td><td>0x00000000 .. 0xFFFFFFFF<br/> + [each bit represents an interrupt] </td><td>0x00000000 </td><td>Interrupt vector target<ul> +<li>0: Secure state</li> +<li>1: Non-Secure state </li> +</ul> +</td></tr> +</table> +<p>The range of <number> is 0 .. (<number of external interrupts> + 31) / 32.</p> +<p>The following example shows the configuration for a maximum of 64 external interrupts.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS0 0x0000122B</span></div> +<div class="line"><span class="preprocessor">#define NVIC_INIT_ITNS1 0x0000003A</span></div> +</div><!-- fragment --> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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(strgURL.search(arr[i].folderName) > 0) { // if this is the current folder + document.write(arr[i].currentListItem); // then print and hightlight the tab + } else { + document.write(arr[i].listItem); // else, print the tab + } + } +}; diff --git a/docs/Core/html/regMap_pg.html b/docs/Core/html/regMap_pg.html new file mode 100644 index 0000000..a53a4a6 --- /dev/null +++ b/docs/Core/html/regMap_pg.html @@ -0,0 +1,303 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Register Mapping</title> +<title>CMSIS-Core (Cortex-M): Register Mapping</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script 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+  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + 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href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Register Mapping </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.</p> +<table class="cmtable" summary="Register Mapping"> +<tr> +<th>CMSIS Register Name </th><th>Cortex-M3, Cortex-M4, and Cortex-M7 </th><th>Cortex-M0 and Cortex-M0+ </th><th>Register Name </th></tr> +<tr> +<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access </th></tr> +<tr> +<td>NVIC->ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers </td></tr> +<tr> +<td>NVIC->ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers </td></tr> +<tr> +<td>NVIC->ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers </td></tr> +<tr> +<td>NVIC->ICPR[] </td><td>NVIC_ICPR0..7 </td><td>ICPR </td><td>Interrupt Clear-Pending Registers </td></tr> +<tr> +<td>NVIC->IABR[] </td><td>NVIC_IABR0..7 </td><td>- </td><td>Interrupt Active Bit Register </td></tr> +<tr> +<td>NVIC->IP[] </td><td>NVIC_IPR0..59 </td><td>IPR0..7 </td><td>Interrupt Priority Register </td></tr> +<tr> +<td>NVIC->STIR </td><td>STIR </td><td>- </td><td>Software Triggered Interrupt Register </td></tr> +<tr> +<th colspan="4">System Control Block (SCB) Register Access </th></tr> +<tr> +<td>SCB->CPUID </td><td>CPUID </td><td>CPUID </td><td>CPUID Base Register </td></tr> +<tr> +<td>SCB->ICSR </td><td>ICSR </td><td>ICSR </td><td>Interrupt Control and State Register </td></tr> +<tr> +<td>SCB->VTOR </td><td>VTOR </td><td>- </td><td>Vector Table Offset Register </td></tr> +<tr> +<td>SCB->AIRCR </td><td>AIRCR </td><td>AIRCR </td><td>Application Interrupt and Reset Control Register </td></tr> +<tr> +<td>SCB->SCR </td><td>SCR </td><td>SCR </td><td>System Control Register </td></tr> +<tr> +<td>SCB->CCR </td><td>CCR </td><td>CCR </td><td>Configuration and Control Register </td></tr> +<tr> +<td>SCB->SHP[] </td><td>SHPR1..3 </td><td>SHPR2..3 </td><td>System Handler Priority Registers </td></tr> +<tr> +<td>SCB->SHCSR </td><td>SHCSR </td><td>SHCSR </td><td>System Handler Control and State Register </td></tr> +<tr> +<td>SCB->CFSR </td><td>CFSR </td><td>- </td><td>Configurable Fault Status Registers </td></tr> +<tr> +<td>SCB->HFSR </td><td>HFSR </td><td>- </td><td>HardFault Status Register </td></tr> +<tr> +<td>SCB->DFSR </td><td>DFSR </td><td>- </td><td>Debug Fault Status Register </td></tr> +<tr> +<td>SCB->MMFAR </td><td>MMFAR </td><td>- </td><td>MemManage Fault Address Register </td></tr> +<tr> +<td>SCB->BFAR </td><td>BFAR </td><td>- </td><td>BusFault Address Register </td></tr> +<tr> +<td>SCB->AFSR </td><td>AFSR </td><td>- </td><td>Auxiliary Fault Status Register </td></tr> +<tr> +<td>SCB->PFR[] </td><td>ID_PFR0..1 </td><td>- </td><td>Processor Feature Registers </td></tr> +<tr> +<td>SCB->DFR </td><td>ID_DFR0 </td><td>- </td><td>Debug Feature Register </td></tr> +<tr> +<td>SCB->ADR </td><td>ID_AFR0 </td><td>- </td><td>Auxiliary Feature Register </td></tr> +<tr> +<td>SCB->MMFR[] </td><td>ID_MMFR0..3 </td><td>- </td><td>Memory Model Feature Registers </td></tr> +<tr> +<td>SCB->ISAR[] </td><td>ID_ISAR0..4 </td><td>- </td><td>Instruction Set Attributes Registers </td></tr> +<tr> +<td>SCB->CPACR </td><td>CPACR </td><td>- </td><td>Coprocessor Access Control Register </td></tr> +<tr> +<th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access </th></tr> +<tr> +<td>SCnSCB->ICTR </td><td>ICTR </td><td>- </td><td>Interrupt Controller Type Register </td></tr> +<tr> +<td>SCnSCB->ACTLR </td><td>ACTLR </td><td>- </td><td>Auxiliary Control Register </td></tr> +<tr> +<th colspan="4">System Timer (SysTick) Control and Status Register Access </th></tr> +<tr> +<td>SysTick->CTRL </td><td>STCSR </td><td>SYST_CSR </td><td>SysTick Control and Status Register </td></tr> +<tr> +<td>SysTick->LOAD </td><td>STRVR </td><td>SYST_RVR </td><td>SysTick Reload Value Register </td></tr> +<tr> +<td>SysTick->VAL </td><td>STCVR </td><td>SYST_CVR </td><td>SysTick Current Value Register </td></tr> +<tr> +<td>SysTick->CALIB </td><td>STCR </td><td>SYST_CALIB </td><td>SysTick Calibaration Value Register </td></tr> +<tr> +<th colspan="4">Data Watchpoint and Trace (DWT) Register Access </th></tr> +<tr> +<td>DWT->CTRL </td><td>DWT_CTRL </td><td>- </td><td>Control Register </td></tr> +<tr> +<td>DWT->CYCCNT </td><td>DWT_CYCCNT </td><td>- </td><td>Cycle Count Register </td></tr> +<tr> +<td>DWT->CPICNT </td><td>DWT_CPICNT </td><td>- </td><td>CPI Count Register </td></tr> +<tr> +<td>DWT->EXCCNT </td><td>DWT_EXCCNT </td><td>- </td><td>Exception Overhead Count Register </td></tr> +<tr> +<td>DWT->SLEEPCNT </td><td>DWT_SLEEPCNT </td><td>- </td><td>Sleep Count Register </td></tr> +<tr> +<td>DWT->LSUCNT </td><td>DWT_LSUCNT </td><td>- </td><td>LSU Count Register </td></tr> +<tr> +<td>DWT->FOLDCNT </td><td>DWT_FOLDCNT </td><td>- </td><td>Folded-instruction Count Register </td></tr> +<tr> +<td>DWT->PCSR </td><td>DWT_PCSR </td><td>- </td><td>Program Counter Sample Register </td></tr> +<tr> +<td>DWT->COMP0..3 </td><td>DWT_COMP0..3 </td><td>- </td><td>Comparator Register 0..3 </td></tr> +<tr> +<td>DWT->MASK0..3 </td><td>DWT_MASK0..3 </td><td>- </td><td>Mask Register 0..3 </td></tr> +<tr> +<td>DWT->FUNCTION0..3 </td><td>DWT_FUNCTION0..3 </td><td>- </td><td>Function Register 0..3 </td></tr> +<tr> +<th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access </th></tr> +<tr> +<td>ITM->PORT[] </td><td>ITM_STIM0..31 </td><td>- </td><td>Stimulus Port Registers </td></tr> +<tr> +<td>ITM->TER </td><td>ITM_TER </td><td>- </td><td>Trace Enable Register </td></tr> +<tr> +<td>ITM->TPR </td><td>ITM_TPR </td><td>- </td><td>ITM Trace Privilege Register </td></tr> +<tr> +<td>ITM->TCR </td><td>ITM_TCR </td><td>- </td><td>Trace Control Register </td></tr> +<tr> +<th colspan="4">Trace Port Interface (TPIU) Register Access </th></tr> +<tr> +<td>TPI->SSPSR </td><td>TPIU_SSPR </td><td>- </td><td>Supported Parallel Port Size Register </td></tr> +<tr> +<td>TPI->CSPSR </td><td>TPIU_CSPSR </td><td>- </td><td>Current Parallel Port Size Register </td></tr> +<tr> +<td>TPI->ACPR </td><td>TPIU_ACPR </td><td>- </td><td>Asynchronous Clock Prescaler Register </td></tr> +<tr> +<td>TPI->SPPR </td><td>TPIU_SPPR </td><td>- </td><td>Selected Pin Protocol Register </td></tr> +<tr> +<td>TPI->FFSR </td><td>TPIU_FFSR </td><td>- </td><td>Formatter and Flush Status Register </td></tr> +<tr> +<td>TPI->FFCR </td><td>TPIU_FFCR </td><td>- </td><td>Formatter and Flush Control Register </td></tr> +<tr> +<td>TPI->FSCR </td><td>TPIU_FSCR </td><td>- </td><td>Formatter Synchronization Counter Register </td></tr> +<tr> +<td>TPI->TRIGGER </td><td>TRIGGER </td><td>- </td><td>TRIGGER </td></tr> +<tr> +<td>TPI->FIFO0 </td><td>FIFO data 0 </td><td>- </td><td>Integration ETM Data </td></tr> +<tr> +<td>TPI->ITATBCTR2 </td><td>ITATBCTR2 </td><td>- </td><td>ITATBCTR2 </td></tr> +<tr> +<td>TPI->ITATBCTR0 </td><td>ITATBCTR0 </td><td>- </td><td>ITATBCTR0 </td></tr> +<tr> +<td>TPI->FIFO1 </td><td>FIFO data 1 </td><td>- </td><td>Integration ITM Data </td></tr> +<tr> +<td>TPI->ITCTRL </td><td>TPIU_ITCTRL </td><td>- </td><td>Integration Mode Control </td></tr> +<tr> +<td>TPI->CLAIMSET </td><td>CLAIMSET </td><td>- </td><td>Claim tag set </td></tr> +<tr> +<td>TPI->CLAIMCLR </td><td>CLAIMCLR </td><td>- </td><td>Claim tag clear </td></tr> +<tr> +<td>TPI->DEVID </td><td>TPIU_DEVID </td><td>- </td><td>TPIU_DEVID </td></tr> +<tr> +<td>TPI->DEVTYPE </td><td>TPIU_DEVTYPE </td><td>- </td><td>TPIU_DEVTYPE </td></tr> +<tr> +<th colspan="4">Memory Protection Unit (MPU) Register Access </th></tr> +<tr> +<td>MPU->TYPE </td><td>MPU_TYPE </td><td>- </td><td>MPU Type Register </td></tr> +<tr> +<td>MPU->CTRL </td><td>MPU_CTRL </td><td>- </td><td>MPU Control Register </td></tr> +<tr> +<td>MPU->RNR </td><td>MPU_RNR </td><td>- </td><td>MPU Region Number Register </td></tr> +<tr> +<td>MPU->RBAR </td><td>MPU_RBAR </td><td>- </td><td>MPU Region Base Address Register </td></tr> +<tr> +<td>MPU->RASR </td><td>MPU_RASR </td><td>- </td><td>MPU Region Attribute and Size Register </td></tr> +<tr> +<td>MPU->RBAR_A1..3 </td><td>MPU_RBAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr> +<tr> +<td>MPU->RSAR_A1..3 </td><td>MPU_RSAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr> +<tr> +<th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU] </th></tr> +<tr> +<td>FPU->FPCCR </td><td>FPCCR </td><td>- </td><td>FP Context Control Register </td></tr> +<tr> +<td>FPU->FPCAR </td><td>FPCAR </td><td>- </td><td>FP Context Address Register </td></tr> +<tr> +<td>FPU->FPDSCR </td><td>FPDSCR </td><td>- </td><td>FP Default Status Control Register </td></tr> +<tr> +<td>FPU->MVFR0..1 </td><td>MVFR0..1 </td><td>- </td><td>Media and VFP Feature Registers </td></tr> +</table> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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content="text/xhtml;charset=UTF-8"/> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="NoMatches">No Matches</div> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_0.html b/docs/Core/html/search/pages_0.html new file mode 100644 index 0000000..c51c834 --- /dev/null +++ b/docs/Core/html/search/pages_0.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_0.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_0.js b/docs/Core/html/search/pages_0.js new file mode 100644 index 0000000..2ad9451 --- /dev/null +++ b/docs/Core/html/search/pages_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['basic_20cmsis_20example',['Basic CMSIS Example',['../using_CMSIS.html',1,'using_pg']]] +]; diff --git a/docs/Core/html/search/pages_1.html b/docs/Core/html/search/pages_1.html new file mode 100644 index 0000000..2a98fce --- /dev/null +++ b/docs/Core/html/search/pages_1.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_1.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_1.js b/docs/Core/html/search/pages_1.js new file mode 100644 index 0000000..18a701d --- /dev/null +++ b/docs/Core/html/search/pages_1.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['cmsis_2dcore_20device_20templates',['CMSIS-Core Device Templates',['../templates_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_2.html b/docs/Core/html/search/pages_2.html new file mode 100644 index 0000000..0711a0b --- /dev/null +++ b/docs/Core/html/search/pages_2.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_2.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_2.js b/docs/Core/html/search/pages_2.js new file mode 100644 index 0000000..339548f --- /dev/null +++ b/docs/Core/html/search/pages_2.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['deprecated_20list',['Deprecated List',['../deprecated.html',1,'']]], + ['device_20header_20file_20_3cdevice_2eh_3e',['Device Header File <device.h>',['../device_h_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core/html/search/pages_3.html b/docs/Core/html/search/pages_3.html new file mode 100644 index 0000000..4310311 --- /dev/null +++ b/docs/Core/html/search/pages_3.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_3.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_3.js b/docs/Core/html/search/pages_3.js new file mode 100644 index 0000000..b1e934d --- /dev/null +++ b/docs/Core/html/search/pages_3.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['misra_2dc_20deviations',['MISRA-C Deviations',['../coreMISRA_Exceptions_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_4.html b/docs/Core/html/search/pages_4.html new file mode 100644 index 0000000..ae5ce18 --- /dev/null +++ b/docs/Core/html/search/pages_4.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_4.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_4.js b/docs/Core/html/search/pages_4.js new file mode 100644 index 0000000..277cca0 --- /dev/null +++ b/docs/Core/html/search/pages_4.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['overview',['Overview',['../index.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_5.html b/docs/Core/html/search/pages_5.html new file mode 100644 index 0000000..02c1114 --- /dev/null +++ b/docs/Core/html/search/pages_5.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_5.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_5.js b/docs/Core/html/search/pages_5.js new file mode 100644 index 0000000..8247a57 --- /dev/null +++ b/docs/Core/html/search/pages_5.js @@ -0,0 +1,5 @@ +var searchData= +[ + ['revision_20history_20of_20cmsis_2dcore_20_28cortex_2dm_29',['Revision History of CMSIS-Core (Cortex-M)',['../core_revisionHistory.html',1,'']]], + ['register_20mapping',['Register Mapping',['../regMap_pg.html',1,'']]] +]; diff --git a/docs/Core/html/search/pages_6.html b/docs/Core/html/search/pages_6.html new file mode 100644 index 0000000..afb70af --- /dev/null +++ b/docs/Core/html/search/pages_6.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_6.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_6.js b/docs/Core/html/search/pages_6.js new file mode 100644 index 0000000..80ddf96 --- /dev/null +++ b/docs/Core/html/search/pages_6.js @@ -0,0 +1,6 @@ +var searchData= +[ + ['system_20partition_20header_20file_20partition_5f_3cdevice_3e_2eh',['System Partition Header File partition_<device>.h',['../partition_h_pg.html',1,'templates_pg']]], + ['startup_20file_20startup_5f_3cdevice_3e_2es',['Startup File startup_<device>.s',['../startup_s_pg.html',1,'templates_pg']]], + ['system_20configuration_20files_20system_5f_3cdevice_3e_2ec_20and_20system_5f_3cdevice_3e_2eh',['System Configuration Files system_<device>.c and system_<device>.h',['../system_c_pg.html',1,'templates_pg']]] +]; diff --git a/docs/Core/html/search/pages_7.html b/docs/Core/html/search/pages_7.html new file mode 100644 index 0000000..9d7ba25 --- /dev/null +++ b/docs/Core/html/search/pages_7.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="pages_7.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/pages_7.js b/docs/Core/html/search/pages_7.js new file mode 100644 index 0000000..7812e12 --- /dev/null +++ b/docs/Core/html/search/pages_7.js @@ -0,0 +1,7 @@ +var searchData= +[ + ['using_20cmsis_20with_20generic_20arm_20processors',['Using CMSIS with generic Arm Processors',['../using_ARM_pg.html',1,'using_pg']]], + ['using_20cmsis_20in_20embedded_20applications',['Using CMSIS in Embedded Applications',['../using_pg.html',1,'']]], + ['using_20trustzone_20for_20armv8_2dm',['Using TrustZone for Armv8-M',['../using_TrustZone_pg.html',1,'']]], + ['using_20interrupt_20vector_20remap',['Using Interrupt Vector Remap',['../using_VTOR_pg.html',1,'using_pg']]] +]; diff --git a/docs/Core/html/search/search.css b/docs/Core/html/search/search.css new file mode 100644 index 0000000..1746d13 --- /dev/null +++ b/docs/Core/html/search/search.css @@ -0,0 +1,240 @@ +/*---------------- Search Box */ + +#FSearchBox { + float: left; +} + +#searchli { + float: right; + display: block; + width: 170px; + height: 24px; +} + +#MSearchBox { + white-space : nowrap; + position: absolute; + float: none; + display: inline; + margin-top: 3px; + right: 0px; + width: 170px; + z-index: 102; +} + +#MSearchBox .left +{ + display:block; + position:absolute; + left:10px; + width:20px; + height:19px; + background:url('search_l.png') no-repeat; + background-position:right; +} + +#MSearchSelect { + display:block; + position:absolute; + width:20px; + height:19px; +} + +.left #MSearchSelect { + left:4px; +} + +.right #MSearchSelect { + right:5px; +} + +#MSearchField { + display:block; + position:absolute; + height:19px; + background:url('search_m.png') repeat-x; + border:none; + width:116px; + margin-left:20px; + padding-left:4px; + color: #909090; + outline: none; + font: 9pt Arial, Verdana, sans-serif; +} + +#FSearchBox #MSearchField { + margin-left:15px; +} + +#MSearchBox .right { + display:block; + position:absolute; + right:10px; + top:0px; + width:20px; + height:19px; + background:url('search_r.png') no-repeat; + background-position:left; +} + +#MSearchClose { + display: none; + position: absolute; + top: 4px; + background : none; + border: none; + margin: 0px 4px 0px 0px; + padding: 0px 0px; + outline: none; +} + +.left #MSearchClose { + left: 6px; +} + +.right #MSearchClose { + right: 2px; +} + +.MSearchBoxActive #MSearchField { + color: #000000; +} + +/*---------------- Search filter selection */ + +#MSearchSelectWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #90A5CE; + background-color: #F9FAFC; + z-index: 1; + padding-top: 4px; + padding-bottom: 4px; + -moz-border-radius: 4px; + -webkit-border-top-left-radius: 4px; + -webkit-border-top-right-radius: 4px; + -webkit-border-bottom-left-radius: 4px; + -webkit-border-bottom-right-radius: 4px; + -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15); +} + +.SelectItem { + font: 8pt Arial, Verdana, sans-serif; + padding-left: 2px; + padding-right: 12px; + border: 0px; +} + +span.SelectionMark { + margin-right: 4px; + font-family: monospace; + outline-style: none; + text-decoration: none; +} + +a.SelectItem { + display: block; + outline-style: none; + color: #000000; + text-decoration: none; + padding-left: 6px; + padding-right: 12px; +} + +a.SelectItem:focus, +a.SelectItem:active { + color: #000000; + outline-style: none; + text-decoration: none; +} + +a.SelectItem:hover { + color: #FFFFFF; + background-color: #3D578C; + outline-style: none; + text-decoration: none; + cursor: pointer; + display: block; +} + +/*---------------- Search results window */ + +iframe#MSearchResults { + width: 60ex; + height: 15em; +} + +#MSearchResultsWindow { + display: none; + position: absolute; + left: 0; top: 0; + border: 1px solid #000; + background-color: #EEF1F7; +} + +/* ----------------------------------- */ + + +#SRIndex { + clear:both; + padding-bottom: 15px; +} + +.SREntry { + font-size: 10pt; + padding-left: 1ex; +} + +.SRPage .SREntry { + font-size: 8pt; + padding: 1px 5px; +} + +body.SRPage { + margin: 5px 2px; +} + +.SRChildren { + padding-left: 3ex; padding-bottom: .5em +} + +.SRPage .SRChildren { + display: none; +} + +.SRSymbol { + font-weight: bold; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRScope { + display: block; + color: #425E97; + font-family: Arial, Verdana, sans-serif; + text-decoration: none; + outline: none; +} + +a.SRSymbol:focus, a.SRSymbol:active, +a.SRScope:focus, a.SRScope:active { + text-decoration: underline; +} + +.SRPage .SRStatus { + padding: 2px 5px; + font-size: 8pt; + font-style: italic; +} + +.SRResult { + display: none; +} + +DIV.searchresults { + margin-left: 10px; + margin-right: 10px; +} diff --git a/docs/Core/html/search/search.js b/docs/Core/html/search/search.js new file mode 100644 index 0000000..54b1a2a --- /dev/null +++ b/docs/Core/html/search/search.js @@ -0,0 +1,809 @@ +// Search script generated by doxygen +// Copyright (C) 2009 by Dimitri van Heesch. + +// The code in this file is loosly based on main.js, part of Natural Docs, +// which is Copyright (C) 2003-2008 Greg Valure +// Natural Docs is licensed under the GPL. + +var indexSectionsWithContent = +{ + 0: "_abcdefhilmnopqrstuvwxz", + 1: "acdfimnstx", + 2: "cmortu", + 3: "_ainst", + 4: "_abcdefhilmnpqrstuvwz", + 5: "i", + 6: "bdhmnpsuw", + 7: "cdfimnprstv", + 8: "bcdmorsu" +}; + +var indexSectionNames = +{ + 0: "all", + 1: "classes", + 2: "files", + 3: "functions", + 4: "variables", + 5: "enums", + 6: "enumvalues", + 7: "groups", + 8: "pages" +}; + +function convertToId(search) +{ + var result = ''; + for (i=0;i<search.length;i++) + { + var c = search.charAt(i); + var cn = c.charCodeAt(0); + if (c.match(/[a-z0-9\u0080-\uFFFF]/)) + { + result+=c; + } + else if (cn<16) + { + result+="_0"+cn.toString(16); + } + else + { + result+="_"+cn.toString(16); + } + } + return result; +} + +function getXPos(item) +{ + var x = 0; + if (item.offsetWidth) + { + while (item && item!=document.body) + { + x += item.offsetLeft; + item = item.offsetParent; + } + } + return x; +} + +function getYPos(item) +{ + var y = 0; + if (item.offsetWidth) + { + while (item && item!=document.body) + { + y += item.offsetTop; + item = item.offsetParent; + } + } + return y; +} + +/* A class handling everything associated with the search panel. + + Parameters: + name - The name of the global variable that will be + storing this instance. Is needed to be able to set timeouts. + resultPath - path to use for external files +*/ +function SearchBox(name, resultsPath, inFrame, label) +{ + if (!name || !resultsPath) { alert("Missing parameters to SearchBox."); } + + // ---------- Instance variables + this.name = name; + this.resultsPath = resultsPath; + this.keyTimeout = 0; + this.keyTimeoutLength = 500; + this.closeSelectionTimeout = 300; + this.lastSearchValue = ""; + this.lastResultsPage = ""; + this.hideTimeout = 0; + this.searchIndex = 0; + this.searchActive = false; + this.insideFrame = inFrame; + this.searchLabel = label; + + // ----------- DOM Elements + + this.DOMSearchField = function() + { return document.getElementById("MSearchField"); } + + this.DOMSearchSelect = function() + { return document.getElementById("MSearchSelect"); } + + this.DOMSearchSelectWindow = function() + { return document.getElementById("MSearchSelectWindow"); } + + this.DOMPopupSearchResults = function() + { return document.getElementById("MSearchResults"); } + + this.DOMPopupSearchResultsWindow = function() + { return document.getElementById("MSearchResultsWindow"); } + + this.DOMSearchClose = function() + { return document.getElementById("MSearchClose"); } + + this.DOMSearchBox = function() + { return document.getElementById("MSearchBox"); } + + // ------------ Event Handlers + + // Called when focus is added or removed from the search field. + this.OnSearchFieldFocus = function(isActive) + { + this.Activate(isActive); + } + + this.OnSearchSelectShow = function() + { + var searchSelectWindow = this.DOMSearchSelectWindow(); + var searchField = this.DOMSearchSelect(); + + if (this.insideFrame) + { + var left = getXPos(searchField); + var top = getYPos(searchField); + left += searchField.offsetWidth + 6; + top += searchField.offsetHeight; + + // show search selection popup + searchSelectWindow.style.display='block'; + left -= searchSelectWindow.offsetWidth; + searchSelectWindow.style.left = left + 'px'; + searchSelectWindow.style.top = top + 'px'; + } + else + { + var left = getXPos(searchField); + var top = getYPos(searchField); + top += searchField.offsetHeight; + + // show search selection popup + searchSelectWindow.style.display='block'; + searchSelectWindow.style.left = left + 'px'; + searchSelectWindow.style.top = top + 'px'; + } + + // stop selection hide timer + if (this.hideTimeout) + { + clearTimeout(this.hideTimeout); + this.hideTimeout=0; + } + return false; // to avoid "image drag" default event + } + + this.OnSearchSelectHide = function() + { + this.hideTimeout = setTimeout(this.name +".CloseSelectionWindow()", + this.closeSelectionTimeout); + } + + // Called when the content of the search field is changed. + this.OnSearchFieldChange = function(evt) + { + if (this.keyTimeout) // kill running timer + { + clearTimeout(this.keyTimeout); + this.keyTimeout = 0; + } + + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 || e.keyCode==13) + { + if (e.shiftKey==1) + { + this.OnSearchSelectShow(); + var win=this.DOMSearchSelectWindow(); + for (i=0;i<win.childNodes.length;i++) + { + var child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') + { + child.focus(); + return; + } + } + return; + } + else if (window.frames.MSearchResults.searchResults) + { + var elem = window.frames.MSearchResults.searchResults.NavNext(0); + if (elem) elem.focus(); + } + } + else if (e.keyCode==27) // Escape out of the search field + { + this.DOMSearchField().blur(); + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.lastSearchValue = ''; + this.Activate(false); + return; + } + + // strip whitespaces + var searchValue = this.DOMSearchField().value.replace(/ +/g, ""); + + if (searchValue != this.lastSearchValue) // search value has changed + { + if (searchValue != "") // non-empty search + { + // set timer for search update + this.keyTimeout = setTimeout(this.name + '.Search()', + this.keyTimeoutLength); + } + else // empty search field + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.lastSearchValue = ''; + } + } + } + + this.SelectItemCount = function(id) + { + var count=0; + var win=this.DOMSearchSelectWindow(); + for (i=0;i<win.childNodes.length;i++) + { + var child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') + { + count++; + } + } + return count; + } + + this.SelectItemSet = function(id) + { + var i,j=0; + var win=this.DOMSearchSelectWindow(); + for (i=0;i<win.childNodes.length;i++) + { + var child = win.childNodes[i]; // get span within a + if (child.className=='SelectItem') + { + var node = child.firstChild; + if (j==id) + { + node.innerHTML='•'; + } + else + { + node.innerHTML=' '; + } + j++; + } + } + } + + // Called when an search filter selection is made. + // set item with index id as the active item + this.OnSelectItem = function(id) + { + this.searchIndex = id; + this.SelectItemSet(id); + var searchValue = this.DOMSearchField().value.replace(/ +/g, ""); + if (searchValue!="" && this.searchActive) // something was found -> do a search + { + this.Search(); + } + } + + this.OnSearchSelectKey = function(evt) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==40 && this.searchIndex<this.SelectItemCount()) // Down + { + this.searchIndex++; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==38 && this.searchIndex>0) // Up + { + this.searchIndex--; + this.OnSelectItem(this.searchIndex); + } + else if (e.keyCode==13 || e.keyCode==27) + { + this.OnSelectItem(this.searchIndex); + this.CloseSelectionWindow(); + this.DOMSearchField().focus(); + } + return false; + } + + // --------- Actions + + // Closes the results window. + this.CloseResultsWindow = function() + { + this.DOMPopupSearchResultsWindow().style.display = 'none'; + this.DOMSearchClose().style.display = 'none'; + this.Activate(false); + } + + this.CloseSelectionWindow = function() + { + this.DOMSearchSelectWindow().style.display = 'none'; + } + + // Performs a search. + this.Search = function() + { + this.keyTimeout = 0; + + // strip leading whitespace + var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); + + var code = searchValue.toLowerCase().charCodeAt(0); + var idxChar = searchValue.substr(0, 1).toLowerCase(); + if ( 0xD800 <= code && code <= 0xDBFF && searchValue > 1) // surrogate pair + { + idxChar = searchValue.substr(0, 2); + } + + var resultsPage; + var resultsPageWithSearch; + var hasResultsPage; + + var idx = indexSectionsWithContent[this.searchIndex].indexOf(idxChar); + if (idx!=-1) + { + var hexCode=idx.toString(16); + resultsPage = this.resultsPath + '/' + indexSectionNames[this.searchIndex] + '_' + hexCode + '.html'; + resultsPageWithSearch = resultsPage+'?'+escape(searchValue); + hasResultsPage = true; + } + else // nothing available for this search term + { + resultsPage = this.resultsPath + '/nomatches.html'; + resultsPageWithSearch = resultsPage; + hasResultsPage = false; + } + + window.frames.MSearchResults.location = resultsPageWithSearch; + var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); + + if (domPopupSearchResultsWindow.style.display!='block') + { + var domSearchBox = this.DOMSearchBox(); + this.DOMSearchClose().style.display = 'inline'; + if (this.insideFrame) + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + domPopupSearchResultsWindow.style.position = 'relative'; + domPopupSearchResultsWindow.style.display = 'block'; + var width = document.body.clientWidth - 8; // the -8 is for IE :-( + domPopupSearchResultsWindow.style.width = width + 'px'; + domPopupSearchResults.style.width = width + 'px'; + } + else + { + var domPopupSearchResults = this.DOMPopupSearchResults(); + var left = getXPos(domSearchBox) + 150; // domSearchBox.offsetWidth; + var top = getYPos(domSearchBox) + 20; // domSearchBox.offsetHeight + 1; + domPopupSearchResultsWindow.style.display = 'block'; + left -= domPopupSearchResults.offsetWidth; + domPopupSearchResultsWindow.style.top = top + 'px'; + domPopupSearchResultsWindow.style.left = left + 'px'; + } + } + + this.lastSearchValue = searchValue; + this.lastResultsPage = resultsPage; + } + + // -------- Activation Functions + + // Activates or deactivates the search panel, resetting things to + // their default values if necessary. + this.Activate = function(isActive) + { + if (isActive || // open it + this.DOMPopupSearchResultsWindow().style.display == 'block' + ) + { + this.DOMSearchBox().className = 'MSearchBoxActive'; + + var searchField = this.DOMSearchField(); + + if (searchField.value == this.searchLabel) // clear "Search" term upon entry + { + searchField.value = ''; + this.searchActive = true; + } + } + else if (!isActive) // directly remove the panel + { + this.DOMSearchBox().className = 'MSearchBoxInactive'; + this.DOMSearchField().value = this.searchLabel; + this.searchActive = false; + this.lastSearchValue = '' + this.lastResultsPage = ''; + } + } +} + +// ----------------------------------------------------------------------- + +// The class that handles everything on the search results page. +function SearchResults(name) +{ + // The number of matches from the last run of <Search()>. + this.lastMatchCount = 0; + this.lastKey = 0; + this.repeatOn = false; + + // Toggles the visibility of the passed element ID. + this.FindChildElement = function(id) + { + var parentElement = document.getElementById(id); + var element = parentElement.firstChild; + + while (element && element!=parentElement) + { + if (element.nodeName == 'DIV' && element.className == 'SRChildren') + { + return element; + } + + if (element.nodeName == 'DIV' && element.hasChildNodes()) + { + element = element.firstChild; + } + else if (element.nextSibling) + { + element = element.nextSibling; + } + else + { + do + { + element = element.parentNode; + } + while (element && element!=parentElement && !element.nextSibling); + + if (element && element!=parentElement) + { + element = element.nextSibling; + } + } + } + } + + this.Toggle = function(id) + { + var element = this.FindChildElement(id); + if (element) + { + if (element.style.display == 'block') + { + element.style.display = 'none'; + } + else + { + element.style.display = 'block'; + } + } + } + + // Searches for the passed string. If there is no parameter, + // it takes it from the URL query. + // + // Always returns true, since other documents may try to call it + // and that may or may not be possible. + this.Search = function(search) + { + if (!search) // get search word from URL + { + search = window.location.search; + search = search.substring(1); // Remove the leading '?' + search = unescape(search); + } + + search = search.replace(/^ +/, ""); // strip leading spaces + search = search.replace(/ +$/, ""); // strip trailing spaces + search = search.toLowerCase(); + search = convertToId(search); + + var resultRows = document.getElementsByTagName("div"); + var matches = 0; + + var i = 0; + while (i < resultRows.length) + { + var row = resultRows.item(i); + if (row.className == "SRResult") + { + var rowMatchName = row.id.toLowerCase(); + rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); // strip 'sr123_' + + if (search.length<=rowMatchName.length && + rowMatchName.substr(0, search.length)==search) + { + row.style.display = 'block'; + matches++; + } + else + { + row.style.display = 'none'; + } + } + i++; + } + document.getElementById("Searching").style.display='none'; + if (matches == 0) // no results + { + document.getElementById("NoMatches").style.display='block'; + } + else // at least one result + { + document.getElementById("NoMatches").style.display='none'; + } + this.lastMatchCount = matches; + return true; + } + + // return the first item with index index or higher that is visible + this.NavNext = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index++; + } + return focusItem; + } + + this.NavPrev = function(index) + { + var focusItem; + while (1) + { + var focusName = 'Item'+index; + focusItem = document.getElementById(focusName); + if (focusItem && focusItem.parentNode.parentNode.style.display=='block') + { + break; + } + else if (!focusItem) // last element + { + break; + } + focusItem=null; + index--; + } + return focusItem; + } + + this.ProcessKeys = function(e) + { + if (e.type == "keydown") + { + this.repeatOn = false; + this.lastKey = e.keyCode; + } + else if (e.type == "keypress") + { + if (!this.repeatOn) + { + if (this.lastKey) this.repeatOn = true; + return false; // ignore first keypress after keydown + } + } + else if (e.type == "keyup") + { + this.lastKey = 0; + this.repeatOn = false; + } + return this.lastKey!=0; + } + + this.Nav = function(evt,itemIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + var newIndex = itemIndex-1; + var focusItem = this.NavPrev(newIndex); + if (focusItem) + { + var child = this.FindChildElement(focusItem.parentNode.parentNode.id); + if (child && child.style.display == 'block') // children visible + { + var n=0; + var tmpElem; + while (1) // search for last child + { + tmpElem = document.getElementById('Item'+newIndex+'_c'+n); + if (tmpElem) + { + focusItem = tmpElem; + } + else // found it! + { + break; + } + n++; + } + } + } + if (focusItem) + { + focusItem.focus(); + } + else // return focus to search field + { + parent.document.getElementById("MSearchField").focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = itemIndex+1; + var focusItem; + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem && elem.style.display == 'block') // children visible + { + focusItem = document.getElementById('Item'+itemIndex+'_c0'); + } + if (!focusItem) focusItem = this.NavNext(newIndex); + if (focusItem) focusItem.focus(); + } + else if (this.lastKey==39) // Right + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'block'; + } + else if (this.lastKey==37) // Left + { + var item = document.getElementById('Item'+itemIndex); + var elem = this.FindChildElement(item.parentNode.parentNode.id); + if (elem) elem.style.display = 'none'; + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } + + this.NavChild = function(evt,itemIndex,childIndex) + { + var e = (evt) ? evt : window.event; // for IE + if (e.keyCode==13) return true; + if (!this.ProcessKeys(e)) return false; + + if (this.lastKey==38) // Up + { + if (childIndex>0) + { + var newIndex = childIndex-1; + document.getElementById('Item'+itemIndex+'_c'+newIndex).focus(); + } + else // already at first child, jump to parent + { + document.getElementById('Item'+itemIndex).focus(); + } + } + else if (this.lastKey==40) // Down + { + var newIndex = childIndex+1; + var elem = document.getElementById('Item'+itemIndex+'_c'+newIndex); + if (!elem) // last child, jump to parent next parent + { + elem = this.NavNext(itemIndex+1); + } + if (elem) + { + elem.focus(); + } + } + else if (this.lastKey==27) // Escape + { + parent.searchBox.CloseResultsWindow(); + parent.document.getElementById("MSearchField").focus(); + } + else if (this.lastKey==13) // Enter + { + return true; + } + return false; + } +} + +function setKeyActions(elem,action) +{ + elem.setAttribute('onkeydown',action); + elem.setAttribute('onkeypress',action); + elem.setAttribute('onkeyup',action); +} + +function setClassAttr(elem,attr) +{ + elem.setAttribute('class',attr); + elem.setAttribute('className',attr); +} + +function createResults() +{ + var results = document.getElementById("SRResults"); + for (var e=0; e<searchData.length; e++) + { + var id = searchData[e][0]; + var srResult = document.createElement('div'); + srResult.setAttribute('id','SR_'+id); + setClassAttr(srResult,'SRResult'); + var srEntry = document.createElement('div'); + setClassAttr(srEntry,'SREntry'); + var srLink = document.createElement('a'); + srLink.setAttribute('id','Item'+e); + setKeyActions(srLink,'return searchResults.Nav(event,'+e+')'); + setClassAttr(srLink,'SRSymbol'); + srLink.innerHTML = searchData[e][1][0]; + srEntry.appendChild(srLink); + if (searchData[e][1].length==2) // single result + { + srLink.setAttribute('href',searchData[e][1][1][0]); + if (searchData[e][1][1][1]) + { + srLink.setAttribute('target','_parent'); + } + var srScope = document.createElement('span'); + setClassAttr(srScope,'SRScope'); + srScope.innerHTML = searchData[e][1][1][2]; + srEntry.appendChild(srScope); + } + else // multiple results + { + srLink.setAttribute('href','javascript:searchResults.Toggle("SR_'+id+'")'); + var srChildren = document.createElement('div'); + setClassAttr(srChildren,'SRChildren'); + for (var c=0; c<searchData[e][1].length-1; c++) + { + var srChild = document.createElement('a'); + srChild.setAttribute('id','Item'+e+'_c'+c); + setKeyActions(srChild,'return searchResults.NavChild(event,'+e+','+c+')'); + setClassAttr(srChild,'SRScope'); + srChild.setAttribute('href',searchData[e][1][c+1][0]); + if (searchData[e][1][c+1][1]) + { + srChild.setAttribute('target','_parent'); + } + srChild.innerHTML = searchData[e][1][c+1][2]; + srChildren.appendChild(srChild); + } + srEntry.appendChild(srChildren); + } + srResult.appendChild(srEntry); + results.appendChild(srResult); + } +} + diff --git a/docs/Core/html/search/search_l.png b/docs/Core/html/search/search_l.png Binary files differnew file mode 100644 index 0000000..c872f4d --- /dev/null +++ b/docs/Core/html/search/search_l.png diff --git a/docs/Core/html/search/search_m.png b/docs/Core/html/search/search_m.png Binary files differnew file mode 100644 index 0000000..b429a16 --- /dev/null +++ b/docs/Core/html/search/search_m.png diff --git a/docs/Core/html/search/search_r.png b/docs/Core/html/search/search_r.png Binary files differnew file mode 100644 index 0000000..97ee8b4 --- /dev/null +++ b/docs/Core/html/search/search_r.png diff --git a/docs/Core/html/search/variables_0.html b/docs/Core/html/search/variables_0.html new file mode 100644 index 0000000..1b8adc9 --- /dev/null +++ b/docs/Core/html/search/variables_0.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="variables_0.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/variables_0.js b/docs/Core/html/search/variables_0.js new file mode 100644 index 0000000..d16d2a2 --- /dev/null +++ b/docs/Core/html/search/variables_0.js @@ -0,0 +1,4 @@ +var searchData= +[ + ['_5freserved0',['_reserved0',['../unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728',1,'APSR_Type::_reserved0()'],['../unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa',1,'IPSR_Type::_reserved0()'],['../unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5',1,'xPSR_Type::_reserved0()'],['../unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50',1,'CONTROL_Type::_reserved0()']]] +]; diff --git a/docs/Core/html/search/variables_1.html b/docs/Core/html/search/variables_1.html new file mode 100644 index 0000000..78f63cd --- /dev/null +++ b/docs/Core/html/search/variables_1.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="variables_1.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/variables_1.js b/docs/Core/html/search/variables_1.js new file mode 100644 index 0000000..8f4757e --- /dev/null +++ b/docs/Core/html/search/variables_1.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['acpr',['ACPR',['../structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3',1,'TPI_Type']]], + ['actlr',['ACTLR',['../structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23',1,'SCnSCB_Type']]], + ['adr',['ADR',['../structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1',1,'SCB_Type']]], + ['afsr',['AFSR',['../structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e',1,'SCB_Type']]], + ['aircr',['AIRCR',['../structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380',1,'SCB_Type']]] +]; diff --git a/docs/Core/html/search/variables_10.html b/docs/Core/html/search/variables_10.html new file mode 100644 index 0000000..c43ead3 --- /dev/null +++ b/docs/Core/html/search/variables_10.html @@ -0,0 +1,26 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html><head><title></title> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta name="generator" content="Doxygen 1.8.6"> +<link rel="stylesheet" type="text/css" href="search.css"/> +<script type="text/javascript" src="variables_10.js"></script> +<script type="text/javascript" src="search.js"></script> +</head> +<body class="SRPage"> +<div id="SRIndex"> +<div class="SRStatus" id="Loading">Loading...</div> +<div id="SRResults"></div> +<script type="text/javascript"><!-- +createResults(); +--></script> +<div class="SRStatus" id="Searching">Searching...</div> +<div class="SRStatus" id="NoMatches">No Matches</div> +<script type="text/javascript"><!-- +document.getElementById("Loading").style.display="none"; +document.getElementById("NoMatches").style.display="none"; +var searchResults = new SearchResults("searchResults"); +searchResults.Search(); +--></script> +</div> +</body> +</html> diff --git a/docs/Core/html/search/variables_10.js b/docs/Core/html/search/variables_10.js new file mode 100644 index 0000000..71289fd --- /dev/null +++ b/docs/Core/html/search/variables_10.js @@ -0,0 +1,9 @@ +var searchData= +[ + ['t',['T',['../unionxPSR__Type.html#a7eed9fe24ae8d354cd76ae1c1110a658',1,'xPSR_Type']]], + ['tcr',['TCR',['../structITM__Type.html#a04b9fbc83759cb818dfa161d39628426',1,'ITM_Type']]], + ['ter',['TER',['../structITM__Type.html#acd03c6858f7b678dab6a6121462e7807',1,'ITM_Type']]], + ['tpr',['TPR',['../structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2',1,'ITM_Type']]], + ['trigger',['TRIGGER',['../structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd',1,'TPI_Type']]], + ['type',['TYPE',['../structMPU__Type.html#aba02af87f77577c725cf73879cabb609',1,'MPU_Type']]] +]; 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diff --git a/docs/Core/html/startup_s_pg.html b/docs/Core/html/startup_s_pg.html new file mode 100644 index 0000000..09790b2 --- /dev/null +++ b/docs/Core/html/startup_s_pg.html @@ -0,0 +1,333 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Startup File startup_<device>.s</title> +<title>CMSIS-Core (Cortex-M): Startup File startup_<device>.s</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); 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+</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('startup_s_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Startup File startup_<device>.s </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>The <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> contains:</p> +<ul> +<li>The reset handler which is executed after CPU reset and typically calls the <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> function.</li> +<li>The setup values for the Main Stack Pointer (MSP).</li> +<li>Exception vectors of the Cortex-M Processor with weak functions that implement default routines.</li> +<li>Interrupt vectors that are device specific with weak functions that implement default routines.</li> +</ul> +<p>The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.</p> +<p>To adapt the file to a new device only the interrupt vector table needs to be extended with the device-specific interrupt handlers. The naming convention for the interrupt handler names are <interrupt_name>_IRQHandler. This table needs to be consistent with <a class="el" href="group__NVIC__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all the IRQ numbers for each interrupt.</p> +<p><b>Example:</b> </p> +<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p> +<div class="fragment"><div class="line"> ; External Interrupts</div> +<div class="line"> DCD WAKEUP0_IRQHandler ; 16+ 0: Wakeup PIO0.0</div> +<div class="line"> DCD WAKEUP1_IRQHandler ; 16+ 1: Wakeup PIO0.1</div> +<div class="line"> DCD WAKEUP2_IRQHandler ; 16+ 2: Wakeup PIO0.2</div> +<div class="line"> : :</div> +<div class="line"> : :</div> +<div class="line"> DCD EINT1_IRQHandler ; 16+30: PIO INT1</div> +<div class="line"> DCD EINT0_IRQHandler ; 16+31: PIO INT0</div> +<div class="line"> :</div> +<div class="line"> :</div> +<div class="line"> EXPORT WAKEUP0_IRQHandler [WEAK]</div> +<div class="line"> EXPORT WAKEUP1_IRQHandler [WEAK]</div> +<div class="line"> EXPORT WAKEUP2_IRQHandler [WEAK]</div> +<div class="line"> : :</div> +<div class="line"> : :</div> +<div class="line"> EXPORT EINT1_IRQHandler [WEAK]</div> +<div class="line"> EXPORT EINT0_IRQHandler [WEAK]</div> +<div class="line"></div> +<div class="line">WAKEUP0_IRQHandler</div> +<div class="line">WAKEUP1_IRQHandler</div> +<div class="line">WAKEUP1_IRQHandler</div> +<div class="line"> :</div> +<div class="line"> :</div> +<div class="line">EINT1_IRQHandler</div> +<div class="line">EINT0_IRQHandler</div> +<div class="line"> B .</div> +</div><!-- fragment --><h1><a class="anchor" id="startup_s_sec"></a> +startup_Device.s Template File</h1> +<p>An Arm Compiler <a class="el" href="startup_s_pg.html#startup_s_sec">startup_Device.s Template File</a> for an Armv7-M processor like Cortex-M3 is shown below. The files for other compiler vendors differ slightly in the syntax, but not in the overall structure.</p> +<pre class="fragment">;/**************************************************************************//** +; * @file startup_<Device>.s +; * @brief CMSIS Cortex-M ARMv7-M based Core Device Startup File for +; * Device <Device> +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +;<h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +;</h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +;<h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +;</h> + +Heap_Size EQU 0x00000C00 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; External Interrupts +; ToDo: Add here the vectors for the device specific external interrupts handler + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD Interrupt3_Handler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler Interrupt3_Handler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END +</pre> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. 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+</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">ARM_MPU_Region_t Struct Reference<div class="ingroups"><a class="el" href="group__mpu__functions.html">MPU Functions for Armv7-M</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>Setup information of a single MPU Region. + <a href="structARM__MPU__Region__t.html#details">More...</a></p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:aa5e3c6aeaddbc0c283085dc971dd1a22"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22">RBAR</a></td></tr> +<tr class="memdesc:aa5e3c6aeaddbc0c283085dc971dd1a22"><td class="mdescLeft"> </td><td class="mdescRight">The region base address register value (<a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a>) <a href="#aa5e3c6aeaddbc0c283085dc971dd1a22">More...</a><br/></td></tr> +<tr class="separator:aa5e3c6aeaddbc0c283085dc971dd1a22"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6a3e404b403c8df611f27d902d745d8d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d">RASR</a></td></tr> +<tr class="memdesc:a6a3e404b403c8df611f27d902d745d8d"><td class="mdescLeft"> </td><td class="mdescRight">The region attribute and size register value (<a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a>), see <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a>. <a href="#a6a3e404b403c8df611f27d902d745d8d">More...</a><br/></td></tr> +<tr class="separator:a6a3e404b403c8df611f27d902d745d8d"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<a name="details" id="details"></a><h2 class="groupheader">Description</h2> +<div class="textblock"><p>The typedef <a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a> allows to define a MPU table (array of MPU regions) with pre-compiled register values. Such tables enable efficient MPU setup using the function <a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a>.</p> +<p><b>Example:</b> See <a class="el" href="group__mpu__functions.html#gafa27b26d5847fa8e465584e376b6078a">ARM_MPU_Load</a> </p> +</div><h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a6a3e404b403c8df611f27d902d745d8d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">ARM_MPU_Region_t::RASR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>This value specifies region attributes and size. Use the <a class="el" href="group__mpu__functions.html#ga96b93785c92e2dbcb3a2356c25bf2adc">ARM_MPU_RASR</a> macro to compose this value. </p> + +</div> +</div> +<a class="anchor" id="aa5e3c6aeaddbc0c283085dc971dd1a22"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">ARM_MPU_Region_t::RBAR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>This value specifies the start address of the MPU protected memory region. The address must be a multiple of the region size (size aligned).</p> +<p>See <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a> for details about field bit format. </p> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structARM__MPU__Region__t.html">ARM_MPU_Region_t</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structARM__MPU__Region__t.js b/docs/Core/html/structARM__MPU__Region__t.js new file mode 100644 index 0000000..0a08361 --- /dev/null +++ b/docs/Core/html/structARM__MPU__Region__t.js @@ -0,0 +1,5 @@ +var structARM__MPU__Region__t = +[ + [ "RASR", "structARM__MPU__Region__t.html#a6a3e404b403c8df611f27d902d745d8d", null ], + [ "RBAR", "structARM__MPU__Region__t.html#aa5e3c6aeaddbc0c283085dc971dd1a22", null ] +];
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(CoreDebug). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:ad63554e4650da91a8e79929cbb63db66"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66">DHCSR</a></td></tr> +<tr class="memdesc:ad63554e4650da91a8e79929cbb63db66"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Debug Halting Control and Status Register. <a href="#ad63554e4650da91a8e79929cbb63db66">More...</a><br/></td></tr> +<tr class="separator:ad63554e4650da91a8e79929cbb63db66"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af907cf64577eaf927dac6787df6dd98b"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b">DCRSR</a></td></tr> +<tr class="memdesc:af907cf64577eaf927dac6787df6dd98b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 ( /W) Debug Core Register Selector Register. <a href="#af907cf64577eaf927dac6787df6dd98b">More...</a><br/></td></tr> +<tr class="separator:af907cf64577eaf927dac6787df6dd98b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">DCRDR</a></td></tr> +<tr class="memdesc:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Debug Core Register Data Register. <a href="#aab3cc92ef07bc1f04b3a3aa6db2c2d55">More...</a><br/></td></tr> +<tr class="separator:aab3cc92ef07bc1f04b3a3aa6db2c2d55"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aeb3126abc4c258a858f21f356c0df6ee"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee">DEMCR</a></td></tr> +<tr class="memdesc:aeb3126abc4c258a858f21f356c0df6ee"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Debug Exception and Monitor Control Register. <a href="#aeb3126abc4c258a858f21f356c0df6ee">More...</a><br/></td></tr> +<tr class="separator:aeb3126abc4c258a858f21f356c0df6ee"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="aab3cc92ef07bc1f04b3a3aa6db2c2d55"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t CoreDebug_Type::DCRDR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="af907cf64577eaf927dac6787df6dd98b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM uint32_t CoreDebug_Type::DCRSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="aeb3126abc4c258a858f21f356c0df6ee"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t CoreDebug_Type::DEMCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ad63554e4650da91a8e79929cbb63db66"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t CoreDebug_Type::DHCSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structCoreDebug__Type.html">CoreDebug_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structCoreDebug__Type.js b/docs/Core/html/structCoreDebug__Type.js new file mode 100644 index 0000000..970a8dc --- /dev/null +++ b/docs/Core/html/structCoreDebug__Type.js @@ -0,0 +1,7 @@ +var structCoreDebug__Type = +[ + [ "DCRDR", "structCoreDebug__Type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55", null ], + [ "DCRSR", "structCoreDebug__Type.html#af907cf64577eaf927dac6787df6dd98b", null ], + [ "DEMCR", "structCoreDebug__Type.html#aeb3126abc4c258a858f21f356c0df6ee", null ], + [ "DHCSR", "structCoreDebug__Type.html#ad63554e4650da91a8e79929cbb63db66", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structDWT__Type.html b/docs/Core/html/structDWT__Type.html new file mode 100644 index 0000000..a02d24b --- /dev/null +++ b/docs/Core/html/structDWT__Type.html @@ -0,0 +1,490 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>DWT_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): DWT_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">DWT_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the Data Watchpoint and Trace Register (DWT). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:add790c53410023b3b581919bb681fe2a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#add790c53410023b3b581919bb681fe2a">CTRL</a></td></tr> +<tr class="memdesc:add790c53410023b3b581919bb681fe2a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Control Register. <a href="#add790c53410023b3b581919bb681fe2a">More...</a><br/></td></tr> +<tr class="separator:add790c53410023b3b581919bb681fe2a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a102eaa529d9098242851cb57c52b42d9"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a102eaa529d9098242851cb57c52b42d9">CYCCNT</a></td></tr> +<tr class="memdesc:a102eaa529d9098242851cb57c52b42d9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Cycle Count Register. <a href="#a102eaa529d9098242851cb57c52b42d9">More...</a><br/></td></tr> +<tr class="separator:a102eaa529d9098242851cb57c52b42d9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2c08096c82abe245c0fa97badc458154"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a2c08096c82abe245c0fa97badc458154">CPICNT</a></td></tr> +<tr class="memdesc:a2c08096c82abe245c0fa97badc458154"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) CPI Count Register. <a href="#a2c08096c82abe245c0fa97badc458154">More...</a><br/></td></tr> +<tr class="separator:a2c08096c82abe245c0fa97badc458154"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a9fe20c16c5167ca61486caf6832686d1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a9fe20c16c5167ca61486caf6832686d1">EXCCNT</a></td></tr> +<tr class="memdesc:a9fe20c16c5167ca61486caf6832686d1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Exception Overhead Count Register. <a href="#a9fe20c16c5167ca61486caf6832686d1">More...</a><br/></td></tr> +<tr class="separator:a9fe20c16c5167ca61486caf6832686d1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a416a54e2084ce66e5ca74f152a5ecc70"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a416a54e2084ce66e5ca74f152a5ecc70">SLEEPCNT</a></td></tr> +<tr class="memdesc:a416a54e2084ce66e5ca74f152a5ecc70"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Sleep Count Register. <a href="#a416a54e2084ce66e5ca74f152a5ecc70">More...</a><br/></td></tr> +<tr class="separator:a416a54e2084ce66e5ca74f152a5ecc70"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">LSUCNT</a></td></tr> +<tr class="memdesc:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) LSU Count Register. <a href="#acc05d89bdb1b4fe2fa499920ec02d0b1">More...</a><br/></td></tr> +<tr class="separator:acc05d89bdb1b4fe2fa499920ec02d0b1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">FOLDCNT</a></td></tr> +<tr class="memdesc:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) Folded-instruction Count Register. <a href="#a1cfc48384ebd8fd8fb7e5d955aae6c97">More...</a><br/></td></tr> +<tr class="separator:a1cfc48384ebd8fd8fb7e5d955aae6c97"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6353ca1d1ad9bc1be05d3b5632960113"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a6353ca1d1ad9bc1be05d3b5632960113">PCSR</a></td></tr> +<tr class="memdesc:a6353ca1d1ad9bc1be05d3b5632960113"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/ ) Program Counter Sample Register. <a href="#a6353ca1d1ad9bc1be05d3b5632960113">More...</a><br/></td></tr> +<tr class="separator:a6353ca1d1ad9bc1be05d3b5632960113"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a61c2965af5bc0643f9af65620b0e67c9"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a61c2965af5bc0643f9af65620b0e67c9">COMP0</a></td></tr> +<tr class="memdesc:a61c2965af5bc0643f9af65620b0e67c9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) Comparator Register 0. <a href="#a61c2965af5bc0643f9af65620b0e67c9">More...</a><br/></td></tr> +<tr class="separator:a61c2965af5bc0643f9af65620b0e67c9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a821eb5e71f340ec077efc064cfc567db"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a821eb5e71f340ec077efc064cfc567db">MASK0</a></td></tr> +<tr class="memdesc:a821eb5e71f340ec077efc064cfc567db"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) Mask Register 0. <a href="#a821eb5e71f340ec077efc064cfc567db">More...</a><br/></td></tr> +<tr class="separator:a821eb5e71f340ec077efc064cfc567db"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a579ae082f58a0317b7ef029b20f52889"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a579ae082f58a0317b7ef029b20f52889">FUNCTION0</a></td></tr> +<tr class="memdesc:a579ae082f58a0317b7ef029b20f52889"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Function Register 0. <a href="#a579ae082f58a0317b7ef029b20f52889">More...</a><br/></td></tr> +<tr class="separator:a579ae082f58a0317b7ef029b20f52889"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:addd893d655ed90d40705b20170daac59"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#addd893d655ed90d40705b20170daac59">RESERVED0</a> [1]</td></tr> +<tr class="memdesc:addd893d655ed90d40705b20170daac59"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#addd893d655ed90d40705b20170daac59">More...</a><br/></td></tr> +<tr class="separator:addd893d655ed90d40705b20170daac59"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a38714af6b7fa7c64d68f5e1efbe7a931">COMP1</a></td></tr> +<tr class="memdesc:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Comparator Register 1. <a href="#a38714af6b7fa7c64d68f5e1efbe7a931">More...</a><br/></td></tr> +<tr class="separator:a38714af6b7fa7c64d68f5e1efbe7a931"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aabf94936c9340e62fed836dcfb152405"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#aabf94936c9340e62fed836dcfb152405">MASK1</a></td></tr> +<tr class="memdesc:aabf94936c9340e62fed836dcfb152405"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W) Mask Register 1. <a href="#aabf94936c9340e62fed836dcfb152405">More...</a><br/></td></tr> +<tr class="separator:aabf94936c9340e62fed836dcfb152405"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8dfcf25675f9606aa305c46e85182e4e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a8dfcf25675f9606aa305c46e85182e4e">FUNCTION1</a></td></tr> +<tr class="memdesc:a8dfcf25675f9606aa305c46e85182e4e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W) Function Register 1. <a href="#a8dfcf25675f9606aa305c46e85182e4e">More...</a><br/></td></tr> +<tr class="separator:a8dfcf25675f9606aa305c46e85182e4e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a069871233a8c1df03521e6d7094f1de4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a069871233a8c1df03521e6d7094f1de4">RESERVED1</a> [1]</td></tr> +<tr class="memdesc:a069871233a8c1df03521e6d7094f1de4"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a069871233a8c1df03521e6d7094f1de4">More...</a><br/></td></tr> +<tr class="separator:a069871233a8c1df03521e6d7094f1de4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a5ae6dde39989f27bae90afc2347deb46"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a5ae6dde39989f27bae90afc2347deb46">COMP2</a></td></tr> +<tr class="memdesc:a5ae6dde39989f27bae90afc2347deb46"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/W) Comparator Register 2. <a href="#a5ae6dde39989f27bae90afc2347deb46">More...</a><br/></td></tr> +<tr class="separator:a5ae6dde39989f27bae90afc2347deb46"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a00ac4d830dfe0070a656cda9baed170f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a00ac4d830dfe0070a656cda9baed170f">MASK2</a></td></tr> +<tr class="memdesc:a00ac4d830dfe0070a656cda9baed170f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x044 (R/W) Mask Register 2. <a href="#a00ac4d830dfe0070a656cda9baed170f">More...</a><br/></td></tr> +<tr class="separator:a00ac4d830dfe0070a656cda9baed170f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ab1b60d6600c38abae515bab8e86a188f"><td class="memItemLeft" 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class="separator:a8556ca1c32590517602d92fe0cd55738"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a85eb73d1848ac3f82d39d6c3e8910847"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a85eb73d1848ac3f82d39d6c3e8910847">COMP3</a></td></tr> +<tr class="memdesc:a85eb73d1848ac3f82d39d6c3e8910847"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/W) Comparator Register 3. <a href="#a85eb73d1848ac3f82d39d6c3e8910847">More...</a><br/></td></tr> +<tr class="separator:a85eb73d1848ac3f82d39d6c3e8910847"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2a509d8505c37a3b64f6b24993df5f3f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a2a509d8505c37a3b64f6b24993df5f3f">MASK3</a></td></tr> +<tr class="memdesc:a2a509d8505c37a3b64f6b24993df5f3f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x054 (R/W) Mask Register 3. <a href="#a2a509d8505c37a3b64f6b24993df5f3f">More...</a><br/></td></tr> +<tr class="separator:a2a509d8505c37a3b64f6b24993df5f3f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a52d4ff278fae6f9216c63b74ce328841"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structDWT__Type.html#a52d4ff278fae6f9216c63b74ce328841">FUNCTION3</a></td></tr> +<tr class="memdesc:a52d4ff278fae6f9216c63b74ce328841"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x058 (R/W) Function Register 3. <a href="#a52d4ff278fae6f9216c63b74ce328841">More...</a><br/></td></tr> +<tr class="separator:a52d4ff278fae6f9216c63b74ce328841"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" 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class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">FPU_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the Floating Point Unit (FPU). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a7b2967b069046c8544adbbc1db143a36"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a7b2967b069046c8544adbbc1db143a36">RESERVED0</a> [1]</td></tr> +<tr class="memdesc:a7b2967b069046c8544adbbc1db143a36"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a7b2967b069046c8544adbbc1db143a36">More...</a><br/></td></tr> +<tr class="separator:a7b2967b069046c8544adbbc1db143a36"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af1b708c5e413739150df3d16ca3b7061"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061">FPCCR</a></td></tr> +<tr class="memdesc:af1b708c5e413739150df3d16ca3b7061"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Floating-Point Context Control Register. <a href="#af1b708c5e413739150df3d16ca3b7061">More...</a><br/></td></tr> +<tr class="separator:af1b708c5e413739150df3d16ca3b7061"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a55263b468d0f8e11ac77aec9ff87c820"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820">FPCAR</a></td></tr> +<tr class="memdesc:a55263b468d0f8e11ac77aec9ff87c820"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Floating-Point Context Address Register. <a href="#a55263b468d0f8e11ac77aec9ff87c820">More...</a><br/></td></tr> +<tr class="separator:a55263b468d0f8e11ac77aec9ff87c820"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a58d1989664a06db6ec2e122eefa9f04a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a">FPDSCR</a></td></tr> +<tr class="memdesc:a58d1989664a06db6ec2e122eefa9f04a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Floating-Point Default Status Control Register. <a href="#a58d1989664a06db6ec2e122eefa9f04a">More...</a><br/></td></tr> +<tr class="separator:a58d1989664a06db6ec2e122eefa9f04a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4f19014defe6033d070b80af19ef627c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a4f19014defe6033d070b80af19ef627c">MVFR0</a></td></tr> +<tr class="memdesc:a4f19014defe6033d070b80af19ef627c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/ ) Media and FP Feature Register 0. <a href="#a4f19014defe6033d070b80af19ef627c">More...</a><br/></td></tr> +<tr class="separator:a4f19014defe6033d070b80af19ef627c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a66f8cfa49a423b480001a4e101bf842d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d">MVFR1</a></td></tr> +<tr class="memdesc:a66f8cfa49a423b480001a4e101bf842d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/ ) Media and FP Feature Register 1. <a href="#a66f8cfa49a423b480001a4e101bf842d">More...</a><br/></td></tr> +<tr class="separator:a66f8cfa49a423b480001a4e101bf842d"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a55263b468d0f8e11ac77aec9ff87c820"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t FPU_Type::FPCAR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="af1b708c5e413739150df3d16ca3b7061"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t FPU_Type::FPCCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a58d1989664a06db6ec2e122eefa9f04a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t FPU_Type::FPDSCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4f19014defe6033d070b80af19ef627c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t FPU_Type::MVFR0</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a66f8cfa49a423b480001a4e101bf842d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t FPU_Type::MVFR1</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a7b2967b069046c8544adbbc1db143a36"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t FPU_Type::RESERVED0[1]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structFPU__Type.html">FPU_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structFPU__Type.js b/docs/Core/html/structFPU__Type.js new file mode 100644 index 0000000..0a8dfde --- /dev/null +++ b/docs/Core/html/structFPU__Type.js @@ -0,0 +1,9 @@ +var structFPU__Type = +[ + [ "FPCAR", "structFPU__Type.html#a55263b468d0f8e11ac77aec9ff87c820", null ], + [ "FPCCR", "structFPU__Type.html#af1b708c5e413739150df3d16ca3b7061", null ], + [ "FPDSCR", "structFPU__Type.html#a58d1989664a06db6ec2e122eefa9f04a", null ], + [ "MVFR0", "structFPU__Type.html#a4f19014defe6033d070b80af19ef627c", null ], + [ "MVFR1", "structFPU__Type.html#a66f8cfa49a423b480001a4e101bf842d", null ], + [ "RESERVED0", "structFPU__Type.html#a7b2967b069046c8544adbbc1db143a36", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structITM__Type.html b/docs/Core/html/structITM__Type.html new file mode 100644 index 0000000..b163e30 --- /dev/null +++ b/docs/Core/html/structITM__Type.html @@ -0,0 +1,521 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>ITM_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): ITM_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:af95bc1810f9ea802d628cb9dea81e02e"><td class="memItemLeft" >union {</td></tr> +<tr class="memitem:a19715ce0fd48d4015c27db6d0a41d49a"><td class="memItemLeft" >   __OM uint8_t   <a class="el" href="structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275">u8</a></td></tr> +<tr class="separator:a19715ce0fd48d4015c27db6d0a41d49a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:add6779a5b967324d2700661c93283103"><td class="memItemLeft" >   __OM uint16_t   <a class="el" href="structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3">u16</a></td></tr> +<tr class="separator:add6779a5b967324d2700661c93283103"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a74a1dd7cc6bced8cb3b1da2ce6ea7eed"><td class="memItemLeft" >   __OM uint32_t   <a class="el" href="structITM__Type.html#a5834885903a557674f078f3b71fa8bc8">u32</a></td></tr> +<tr class="separator:a74a1dd7cc6bced8cb3b1da2ce6ea7eed"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af95bc1810f9ea802d628cb9dea81e02e"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e">PORT</a> [32U]</td></tr> +<tr class="separator:af95bc1810f9ea802d628cb9dea81e02e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:acd03c6858f7b678dab6a6121462e7807"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#acd03c6858f7b678dab6a6121462e7807">TER</a></td></tr> +<tr class="separator:acd03c6858f7b678dab6a6121462e7807"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae907229ba50538bf370fbdfd54c099a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2">TPR</a></td></tr> +<tr class="separator:ae907229ba50538bf370fbdfd54c099a2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a04b9fbc83759cb818dfa161d39628426"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a04b9fbc83759cb818dfa161d39628426">TCR</a></td></tr> +<tr class="separator:a04b9fbc83759cb818dfa161d39628426"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa9da04891e48d1a2f054de186e9c4c94"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94">IWR</a></td></tr> +<tr class="separator:aa9da04891e48d1a2f054de186e9c4c94"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a66eb82a070953f09909f39b8e516fb91"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a66eb82a070953f09909f39b8e516fb91">IRR</a></td></tr> +<tr class="separator:a66eb82a070953f09909f39b8e516fb91"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae2ce4d3a54df2fd11a197ccac4406cd0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0">IMCR</a></td></tr> +<tr class="separator:ae2ce4d3a54df2fd11a197ccac4406cd0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7f9c2a2113a11c7f3e98915f95b669d5"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5">LAR</a></td></tr> +<tr class="separator:a7f9c2a2113a11c7f3e98915f95b669d5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3861c67933a24dd6632288c4ed0b80c8"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8">LSR</a></td></tr> +<tr class="separator:a3861c67933a24dd6632288c4ed0b80c8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2372a4ebb63e36d1eb3fcf83a74fd537"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537">DEVARCH</a></td></tr> +<tr class="separator:a2372a4ebb63e36d1eb3fcf83a74fd537"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aad5e11dd4baf6d941bd6c7450f60a158"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158">PID4</a></td></tr> +<tr class="separator:aad5e11dd4baf6d941bd6c7450f60a158"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af9085648bf18f69b5f9d1136d45e1d37"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#af9085648bf18f69b5f9d1136d45e1d37">PID5</a></td></tr> +<tr class="separator:af9085648bf18f69b5f9d1136d45e1d37"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ad34dbe6b1072c77d36281049c8b169f6"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ad34dbe6b1072c77d36281049c8b169f6">PID6</a></td></tr> +<tr class="separator:ad34dbe6b1072c77d36281049c8b169f6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2bcec6803f28f30d5baf5e20e3517d3d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d">PID7</a></td></tr> +<tr class="separator:a2bcec6803f28f30d5baf5e20e3517d3d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ab4a4cc97ad658e9c46cf17490daffb8a"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ab4a4cc97ad658e9c46cf17490daffb8a">PID0</a></td></tr> +<tr class="separator:ab4a4cc97ad658e9c46cf17490daffb8a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a89ea1d805a668d6589b22d8e678eb6a4"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a89ea1d805a668d6589b22d8e678eb6a4">PID1</a></td></tr> +<tr class="separator:a89ea1d805a668d6589b22d8e678eb6a4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8471c4d77b7107cf580587509da69f38"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a8471c4d77b7107cf580587509da69f38">PID2</a></td></tr> +<tr class="separator:a8471c4d77b7107cf580587509da69f38"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af317d5e2d946d70e6fb67c02b92cc8a3"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#af317d5e2d946d70e6fb67c02b92cc8a3">PID3</a></td></tr> +<tr class="separator:af317d5e2d946d70e6fb67c02b92cc8a3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a30bb2b166b1723867da4a708935677ba"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a30bb2b166b1723867da4a708935677ba">CID0</a></td></tr> +<tr class="separator:a30bb2b166b1723867da4a708935677ba"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac40df2c3a6cef02f90b4e82c8204756f"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f">CID1</a></td></tr> +<tr class="separator:ac40df2c3a6cef02f90b4e82c8204756f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8000b92e4e528ae7ac4cb8b8d9f6757d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d">CID2</a></td></tr> +<tr class="separator:a8000b92e4e528ae7ac4cb8b8d9f6757d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a43451f43f514108d9eaed5b017f8d921"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structITM__Type.html#a43451f43f514108d9eaed5b017f8d921">CID3</a></td></tr> +<tr class="separator:a43451f43f514108d9eaed5b017f8d921"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a30bb2b166b1723867da4a708935677ba"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::CID0</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 </p> + +</div> +</div> +<a class="anchor" id="ac40df2c3a6cef02f90b4e82c8204756f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::CID1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 </p> + +</div> +</div> +<a class="anchor" id="a8000b92e4e528ae7ac4cb8b8d9f6757d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::CID2</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 </p> + +</div> +</div> +<a class="anchor" id="a43451f43f514108d9eaed5b017f8d921"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::CID3</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFFC (R/ ) ITM Component Identification Register #3 </p> + +</div> +</div> +<a class="anchor" id="a2372a4ebb63e36d1eb3fcf83a74fd537"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::DEVARCH</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) </p> + +</div> +</div> +<a class="anchor" id="ae2ce4d3a54df2fd11a197ccac4406cd0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t ITM_Type::IMCR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xF00 (R/W) ITM Integration Mode Control Register </p> + +</div> +</div> +<a class="anchor" id="a66eb82a070953f09909f39b8e516fb91"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::IRR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xEFC (R/ ) ITM Integration Read Register </p> + +</div> +</div> +<a class="anchor" id="aa9da04891e48d1a2f054de186e9c4c94"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM uint32_t ITM_Type::IWR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xEF8 ( /W) ITM Integration Write Register </p> + +</div> +</div> +<a class="anchor" id="a7f9c2a2113a11c7f3e98915f95b669d5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM uint32_t ITM_Type::LAR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFB0 ( /W) ITM Lock Access Register </p> + +</div> +</div> +<a class="anchor" id="a3861c67933a24dd6632288c4ed0b80c8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::LSR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFB4 (R/ ) ITM Lock Status Register </p> + +</div> +</div> +<a class="anchor" id="ab4a4cc97ad658e9c46cf17490daffb8a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::PID0</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 </p> + +</div> +</div> +<a class="anchor" id="a89ea1d805a668d6589b22d8e678eb6a4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::PID1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 </p> + +</div> +</div> +<a class="anchor" id="a8471c4d77b7107cf580587509da69f38"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::PID2</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 </p> + +</div> +</div> +<a class="anchor" id="af317d5e2d946d70e6fb67c02b92cc8a3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::PID3</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 </p> + +</div> +</div> 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+</div> +<a class="anchor" id="a2bcec6803f28f30d5baf5e20e3517d3d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t ITM_Type::PID7</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 </p> + +</div> +</div> +<a class="anchor" id="af95bc1810f9ea802d628cb9dea81e02e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM { ... } ITM_Type::PORT[32U]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0x000 ( /W) ITM Stimulus Port Registers </p> + +</div> +</div> +<a class="anchor" id="a04b9fbc83759cb818dfa161d39628426"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t ITM_Type::TCR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xE80 (R/W) ITM Trace Control Register </p> + +</div> +</div> +<a class="anchor" id="acd03c6858f7b678dab6a6121462e7807"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t ITM_Type::TER</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xE00 (R/W) ITM Trace Enable Register </p> + +</div> +</div> +<a class="anchor" id="ae907229ba50538bf370fbdfd54c099a2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t ITM_Type::TPR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0xE40 (R/W) ITM Trace Privilege Register </p> + +</div> +</div> +<a class="anchor" id="a962a970dfd286cad7f8a8577e87d4ad3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM uint16_t ITM_Type::u16</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Offset: 0x000 ( /W) ITM Stimulus Port 16-bit </p> + +</div> +</div> +<a class="anchor" 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All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structITM__Type.js b/docs/Core/html/structITM__Type.js new file mode 100644 index 0000000..8aa3816 --- /dev/null +++ b/docs/Core/html/structITM__Type.js @@ -0,0 +1,28 @@ +var structITM__Type = +[ + [ "CID0", "structITM__Type.html#a30bb2b166b1723867da4a708935677ba", null ], + [ "CID1", "structITM__Type.html#ac40df2c3a6cef02f90b4e82c8204756f", null ], + [ "CID2", "structITM__Type.html#a8000b92e4e528ae7ac4cb8b8d9f6757d", null ], + [ "CID3", "structITM__Type.html#a43451f43f514108d9eaed5b017f8d921", null ], + [ "DEVARCH", "structITM__Type.html#a2372a4ebb63e36d1eb3fcf83a74fd537", null ], + [ "IMCR", "structITM__Type.html#ae2ce4d3a54df2fd11a197ccac4406cd0", null ], + [ "IRR", "structITM__Type.html#a66eb82a070953f09909f39b8e516fb91", null ], + [ "IWR", "structITM__Type.html#aa9da04891e48d1a2f054de186e9c4c94", null ], + [ "LAR", "structITM__Type.html#a7f9c2a2113a11c7f3e98915f95b669d5", null ], + [ "LSR", "structITM__Type.html#a3861c67933a24dd6632288c4ed0b80c8", null ], + [ "PID0", "structITM__Type.html#ab4a4cc97ad658e9c46cf17490daffb8a", null ], + [ "PID1", "structITM__Type.html#a89ea1d805a668d6589b22d8e678eb6a4", null ], + [ "PID2", "structITM__Type.html#a8471c4d77b7107cf580587509da69f38", null ], + [ "PID3", "structITM__Type.html#af317d5e2d946d70e6fb67c02b92cc8a3", null ], + [ "PID4", "structITM__Type.html#aad5e11dd4baf6d941bd6c7450f60a158", null ], + [ "PID5", "structITM__Type.html#af9085648bf18f69b5f9d1136d45e1d37", null ], + [ "PID6", "structITM__Type.html#ad34dbe6b1072c77d36281049c8b169f6", null ], + [ "PID7", "structITM__Type.html#a2bcec6803f28f30d5baf5e20e3517d3d", null ], + [ "PORT", "structITM__Type.html#af95bc1810f9ea802d628cb9dea81e02e", null ], + [ "TCR", "structITM__Type.html#a04b9fbc83759cb818dfa161d39628426", null ], + [ "TER", "structITM__Type.html#acd03c6858f7b678dab6a6121462e7807", null ], + [ "TPR", "structITM__Type.html#ae907229ba50538bf370fbdfd54c099a2", null ], + [ "u16", "structITM__Type.html#a962a970dfd286cad7f8a8577e87d4ad3", null ], + [ "u32", "structITM__Type.html#a5834885903a557674f078f3b71fa8bc8", null ], + [ "u8", "structITM__Type.html#ae773bf9f9dac64e6c28b14aa39f74275", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structMPU__Type.html b/docs/Core/html/structMPU__Type.html new file mode 100644 index 0000000..2e66293 --- /dev/null +++ b/docs/Core/html/structMPU__Type.html @@ -0,0 +1,395 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>MPU_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): MPU_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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(MPU). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:aba02af87f77577c725cf73879cabb609"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#aba02af87f77577c725cf73879cabb609">TYPE</a></td></tr> +<tr class="memdesc:aba02af87f77577c725cf73879cabb609"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) MPU Type Register. <a href="#aba02af87f77577c725cf73879cabb609">More...</a><br/></td></tr> +<tr class="separator:aba02af87f77577c725cf73879cabb609"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f">CTRL</a></td></tr> +<tr class="memdesc:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) MPU Control Register. <a href="#a769178ef949f0d5d8f18ddbd9e4e926f">More...</a><br/></td></tr> +<tr class="separator:a769178ef949f0d5d8f18ddbd9e4e926f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2f7a117a12cb661c76edc4765453f05c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">RNR</a></td></tr> +<tr class="memdesc:a2f7a117a12cb661c76edc4765453f05c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) MPU Region RNRber Register. <a href="#a2f7a117a12cb661c76edc4765453f05c">More...</a><br/></td></tr> +<tr class="separator:a2f7a117a12cb661c76edc4765453f05c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a990c609b26d990b8ba832b110adfd353"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">RBAR</a></td></tr> +<tr class="memdesc:a990c609b26d990b8ba832b110adfd353"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) MPU Region Base Address Register. <a href="#a990c609b26d990b8ba832b110adfd353">More...</a><br/></td></tr> +<tr class="separator:a990c609b26d990b8ba832b110adfd353"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">RASR</a></td></tr> +<tr class="memdesc:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) MPU Region Attribute and Size Register. <a href="#a8f00c4a5e31b0a8d103ed3b0732c17a3">More...</a><br/></td></tr> +<tr class="separator:a8f00c4a5e31b0a8d103ed3b0732c17a3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af8b510a85b175edfd8dd8cc93e967066"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066">RBAR_A1</a></td></tr> +<tr class="memdesc:af8b510a85b175edfd8dd8cc93e967066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register. <a href="#af8b510a85b175edfd8dd8cc93e967066">More...</a><br/></td></tr> +<tr class="separator:af8b510a85b175edfd8dd8cc93e967066"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a1658326c6762637eeef8a79bb467445e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a1658326c6762637eeef8a79bb467445e">RASR_A1</a></td></tr> +<tr class="memdesc:a1658326c6762637eeef8a79bb467445e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register. <a href="#a1658326c6762637eeef8a79bb467445e">More...</a><br/></td></tr> +<tr class="separator:a1658326c6762637eeef8a79bb467445e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a80d534f0dfc080c841e1772c7a68e1a2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2">RBAR_A2</a></td></tr> +<tr class="memdesc:a80d534f0dfc080c841e1772c7a68e1a2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register. <a href="#a80d534f0dfc080c841e1772c7a68e1a2">More...</a><br/></td></tr> +<tr class="separator:a80d534f0dfc080c841e1772c7a68e1a2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a37131c513d8a8d211b402e5dfda97205"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205">RASR_A2</a></td></tr> +<tr class="memdesc:a37131c513d8a8d211b402e5dfda97205"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register. <a href="#a37131c513d8a8d211b402e5dfda97205">More...</a><br/></td></tr> +<tr class="separator:a37131c513d8a8d211b402e5dfda97205"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a207f6e9c3af753367554cc06df300a55"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a207f6e9c3af753367554cc06df300a55">RBAR_A3</a></td></tr> +<tr class="memdesc:a207f6e9c3af753367554cc06df300a55"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register. <a href="#a207f6e9c3af753367554cc06df300a55">More...</a><br/></td></tr> +<tr class="separator:a207f6e9c3af753367554cc06df300a55"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd">RASR_A3</a></td></tr> +<tr class="memdesc:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register. <a href="#a7d15172b163797736a6c6b4dcc0fa3dd">More...</a><br/></td></tr> +<tr class="separator:a7d15172b163797736a6c6b4dcc0fa3dd"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a769178ef949f0d5d8f18ddbd9e4e926f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Enables the MPU, and when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[2] </td><td align="left">PRIVDEFENA </td><td align="left">0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. </td></tr> +<tr> +<td align="left">[1] </td><td align="left">HFNMIENA </td><td align="left">0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - The MPU is disabled. 1 - The MPU is enabled. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a8f00c4a5e31b0a8d103ed3b0732c17a3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RASR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Defines the size and access behavior of the region identified by MPU_RNR, and enables that region.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:29] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[28] </td><td align="left">XN </td><td align="left">Execute Never. </td></tr> +<tr> +<td align="left">[27] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[26:24] </td><td align="left">AP </td><td align="left">Access Permissions, see <a class="el" href="group__mpu__defines.html#gabc4788126d7798469cb862a08d3050cc">ARM_MPU_AP_xxx</a>. </td></tr> +<tr> +<td align="left">[23:22] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[21:19] </td><td align="left">TEX </td><td align="left">Type Extension. </td></tr> +<tr> +<td align="left">[18] </td><td align="left">S </td><td align="left">Shareable. </td></tr> +<tr> +<td align="left">[17] </td><td align="left">C </td><td align="left">Cacheable. </td></tr> +<tr> +<td align="left">[16] </td><td align="left">B </td><td align="left">Bufferable. </td></tr> +<tr> +<td align="left">[15:8] </td><td align="left">SRD </td><td align="left">Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1). </td></tr> +<tr> +<td align="left">[7:6] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[5:1] </td><td align="left">SIZE </td><td align="left">Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">ENABLE </td><td align="left">0 - This region is disabled. 1 - This region is enabled. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a1658326c6762637eeef8a79bb467445e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RASR_A1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p> + +</div> +</div> +<a class="anchor" id="a37131c513d8a8d211b402e5dfda97205"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RASR_A2</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p> + +</div> +</div> +<a class="anchor" id="a7d15172b163797736a6c6b4dcc0fa3dd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RASR_A3</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>. </p> + +</div> +</div> +<a class="anchor" id="a990c609b26d990b8ba832b110adfd353"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RBAR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Holds the base address of the region identified by MPU_RNR. On a write, can also be used to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with the new region number.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:5] </td><td align="left">ADDR </td><td align="left">Base address of the region. </td></tr> +<tr> +<td align="left">[4] </td><td align="left">VALID </td><td align="left">1 - Update <a class="el" href="structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c">MPU_Type::RNR</a> to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. </td></tr> +<tr> +<td align="left">[3:0] </td><td align="left">REGION </td><td align="left">On writes, can specify the number of the region to update, see VALID field description. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="af8b510a85b175edfd8dd8cc93e967066"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RBAR_A1</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p> + +</div> +</div> +<a class="anchor" id="a80d534f0dfc080c841e1772c7a68e1a2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RBAR_A2</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p> + +</div> +</div> +<a class="anchor" id="a207f6e9c3af753367554cc06df300a55"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RBAR_A3</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Alias for <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a>. </p> + +</div> +</div> +<a class="anchor" id="a2f7a117a12cb661c76edc4765453f05c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::RNR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>Selects the region currently accessed by <a class="el" href="structMPU__Type.html#a990c609b26d990b8ba832b110adfd353">MPU_Type::RBAR</a> and <a class="el" href="structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3">MPU_Type::RASR</a>.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[7:0] </td><td align="left">REGION </td><td align="left">Indicates the memory region accessed. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="aba02af87f77577c725cf73879cabb609"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">MPU_Type::TYPE</td> + </tr> + </table> +</div><div class="memdoc"> +<p>The MPU Type Register indicates how many regions the MPU support. Software can use it to determine if the processor implements an MPU.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[23:16] </td><td align="left">IREGION </td><td align="left">Instruction region. RAZ. Armv7-M only supports a unified MPU. </td></tr> +<tr> +<td align="left">[15:8] </td><td align="left">DREGION </td><td align="left">Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. </td></tr> +<tr> +<td align="left">[7:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">SEPARATE </td><td align="left">Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. </td></tr> +</table> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structMPU__Type.html">MPU_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structMPU__Type.js b/docs/Core/html/structMPU__Type.js new file mode 100644 index 0000000..d66b592 --- /dev/null +++ b/docs/Core/html/structMPU__Type.js @@ -0,0 +1,14 @@ +var structMPU__Type = +[ + [ "CTRL", "structMPU__Type.html#a769178ef949f0d5d8f18ddbd9e4e926f", null ], + [ "RASR", "structMPU__Type.html#a8f00c4a5e31b0a8d103ed3b0732c17a3", null ], + [ "RASR_A1", "structMPU__Type.html#a1658326c6762637eeef8a79bb467445e", null ], + [ "RASR_A2", "structMPU__Type.html#a37131c513d8a8d211b402e5dfda97205", null ], + [ "RASR_A3", "structMPU__Type.html#a7d15172b163797736a6c6b4dcc0fa3dd", null ], + [ "RBAR", "structMPU__Type.html#a990c609b26d990b8ba832b110adfd353", null ], + [ "RBAR_A1", "structMPU__Type.html#af8b510a85b175edfd8dd8cc93e967066", null ], + [ "RBAR_A2", "structMPU__Type.html#a80d534f0dfc080c841e1772c7a68e1a2", null ], + [ "RBAR_A3", "structMPU__Type.html#a207f6e9c3af753367554cc06df300a55", null ], + [ "RNR", "structMPU__Type.html#a2f7a117a12cb661c76edc4765453f05c", null ], + [ "TYPE", "structMPU__Type.html#aba02af87f77577c725cf73879cabb609", null ] +];
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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a 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class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47">ISER</a> [8]</td></tr> +<tr class="memdesc:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) Interrupt Set Enable Register. <a href="#a9fccef5a60a0d5e81fcd7869a6274f47">More...</a><br/></td></tr> +<tr class="separator:a9fccef5a60a0d5e81fcd7869a6274f47"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2de17698945ea49abd58a2d45bdc9c80"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80">RESERVED0</a> [24]</td></tr> +<tr class="memdesc:a2de17698945ea49abd58a2d45bdc9c80"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a2de17698945ea49abd58a2d45bdc9c80">More...</a><br/></td></tr> +<tr class="separator:a2de17698945ea49abd58a2d45bdc9c80"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a245df8bac1da05c39eadabede9323203"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a245df8bac1da05c39eadabede9323203">ICER</a> [8]</td></tr> +<tr class="memdesc:a245df8bac1da05c39eadabede9323203"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Clear Enable Register. <a href="#a245df8bac1da05c39eadabede9323203">More...</a><br/></td></tr> +<tr class="separator:a245df8bac1da05c39eadabede9323203"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">RSERVED1</a> [24]</td></tr> +<tr class="memdesc:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a6d1daf7ab6f2ba83f57ff67ae6f571fe">More...</a><br/></td></tr> +<tr class="separator:a6d1daf7ab6f2ba83f57ff67ae6f571fe"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8f731a9f428efc86e8d311b52ce823d0"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0">ISPR</a> [8]</td></tr> +<tr class="memdesc:a8f731a9f428efc86e8d311b52ce823d0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set Pending Register. <a href="#a8f731a9f428efc86e8d311b52ce823d0">More...</a><br/></td></tr> +<tr class="separator:a8f731a9f428efc86e8d311b52ce823d0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0953af43af8ec7fd5869a1d826ce5b72"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72">RESERVED2</a> [24]</td></tr> +<tr class="memdesc:a0953af43af8ec7fd5869a1d826ce5b72"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a0953af43af8ec7fd5869a1d826ce5b72">More...</a><br/></td></tr> +<tr class="separator:a0953af43af8ec7fd5869a1d826ce5b72"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95">ICPR</a> [8]</td></tr> +<tr class="memdesc:a8d8f45d9c5c67bba3c153c55574bac95"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear Pending Register. <a href="#a8d8f45d9c5c67bba3c153c55574bac95">More...</a><br/></td></tr> +<tr class="separator:a8d8f45d9c5c67bba3c153c55574bac95"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a9dd330835dbf21471e7b5be8692d77ab"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab">RESERVED3</a> [24]</td></tr> +<tr class="memdesc:a9dd330835dbf21471e7b5be8692d77ab"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a9dd330835dbf21471e7b5be8692d77ab">More...</a><br/></td></tr> +<tr class="separator:a9dd330835dbf21471e7b5be8692d77ab"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4bca5452748ba84d64536fb6a5d795af"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af">IABR</a> [8]</td></tr> +<tr class="memdesc:a4bca5452748ba84d64536fb6a5d795af"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Active bit Register. <a href="#a4bca5452748ba84d64536fb6a5d795af">More...</a><br/></td></tr> +<tr class="separator:a4bca5452748ba84d64536fb6a5d795af"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">RESERVED4</a> [56]</td></tr> +<tr class="memdesc:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a5c0e5d507ac3c1bd5cdaaf9bbd177790">More...</a><br/></td></tr> +<tr class="separator:a5c0e5d507ac3c1bd5cdaaf9bbd177790"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7ff7364a4260df67a2784811e8da4efd"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd">IP</a> [240]</td></tr> +<tr class="memdesc:a7ff7364a4260df67a2784811e8da4efd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) <a href="#a7ff7364a4260df67a2784811e8da4efd">More...</a><br/></td></tr> +<tr class="separator:a7ff7364a4260df67a2784811e8da4efd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4f753b4f824270175af045ac99bc12e8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8">RESERVED5</a> [644]</td></tr> +<tr class="memdesc:a4f753b4f824270175af045ac99bc12e8"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a4f753b4f824270175af045ac99bc12e8">More...</a><br/></td></tr> +<tr class="separator:a4f753b4f824270175af045ac99bc12e8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a37de89637466e007171c6b135299bc75"><td class="memItemLeft" align="right" valign="top">__OM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structNVIC__Type.html#a37de89637466e007171c6b135299bc75">STIR</a></td></tr> +<tr class="memdesc:a37de89637466e007171c6b135299bc75"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xE00 ( /W) Software Trigger Interrupt Register. <a href="#a37de89637466e007171c6b135299bc75">More...</a><br/></td></tr> +<tr class="separator:a37de89637466e007171c6b135299bc75"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a4bca5452748ba84d64536fb6a5d795af"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t NVIC_Type::IABR[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a245df8bac1da05c39eadabede9323203"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t NVIC_Type::ICER[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a8d8f45d9c5c67bba3c153c55574bac95"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t NVIC_Type::ICPR[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a7ff7364a4260df67a2784811e8da4efd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint8_t NVIC_Type::IP[240]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a9fccef5a60a0d5e81fcd7869a6274f47"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t NVIC_Type::ISER[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a8f731a9f428efc86e8d311b52ce823d0"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t NVIC_Type::ISPR[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2de17698945ea49abd58a2d45bdc9c80"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RESERVED0[24]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0953af43af8ec7fd5869a1d826ce5b72"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RESERVED2[24]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a9dd330835dbf21471e7b5be8692d77ab"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RESERVED3[24]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a5c0e5d507ac3c1bd5cdaaf9bbd177790"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RESERVED4[56]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4f753b4f824270175af045ac99bc12e8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RESERVED5[644]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a6d1daf7ab6f2ba83f57ff67ae6f571fe"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t NVIC_Type::RSERVED1[24]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a37de89637466e007171c6b135299bc75"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__OM uint32_t NVIC_Type::STIR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structNVIC__Type.html">NVIC_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structNVIC__Type.js b/docs/Core/html/structNVIC__Type.js new file mode 100644 index 0000000..8ba5410 --- /dev/null +++ b/docs/Core/html/structNVIC__Type.js @@ -0,0 +1,16 @@ +var structNVIC__Type = +[ + [ "IABR", "structNVIC__Type.html#a4bca5452748ba84d64536fb6a5d795af", null ], + [ "ICER", "structNVIC__Type.html#a245df8bac1da05c39eadabede9323203", null ], + [ "ICPR", "structNVIC__Type.html#a8d8f45d9c5c67bba3c153c55574bac95", null ], + [ "IP", "structNVIC__Type.html#a7ff7364a4260df67a2784811e8da4efd", null ], + [ "ISER", "structNVIC__Type.html#a9fccef5a60a0d5e81fcd7869a6274f47", null ], + [ "ISPR", "structNVIC__Type.html#a8f731a9f428efc86e8d311b52ce823d0", null ], + [ "RESERVED0", "structNVIC__Type.html#a2de17698945ea49abd58a2d45bdc9c80", null ], + [ "RESERVED2", "structNVIC__Type.html#a0953af43af8ec7fd5869a1d826ce5b72", null ], + [ "RESERVED3", "structNVIC__Type.html#a9dd330835dbf21471e7b5be8692d77ab", null ], + [ "RESERVED4", "structNVIC__Type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790", null ], + [ "RESERVED5", "structNVIC__Type.html#a4f753b4f824270175af045ac99bc12e8", null ], + [ "RSERVED1", "structNVIC__Type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe", null ], + [ "STIR", "structNVIC__Type.html#a37de89637466e007171c6b135299bc75", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structSCB__Type.html b/docs/Core/html/structSCB__Type.html new file mode 100644 index 0000000..c3facb9 --- /dev/null +++ b/docs/Core/html/structSCB__Type.html @@ -0,0 +1,460 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SCB_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): SCB_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">SCB_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the System Control Block (SCB). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a21e08d546d8b641bee298a459ea73e46"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46">CPUID</a></td></tr> +<tr class="memdesc:a21e08d546d8b641bee298a459ea73e46"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) CPUID Base Register. <a href="#a21e08d546d8b641bee298a459ea73e46">More...</a><br/></td></tr> +<tr class="separator:a21e08d546d8b641bee298a459ea73e46"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">ICSR</a></td></tr> +<tr class="memdesc:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Control and State Register. <a href="#a0ca18ef984d132c6bf4d9b61cd00f05a">More...</a><br/></td></tr> +<tr class="separator:a0ca18ef984d132c6bf4d9b61cd00f05a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a187a4578e920544ed967f98020fb8170"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a187a4578e920544ed967f98020fb8170">VTOR</a></td></tr> +<tr class="memdesc:a187a4578e920544ed967f98020fb8170"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Vector Table Offset Register. <a href="#a187a4578e920544ed967f98020fb8170">More...</a><br/></td></tr> +<tr class="separator:a187a4578e920544ed967f98020fb8170"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ad3e5b8934c647eb1b7383c1894f01380"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380">AIRCR</a></td></tr> +<tr class="memdesc:ad3e5b8934c647eb1b7383c1894f01380"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/W) Application Interrupt and Reset Control Register. <a href="#ad3e5b8934c647eb1b7383c1894f01380">More...</a><br/></td></tr> +<tr class="separator:ad3e5b8934c647eb1b7383c1894f01380"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCR</a></td></tr> +<tr class="memdesc:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) System Control Register. <a href="#a3a4840c6fa4d1ee75544f4032c88ec34">More...</a><br/></td></tr> +<tr class="separator:a3a4840c6fa4d1ee75544f4032c88ec34"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2d6653b0b70faac936046a02809b577f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d6653b0b70faac936046a02809b577f">CCR</a></td></tr> +<tr class="memdesc:a2d6653b0b70faac936046a02809b577f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/W) Configuration Control Register. <a href="#a2d6653b0b70faac936046a02809b577f">More...</a><br/></td></tr> +<tr class="separator:a2d6653b0b70faac936046a02809b577f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a85768f4b3dbbc41fd760041ee1202162"><td class="memItemLeft" align="right" valign="top">__IOM uint8_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162">SHP</a> [12]</td></tr> +<tr class="memdesc:a85768f4b3dbbc41fd760041ee1202162"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) <a href="#a85768f4b3dbbc41fd760041ee1202162">More...</a><br/></td></tr> +<tr class="separator:a85768f4b3dbbc41fd760041ee1202162"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7b5ae9741a99808043394c4743b635c4"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4">SHCSR</a></td></tr> +<tr class="memdesc:a7b5ae9741a99808043394c4743b635c4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 (R/W) System Handler Control and State Register. <a href="#a7b5ae9741a99808043394c4743b635c4">More...</a><br/></td></tr> +<tr class="separator:a7b5ae9741a99808043394c4743b635c4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0cda9e061b42373383418663092ad19a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a0cda9e061b42373383418663092ad19a">CFSR</a></td></tr> +<tr class="memdesc:a0cda9e061b42373383418663092ad19a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/W) Configurable Fault Status Register. <a href="#a0cda9e061b42373383418663092ad19a">More...</a><br/></td></tr> +<tr class="separator:a0cda9e061b42373383418663092ad19a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a14ad254659362b9752c69afe3fd80934"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a14ad254659362b9752c69afe3fd80934">HFSR</a></td></tr> +<tr class="memdesc:a14ad254659362b9752c69afe3fd80934"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) HardFault Status Register. <a href="#a14ad254659362b9752c69afe3fd80934">More...</a><br/></td></tr> +<tr class="separator:a14ad254659362b9752c69afe3fd80934"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a191579bde0d21ff51d30a714fd887033"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a191579bde0d21ff51d30a714fd887033">DFSR</a></td></tr> +<tr class="memdesc:a191579bde0d21ff51d30a714fd887033"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x030 (R/W) Debug Fault Status Register. <a href="#a191579bde0d21ff51d30a714fd887033">More...</a><br/></td></tr> +<tr class="separator:a191579bde0d21ff51d30a714fd887033"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80">MMFAR</a></td></tr> +<tr class="memdesc:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x034 (R/W) MemManage Fault Address Register. <a href="#a2d03d0b7cec2254f39eb1c46c7445e80">More...</a><br/></td></tr> +<tr class="separator:a2d03d0b7cec2254f39eb1c46c7445e80"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c">BFAR</a></td></tr> +<tr class="memdesc:a3f8e7e58be4e41c88dfa78f54589271c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x038 (R/W) BusFault Address Register. <a href="#a3f8e7e58be4e41c88dfa78f54589271c">More...</a><br/></td></tr> +<tr class="separator:a3f8e7e58be4e41c88dfa78f54589271c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ab65372404ce64b0f0b35e2709429404e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e">AFSR</a></td></tr> +<tr class="memdesc:ab65372404ce64b0f0b35e2709429404e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x03C (R/W) Auxiliary Fault Status Register. <a href="#ab65372404ce64b0f0b35e2709429404e">More...</a><br/></td></tr> +<tr class="separator:ab65372404ce64b0f0b35e2709429404e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a681c9d9e518b217976bef38c2423d83d"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d">PFR</a> [2]</td></tr> +<tr class="memdesc:a681c9d9e518b217976bef38c2423d83d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x040 (R/ ) Processor Feature Register. <a href="#a681c9d9e518b217976bef38c2423d83d">More...</a><br/></td></tr> +<tr class="separator:a681c9d9e518b217976bef38c2423d83d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004">DFR</a></td></tr> +<tr class="memdesc:a85dd6fe77aab17e7ea89a52c59da6004"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x048 (R/ ) Debug Feature Register. <a href="#a85dd6fe77aab17e7ea89a52c59da6004">More...</a><br/></td></tr> +<tr class="separator:a85dd6fe77aab17e7ea89a52c59da6004"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af084e1b2dad004a88668efea1dfe7fa1"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1">ADR</a></td></tr> +<tr class="memdesc:af084e1b2dad004a88668efea1dfe7fa1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04C (R/ ) Auxiliary Feature Register. <a href="#af084e1b2dad004a88668efea1dfe7fa1">More...</a><br/></td></tr> +<tr class="separator:af084e1b2dad004a88668efea1dfe7fa1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa11887804412bda283cc85a83fdafa7c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c">MMFR</a> [4]</td></tr> +<tr class="memdesc:aa11887804412bda283cc85a83fdafa7c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x050 (R/ ) Memory Model Feature Register. <a href="#aa11887804412bda283cc85a83fdafa7c">More...</a><br/></td></tr> +<tr class="separator:aa11887804412bda283cc85a83fdafa7c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066">ISAR</a> [5]</td></tr> +<tr class="memdesc:ae0136a2d2d3c45f016b2c449e92b2066"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x060 (R/ ) Instruction Set Attributes Register. <a href="#ae0136a2d2d3c45f016b2c449e92b2066">More...</a><br/></td></tr> +<tr class="separator:ae0136a2d2d3c45f016b2c449e92b2066"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6">RESERVED0</a> [5]</td></tr> +<tr class="memdesc:ac89a5d9901e3748d22a7090bfca2bee6"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac89a5d9901e3748d22a7090bfca2bee6">More...</a><br/></td></tr> +<tr class="separator:ac89a5d9901e3748d22a7090bfca2bee6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764">CPACR</a></td></tr> +<tr class="memdesc:ac6a860c1b8d8154a1f00d99d23b67764"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x088 (R/W) Coprocessor Access Control Register. <a href="#ac6a860c1b8d8154a1f00d99d23b67764">More...</a><br/></td></tr> +<tr class="separator:ac6a860c1b8d8154a1f00d99d23b67764"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="af084e1b2dad004a88668efea1dfe7fa1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::ADR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ab65372404ce64b0f0b35e2709429404e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::AFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ad3e5b8934c647eb1b7383c1894f01380"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::AIRCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3f8e7e58be4e41c88dfa78f54589271c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::BFAR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2d6653b0b70faac936046a02809b577f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0cda9e061b42373383418663092ad19a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ac6a860c1b8d8154a1f00d99d23b67764"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::CPACR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a21e08d546d8b641bee298a459ea73e46"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::CPUID</td> + </tr> + </table> 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class="memname">__IOM uint32_t SCB_Type::ICSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ae0136a2d2d3c45f016b2c449e92b2066"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::ISAR[5]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a2d03d0b7cec2254f39eb1c46c7445e80"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCB_Type::MMFAR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="aa11887804412bda283cc85a83fdafa7c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCB_Type::MMFR[4]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a681c9d9e518b217976bef38c2423d83d"></a> +<div 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All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structSCB__Type.js b/docs/Core/html/structSCB__Type.js new file mode 100644 index 0000000..a0ae15a --- /dev/null +++ b/docs/Core/html/structSCB__Type.js @@ -0,0 +1,24 @@ +var structSCB__Type = +[ + [ "ADR", "structSCB__Type.html#af084e1b2dad004a88668efea1dfe7fa1", null ], + [ "AFSR", "structSCB__Type.html#ab65372404ce64b0f0b35e2709429404e", null ], + [ "AIRCR", "structSCB__Type.html#ad3e5b8934c647eb1b7383c1894f01380", null ], + [ "BFAR", "structSCB__Type.html#a3f8e7e58be4e41c88dfa78f54589271c", null ], + [ "CCR", "structSCB__Type.html#a2d6653b0b70faac936046a02809b577f", null ], + [ "CFSR", "structSCB__Type.html#a0cda9e061b42373383418663092ad19a", null ], + [ "CPACR", "structSCB__Type.html#ac6a860c1b8d8154a1f00d99d23b67764", null ], + [ "CPUID", "structSCB__Type.html#a21e08d546d8b641bee298a459ea73e46", null ], + [ "DFR", "structSCB__Type.html#a85dd6fe77aab17e7ea89a52c59da6004", null ], + [ "DFSR", "structSCB__Type.html#a191579bde0d21ff51d30a714fd887033", null ], + [ "HFSR", "structSCB__Type.html#a14ad254659362b9752c69afe3fd80934", null ], + [ "ICSR", "structSCB__Type.html#a0ca18ef984d132c6bf4d9b61cd00f05a", null ], + [ "ISAR", "structSCB__Type.html#ae0136a2d2d3c45f016b2c449e92b2066", null ], + [ "MMFAR", "structSCB__Type.html#a2d03d0b7cec2254f39eb1c46c7445e80", null ], + [ "MMFR", "structSCB__Type.html#aa11887804412bda283cc85a83fdafa7c", null ], + [ "PFR", "structSCB__Type.html#a681c9d9e518b217976bef38c2423d83d", null ], + [ "RESERVED0", "structSCB__Type.html#ac89a5d9901e3748d22a7090bfca2bee6", null ], + [ "SCR", "structSCB__Type.html#a3a4840c6fa4d1ee75544f4032c88ec34", null ], + [ "SHCSR", "structSCB__Type.html#a7b5ae9741a99808043394c4743b635c4", null ], + [ "SHP", "structSCB__Type.html#a85768f4b3dbbc41fd760041ee1202162", null ], + [ "VTOR", "structSCB__Type.html#a187a4578e920544ed967f98020fb8170", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structSCnSCB__Type.html b/docs/Core/html/structSCnSCB__Type.html new file mode 100644 index 0000000..b6587c7 --- /dev/null +++ b/docs/Core/html/structSCnSCB__Type.html @@ -0,0 +1,190 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SCnSCB_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): SCnSCB_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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</td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" 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options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">SCnSCB_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the System Control and ID Register not in the SCB. +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:afe1d5fd2966d5062716613b05c8d0ae1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1">RESERVED0</a> [1]</td></tr> +<tr class="memdesc:afe1d5fd2966d5062716613b05c8d0ae1"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#afe1d5fd2966d5062716613b05c8d0ae1">More...</a><br/></td></tr> +<tr class="separator:afe1d5fd2966d5062716613b05c8d0ae1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a34ec1d771245eb9bd0e3ec9336949762"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762">ICTR</a></td></tr> +<tr class="memdesc:a34ec1d771245eb9bd0e3ec9336949762"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register. <a href="#a34ec1d771245eb9bd0e3ec9336949762">More...</a><br/></td></tr> +<tr class="separator:a34ec1d771245eb9bd0e3ec9336949762"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a13af9b718dde7481f1c0344f00593c23"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23">ACTLR</a></td></tr> +<tr class="memdesc:a13af9b718dde7481f1c0344f00593c23"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Auxiliary Control Register. <a href="#a13af9b718dde7481f1c0344f00593c23">More...</a><br/></td></tr> +<tr class="separator:a13af9b718dde7481f1c0344f00593c23"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a13af9b718dde7481f1c0344f00593c23"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SCnSCB_Type::ACTLR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a34ec1d771245eb9bd0e3ec9336949762"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SCnSCB_Type::ICTR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="afe1d5fd2966d5062716613b05c8d0ae1"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t SCnSCB_Type::RESERVED0[1]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structSCnSCB__Type.html">SCnSCB_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structSCnSCB__Type.js b/docs/Core/html/structSCnSCB__Type.js new file mode 100644 index 0000000..cb2bdd0 --- /dev/null +++ b/docs/Core/html/structSCnSCB__Type.js @@ -0,0 +1,6 @@ +var structSCnSCB__Type = +[ + [ "ACTLR", "structSCnSCB__Type.html#a13af9b718dde7481f1c0344f00593c23", null ], + [ "ICTR", "structSCnSCB__Type.html#a34ec1d771245eb9bd0e3ec9336949762", null ], + [ "RESERVED0", "structSCnSCB__Type.html#afe1d5fd2966d5062716613b05c8d0ae1", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structSysTick__Type.html b/docs/Core/html/structSysTick__Type.html new file mode 100644 index 0000000..bcd0dbf --- /dev/null +++ b/docs/Core/html/structSysTick__Type.html @@ -0,0 +1,205 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>SysTick_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): SysTick_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" 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</td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" 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options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">SysTick_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the System Timer (SysTick). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e">CTRL</a></td></tr> +<tr class="memdesc:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) SysTick Control and Status Register. <a href="#a875e7afa5c4fd43997fb544a4ac6e37e">More...</a><br/></td></tr> +<tr class="separator:a875e7afa5c4fd43997fb544a4ac6e37e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4780a489256bb9f54d0ba8ed4de191cd"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd">LOAD</a></td></tr> +<tr class="memdesc:a4780a489256bb9f54d0ba8ed4de191cd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) SysTick Reload Value Register. <a href="#a4780a489256bb9f54d0ba8ed4de191cd">More...</a><br/></td></tr> +<tr class="separator:a4780a489256bb9f54d0ba8ed4de191cd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a9b5420d17e8e43104ddd4ae5a610af93"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93">VAL</a></td></tr> +<tr class="memdesc:a9b5420d17e8e43104ddd4ae5a610af93"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) SysTick Current Value Register. <a href="#a9b5420d17e8e43104ddd4ae5a610af93">More...</a><br/></td></tr> +<tr class="separator:a9b5420d17e8e43104ddd4ae5a610af93"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:afcadb0c6d35b21cdc0018658a13942de"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de">CALIB</a></td></tr> +<tr class="memdesc:afcadb0c6d35b21cdc0018658a13942de"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/ ) SysTick Calibration Register. <a href="#afcadb0c6d35b21cdc0018658a13942de">More...</a><br/></td></tr> +<tr class="separator:afcadb0c6d35b21cdc0018658a13942de"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="afcadb0c6d35b21cdc0018658a13942de"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t SysTick_Type::CALIB</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a875e7afa5c4fd43997fb544a4ac6e37e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SysTick_Type::CTRL</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4780a489256bb9f54d0ba8ed4de191cd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SysTick_Type::LOAD</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a9b5420d17e8e43104ddd4ae5a610af93"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t SysTick_Type::VAL</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structSysTick__Type.html">SysTick_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structSysTick__Type.js b/docs/Core/html/structSysTick__Type.js new file mode 100644 index 0000000..3827439 --- /dev/null +++ b/docs/Core/html/structSysTick__Type.js @@ -0,0 +1,7 @@ +var structSysTick__Type = +[ + [ "CALIB", "structSysTick__Type.html#afcadb0c6d35b21cdc0018658a13942de", null ], + [ "CTRL", "structSysTick__Type.html#a875e7afa5c4fd43997fb544a4ac6e37e", null ], + [ "LOAD", "structSysTick__Type.html#a4780a489256bb9f54d0ba8ed4de191cd", null ], + [ "VAL", "structSysTick__Type.html#a9b5420d17e8e43104ddd4ae5a610af93", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/structTPI__Type.html b/docs/Core/html/structTPI__Type.html new file mode 100644 index 0000000..b5cf052 --- /dev/null +++ b/docs/Core/html/structTPI__Type.html @@ -0,0 +1,505 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>TPI_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-M): TPI_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">TPI_Type Struct Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the Trace Port Interface Register (TPI). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a7b72598e20066133e505bb781690dc22"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a7b72598e20066133e505bb781690dc22">SSPSR</a></td></tr> +<tr class="memdesc:a7b72598e20066133e505bb781690dc22"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/ ) Supported Parallel Port Size Register. <a href="#a7b72598e20066133e505bb781690dc22">More...</a><br/></td></tr> +<tr class="separator:a7b72598e20066133e505bb781690dc22"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8826aa84e5806053395a742d38d59d0f"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f">CSPSR</a></td></tr> +<tr class="memdesc:a8826aa84e5806053395a742d38d59d0f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Current Parallel Port Size Register. <a href="#a8826aa84e5806053395a742d38d59d0f">More...</a><br/></td></tr> +<tr class="separator:a8826aa84e5806053395a742d38d59d0f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">RESERVED0</a> [2]</td></tr> +<tr class="memdesc:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#af143c5e8fc9a3b2be2878e9c1f331aa9">More...</a><br/></td></tr> +<tr class="separator:af143c5e8fc9a3b2be2878e9c1f331aa9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">ACPR</a></td></tr> +<tr class="memdesc:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register. <a href="#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">More...</a><br/></td></tr> +<tr class="separator:a9e5e4421ef9c3d5b7ff8b24abd4e99b3"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac3956fe93987b725d89d3be32738da12"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ac3956fe93987b725d89d3be32738da12">RESERVED1</a> [55]</td></tr> +<tr class="memdesc:ac3956fe93987b725d89d3be32738da12"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac3956fe93987b725d89d3be32738da12">More...</a><br/></td></tr> +<tr class="separator:ac3956fe93987b725d89d3be32738da12"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5">SPPR</a></td></tr> +<tr class="memdesc:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0F0 (R/W) Selected Pin Protocol Register. <a href="#a12f79d4e3ddc69893ba8bff890d04cc5">More...</a><br/></td></tr> +<tr class="separator:a12f79d4e3ddc69893ba8bff890d04cc5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac7bbb92e6231b9b38ac483f7d161a096"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ac7bbb92e6231b9b38ac483f7d161a096">RESERVED2</a> [131]</td></tr> +<tr class="memdesc:ac7bbb92e6231b9b38ac483f7d161a096"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#ac7bbb92e6231b9b38ac483f7d161a096">More...</a><br/></td></tr> +<tr class="separator:ac7bbb92e6231b9b38ac483f7d161a096"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c">FFSR</a></td></tr> +<tr class="memdesc:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x300 (R/ ) Formatter and Flush Status Register. <a href="#a6c47a0b4c7ffc66093ef993d36bb441c">More...</a><br/></td></tr> +<tr class="separator:a6c47a0b4c7ffc66093ef993d36bb441c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3f68b6e73561b4849ebf953a894df8d2"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2">FFCR</a></td></tr> +<tr class="memdesc:a3f68b6e73561b4849ebf953a894df8d2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x304 (R/W) Formatter and Flush Control Register. <a href="#a3f68b6e73561b4849ebf953a894df8d2">More...</a><br/></td></tr> +<tr class="separator:a3f68b6e73561b4849ebf953a894df8d2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8">FSCR</a></td></tr> +<tr class="memdesc:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x308 (R/ ) Formatter Synchronization Counter Register. <a href="#ad6901bfd8a0089ca7e8a20475cf494a8">More...</a><br/></td></tr> +<tr class="separator:ad6901bfd8a0089ca7e8a20475cf494a8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a31700c8cdd26e4c094db72af33d9f24c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a31700c8cdd26e4c094db72af33d9f24c">RESERVED3</a> [759]</td></tr> +<tr class="memdesc:a31700c8cdd26e4c094db72af33d9f24c"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a31700c8cdd26e4c094db72af33d9f24c">More...</a><br/></td></tr> +<tr class="separator:a31700c8cdd26e4c094db72af33d9f24c"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4d4cd2357f72333a82a1313228287bbd"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd">TRIGGER</a></td></tr> +<tr class="memdesc:a4d4cd2357f72333a82a1313228287bbd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEE8 (R/ ) TRIGGER. <a href="#a4d4cd2357f72333a82a1313228287bbd">More...</a><br/></td></tr> +<tr class="separator:a4d4cd2357f72333a82a1313228287bbd"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">FIFO0</a></td></tr> +<tr class="memdesc:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEEC (R/ ) Integration ETM Data. <a href="#aa4d7b5cf39dff9f53bf7f69bc287a814">More...</a><br/></td></tr> +<tr class="separator:aa4d7b5cf39dff9f53bf7f69bc287a814"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ab358319b969d3fed0f89bbe33e9f1652"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652">ITATBCTR2</a></td></tr> +<tr class="memdesc:ab358319b969d3fed0f89bbe33e9f1652"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF0 (R/ ) ITATBCTR2. <a href="#ab358319b969d3fed0f89bbe33e9f1652">More...</a><br/></td></tr> +<tr class="separator:ab358319b969d3fed0f89bbe33e9f1652"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a684071216fafee4e80be6aaa932cec46"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a684071216fafee4e80be6aaa932cec46">RESERVED4</a> [1]</td></tr> +<tr class="memdesc:a684071216fafee4e80be6aaa932cec46"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a684071216fafee4e80be6aaa932cec46">More...</a><br/></td></tr> +<tr class="separator:a684071216fafee4e80be6aaa932cec46"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aaa573b2e073e76e93c51ecec79c616d0"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0">ITATBCTR0</a></td></tr> +<tr class="memdesc:aaa573b2e073e76e93c51ecec79c616d0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEF8 (R/ ) ITATBCTR0. <a href="#aaa573b2e073e76e93c51ecec79c616d0">More...</a><br/></td></tr> +<tr class="separator:aaa573b2e073e76e93c51ecec79c616d0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a061372fcd72f1eea871e2d9c1be849bc"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc">FIFO1</a></td></tr> +<tr class="memdesc:a061372fcd72f1eea871e2d9c1be849bc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xEFC (R/ ) Integration ITM Data. <a href="#a061372fcd72f1eea871e2d9c1be849bc">More...</a><br/></td></tr> +<tr class="separator:a061372fcd72f1eea871e2d9c1be849bc"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aaa4c823c10f115f7517c82ef86a5a68d"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d">ITCTRL</a></td></tr> +<tr class="memdesc:aaa4c823c10f115f7517c82ef86a5a68d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xF00 (R/W) Integration Mode Control. <a href="#aaa4c823c10f115f7517c82ef86a5a68d">More...</a><br/></td></tr> +<tr class="separator:aaa4c823c10f115f7517c82ef86a5a68d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3f80dd93f6bab6524603a7aa58de9a30"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a3f80dd93f6bab6524603a7aa58de9a30">RESERVED5</a> [39]</td></tr> +<tr class="memdesc:a3f80dd93f6bab6524603a7aa58de9a30"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a3f80dd93f6bab6524603a7aa58de9a30">More...</a><br/></td></tr> +<tr class="separator:a3f80dd93f6bab6524603a7aa58de9a30"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a">CLAIMSET</a></td></tr> +<tr class="memdesc:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA0 (R/W) Claim tag set. <a href="#af8b7d15fa5252b733dd4b11fa1b5730a">More...</a><br/></td></tr> +<tr class="separator:af8b7d15fa5252b733dd4b11fa1b5730a"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0e10e292cb019a832b03ddd055b2f6ac"><td class="memItemLeft" align="right" valign="top">__IOM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac">CLAIMCLR</a></td></tr> +<tr class="memdesc:a0e10e292cb019a832b03ddd055b2f6ac"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFA4 (R/W) Claim tag clear. <a href="#a0e10e292cb019a832b03ddd055b2f6ac">More...</a><br/></td></tr> +<tr class="separator:a0e10e292cb019a832b03ddd055b2f6ac"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a476ca23fbc9480f1697fbec871130550"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#a476ca23fbc9480f1697fbec871130550">RESERVED7</a> [8]</td></tr> +<tr class="memdesc:a476ca23fbc9480f1697fbec871130550"><td class="mdescLeft"> </td><td class="mdescRight">Reserved. <a href="#a476ca23fbc9480f1697fbec871130550">More...</a><br/></td></tr> +<tr class="separator:a476ca23fbc9480f1697fbec871130550"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:abc0ecda8a5446bc754080276bad77514"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#abc0ecda8a5446bc754080276bad77514">DEVID</a></td></tr> +<tr class="memdesc:abc0ecda8a5446bc754080276bad77514"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFC8 (R/ ) TPIU_DEVID. <a href="#abc0ecda8a5446bc754080276bad77514">More...</a><br/></td></tr> +<tr class="separator:abc0ecda8a5446bc754080276bad77514"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ad98855854a719bbea33061e71529a472"><td class="memItemLeft" align="right" valign="top">__IM uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structTPI__Type.html#ad98855854a719bbea33061e71529a472">DEVTYPE</a></td></tr> +<tr class="memdesc:ad98855854a719bbea33061e71529a472"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0xFCC (R/ ) TPIU_DEVTYPE. <a href="#ad98855854a719bbea33061e71529a472">More...</a><br/></td></tr> +<tr class="separator:ad98855854a719bbea33061e71529a472"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a9e5e4421ef9c3d5b7ff8b24abd4e99b3"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::ACPR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a0e10e292cb019a832b03ddd055b2f6ac"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::CLAIMCLR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="af8b7d15fa5252b733dd4b11fa1b5730a"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::CLAIMSET</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a8826aa84e5806053395a742d38d59d0f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::CSPSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="abc0ecda8a5446bc754080276bad77514"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t TPI_Type::DEVID</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ad98855854a719bbea33061e71529a472"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t TPI_Type::DEVTYPE</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3f68b6e73561b4849ebf953a894df8d2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::FFCR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a6c47a0b4c7ffc66093ef993d36bb441c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t TPI_Type::FFSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="aa4d7b5cf39dff9f53bf7f69bc287a814"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t TPI_Type::FIFO0</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a061372fcd72f1eea871e2d9c1be849bc"></a> +<div class="memitem"> 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</table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a31700c8cdd26e4c094db72af33d9f24c"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TPI_Type::RESERVED3[759]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a684071216fafee4e80be6aaa932cec46"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TPI_Type::RESERVED4[1]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a3f80dd93f6bab6524603a7aa58de9a30"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TPI_Type::RESERVED5[39]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a476ca23fbc9480f1697fbec871130550"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t TPI_Type::RESERVED7[8]</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a12f79d4e3ddc69893ba8bff890d04cc5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::SPPR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a7b72598e20066133e505bb781690dc22"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IOM uint32_t TPI_Type::SSPSR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4d4cd2357f72333a82a1313228287bbd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">__IM uint32_t TPI_Type::TRIGGER</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structTPI__Type.html">TPI_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/structTPI__Type.js b/docs/Core/html/structTPI__Type.js new file mode 100644 index 0000000..49365fe --- /dev/null +++ b/docs/Core/html/structTPI__Type.js @@ -0,0 +1,27 @@ +var structTPI__Type = +[ + [ "ACPR", "structTPI__Type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3", null ], + [ "CLAIMCLR", "structTPI__Type.html#a0e10e292cb019a832b03ddd055b2f6ac", null ], + [ "CLAIMSET", "structTPI__Type.html#af8b7d15fa5252b733dd4b11fa1b5730a", null ], + [ "CSPSR", "structTPI__Type.html#a8826aa84e5806053395a742d38d59d0f", null ], + [ "DEVID", "structTPI__Type.html#abc0ecda8a5446bc754080276bad77514", null ], + [ "DEVTYPE", "structTPI__Type.html#ad98855854a719bbea33061e71529a472", null ], + [ "FFCR", "structTPI__Type.html#a3f68b6e73561b4849ebf953a894df8d2", null ], + [ "FFSR", "structTPI__Type.html#a6c47a0b4c7ffc66093ef993d36bb441c", null ], + [ "FIFO0", "structTPI__Type.html#aa4d7b5cf39dff9f53bf7f69bc287a814", null ], + [ "FIFO1", "structTPI__Type.html#a061372fcd72f1eea871e2d9c1be849bc", null ], + [ "FSCR", "structTPI__Type.html#ad6901bfd8a0089ca7e8a20475cf494a8", null ], + [ "ITATBCTR0", "structTPI__Type.html#aaa573b2e073e76e93c51ecec79c616d0", null ], + [ "ITATBCTR2", "structTPI__Type.html#ab358319b969d3fed0f89bbe33e9f1652", null ], + [ "ITCTRL", "structTPI__Type.html#aaa4c823c10f115f7517c82ef86a5a68d", null ], + [ "RESERVED0", "structTPI__Type.html#af143c5e8fc9a3b2be2878e9c1f331aa9", null ], + [ "RESERVED1", "structTPI__Type.html#ac3956fe93987b725d89d3be32738da12", null ], + [ "RESERVED2", "structTPI__Type.html#ac7bbb92e6231b9b38ac483f7d161a096", null ], + [ "RESERVED3", "structTPI__Type.html#a31700c8cdd26e4c094db72af33d9f24c", null ], + [ "RESERVED4", "structTPI__Type.html#a684071216fafee4e80be6aaa932cec46", null ], + [ "RESERVED5", "structTPI__Type.html#a3f80dd93f6bab6524603a7aa58de9a30", null ], + [ "RESERVED7", "structTPI__Type.html#a476ca23fbc9480f1697fbec871130550", null ], + [ "SPPR", "structTPI__Type.html#a12f79d4e3ddc69893ba8bff890d04cc5", null ], + [ "SSPSR", "structTPI__Type.html#a7b72598e20066133e505bb781690dc22", null ], + [ "TRIGGER", "structTPI__Type.html#a4d4cd2357f72333a82a1313228287bbd", null ] +];
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These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings.</p> +<p>For devices with external memory BUS the system_<device>.c also configures the BUS system.</p> +<p>The silicon vendor might expose other functions (i.e. for power configuration) in the system_<device>.c file. In case of additional features the function prototypes need to be added to the system_<device>.h header file.</p> +<h1><a class="anchor" id="system_Device_sec"></a> +system_Device.c Template File</h1> +<p>The <a class="el" href="system_c_pg.html#system_Device_sec">system_Device.c Template File</a> for the Cortex-M3 is shown below.</p> +<pre class="fragment">/**************************************************************************//** + * @file system_<Device>.c + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Source File for + * Device <Device> + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <stdint.h> +#include "<Device>.h" + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +/* ToDo: add here your necessary defines for device initialization + following is an example for different system frequencies */ +#define XTAL (12000000U) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5 * XTAL) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +/* ToDo: initialize SystemCoreClock with the system core clock frequency value + achieved after system intitialization. + This means system core clock frequency after call to SystemInit() */ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Clock Frequency (Core Clock)*/ + + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ +/* ToDo: add code to calculate the system frequency based upon the current + register settings. + This function can be used to retrieve the system core clock frequeny + after user changed register sittings. */ + SystemCoreClock = SYSTEM_CLOCK; +} + +void SystemInit (void) +{ +/* ToDo: add code to initialize the system + do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + SystemCoreClock = SYSTEM_CLOCK; +} +</pre><h1><a class="anchor" id="system_Device_h_sec"></a> +system_Device.h Template File</h1> +<p>The system_<device>.h header file contains prototypes to access the public functions in the system_<device>.c file. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> is shown below.</p> +<pre class="fragment">/**************************************************************************//** + * @file system_<Device>.h + * @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for + * Device <Device> + * @version V5.00 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_<Device>_H /* ToDo: replace '<Device>' with your device name */ +#define SYSTEM_<Device>_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_<Device>_H */ +</pre> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/tab_a.png b/docs/Core/html/tab_a.png Binary files differnew file mode 100644 index 0000000..fffadc1 --- /dev/null +++ b/docs/Core/html/tab_a.png diff --git a/docs/Core/html/tab_b.png b/docs/Core/html/tab_b.png Binary files differnew file mode 100644 index 0000000..b7ce1af --- /dev/null +++ b/docs/Core/html/tab_b.png diff --git a/docs/Core/html/tab_h.png b/docs/Core/html/tab_h.png Binary files differnew file mode 100644 index 0000000..5e9188f --- /dev/null +++ b/docs/Core/html/tab_h.png diff --git a/docs/Core/html/tab_s.png b/docs/Core/html/tab_s.png Binary files differnew file mode 100644 index 0000000..956e1c2 --- /dev/null +++ b/docs/Core/html/tab_s.png diff --git a/docs/Core/html/tab_topnav.png b/docs/Core/html/tab_topnav.png Binary files differnew file mode 100644 index 0000000..b257b77 --- /dev/null +++ b/docs/Core/html/tab_topnav.png diff --git a/docs/Core/html/tabs.css b/docs/Core/html/tabs.css new file mode 100644 index 0000000..ffbab50 --- /dev/null +++ b/docs/Core/html/tabs.css @@ -0,0 +1,71 @@ +.tabs, .tabs1, .tabs2, .tabs3 { + background-image: url('tab_b.png'); + width: 100%; + z-index: 101; + font-size: 10px; +} + +.tabs1 { + background-image: url('tab_topnav.png'); + font-size: 12px; +} + +.tabs2 { + font-size: 10px; +} +.tabs3 { + font-size: 9px; +} + +.tablist { + margin: 0; + padding: 0; + display: table; + line-height: 24px; +} + +.tablist li { + float: left; + display: table-cell; + background-image: url('tab_b.png'); + list-style: none; +} + +.tabs1 .tablist li { + float: left; + display: table-cell; + background-image: url('tab_topnav.png'); + list-style: none; +} + +.tablist a { + display: block; + padding: 0 20px; + font-weight: bold; + background-image:url('tab_s.png'); + background-repeat:no-repeat; + background-position:right; + color: #283A5D; + text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9); + text-decoration: none; + outline: none; +} + +.tabs3 .tablist a { + padding: 0 10px; +} + +.tablist a:hover { + background-image: url('tab_h.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); + text-decoration: none; +} + +.tablist li.current a { + background-image: url('tab_a.png'); + background-repeat:repeat-x; + color: #fff; + text-shadow: 0px 1px 1px rgba(0, 0, 0, 1.0); +} diff --git a/docs/Core/html/templates_pg.html b/docs/Core/html/templates_pg.html new file mode 100644 index 0000000..41927d4 --- /dev/null +++ b/docs/Core/html/templates_pg.html @@ -0,0 +1,275 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>CMSIS-Core Device Templates</title> +<title>CMSIS-Core (Cortex-M): CMSIS-Core Device Templates</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('templates_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">CMSIS-Core Device Templates </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>Arm supplies CMSIS-Core device template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of <a class="el" href="index.html#tested_tools_sec">Tested and Verified Toolchains</a> for compliance.</p> +<p>These CMSIS-Core device template files include the following:</p> +<ul> +<li>Register names of the Core Peripherals and names of the Core Exception Vectors.</li> +<li>Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)</li> +<li>Generic startup code and system configuration code.</li> +</ul> +<p>The detailed file structure of the CMSIS-Core device templates is shown in the following picture.</p> +<div class="image"> +<img src="CMSIS_CORE_Files.png" alt="CMSIS_CORE_Files.png"/> +<div class="caption"> +CMSIS-Core File Structure</div></div> + <h1><a class="anchor" id="CMSIS_Processor_files"></a> +CMSIS-Core Processor Files</h1> +<p>The CMSIS-Core processor files provided by Arm are in the directory .\CMSIS\Core\Include. These header files define all processor specific attributes do not need any modifications. The <b>core_<cpu>.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-M processor:</p> +<table class="doxtable"> +<tr> +<th align="left">Header File </th><th align="left">Processor </th></tr> +<tr> +<td align="left">core_cm0.h </td><td align="left">for the Cortex-M0 processor </td></tr> +<tr> +<td align="left">core_cm0plus.h </td><td align="left">for the Cortex-M0+ processor </td></tr> +<tr> +<td align="left">core_cm3.h </td><td align="left">for the Cortex-M3 processor </td></tr> +<tr> +<td align="left">core_cm4.h </td><td align="left">for the Cortex-M4 processor </td></tr> +<tr> +<td align="left">core_cm7.h </td><td align="left">for the Cortex-M7 processor </td></tr> +<tr> +<td align="left">core_cm23.h </td><td align="left">for the Cortex-M23 processor </td></tr> +<tr> +<td align="left">core_cm33.h </td><td align="left">for the Cortex-M33 processor </td></tr> +<tr> +<td align="left">core_sc000.h </td><td align="left">for the SecurCore SC000 processor </td></tr> +<tr> +<td align="left">core_sc300.h </td><td align="left">for the SecurCore SC300 processor </td></tr> +<tr> +<td align="left">core_armv8mbl.h </td><td align="left">for the Armv8-M Baseline processor </td></tr> +<tr> +<td align="left">core_armv8mml.h </td><td align="left">for the Armv8-M Mainline processor </td></tr> +</table> +<h1><a class="anchor" id="device_examples"></a> +Device Examples</h1> +<p>The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\Device\ARM and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:</p> +<table class="doxtable"> +<tr> +<th align="left">Family </th><th align="left">Device </th><th align="left">Description </th></tr> +<tr> +<td align="left">ARM Cortex-M0 </td><td align="left">ARMCM0 </td><td align="left">Cortex-M0 based device </td></tr> +<tr> +<td align="left">ARM Cortex-M0 plus </td><td align="left">ARMCM0P </td><td align="left">Cortex-M0+ based device </td></tr> +<tr> +<td align="left">ARM Cortex-M3 </td><td align="left">ARMCM3 </td><td align="left">Cortex-M3 based device </td></tr> +<tr> +<td align="left">ARM Cortex-M4 </td><td align="left">ARMCM4 </td><td align="left">Cortex-M4 based device without floating-point hardware </td></tr> +<tr> +<td align="left">ARM Cortex-M4 </td><td align="left">ARMCM4_FP </td><td align="left">Cortex-M4 based device with floating-point hardware </td></tr> +<tr> +<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7 </td><td align="left">Cortex-M4 based device without floating-point hardware </td></tr> +<tr> +<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7_FP </td><td align="left">Cortex-M7 based device with single precision floating-point unit (FPU) </td></tr> +<tr> +<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7_DP </td><td align="left">Cortex-M7 based device with double precision floating-point unit </td></tr> +<tr> +<td align="left">ARM Cortex-M7 </td><td align="left">ARMCM7 </td><td align="left">Cortex-M7 based device without floating-point hardware </td></tr> +<tr> +<td align="left">ARM Cortex-M23 </td><td align="left">ARMCM23 </td><td align="left">Cortex-M23 based device without TrustZone </td></tr> +<tr> +<td align="left">ARM Cortex-M23 </td><td align="left">ARMCM23_TZ </td><td align="left">Cortex-M23 based device with TrustZone </td></tr> +<tr> +<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33 </td><td align="left">Cortex-M33 based device without TrustZone, SIMD, FPU </td></tr> +<tr> +<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_TZ </td><td align="left">Cortex-M33 based device with TrustZone, no SIMD, no FPU </td></tr> +<tr> +<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_DSP_FP </td><td align="left">Cortex-M23 based device with SIMD, FPU, no TrustZone </td></tr> +<tr> +<td align="left">ARM Cortex-M33 </td><td align="left">ARMCM33_DSP_FP_TZ </td><td align="left">Cortex-M23 based device with TrustZone, SIMD, FPU </td></tr> +<tr> +<td align="left">ARM SC000 </td><td align="left">ARM SC000 </td><td align="left">SC000 based device </td></tr> +<tr> +<td align="left">ARM SC300 </td><td align="left">ARM SC300 </td><td align="left">SC300 based device </td></tr> +<tr> +<td align="left">ARMv8-M Baseline </td><td align="left">ARMv8MBL </td><td align="left">Armv8-M Baseline based device with TrustZone </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML </td><td align="left">Armv8-M Mainline based device with TrustZone </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DP </td><td align="left">Armv8-M Mainline based device with TrustZone and double precision FPU </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_SP </td><td align="left">Armv8-M Mainline based device with TrustZone and single precision FPU </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP </td><td align="left">Armv8-M Mainline based device with TrustZone and SIMD </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP_DP </td><td align="left">Armv8-M Mainline based device with TrustZone, SIMD, and double precision FPU </td></tr> +<tr> +<td align="left">ARMv8-M Mainline </td><td align="left">ARMv8MML_DSP_SP </td><td align="left">Armv8-M Mainline based device with TrustZone, SIMD, and single precision FPU </td></tr> +</table> +<h1><a class="anchor" id="template_files_sec"></a> +Template Files</h1> +<p>To simplify the creation of CMSIS-Core device files, the following template files are provided that should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add to these template files the following information:</p> +<ul> +<li><b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.</li> +<li><b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.</li> +<li><b>Interrupt vectors</b> in the startup file that are device specific.</li> +</ul> +<table class="cmtable"> +<tr> +<th>Template File </th><th>Description </th></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s </td><td>Startup file template for Arm C/C++ Compiler. </td></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s </td><td>Startup file template for GNU GCC Arm Embedded Compiler. </td></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s </td><td>Startup file template for IAR C/C++ Compiler. </td></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c </td><td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system). </td></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Include\Device.h </td><td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file. </td></tr> +<tr> +<td>.\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h </td><td>Generic system device configuration include file. </td></tr> +</table> +<p><b>Adapt Template Files to a Device</b></p> +<p>The following steps describe how to adopt the template files to a specific device or device family. Copy the complete all files in the template directory and replace:</p> +<ul> +<li>directory name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.</li> +<li>directory name 'Device' with the specific device name e.g.: LPC17xx.</li> +<li>in the file names 'Device' with the specific device name e.g.: LPC17xx.</li> +</ul> +<p>Each template file contains comments that start with <b>ToDo:</b> that describe a required modification. The template files contain place holders:</p> +<table class="cmtable"> +<tr> +<th>Placeholder </th><th>Replaced with </th></tr> +<tr> +<td><Device> </td><td>the specific device name or device family name; i.e. LPC17xx. </td></tr> +<tr> +<td><DeviceInterrupt> </td><td>a specific interrupt name of the device; i.e. TIM1 for Timer 1. </td></tr> +<tr> +<td><DeviceAbbreviation> </td><td>short name or abbreviation of the device family; i.e. LPC. </td></tr> +<tr> +<td>Cortex-M# </td><td>the specific Cortex-M processor name; i.e. Cortex-M3. </td></tr> +</table> +<p>The device configuration of the template files is described in detail on the following pages:</p> +<ul> +<li><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a></li> +<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a></li> +<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a></li> +<li><a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> </li> +</ul> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/templates_pg.js b/docs/Core/html/templates_pg.js new file mode 100644 index 0000000..d47081f --- /dev/null +++ b/docs/Core/html/templates_pg.js @@ -0,0 +1,26 @@ +var templates_pg = +[ + [ "CMSIS-Core Processor Files", "templates_pg.html#CMSIS_Processor_files", null ], + [ "Device Examples", "templates_pg.html#device_examples", null ], + [ "Template Files", "templates_pg.html#template_files_sec", null ], + [ "Startup File startup_<device>.s", "startup_s_pg.html", [ + [ "startup_Device.s Template File", "startup_s_pg.html#startup_s_sec", null ] + ] ], + [ "System Configuration Files system_<device>.c and system_<device>.h", "system_c_pg.html", [ + [ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ], + [ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ] + ] ], + [ "Device Header File <device.h>", "device_h_pg.html", [ + [ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ], + [ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ], + [ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ], + [ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ], + [ "Device.h Template File", "device_h_pg.html#device_h_sec", null ] + ] ], + [ "System Partition Header File partition_<device>.h", "partition_h_pg.html", [ + [ "SAU CTRL register settings", "partition_h_pg.html#sau_ctrlregister_sec", null ], + [ "Configuration of the SAU Address Regions", "partition_h_pg.html#sau_regions_sect", null ], + [ "Configuration of Sleep and Exception behaviour", "partition_h_pg.html#sau_sleepexception_sec", null ], + [ "Configuration of Interrupt Target settings", "partition_h_pg.html#sau_interrupttarget_sec", null ] + ] ] +];
\ No newline at end of file diff --git a/docs/Core/html/unionAPSR__Type.html b/docs/Core/html/unionAPSR__Type.html new file mode 100644 index 0000000..47c8164 --- /dev/null +++ b/docs/Core/html/unionAPSR__Type.html @@ -0,0 +1,266 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>APSR_Type Union Reference</title> +<title>CMSIS-Core (Cortex-M): APSR_Type Union Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> + <div id="navrow2" class="tabs2"> + <ul class="tablist"> + <li><a href="annotated.html"><span>Data Structures</span></a></li> + <li><a href="functions.html"><span>Data Fields</span></a></li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('unionAPSR__Type.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">APSR_Type Union Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Union type to access the Application Program Status Register (APSR). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memItemLeft" >struct {</td></tr> +<tr class="memitem:a40a16164602a889d31a6bd92e9ccde92"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#afbce95646fd514c10aa85ec0a33db728">_reserved0</a>:27</td></tr> +<tr class="memdesc:a40a16164602a889d31a6bd92e9ccde92"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0..26 Reserved <a href="#a40a16164602a889d31a6bd92e9ccde92">More...</a><br/></td></tr> +<tr class="separator:a40a16164602a889d31a6bd92e9ccde92"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aebf336ed17f711353ef40d16b9fcc305"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a22d10913489d24ab08bd83457daa88de">Q</a>:1</td></tr> +<tr class="memdesc:aebf336ed17f711353ef40d16b9fcc305"><td class="mdescLeft"> </td><td class="mdescRight">bit: 27 Saturation condition flag <a href="#aebf336ed17f711353ef40d16b9fcc305">More...</a><br/></td></tr> +<tr class="separator:aebf336ed17f711353ef40d16b9fcc305"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8003e190933fcfbff0b0878f48aa32b6"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a8004d224aacb78ca37774c35f9156e7e">V</a>:1</td></tr> +<tr class="memdesc:a8003e190933fcfbff0b0878f48aa32b6"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Overflow condition code flag <a href="#a8003e190933fcfbff0b0878f48aa32b6">More...</a><br/></td></tr> +<tr class="separator:a8003e190933fcfbff0b0878f48aa32b6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7c6e27604bd227c0c7685ae13ee33dc4"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a86e2c5b891ecef1ab55b1edac0da79a6">C</a>:1</td></tr> +<tr class="memdesc:a7c6e27604bd227c0c7685ae13ee33dc4"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Carry condition code flag <a href="#a7c6e27604bd227c0c7685ae13ee33dc4">More...</a><br/></td></tr> +<tr class="separator:a7c6e27604bd227c0c7685ae13ee33dc4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">Z</a>:1</td></tr> +<tr class="memdesc:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Zero condition code flag <a href="#a8030e626bbdfa4d8f50cf01ea2d1c0ea">More...</a><br/></td></tr> +<tr class="separator:a8030e626bbdfa4d8f50cf01ea2d1c0ea"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a77dede9507ca1f554043f49035299f2e"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionAPSR__Type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">N</a>:1</td></tr> +<tr class="memdesc:a77dede9507ca1f554043f49035299f2e"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Negative condition code flag <a href="#a77dede9507ca1f554043f49035299f2e">More...</a><br/></td></tr> +<tr class="separator:a77dede9507ca1f554043f49035299f2e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionAPSR__Type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">b</a></td></tr> +<tr class="memdesc:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a7dbc79a057ded4b11ca5323fc2d5ab14">More...</a><br/></td></tr> +<tr class="separator:a7dbc79a057ded4b11ca5323fc2d5ab14"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae4c2ef8c9430d7b7bef5cbfbbaed3a94"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" 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options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">CONTROL_Type Union Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Union type to access the Control Registers (CONTROL). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:adc6a38ab2980d0e9577b5a871da14eb9"><td class="memItemLeft" >struct {</td></tr> +<tr class="memitem:a666f4d16841194dd2ffb38cd9c1ff021"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605">nPRIV</a>:1</td></tr> +<tr class="memdesc:a666f4d16841194dd2ffb38cd9c1ff021"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0 Execution privilege in Thread mode <a href="#a666f4d16841194dd2ffb38cd9c1ff021">More...</a><br/></td></tr> +<tr class="separator:a666f4d16841194dd2ffb38cd9c1ff021"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae452742bb12b77c4cae20418495334f1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2">SPSEL</a>:1</td></tr> +<tr class="memdesc:ae452742bb12b77c4cae20418495334f1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 1 Stack to be used <a href="#ae452742bb12b77c4cae20418495334f1">More...</a><br/></td></tr> +<tr class="separator:ae452742bb12b77c4cae20418495334f1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a63fd27005fb7c3828f9f145a4fccf9a8"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd">FPCA</a>:1</td></tr> +<tr class="memdesc:a63fd27005fb7c3828f9f145a4fccf9a8"><td class="mdescLeft"> </td><td class="mdescRight">bit: 2 FP extension active flag <a href="#a63fd27005fb7c3828f9f145a4fccf9a8">More...</a><br/></td></tr> +<tr class="separator:a63fd27005fb7c3828f9f145a4fccf9a8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ada408fafd29cbe29e0c71ef479bd7564"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50">_reserved0</a>:29</td></tr> +<tr class="memdesc:ada408fafd29cbe29e0c71ef479bd7564"><td class="mdescLeft"> </td><td class="mdescRight">bit: 3..31 Reserved <a href="#ada408fafd29cbe29e0c71ef479bd7564">More...</a><br/></td></tr> +<tr class="separator:ada408fafd29cbe29e0c71ef479bd7564"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:adc6a38ab2980d0e9577b5a871da14eb9"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9">b</a></td></tr> +<tr class="memdesc:adc6a38ab2980d0e9577b5a871da14eb9"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#adc6a38ab2980d0e9577b5a871da14eb9">More...</a><br/></td></tr> +<tr class="separator:adc6a38ab2980d0e9577b5a871da14eb9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6b642cca3d96da660b1198c133ca2a1f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f">w</a></td></tr> +<tr class="memdesc:a6b642cca3d96da660b1198c133ca2a1f"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a6b642cca3d96da660b1198c133ca2a1f">More...</a><br/></td></tr> +<tr class="separator:a6b642cca3d96da660b1198c133ca2a1f"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="af8c314273a1e4970a5671bd7f8184f50"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t CONTROL_Type::_reserved0</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="adc6a38ab2980d0e9577b5a871da14eb9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">struct { ... } CONTROL_Type::b</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ac62cfff08e6f055e0101785bad7094cd"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t CONTROL_Type::FPCA</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a35c1732cf153b7b5c4bd321cf1de9605"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t CONTROL_Type::nPRIV</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a8cc085fea1c50a8bd9adea63931ee8e2"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t CONTROL_Type::SPSEL</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a6b642cca3d96da660b1198c133ca2a1f"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t CONTROL_Type::w</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="unionCONTROL__Type.html">CONTROL_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/unionCONTROL__Type.js b/docs/Core/html/unionCONTROL__Type.js new file mode 100644 index 0000000..059a405 --- /dev/null +++ b/docs/Core/html/unionCONTROL__Type.js @@ -0,0 +1,9 @@ +var unionCONTROL__Type = +[ + [ "_reserved0", "unionCONTROL__Type.html#af8c314273a1e4970a5671bd7f8184f50", null ], + [ "b", "unionCONTROL__Type.html#adc6a38ab2980d0e9577b5a871da14eb9", null ], + [ "FPCA", "unionCONTROL__Type.html#ac62cfff08e6f055e0101785bad7094cd", null ], + [ "nPRIV", "unionCONTROL__Type.html#a35c1732cf153b7b5c4bd321cf1de9605", null ], + [ "SPSEL", "unionCONTROL__Type.html#a8cc085fea1c50a8bd9adea63931ee8e2", null ], + [ "w", "unionCONTROL__Type.html#a6b642cca3d96da660b1198c133ca2a1f", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/unionIPSR__Type.html b/docs/Core/html/unionIPSR__Type.html new file mode 100644 index 0000000..e36bca0 --- /dev/null +++ b/docs/Core/html/unionIPSR__Type.html @@ -0,0 +1,206 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>IPSR_Type Union Reference</title> +<title>CMSIS-Core (Cortex-M): IPSR_Type Union Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">IPSR_Type Union Reference</div> </div> +</div><!--header--> +<div class="contents"> + +<p>Union type to access the Interrupt Program Status Register (IPSR). +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:add0d6497bd50c25569ea22b48a03ec50"><td class="memItemLeft" >struct {</td></tr> +<tr class="memitem:afaf0827367274b557f0d28e0a2398229"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">ISR</a>:9</td></tr> +<tr class="memdesc:afaf0827367274b557f0d28e0a2398229"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 8 Exception number <a href="#afaf0827367274b557f0d28e0a2398229">More...</a><br/></td></tr> +<tr class="separator:afaf0827367274b557f0d28e0a2398229"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa0449af1acf460572a66b57e2d07a931"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa">_reserved0</a>:23</td></tr> +<tr class="memdesc:aa0449af1acf460572a66b57e2d07a931"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9..31 Reserved <a href="#aa0449af1acf460572a66b57e2d07a931">More...</a><br/></td></tr> +<tr class="separator:aa0449af1acf460572a66b57e2d07a931"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:add0d6497bd50c25569ea22b48a03ec50"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50">b</a></td></tr> +<tr class="memdesc:add0d6497bd50c25569ea22b48a03ec50"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#add0d6497bd50c25569ea22b48a03ec50">More...</a><br/></td></tr> +<tr class="separator:add0d6497bd50c25569ea22b48a03ec50"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4adca999d3a0bc1ae682d73ea7cfa879"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879">w</a></td></tr> +<tr class="memdesc:a4adca999d3a0bc1ae682d73ea7cfa879"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a4adca999d3a0bc1ae682d73ea7cfa879">More...</a><br/></td></tr> +<tr class="separator:a4adca999d3a0bc1ae682d73ea7cfa879"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="ad2eb0a06de4f03f58874a727716aa9aa"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t IPSR_Type::_reserved0</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="add0d6497bd50c25569ea22b48a03ec50"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">struct { ... } IPSR_Type::b</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="ab46e5f1b2f4d17cfb9aca4fffcbb2fa5"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t IPSR_Type::ISR</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +<a class="anchor" id="a4adca999d3a0bc1ae682d73ea7cfa879"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname">uint32_t IPSR_Type::w</td> + </tr> + </table> +</div><div class="memdoc"> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="unionIPSR__Type.html">IPSR_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/unionIPSR__Type.js b/docs/Core/html/unionIPSR__Type.js new file mode 100644 index 0000000..e341e5f --- /dev/null +++ b/docs/Core/html/unionIPSR__Type.js @@ -0,0 +1,7 @@ +var unionIPSR__Type = +[ + [ "_reserved0", "unionIPSR__Type.html#ad2eb0a06de4f03f58874a727716aa9aa", null ], + [ "b", "unionIPSR__Type.html#add0d6497bd50c25569ea22b48a03ec50", null ], + [ "ISR", "unionIPSR__Type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5", null ], + [ "w", "unionIPSR__Type.html#a4adca999d3a0bc1ae682d73ea7cfa879", null ] +];
\ No newline at end of file diff --git a/docs/Core/html/unionxPSR__Type.html b/docs/Core/html/unionxPSR__Type.html new file mode 100644 index 0000000..017f0a1 --- /dev/null +++ b/docs/Core/html/unionxPSR__Type.html @@ -0,0 +1,311 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>xPSR_Type Union Reference</title> +<title>CMSIS-Core (Cortex-M): xPSR_Type Union Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" 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</tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + 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--> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a 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class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a3b1063bb5cdad67e037cba993b693b70"><td class="memItemLeft" >struct {</td></tr> +<tr class="memitem:a14aa41f658bf70c2d44435d24761a760"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a3e9120dcf1a829fc8d2302b4d0673970">ISR</a>:9</td></tr> +<tr class="memdesc:a14aa41f658bf70c2d44435d24761a760"><td class="mdescLeft"> </td><td class="mdescRight">bit: 0.. 8 Exception number <a href="#a14aa41f658bf70c2d44435d24761a760">More...</a><br/></td></tr> +<tr class="separator:a14aa41f658bf70c2d44435d24761a760"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a7af0067da9805e481890c297bf4ed70f"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#af438e0f407357e914a70b5bd4d6a97c5">_reserved0</a>:15</td></tr> +<tr class="memdesc:a7af0067da9805e481890c297bf4ed70f"><td class="mdescLeft"> </td><td class="mdescRight">bit: 9..23 Reserved <a href="#a7af0067da9805e481890c297bf4ed70f">More...</a><br/></td></tr> +<tr class="separator:a7af0067da9805e481890c297bf4ed70f"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a5224815d0f90fb7d26c7007bfb8e38d5"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a7eed9fe24ae8d354cd76ae1c1110a658">T</a>:1</td></tr> +<tr class="memdesc:a5224815d0f90fb7d26c7007bfb8e38d5"><td class="mdescLeft"> </td><td class="mdescRight">bit: 24 Thumb bit (read 0) <a href="#a5224815d0f90fb7d26c7007bfb8e38d5">More...</a><br/></td></tr> +<tr class="separator:a5224815d0f90fb7d26c7007bfb8e38d5"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0c9d4cef85e4cc7d6dc701d7d3377af0"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a3200966922a194d84425e2807a7f1328">IT</a>:2</td></tr> +<tr class="memdesc:a0c9d4cef85e4cc7d6dc701d7d3377af0"><td class="mdescLeft"> </td><td class="mdescRight">bit: 25..26 saved IT state (read 0) <a href="#a0c9d4cef85e4cc7d6dc701d7d3377af0">More...</a><br/></td></tr> +<tr class="separator:a0c9d4cef85e4cc7d6dc701d7d3377af0"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0713a6888c5b556e9050aa82d2c1b0e1"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#add7cbd2b0abd8954d62cd7831796ac7c">Q</a>:1</td></tr> +<tr class="memdesc:a0713a6888c5b556e9050aa82d2c1b0e1"><td class="mdescLeft"> </td><td class="mdescRight">bit: 27 Saturation condition flag <a href="#a0713a6888c5b556e9050aa82d2c1b0e1">More...</a><br/></td></tr> +<tr class="separator:a0713a6888c5b556e9050aa82d2c1b0e1"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6dd30396c78f8bc53d30ca13b058cbb2"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#af14df16ea0690070c45b95f2116b7a0a">V</a>:1</td></tr> +<tr class="memdesc:a6dd30396c78f8bc53d30ca13b058cbb2"><td class="mdescLeft"> </td><td class="mdescRight">bit: 28 Overflow condition code flag <a href="#a6dd30396c78f8bc53d30ca13b058cbb2">More...</a><br/></td></tr> +<tr class="separator:a6dd30396c78f8bc53d30ca13b058cbb2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ae33d83822b56cd849b9fa9affddd59b2"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a40213a6b5620410cac83b0d89564609d">C</a>:1</td></tr> +<tr class="memdesc:ae33d83822b56cd849b9fa9affddd59b2"><td class="mdescLeft"> </td><td class="mdescRight">bit: 29 Carry condition code flag <a href="#ae33d83822b56cd849b9fa9affddd59b2">More...</a><br/></td></tr> +<tr class="separator:ae33d83822b56cd849b9fa9affddd59b2"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ac1f7475b01a46aef06d9f53d3a2a69ef"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a1e5d9801013d5146f2e02d9b7b3da562">Z</a>:1</td></tr> +<tr class="memdesc:ac1f7475b01a46aef06d9f53d3a2a69ef"><td class="mdescLeft"> </td><td class="mdescRight">bit: 30 Zero condition code flag <a href="#ac1f7475b01a46aef06d9f53d3a2a69ef">More...</a><br/></td></tr> +<tr class="separator:ac1f7475b01a46aef06d9f53d3a2a69ef"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a38ba57343e56c653939fd792c19af047"><td class="memItemLeft" >   uint32_t   <a class="el" href="unionxPSR__Type.html#a2db9a52f6d42809627d1a7a607c5dbc5">N</a>:1</td></tr> +<tr class="memdesc:a38ba57343e56c653939fd792c19af047"><td class="mdescLeft"> </td><td class="mdescRight">bit: 31 Negative condition code flag <a href="#a38ba57343e56c653939fd792c19af047">More...</a><br/></td></tr> +<tr class="separator:a38ba57343e56c653939fd792c19af047"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a3b1063bb5cdad67e037cba993b693b70"><td class="memItemLeft" valign="top">} </td><td class="memItemRight" valign="bottom"><a class="el" href="unionxPSR__Type.html#a3b1063bb5cdad67e037cba993b693b70">b</a></td></tr> +<tr class="memdesc:a3b1063bb5cdad67e037cba993b693b70"><td class="mdescLeft"> </td><td class="mdescRight">Structure used for bit access. <a href="#a3b1063bb5cdad67e037cba993b693b70">More...</a><br/></td></tr> +<tr class="separator:a3b1063bb5cdad67e037cba993b693b70"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a1a47176768f45f79076c4f5b1b534bc2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="unionxPSR__Type.html#a1a47176768f45f79076c4f5b1b534bc2">w</a></td></tr> +<tr class="memdesc:a1a47176768f45f79076c4f5b1b534bc2"><td class="mdescLeft"> </td><td class="mdescRight">Type used for word access. <a href="#a1a47176768f45f79076c4f5b1b534bc2">More...</a><br/></td></tr> +<tr class="separator:a1a47176768f45f79076c4f5b1b534bc2"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="af438e0f407357e914a70b5bd4d6a97c5"></a> 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href="unionxPSR__Type.html">xPSR_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:09 for CMSIS-Core (Cortex-M) by Arm Ltd. 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\ No newline at end of file diff --git a/docs/Core/html/using_ARM_pg.html b/docs/Core/html/using_ARM_pg.html new file mode 100644 index 0000000..551b056 --- /dev/null +++ b/docs/Core/html/using_ARM_pg.html @@ -0,0 +1,169 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Using CMSIS with generic Arm Processors</title> +<title>CMSIS-Core (Cortex-M): Using CMSIS with generic Arm Processors</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('using_ARM_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Using CMSIS with generic Arm Processors </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors. These files can be used when standard Arm processors should be used in a project. The table below lists the folder and device names of the Arm processors.</p> +<table class="cmtable"> +<tr> +<th>Folder </th><th>Processor </th><th>Description </th></tr> +<tr> +<td>".\Device\ARM\ARMCM0" </td><td>Cortex-M0 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMCM0plus" </td><td>Cortex-M0+ </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0plus.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMCM3" </td><td>Cortex-M3 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM3.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMCM4" </td><td>Cortex-M4 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM4.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMCM7" </td><td>Cortex-M7 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M7 processor. The device name is ARMCM7 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM7.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMSC000" </td><td>SecurCore SC000 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC000.h>. </td></tr> +<tr> +<td>".\Device\ARM\ARMSC300" </td><td>SecurCore SC300 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC300.h>. </td></tr> +</table> +<h1><a class="anchor" id="using_ARM_Lib_sec"></a> +Create generic Libraries with CMSIS</h1> +<p>The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The <a href="../../DSP/html/index.html"><b>CMSIS-DSP</b> </a> Libraries are an example for such a generic library.</p> +<p>To build a generic Library set the define <b>__CMSIS_GENERIC</b> and include the relevant <b>core_<cpu>.h</b> CMSIS CPU & Core Access header file for the processor. The define <b>__CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>. Refer to <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> for a list of the available <b>core_<cpu>.h</b> header files.</p> +<p><b>Example:</b> </p> +<p>The following code section shows the usage of the <b>core_<cpu>.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To select the processor, the source code uses the define <b>CORTEX_M7</b>, <b>CORTEX_M4</b>, <b>CORTEX_M3</b>, <b>CORTEX_M0</b>, or <b>CORTEX_M0PLUS</b>. One of these defines needs to be provided on the compiler command line. By using this header file, the source code can access the functions for <a class="el" href="group__Core__Register__gr.html">Core Register Access</a>, <a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a>, <a class="el" href="group__intrinsic__SIMD__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a>, and <a class="el" href="group__ITM__Debug__gr.html">Debug Access</a>.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#define __CMSIS_GENERIC </span><span class="comment">/* disable NVIC and Systick functions */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor">#if defined (CORTEX_M7)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm7.h"</span></div> +<div class="line"><span class="preprocessor">#elif defined (CORTEX_M4)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm4.h"</span></div> +<div class="line"><span class="preprocessor">#elif defined (CORTEX_M3)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm3.h"</span></div> +<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0.h"</span></div> +<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0PLUS)</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0plus.h"</span></div> +<div class="line"><span class="preprocessor">#else</span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #error "Processor not specified or unsupported."</span></div> +<div class="line"><span class="preprocessor">#endif</span></div> +</div><!-- fragment --> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/using_CMSIS.html b/docs/Core/html/using_CMSIS.html new file mode 100644 index 0000000..dbd6688 --- /dev/null +++ b/docs/Core/html/using_CMSIS.html @@ -0,0 +1,177 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Basic CMSIS Example</title> +<title>CMSIS-Core (Cortex-M): Basic CMSIS Example</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('using_CMSIS.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Basic CMSIS Example </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#include <stm32f10x.h></span> <span class="comment">// File name depends on device used</span></div> +<div class="line"> </div> +<div class="line">uint32_t <span class="keyword">volatile</span> msTicks; <span class="comment">// Counter for millisecond Interval</span></div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> SysTick_Handler (<span class="keywordtype">void</span>) { <span class="comment">// SysTick Interrupt Handler</span></div> +<div class="line"> msTicks++; <span class="comment">// Increment Counter</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> WaitForTick (<span class="keywordtype">void</span>) {</div> +<div class="line"> uint32_t curTicks;</div> +<div class="line"> </div> +<div class="line"> curTicks = msTicks; <span class="comment">// Save Current SysTick Value</span></div> +<div class="line"> <span class="keywordflow">while</span> (msTicks == curTicks) { <span class="comment">// Wait for next SysTick Interrupt</span></div> +<div class="line"> <a class="code" href="group__intrinsic__CPU__gr.html#gad3efec76c3bfa2b8528ded530386c563">__WFE</a> (); <span class="comment">// Power-Down until next Event/Interrupt</span></div> +<div class="line"> }</div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> TIM1_UP_IRQHandler (<span class="keywordtype">void</span>) { <span class="comment">// Timer Interrupt Handler</span></div> +<div class="line"> ; <span class="comment">// Add user code here</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> timer1_init(<span class="keywordtype">int</span> frequency) { <span class="comment">// Set up Timer (device specific)</span></div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">NVIC_SetPriority</a> (TIM1_UP_IRQn, 1); <span class="comment">// Set Timer priority</span></div> +<div class="line"> <a class="code" href="group__NVIC__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">NVIC_EnableIRQ</a> (TIM1_UP_IRQn); <span class="comment">// Enable Timer Interrupt</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"> </div> +<div class="line"><span class="keywordtype">void</span> Device_Initialization (<span class="keywordtype">void</span>) { <span class="comment">// Configure & Initialize MCU</span></div> +<div class="line"> <span class="keywordflow">if</span> (<a class="code" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a> (<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000)) { <span class="comment">// SysTick 1mSec</span></div> +<div class="line"> : <span class="comment">// Handle Error </span></div> +<div class="line"> }</div> +<div class="line"> timer1_init (); <span class="comment">// setup device-specific timer</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"> </div> +<div class="line"><span class="comment">// The processor clock is initialized by CMSIS startup + system file</span></div> +<div class="line"><span class="keywordtype">void</span> main (<span class="keywordtype">void</span>) { <span class="comment">// user application starts here</span></div> +<div class="line"> Device_Initialization (); <span class="comment">// Configure & Initialize MCU</span></div> +<div class="line"> <span class="keywordflow">while</span> (1) { <span class="comment">// Endless Loop (the Super-Loop)</span></div> +<div class="line"> <a class="code" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> (); <span class="comment">// Disable all interrupts</span></div> +<div class="line"> Get_InputValues (); <span class="comment">// Read Values</span></div> +<div class="line"> <a class="code" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a> (); <span class="comment">// Enable all interrupts </span></div> +<div class="line"> Calculation_Response (); <span class="comment">// Calculate Results</span></div> +<div class="line"> Output_Response (); <span class="comment">// Output Results</span></div> +<div class="line"> WaitForTick (); <span class="comment">// Synchronize to SysTick Timer</span></div> +<div class="line"> }</div> +<div class="line">}</div> +</div><!-- fragment --> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/using_TrustZone_pg.html b/docs/Core/html/using_TrustZone_pg.html new file mode 100644 index 0000000..1604bbb --- /dev/null +++ b/docs/Core/html/using_TrustZone_pg.html @@ -0,0 +1,216 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Using TrustZone for Armv8-M</title> +<title>CMSIS-Core (Cortex-M): Using TrustZone for Armv8-M</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! 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TrustZone for Armv8-M enables of multiple software security domains that restrict access to secure memory and I/O only for trusted software.</p> +<p>TrustZone for Armv8-M:</p> +<ul> +<li>preserves low interrupt latencies for both Secure and Non-secure domains.</li> +<li>does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.</li> +<li>introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.</li> +</ul> +<p><b>Notations</b> </p> +<p>This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:</p> +<ul> +<li>prefix <b>TZ</b> or <b>__TZ</b> indicates a function that is available only in Armv8-M TrustZone enabled devices.</li> +<li>postfix <b>_NS</b> indicates a hardware resource that belongs to the Non-secure state.</li> +<li>postfix <b>_S</b> indicates a hardware resource that belongs to the Secure state.</li> +</ul> +<h1><a class="anchor" id="useCase_TrustZone"></a> +Simplified Use Case with TrustZone</h1> +<p>An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection, or multi-party embedded software deployments.</p> +<p>The figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b> (executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state).</p> +<ul> +<li><b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.</li> +<li><b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.</li> +<li><b>Firmware callbacks:</b> code running in the <b>Secure state</b> can execute code in the <b>Non-secure state</b> using call-back function pointers. For example, a communication stack (protected firmware) could use an I/O driver that is configured in user space.</li> +</ul> +<p><a class="anchor" id="SimpleUseCase"></a></p> +<div class="image"> +<img src="SimpleUseCase.png" alt="SimpleUseCase.png"/> +<div class="caption"> +Simplified Use Case</div></div> +<p> Program execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures. For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution in <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b> to <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently executing code in <b>Non-secure state</b>.</p> +<h2><a class="anchor" id="Example_TrustZone"></a> +Program Examples</h2> +<p>This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:</p> +<table class="doxtable"> +<tr> +<th align="left">Example </th><th align="left">Description </th></tr> +<tr> +<td align="left">TrustZone for Armv8-M No RTOS </td><td align="left">bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case). </td></tr> +<tr> +<td align="left">TrustZone for Armv8-M RTOS </td><td align="left">secure/non-secure RTOS example with thread context management </td></tr> +<tr> +<td align="left">TrustZone for Armv8-M RTOS Security Tests </td><td align="left">secure/non-secure RTOS example with security test cases and system recovery </td></tr> +</table> +<p>Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in the Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b> (Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).</p> +<h1><a class="anchor" id="Model_TrustZone"></a> +Programmers Model with TrustZone</h1> +<p>The figure <a href="#MemoryMap_S"><b>Secure Memory Map</b></a> shows the memory view for the <b>Secure state</b>. In the Secure state all memory and peripherals can be accessed. The <b>System Control and Debug</b> area provides access to secure peripherals and non-secure peripherals that are mirrored at a memory alias.</p> +<p>The secure peripherals are only accessible during program execution in <b>Secure state</b>. The Secure Attribute Unit (SAU) configures the non-secure memory, peripheral, and interrupt access. Also available are a secure MPU (memory protection unit), secure SCB (system control block), and secure SysTick timer.</p> +<p>The system supports two separate interrupt vector tables for secure and non-secure code execution. This interrupt assignment is controlled during <b>Secure state</b> code execution via the NVIC (nested vector interrupt controller).</p> +<p><a class="anchor" id="MemoryMap_S"></a></p> +<div class="image"> +<img src="MemoryMap_S.png" alt="MemoryMap_S.png"/> +<div class="caption"> +Secure Memory Map</div></div> +<p> The figure <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> shows the memory view for the Non-secure state. This memory view is identical to the traditional Cortex-M memory map. Access to any secure memory or peripheral space triggers the secure exception that executes a handler in <b>Secure state</b>.</p> +<p>The <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> defines the initial setup of the <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> during system start in the Secure state (refer to functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> and <a class="el" href="group__sau__trustzone__functions.html#ga6093bc5939ea8924fbcfdffb8f0553f1">TZ_SAU_Setup</a>).</p> +<p><a class="anchor" id="MemoryMap_NS"></a></p> +<div class="image"> +<img src="MemoryMap_NS.png" alt="MemoryMap_NS.png"/> +<div class="caption"> +Non-Secure Memory Map</div></div> +<p>The figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter and return values.</p> +<p>The register R13 is the stack pointer alias, and the actual stack pointer (PSP_NS, MSP_NS, PSP_S, MSP_S) accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or thread=normal code execution).</p> +<p>In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S) that traps stack overflows with the <b>UsageFault</b> exception (register UFSR bit STKOF=1).</p> +<p>An Armv8-M system with TrustZone has an independent <b>CONTROL</b> register for each state (Secure or Non-secure). The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure), however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that secure interrupts have always higher priority.</p> +<p>The core registers of the current state (Secure or Non-secure) are accessed using the standard <a class="el" href="group__Core__Register__gr.html">Core Register Access</a> functions. In Secure state all non-secure registers are accessible using the <a class="el" href="group__coreregister__trustzone__functions.html">Core Register Access Functions</a> related to TrustZone for Armv8-M.</p> +<div class="image"> +<img src="Registers.png" alt="Registers.png"/> +<div class="caption"> +Registers</div></div> + <h1><a class="anchor" id="CMSIS_Files_TrustZone"></a> +CMSIS Files for TrustZone</h1> +<p>The CMSIS-Core files are extended by the <a class="el" href="partition_h_pg.html">System Partition Header File partition_<device>.h</a> which defines the initial system configuration and during <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> in Secure state.</p> +<div class="image"> +<img src="CMSIS_TZ_files.png" alt="CMSIS_TZ_files.png"/> +<div class="caption"> +CMSIS with extensions for TrustZone</div></div> + <dl class="section note"><dt>Note</dt><dd>Refer to <a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a> for a general description of the CMSIS-Core (Cortex-M) files.</dd></dl> +<h2><a class="anchor" id="RTOS_TrustZone"></a> +RTOS Thread Context Management</h2> +<p>To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions. An <em>non-secure application</em> which uses an RTOS and calls <em>secure</em> library modules requires the management of the <em>secure</em> stack space. Since <em>secure state</em> registers cannot be accessed by the RTOS that runs in <em>non-secure state</em> secure functions implement the thread context switch.</p> +<p>As the <em>non-secure state</em> and <em>secure state</em> parts of an application are separated, the API for managing the <em>secure</em> stack space should be standardized. Otherwise the <em>secure</em> library modules would force the <em>non-secure state</em> application to use a matching RTOS implementation.</p> +<div class="image"> +<img src="TZ_context.png" alt="TZ_context.png"/> +<div class="caption"> +RTOS Thread Context Management for Armv8-M TrustZone</div></div> +<p> To allocate the context memory for threads, an RTOS kernel that runs in <em>non-secure state</em> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are part of the <em>secure state</em> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory management system with additional features such as access control to <em>secure state</em> memory regions using an MPU.</p> +<p>The API functions of <b>TZ_context</b> are described in the chapter <a href="Modules.html"><b>Reference</b> </a> under <a class="el" href="group__trustzone__functions.html">TrustZone for Armv8-M</a> - <a class="el" href="group__context__trustzone__functions.html">RTOS Context Management</a>.</p> +<p>Refer to <a class="el" href="using_TrustZone_pg.html#Example_TrustZone">Program Examples</a> for RTOS examples that provide a template implementation for <b>TZ_context.c</b>. </p> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/using_VTOR_pg.html b/docs/Core/html/using_VTOR_pg.html new file mode 100644 index 0000000..38958cc --- /dev/null +++ b/docs/Core/html/using_VTOR_pg.html @@ -0,0 +1,181 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Using Interrupt Vector Remap</title> +<title>CMSIS-Core (Cortex-M): Using Interrupt Vector Remap</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('using_VTOR_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Using Interrupt Vector Remap </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.</p> +<div class="fragment"><div class="line"><span class="preprocessor">#include "ARMCM3.h"</span> <span class="comment">// Device header</span></div> +<div class="line"> </div> +<div class="line"><span class="comment">/* externals from startup_ARMCM3.s */</span></div> +<div class="line"><span class="keyword">extern</span> uint32_t __Vectors[]; <span class="comment">/* vector table ROM */</span></div> +<div class="line"> </div> +<div class="line"><span class="preprocessor">#define VECTORTABLE_SIZE (256) </span><span class="comment">/* size Cortex-M3 vector table */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define VECTORTABLE_ALIGNMENT (0x100ul) </span><span class="comment">/* 16 Cortex + 32 ARMCM3 = 48 words */</span><span class="preprocessor"></span></div> +<div class="line"><span class="preprocessor"></span> <span class="comment">/* next power of 2 = 256 */</span></div> +<div class="line"> </div> +<div class="line"><span class="comment">/* new vector table in RAM */</span></div> +<div class="line">uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));</div> +<div class="line"> </div> +<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div> +<div class="line"><span class="comment"> SysTick_Handler</span></div> +<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div> +<div class="line"><span class="keyword">volatile</span> uint32_t msTicks = 0; <span class="comment">/* counts 1ms timeTicks */</span></div> +<div class="line"><span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>) {</div> +<div class="line"> msTicks++; <span class="comment">/* increment counter */</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div> +<div class="line"><span class="comment"> SysTick_Handler (RAM)</span></div> +<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div> +<div class="line"><span class="keyword">volatile</span> uint32_t msTicks_RAM = 0; <span class="comment">/* counts 1ms timeTicks */</span></div> +<div class="line"><span class="keywordtype">void</span> SysTick_Handler_RAM(<span class="keywordtype">void</span>) {</div> +<div class="line"> msTicks_RAM++; <span class="comment">/* increment counter */</span></div> +<div class="line">}</div> +<div class="line"> </div> +<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div> +<div class="line"><span class="comment"> MAIN function</span></div> +<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div> +<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div> +<div class="line"> uint32_t i;</div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">for</span> (i = 0; i < VECTORTABLE_SIZE; i++) {</div> +<div class="line"> vectorTable_RAM[i] = __Vectors[i]; <span class="comment">/* copy vector table to RAM */</span></div> +<div class="line"> }</div> +<div class="line"> <span class="comment">/* replace SysTick Handler */</span></div> +<div class="line"> vectorTable_RAM[<a class="code" href="group__NVIC__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">SysTick_IRQn</a> + 16] = (uint32_t)SysTick_Handler_RAM;</div> +<div class="line"> </div> +<div class="line"> <span class="comment">/* relocate vector table */</span> </div> +<div class="line"> <a class="code" href="group__Core__Register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a>();</div> +<div class="line"> SCB->VTOR = (uint32_t)&vectorTable_RAM;</div> +<div class="line"> <a class="code" href="group__intrinsic__CPU__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>();</div> +<div class="line"> <a class="code" href="group__Core__Register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>();</div> +<div class="line"> </div> +<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a>(); <span class="comment">/* Get Core Clock Frequency */</span></div> +<div class="line"> <a class="code" href="group__SysTick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> / 1000ul); <span class="comment">/* Setup SysTick Timer for 1 msec */</span></div> +<div class="line"> </div> +<div class="line"> <span class="keywordflow">while</span>(1);</div> +<div class="line">}</div> +</div><!-- fragment --> </div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="using_pg.html">Using CMSIS in Embedded Applications</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/using_pg.html b/docs/Core/html/using_pg.html new file mode 100644 index 0000000..b82e1c9 --- /dev/null +++ b/docs/Core/html/using_pg.html @@ -0,0 +1,172 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>Using CMSIS in Embedded Applications</title> +<title>CMSIS-Core (Cortex-M): Using CMSIS in Embedded Applications</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-M) +  <span id="projectnumber">Version 5.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-M processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li class="current"><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" + onblur="searchBox.OnSearchFieldFocus(false)" + onkeyup="searchBox.OnSearchFieldChange(event)"/> + </span><span class="right"> + <a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a> + </span> + </div> + </li> + </ul> + </div> +</div><!-- top --> +<div id="side-nav" class="ui-resizable side-nav-resizable"> + <div id="nav-tree"> + <div id="nav-tree-contents"> + <div id="nav-sync" class="sync"></div> + </div> + </div> + <div id="splitbar" style="-moz-user-select:none;" + class="ui-resizable-handle"> + </div> +</div> +<script type="text/javascript"> +$(document).ready(function(){initNavTree('using_pg.html','');}); +</script> +<div id="doc-content"> +<!-- window showing the filter options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="headertitle"> +<div class="title">Using CMSIS in Embedded Applications </div> </div> +</div><!--header--> +<div class="contents"> +<div class="textblock"><p>To use the CMSIS-Core (Cortex-M) the following files are added to the embedded application:</p> +<ul> +<li><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> with reset handler and exception vectors.</li> +<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> with general device configuration (i.e. for clock and BUS setup).</li> +<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a> gives access to processor core and all peripherals.</li> +</ul> +<dl class="section note"><dt>Note</dt><dd>The files <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> and <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.</dd></dl> +<p>The <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> is executed after reset and calls <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the <b>main</b> function in the user code. In addition the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.</p> +<p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> performs the setup for the processor clock. The variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> indicates the CPU clock speed. <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a> describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.</p> +<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is the central include file that the application programmer is using in the C source code. It provides the following features:</p> +<ul> +<li><a class="el" href="group__peripheral__gr.html">Peripheral Access</a> provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.</li> +<li><a class="el" href="group__NVIC__gr.html">Interrupts and Exceptions (NVIC)</a> can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.</li> +<li><a class="el" href="group__intrinsic__CPU__gr.html">Intrinsic Functions for CPU Instructions</a> allow to access special instructions, for example for activating sleep mode or the NOP instruction.</li> +<li><a class="el" href="group__intrinsic__SIMD__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a> provide access to the DSP-oriented instructions.</li> +<li><a class="el" href="group__SysTick__gr.html">Systick Timer (SYSTICK)</a> function to configure and start a periodic timer interrupt.</li> +<li><a class="el" href="group__ITM__Debug__gr.html">Debug Access</a> are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.</li> +</ul> +<div class="image"> +<img src="CMSIS_CORE_Files_user.png" alt="CMSIS_CORE_Files_user.png"/> +<div class="caption"> +CMSIS-Core (Cortex-M) User Files</div></div> +<p> The CMSIS-Core (Cortex-M) are device specific. In addition, the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.</p> +<p>For example, the following files are provided in MDK to support the STM32F10x Connectivity Line device variants:</p> +<table class="cmtable"> +<tr> +<th>File </th><th>Description </th></tr> +<tr> +<td>".\ARM\Startup\ST\STM32F10x\startup_stm32f10x_cl.s" </td><td><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> for the STM32F10x Connectivity Line device variants. </td></tr> +<tr> +<td>".\ARM\Startup\ST\STM32F10x\system_stmf10x.c" </td><td><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> for the STM32F10x device families. </td></tr> +<tr> +<td>".\ARM\INC\ST\STM32F10x\stm32f10x.h" </td><td><a class="el" href="device_h_pg.html">Device Header File <device.h></a> for the STM32F10x device families. </td></tr> +<tr> +<td>".\ARM\INC\ST\STM32F10x\system_stm32f10x.h" </td><td><a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> for the STM32F10x device families. </td></tr> +</table> +<dl class="section note"><dt>Note</dt><dd>The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on <a class="el" href="templates_pg.html">CMSIS-Core Device Templates</a> provide by Arm.</dd></dl> +<p>Thereafter, the functions described under <a href="Modules.html"><b>Reference</b> </a> can be used in the application.</p> +<p><b>Examples</b> </p> +<ul> +<li><a class="el" href="using_CMSIS.html">Basic CMSIS Example</a> is a simple example that shows the usage of the CMSIS layer.</li> +<li><a class="el" href="using_VTOR_pg.html">Using Interrupt Vector Remap</a> shows how to remap the interrupt vector table.</li> +<li><a class="el" href="using_ARM_pg.html">Using CMSIS with generic Arm Processors</a> explains how to use CMSIS-Core (Cortex-M) for Arm processors. </li> +</ul> +</div></div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="footer">Generated on Wed Aug 1 2018 17:12:08 for CMSIS-Core (Cortex-M) by Arm Ltd. All rights reserved. + <!-- + <a href="http://www.doxygen.org/index.html"> + <img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.6 + --> + </li> + </ul> +</div> +</body> +</html> diff --git a/docs/Core/html/using_pg.js b/docs/Core/html/using_pg.js new file mode 100644 index 0000000..caa160b --- /dev/null +++ b/docs/Core/html/using_pg.js @@ -0,0 +1,8 @@ +var using_pg = +[ + [ "Basic CMSIS Example", "using_CMSIS.html", null ], + [ "Using Interrupt Vector Remap", "using_VTOR_pg.html", null ], + [ "Using CMSIS with generic Arm Processors", "using_ARM_pg.html", [ + [ "Create generic Libraries with CMSIS", "using_ARM_pg.html#using_ARM_Lib_sec", null ] + ] ] +];
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