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| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/DSP/html/search/all_17.js | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/DSP/html/search/all_17.js')
| -rw-r--r-- | docs/DSP/html/search/all_17.js | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/docs/DSP/html/search/all_17.js b/docs/DSP/html/search/all_17.js new file mode 100644 index 0000000..bf3ac96 --- /dev/null +++ b/docs/DSP/html/search/all_17.js @@ -0,0 +1,8 @@ +var searchData= +[ + ['x0',['x0',['../structarm__lms__norm__instance__f32.html#aec958fe89b164a30f38bcca9f5d96218',1,'arm_lms_norm_instance_f32::x0()'],['../structarm__lms__norm__instance__q31.html#a47c4466d644e0d8ba407995adfa9b917',1,'arm_lms_norm_instance_q31::x0()'],['../structarm__lms__norm__instance__q15.html#a3fc1d6f97d2c6d5324871de6895cb7e9',1,'arm_lms_norm_instance_q15::x0()']]], + ['x1',['x1',['../structarm__linear__interp__instance__f32.html#a08352dc6ea82fbc0827408e018535481',1,'arm_linear_interp_instance_f32']]], + ['x_5ff32',['X_f32',['../arm__matrix__example__f32_8c.html#a98c67c0fc0cb5f2df51b21482d31d21c',1,'arm_matrix_example_f32.c']]], + ['xref_5ff32',['xRef_f32',['../arm__matrix__example__f32_8c.html#a6184758419722fa16bb883097c2f596b',1,'arm_matrix_example_f32.c']]], + ['xspacing',['xSpacing',['../structarm__linear__interp__instance__f32.html#aa8e2d686b5434a406d390b347b183511',1,'arm_linear_interp_instance_f32::xSpacing()'],['../arm__linear__interp__example__f32_8c.html#a0ecae49cebd837aac53411c8f877503d',1,'XSPACING(): arm_linear_interp_example_f32.c']]] +]; |