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| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core_A/html/structGICInterface__Type.html | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Core_A/html/structGICInterface__Type.html')
| -rw-r--r-- | docs/Core_A/html/structGICInterface__Type.html | 503 |
1 files changed, 503 insertions, 0 deletions
diff --git a/docs/Core_A/html/structGICInterface__Type.html b/docs/Core_A/html/structGICInterface__Type.html new file mode 100644 index 0000000..a47733e --- /dev/null +++ b/docs/Core_A/html/structGICInterface__Type.html @@ -0,0 +1,503 @@ +<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> +<html xmlns="http://www.w3.org/1999/xhtml"> +<head> +<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/> +<meta http-equiv="X-UA-Compatible" content="IE=9"/> +<title>GICInterface_Type Struct Reference</title> +<title>CMSIS-Core (Cortex-A): GICInterface_Type Struct Reference</title> +<link href="tabs.css" rel="stylesheet" type="text/css"/> +<link href="cmsis.css" rel="stylesheet" type="text/css" /> +<script type="text/javascript" src="jquery.js"></script> +<script type="text/javascript" src="dynsections.js"></script> +<script type="text/javascript" src="printComponentTabs.js"></script> +<link href="navtree.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="resize.js"></script> +<script type="text/javascript" src="navtree.js"></script> +<script type="text/javascript"> + $(document).ready(initResizable); + $(window).load(resizeHeight); +</script> +<link href="search/search.css" rel="stylesheet" type="text/css"/> +<script type="text/javascript" src="search/search.js"></script> +<script type="text/javascript"> + $(document).ready(function() { searchBox.OnSelectItem(0); }); +</script> +</head> +<body> +<div id="top"><!-- do not remove this div, it is closed by doxygen! --> +<div id="titlearea"> +<table cellspacing="0" cellpadding="0"> + <tbody> + <tr style="height: 46px;"> + <td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td> + <td style="padding-left: 0.5em;"> + <div id="projectname">CMSIS-Core (Cortex-A) +  <span id="projectnumber">Version 1.1.2</span> + </div> + <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div> + </td> + </tr> + </tbody> +</table> +</div> +<!-- end header part --> +<div id="CMSISnav" class="tabs1"> + <ul class="tablist"> + <script type="text/javascript"> + <!-- + writeComponentTabs.call(this); + //--> + </script> + </ul> +</div> +<!-- Generated by Doxygen 1.8.6 --> +<script type="text/javascript"> +var searchBox = new SearchBox("searchBox", "search",false,'Search'); +</script> + <div id="navrow1" class="tabs"> + <ul class="tablist"> + <li><a href="index.html"><span>Main Page</span></a></li> + <li><a href="pages.html"><span>Usage and Description</span></a></li> + <li><a href="modules.html"><span>Reference</span></a></li> + <li> + <div id="MSearchBox" class="MSearchBoxInactive"> + <span class="left"> + <img id="MSearchSelect" src="search/mag_sel.png" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + alt=""/> + <input type="text" id="MSearchField" value="Search" accesskey="S" + onfocus="searchBox.OnSearchFieldFocus(true)" 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options --> +<div id="MSearchSelectWindow" + onmouseover="return searchBox.OnSearchSelectShow()" + onmouseout="return searchBox.OnSearchSelectHide()" + onkeydown="return searchBox.OnSearchSelectKey(event)"> +<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Typedefs</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Macros</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(9)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(10)"><span class="SelectionMark"> </span>Pages</a></div> + +<!-- iframe showing the search results (closed by default) --> +<div id="MSearchResultsWindow"> +<iframe src="javascript:void(0)" frameborder="0" + name="MSearchResults" id="MSearchResults"> +</iframe> +</div> + +<div class="header"> + <div class="summary"> +<a href="#pub-attribs">Data Fields</a> </div> + <div class="headertitle"> +<div class="title">GICInterface_Type Struct Reference<div class="ingroups"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div> </div> +</div><!--header--> +<div class="contents"> + +<p>Structure type to access the Generic Interrupt Controller Interface (GICC) +</p> +<table class="memberdecls"> +<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a> +Data Fields</h2></td></tr> +<tr class="memitem:a5969edab40aa24e4d96e072af187a3a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a></td></tr> +<tr class="memdesc:a5969edab40aa24e4d96e072af187a3a9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x000 (R/W) CPU Interface Control Register. <a href="#a5969edab40aa24e4d96e072af187a3a9">More...</a><br/></td></tr> +<tr class="separator:a5969edab40aa24e4d96e072af187a3a9"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b">PMR</a></td></tr> +<tr class="memdesc:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Priority Mask Register. <a href="#a0edadabc6e3ce1f36d820f0b52bc143b">More...</a><br/></td></tr> +<tr class="separator:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a949317484547dc1db89c9f7ab40d1829"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">BPR</a></td></tr> +<tr class="memdesc:a949317484547dc1db89c9f7ab40d1829"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x008 (R/W) Binary Point Register. <a href="#a949317484547dc1db89c9f7ab40d1829">More...</a><br/></td></tr> +<tr class="separator:a949317484547dc1db89c9f7ab40d1829"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aa48569605fc0c163e1db35321b4c76ea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">IAR</a></td></tr> +<tr class="memdesc:aa48569605fc0c163e1db35321b4c76ea"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00C (R/ ) Interrupt Acknowledge Register. <a href="#aa48569605fc0c163e1db35321b4c76ea">More...</a><br/></td></tr> +<tr class="separator:aa48569605fc0c163e1db35321b4c76ea"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a4b9baa43aae026438bad64e63df17cdb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">EOIR</a></td></tr> +<tr class="memdesc:a4b9baa43aae026438bad64e63df17cdb"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x010 ( /W) End Of Interrupt Register. <a href="#a4b9baa43aae026438bad64e63df17cdb">More...</a><br/></td></tr> +<tr class="separator:a4b9baa43aae026438bad64e63df17cdb"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a37762d42768ecb3d1302f34abc7f2821"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">RPR</a></td></tr> +<tr class="memdesc:a37762d42768ecb3d1302f34abc7f2821"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x014 (R/ ) Running Priority Register. <a href="#a37762d42768ecb3d1302f34abc7f2821">More...</a><br/></td></tr> +<tr class="separator:a37762d42768ecb3d1302f34abc7f2821"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:af793cd280a74bf73cca8c4fedfc329d6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">HPPIR</a></td></tr> +<tr class="memdesc:af793cd280a74bf73cca8c4fedfc329d6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. <a href="#af793cd280a74bf73cca8c4fedfc329d6">More...</a><br/></td></tr> +<tr class="separator:af793cd280a74bf73cca8c4fedfc329d6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">ABPR</a></td></tr> +<tr class="memdesc:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01C (R/W) Aliased Binary Point Register. <a href="#a6d3ca9eaae5e0ac38f20846a1e67180d">More...</a><br/></td></tr> +<tr class="separator:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">AIAR</a></td></tr> +<tr class="memdesc:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register. <a href="#a849e9ead6e9ced78dc6f0ba9256dd5a6">More...</a><br/></td></tr> +<tr class="separator:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">AEOIR</a></td></tr> +<tr class="memdesc:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x024 ( /W) Aliased End Of Interrupt Register. <a href="#a89d5a920c2b91b4b7bd0312ba4c38a89">More...</a><br/></td></tr> +<tr class="separator:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a12f25dec95ab3dd13a477573fab4b9c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">AHPPIR</a></td></tr> +<tr class="memdesc:a12f25dec95ab3dd13a477573fab4b9c8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register. <a href="#a12f25dec95ab3dd13a477573fab4b9c8">More...</a><br/></td></tr> +<tr class="separator:a12f25dec95ab3dd13a477573fab4b9c8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:abd978b408fb69b7887be2c422f48ce7e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">STATUSR</a></td></tr> +<tr class="memdesc:abd978b408fb69b7887be2c422f48ce7e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02C (R/W) Error Reporting Status Register, optional. <a href="#abd978b408fb69b7887be2c422f48ce7e">More...</a><br/></td></tr> +<tr class="separator:abd978b408fb69b7887be2c422f48ce7e"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aebae4bdcd3930372d639b85c5c9301e8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">APR</a> [4]</td></tr> +<tr class="memdesc:aebae4bdcd3930372d639b85c5c9301e8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D0 (R/W) Active Priority Register. <a href="#aebae4bdcd3930372d639b85c5c9301e8">More...</a><br/></td></tr> +<tr class="separator:aebae4bdcd3930372d639b85c5c9301e8"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:ade3473ace2a8bf7c79a0251457be20f4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">NSAPR</a> [4]</td></tr> +<tr class="memdesc:ade3473ace2a8bf7c79a0251457be20f4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E0 (R/W) Non-secure Active Priority Register. <a href="#ade3473ace2a8bf7c79a0251457be20f4">More...</a><br/></td></tr> +<tr class="separator:ade3473ace2a8bf7c79a0251457be20f4"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">IIDR</a></td></tr> +<tr class="memdesc:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0FC (R/ ) CPU Interface Identification Register. <a href="#aee78d0b6f64a7b47fbd730aabfcc86cf">More...</a><br/></td></tr> +<tr class="separator:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="memSeparator" colspan="2"> </td></tr> +<tr class="memitem:a554bd1f88421df3189c664b9fd9c02aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">DIR</a></td></tr> +<tr class="memdesc:a554bd1f88421df3189c664b9fd9c02aa"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1000( /W) Deactivate Interrupt Register. <a href="#a554bd1f88421df3189c664b9fd9c02aa">More...</a><br/></td></tr> +<tr class="separator:a554bd1f88421df3189c664b9fd9c02aa"><td class="memSeparator" colspan="2"> </td></tr> +</table> +<h2 class="groupheader">Field Documentation</h2> +<a class="anchor" id="a6d3ca9eaae5e0ac38f20846a1e67180d"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::ABPR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Aliased Binary Point Register </p> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register. ">GICInterface_Type::BPR</a> </dd></dl> + +</div> +</div> +<a class="anchor" id="a89d5a920c2b91b4b7bd0312ba4c38a89"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::AEOIR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Aliased End Of Interrupt Register </p> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb" title="Offset: 0x010 ( /W) End Of Interrupt Register. ">GICInterface_Type::EOIR</a> </dd></dl> + +</div> +</div> +<a class="anchor" id="a12f25dec95ab3dd13a477573fab4b9c8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AHPPIR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Aliased Highest Priority Pending Interrupt Register </p> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. ">GICInterface_Type::HPPIR</a> </dd></dl> + +</div> +</div> +<a class="anchor" id="a849e9ead6e9ced78dc6f0ba9256dd5a6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AIAR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Aliased Interrupt Acknowledge Register </p> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register. ">GICInterface_Type::IAR</a> </dd></dl> + +</div> +</div> +<a class="anchor" id="aebae4bdcd3930372d639b85c5c9301e8"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::APR[4]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Active Priorities Registers </p> +<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl> + +</div> +</div> +<a class="anchor" id="a949317484547dc1db89c9f7ab40d1829"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::BPR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Binary Point Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[2:0] </td><td align="left">Binary_Point </td><td align="left">Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. </td></tr> +</table> +<p>The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please refer to the section Interrupt prioritization in the <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a> for details. </p> + +</div> +</div> +<a class="anchor" id="a5969edab40aa24e4d96e072af187a3a9"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::CTLR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Control Register</p> +<p>Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. In a GICv2 implementation, this includes control of the end of interrupt (EOI) behavior.</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">Enable </td><td align="left">Interrupt signaling: 0 - Disable. 1 - Enable. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a554bd1f88421df3189c664b9fd9c02aa"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::DIR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Deactivate Interrupt Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the interrupt to be disabled. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="a4b9baa43aae026438bad64e63df17cdb"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::EOIR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface End Of Interrupt Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the finished interrupt. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="af793cd280a74bf73cca8c4fedfc329d6"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::HPPIR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Highest Priority Pending Interrupt Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the signaled interrupt. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="aa48569605fc0c163e1db35321b4c76ea"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::IAR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Interrupt Acknowledge Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the signaled interrupt. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="aee78d0b6f64a7b47fbd730aabfcc86cf"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::IIDR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Identification Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:20] </td><td align="left">ProductID </td><td align="left">An IMPLEMENTATION DEFINED product identifier </td></tr> +<tr> +<td align="left">[19:16] </td><td align="left">Arch_version </td><td align="left">The version of the GIC architecture that is implemented. </td></tr> +<tr> +<td align="left">[15:12] </td><td align="left">Revision </td><td align="left">An IMPLEMENTATION DEFINED revision number for the CPU interface. </td></tr> +<tr> +<td align="left">[11:0] </td><td align="left">Implementer </td><td align="left">Contains the JEP106 code of the company that implemented the CPU interface. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="ade3473ace2a8bf7c79a0251457be20f4"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::NSAPR[4]</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Non-secure Active Priorities Registers </p> +<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl> +<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8" title="Offset: 0x0D0 (R/W) Active Priority Register. ">GICInterface_Type::APR</a>[4] </dd></dl> + +</div> +</div> +<a class="anchor" id="a0edadabc6e3ce1f36d820f0b52bc143b"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::PMR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Priority Mask Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The priority mask level for the CPU interface. </td></tr> +</table> +<dl class="section note"><dt>Note</dt><dd>IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI. </dd></dl> + +</div> +</div> +<a class="anchor" id="a37762d42768ecb3d1302f34abc7f2821"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::RPR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Running Priority Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The current running priority on the CPU interface. </td></tr> +</table> + +</div> +</div> +<a class="anchor" id="abd978b408fb69b7887be2c422f48ce7e"></a> +<div class="memitem"> +<div class="memproto"> + <table class="memname"> + <tr> + <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::STATUSR</td> + </tr> + </table> +</div><div class="memdoc"> +<p>CPU Interface Status Register</p> +<table class="doxtable"> +<tr> +<th align="left">Bits </th><th align="left">Name </th><th align="left">Function </th></tr> +<tr> +<td align="left">[31:5] </td><td align="left">- </td><td align="left">Reserved. </td></tr> +<tr> +<td align="left">[4] </td><td align="left">ASV </td><td align="left">Attempted security violation. </td></tr> +<tr> +<td align="left">[3] </td><td align="left">WROD </td><td align="left">Write to an RO location. </td></tr> +<tr> +<td align="left">[2] </td><td align="left">RWOD </td><td align="left">Read of a WO location. </td></tr> +<tr> +<td align="left">[1] </td><td align="left">WRD </td><td align="left">Write to a reserved location. </td></tr> +<tr> +<td align="left">[0] </td><td align="left">RRD </td><td align="left">Read of a reserved location. </td></tr> +</table> + +</div> +</div> +</div><!-- contents --> +</div><!-- doc-content --> +<!-- start footer part --> +<div id="nav-path" class="navpath"><!-- id is needed for treeview function! --> + <ul> + <li class="navelem"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></li> + <li class="footer">Generated on Wed Aug 1 2018 17:12:10 for CMSIS-Core (Cortex-A) by Arm Ltd. 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