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authorAli Labbene <ali.labbene@st.com>2019-12-11 08:59:21 +0100
committerAli Labbene <ali.labbene@st.com>2019-12-16 16:35:24 +0100
commit9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch)
tree8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core_A/html/search/groups_5.js
parent76177aa280494bb36d7a0bcbda1078d4db717020 (diff)
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Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder. Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure used in existing projects, and thus avoid projects mass update Note: the following components have been removed from ARM original delivery (as not used in ST packages) - CMSIS_EW2018.pdf - .gitattributes - .gitignore - \Device - \CMSIS - \CoreValidation - \DAP - \Documentation - \DoxyGen - \Driver - \Pack - \RTOS\CMSIS_RTOS_Tutorial.pdf - \RTOS\RTX - \RTOS\Template - \RTOS2\RTX - \Utilities - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2 Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
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diff --git a/docs/Core_A/html/search/groups_5.js b/docs/Core_A/html/search/groups_5.js
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+var searchData=
+[
+ ['intrinsic_20functions',['Intrinsic Functions',['../group__CMSIS__Core__InstructionInterface.html',1,'']]],
+ ['instruction_20fault_20status_20register_20_28ifsr_29',['Instruction Fault Status Register (IFSR)',['../group__CMSIS__IFSR.html',1,'']]],
+ ['ifsr_20bits',['IFSR Bits',['../group__CMSIS__IFSR__BITS.html',1,'']]],
+ ['interrupt_20status_20register_20_28isr_29',['Interrupt Status Register (ISR)',['../group__CMSIS__ISR.html',1,'']]],
+ ['isr_20bits',['ISR Bits',['../group__CMSIS__ISR__BITS.html',1,'']]],
+ ['interrupts_20and_20exceptions',['Interrupts and Exceptions',['../group__irq__ctrl__gr.html',1,'']]],
+ ['irq_20mode_20bit_2dmasks',['IRQ Mode Bit-Masks',['../group__irq__mode__defs.html',1,'']]],
+ ['irq_20priority_20bit_2dmasks',['IRQ Priority Bit-Masks',['../group__irq__priority__defs.html',1,'']]]
+];