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author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
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committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
tree | 8a6e0dda832555c692307869aed49d07ee7facfe /docs/Core_A/html/search/enums_1.js | |
parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'docs/Core_A/html/search/enums_1.js')
-rw-r--r-- | docs/Core_A/html/search/enums_1.js | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/docs/Core_A/html/search/enums_1.js b/docs/Core_A/html/search/enums_1.js new file mode 100644 index 0000000..e1339c8 --- /dev/null +++ b/docs/Core_A/html/search/enums_1.js @@ -0,0 +1,12 @@ +var searchData= +[ + ['mmu_5faccess_5ftype',['mmu_access_Type',['../group__MMU__defs__gr.html#ga2ee598252f996e4f96640b096291d280',1,'core_ca.h']]], + ['mmu_5fcacheability_5ftype',['mmu_cacheability_Type',['../group__MMU__defs__gr.html#ga11c86b7b193efb2c59b6a2179a02f584',1,'core_ca.h']]], + ['mmu_5fecc_5fcheck_5ftype',['mmu_ecc_check_Type',['../group__MMU__defs__gr.html#ga06d94c0eaa22d713636acaff81485409',1,'core_ca.h']]], + ['mmu_5fexecute_5ftype',['mmu_execute_Type',['../group__MMU__defs__gr.html#ga2fe1157deda82e66b9a1b19772309b63',1,'core_ca.h']]], + ['mmu_5fglobal_5ftype',['mmu_global_Type',['../group__MMU__defs__gr.html#ga04160605fbe20914c8ef020430684a30',1,'core_ca.h']]], + ['mmu_5fmemory_5ftype',['mmu_memory_Type',['../group__MMU__defs__gr.html#ga83ac8de9263f89879079da521e86d5f2',1,'core_ca.h']]], + ['mmu_5fregion_5fsize_5ftype',['mmu_region_size_Type',['../group__MMU__defs__gr.html#gab184b824a6d7cb728bd46c6abcd0c21a',1,'core_ca.h']]], + ['mmu_5fsecure_5ftype',['mmu_secure_Type',['../group__MMU__defs__gr.html#gac3d277641df9fb3bb3b555e2e79dd639',1,'core_ca.h']]], + ['mmu_5fshared_5ftype',['mmu_shared_Type',['../group__MMU__defs__gr.html#gab884a11fa8d094573ab77fb1c0f8d8a7',1,'core_ca.h']]] +]; |