Official ARM version: v5.4.0

    Add CMSIS V5.4.0, please refer to index.html available under \docs folder.

    Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
         used in existing projects, and thus avoid projects mass update
    Note: the following components have been removed from ARM original delivery (as not used in ST packages)
        - CMSIS_EW2018.pdf
        - .gitattributes
        - .gitignore
        - \Device
        - \CMSIS
           - \CoreValidation
		   - \DAP
           - \Documentation
           - \DoxyGen
           - \Driver
           - \Pack
           - \RTOS\CMSIS_RTOS_Tutorial.pdf
           - \RTOS\RTX
           - \RTOS\Template
           - \RTOS2\RTX
           - \Utilities
           - All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2

Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3

1 files changed, 45 insertions, 0 deletions

diff --git a/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js
new file mode 100644
index 0000000..b292775
--- /dev/null
+++ b/docs/Core_A/html/group__CMSIS__SCTLR__BITS.js
@@ -0,0 +1,45 @@
+var group__CMSIS__SCTLR__BITS =
+[
+    [ "SCTLR_A_Msk", "group__CMSIS__SCTLR__BITS.html#ga678c919832272745678213e55211e741", null ],
+    [ "SCTLR_A_Pos", "group__CMSIS__SCTLR__BITS.html#ga0d667a307e974515ebc15b5249f34146", null ],
+    [ "SCTLR_AFE_Msk", "group__CMSIS__SCTLR__BITS.html#ga9016d6e50562d2584c1f1a95bde1e957", null ],
+    [ "SCTLR_AFE_Pos", "group__CMSIS__SCTLR__BITS.html#ga4ac80ef4db2641dc9e6e8df0825a151e", null ],
+    [ "SCTLR_B_Msk", "group__CMSIS__SCTLR__BITS.html#ga4853d6f9ccbf919fcdadb0b2a5913cc6", null ],
+    [ "SCTLR_B_Pos", "group__CMSIS__SCTLR__BITS.html#ga5f185efbe1a9eb5738b2573f076a0859", null ],
+    [ "SCTLR_C_Msk", "group__CMSIS__SCTLR__BITS.html#ga2be72788d984153ded81711e20fd2d33", null ],
+    [ "SCTLR_C_Pos", "group__CMSIS__SCTLR__BITS.html#ga8a0394c5147b8212767087e3421deffa", null ],
+    [ "SCTLR_CP15BEN_Msk", "group__CMSIS__SCTLR__BITS.html#ga5541a6a63db4d4d233b8f57b1d46fbac", null ],
+    [ "SCTLR_CP15BEN_Pos", "group__CMSIS__SCTLR__BITS.html#gace284f69e1a810957665adf0cb2e4b2b", null ],
+    [ "SCTLR_EE_Msk", "group__CMSIS__SCTLR__BITS.html#ga8d95cd61bc40dc77f8855f40c797d044", null ],
+    [ "SCTLR_EE_Pos", "group__CMSIS__SCTLR__BITS.html#ga0baec19421bd41277c5d8783c59942fa", null ],
+    [ "SCTLR_FI_Msk", "group__CMSIS__SCTLR__BITS.html#ga316b80925b88fe3b88ec46a55655b0bc", null ],
+    [ "SCTLR_FI_Pos", "group__CMSIS__SCTLR__BITS.html#gad88d563fa9a8b09fe36702a5329b0360", null ],
+    [ "SCTLR_HA_Msk", "group__CMSIS__SCTLR__BITS.html#ga6830e9bf54a6b548f329ac047f59c179", null ],
+    [ "SCTLR_HA_Pos", "group__CMSIS__SCTLR__BITS.html#ga316882abba6c9cdd31dbbd7ba46c9f52", null ],
+    [ "SCTLR_I_Msk", "group__CMSIS__SCTLR__BITS.html#gab3cc0744fb07127e3c0f18cba9d51666", null ],
+    [ "SCTLR_I_Pos", "group__CMSIS__SCTLR__BITS.html#gaaaa818a1da51059bd979f0e768ebcc7c", null ],
+    [ "SCTLR_M_Msk", "group__CMSIS__SCTLR__BITS.html#gaf460824cdbf549bd914aa79762572e8e", null ],
+    [ "SCTLR_M_Pos", "group__CMSIS__SCTLR__BITS.html#ga88e34078fa8cf719aab6f53f138c9810", null ],
+    [ "SCTLR_NMFI_Msk", "group__CMSIS__SCTLR__BITS.html#gab92a3bd63ad9ac3d408e1b615bedc279", null ],
+    [ "SCTLR_NMFI_Pos", "group__CMSIS__SCTLR__BITS.html#gac1cf872c51ed0baa6ed23e26c1ed35a9", null ],
+    [ "SCTLR_RR_Msk", "group__CMSIS__SCTLR__BITS.html#ga1ff9e6766c7e1ca312b025bf34d384bc", null ],
+    [ "SCTLR_RR_Pos", "group__CMSIS__SCTLR__BITS.html#ga86e5b78ba8f818061644688db75ddc64", null ],
+    [ "SCTLR_SW_Msk", "group__CMSIS__SCTLR__BITS.html#gae4074aefcf01786fe199c82e273271b8", null ],
+    [ "SCTLR_SW_Pos", "group__CMSIS__SCTLR__BITS.html#ga3290be0882c1493bca9a0db6b4d0bff8", null ],
+    [ "SCTLR_TE_Msk", "group__CMSIS__SCTLR__BITS.html#ga4a68d6660c76951ada2541ceaf040b3b", null ],
+    [ "SCTLR_TE_Pos", "group__CMSIS__SCTLR__BITS.html#gab0a611e2359e04624379e1ddd4dc64b1", null ],
+    [ "SCTLR_TRE_Msk", "group__CMSIS__SCTLR__BITS.html#gab0481eb9812a4908601cb20c8ae84918", null ],
+    [ "SCTLR_TRE_Pos", "group__CMSIS__SCTLR__BITS.html#gaf76fa48119363f9b88c2c8f5b74e0a04", null ],
+    [ "SCTLR_U_Msk", "group__CMSIS__SCTLR__BITS.html#gaa047daa7ab35b5ad5dd238c7377a232f", null ],
+    [ "SCTLR_U_Pos", "group__CMSIS__SCTLR__BITS.html#gaa0431730d7ce929db03d8accee558e17", null ],
+    [ "SCTLR_UWXN_Msk", "group__CMSIS__SCTLR__BITS.html#gab834e64e0da7c2a98d747ce73252c199", null ],
+    [ "SCTLR_UWXN_Pos", "group__CMSIS__SCTLR__BITS.html#ga7c7d88f3db4de438ddd069cf3fbc88b3", null ],
+    [ "SCTLR_V_Msk", "group__CMSIS__SCTLR__BITS.html#gaf84f3f15bf6917acdc5b5a4ad661ac11", null ],
+    [ "SCTLR_V_Pos", "group__CMSIS__SCTLR__BITS.html#ga57778fd6afbe5b4fe8d8ea828acf833d", null ],
+    [ "SCTLR_VE_Msk", "group__CMSIS__SCTLR__BITS.html#gad94a7feadba850299a68c56e39c0b274", null ],
+    [ "SCTLR_VE_Pos", "group__CMSIS__SCTLR__BITS.html#ga1372b569553a0740d881e24c0be7334f", null ],
+    [ "SCTLR_WXN_Msk", "group__CMSIS__SCTLR__BITS.html#ga510b03214d135f15ad3c5d41ec20a291", null ],
+    [ "SCTLR_WXN_Pos", "group__CMSIS__SCTLR__BITS.html#gaf145654986fd6d014136580ad279d256", null ],
+    [ "SCTLR_Z_Msk", "group__CMSIS__SCTLR__BITS.html#ga12a05acdcb8db6e99970f26206d3067c", null ],
+    [ "SCTLR_Z_Pos", "group__CMSIS__SCTLR__BITS.html#gaa0eade648c9a34de891af0e6f47857dd", null ]
+];
\ No newline at end of file