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| author | Ali Labbene <ali.labbene@st.com> | 2019-12-11 08:59:21 +0100 |
|---|---|---|
| committer | Ali Labbene <ali.labbene@st.com> | 2019-12-16 16:35:24 +0100 |
| commit | 9f95ff5b6ba01db09552b84a0ab79607060a2666 (patch) | |
| tree | 8a6e0dda832555c692307869aed49d07ee7facfe /NN | |
| parent | 76177aa280494bb36d7a0bcbda1078d4db717020 (diff) | |
| download | st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.gz st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.tar.bz2 st-cmsis-core-lowfat-9f95ff5b6ba01db09552b84a0ab79607060a2666.zip | |
Official ARM version: v5.4.0
Add CMSIS V5.4.0, please refer to index.html available under \docs folder.
Note: content of \CMSIS\Core\Include has been copied under \Include to keep the same structure
used in existing projects, and thus avoid projects mass update
Note: the following components have been removed from ARM original delivery (as not used in ST packages)
- CMSIS_EW2018.pdf
- .gitattributes
- .gitignore
- \Device
- \CMSIS
- \CoreValidation
- \DAP
- \Documentation
- \DoxyGen
- \Driver
- \Pack
- \RTOS\CMSIS_RTOS_Tutorial.pdf
- \RTOS\RTX
- \RTOS\Template
- \RTOS2\RTX
- \Utilities
- All ARM/GCC projects files are deleted from \DSP, \RTOS and \RTOS2
Change-Id: Ia026c3f0f0d016627a4fb5a9032852c33d24b4d3
Diffstat (limited to 'NN')
88 files changed, 23109 insertions, 0 deletions
diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/EventRecorderStub.scvd b/NN/Examples/ARM/arm_nn_examples/cifar10/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/EventRecorderStub.scvd @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="utf-8"?> + +<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd"> + +<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component--> + <events> + </events> + +</component_viewer> diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..ddf354d --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,44 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// <h>Event Recorder + +// <o>Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// <i>Configure size of Event Record Buffer (each record is 16 bytes) +// <i>Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// <o>Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// <i>Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// <h>SysTick Configuration +// <i>Configure values when Time Stamp Source is set to SysTick + +// <o>SysTick Input Clock Frequency [Hz] <1-1000000000> +// <i>Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// <o>SysTick Interrupt Period [us] <1-1000000000> +// <i>Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// </h> + +// </h> + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..0c062ad --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..62755a7 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..835cb37 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..d275f41 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp new file mode 100644 index 0000000..471899c --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp @@ -0,0 +1,196 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_cifar10.cpp +* +* Description: Convolutional Neural Network Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup CNNExample Convolutional Neural Network Example + * + * \par Description: + * \par + * Demonstrates a convolutional neural network (CNN) example with the use of convolution, + * ReLU activation, pooling and fully-connected functions. + * + * \par Model definition: + * \par + * The CNN used in this example is based on CIFAR-10 example from Caffe [1]. + * The neural network consists + * of 3 convolution layers interspersed by ReLU activation and max pooling layers, followed by a + * fully-connected layer at the end. The input to the network is a 32x32 pixel color image, which will + * be classified into one of the 10 output classes. + * This example model implementation needs 32.3 KB to store weights, 40 KB for activations and + * 3.1 KB for storing the \c im2col data. + * + * \image html CIFAR10_CNN.gif "Neural Network model definition" + * + * \par Variables Description: + * \par + * \li \c conv1_wt, \c conv2_wt, \c conv3_wt are convolution layer weight matrices + * \li \c conv1_bias, \c conv2_bias, \c conv3_bias are convolution layer bias arrays + * \li \c ip1_wt, ip1_bias point to fully-connected layer weights and biases + * \li \c input_data points to the input image data + * \li \c output_data points to the classification output + * \li \c col_buffer is a buffer to store the \c im2col output + * \li \c scratch_buffer is used to store the activation data (intermediate layer outputs) + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_convolve_HWC_q7_RGB() + * - arm_convolve_HWC_q7_fast() + * - arm_relu_q7() + * - arm_maxpool_q7_HWC() + * - arm_avepool_q7_HWC() + * - arm_fully_connected_q7_opt() + * - arm_fully_connected_q7() + * + * <b> Refer </b> + * \link arm_nnexamples_cifar10.cpp \endlink + * + * \par [1] https://github.com/BVLC/caffe + */ + +#include <stdint.h> +#include <stdio.h> +#include "arm_math.h" +#include "arm_nnexamples_cifar10_parameter.h" +#include "arm_nnexamples_cifar10_weights.h" + +#include "arm_nnfunctions.h" +#include "arm_nnexamples_cifar10_inputs.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +// include the input and weights + +static q7_t conv1_wt[CONV1_IM_CH * CONV1_KER_DIM * CONV1_KER_DIM * CONV1_OUT_CH] = CONV1_WT; +static q7_t conv1_bias[CONV1_OUT_CH] = CONV1_BIAS; + +static q7_t conv2_wt[CONV2_IM_CH * CONV2_KER_DIM * CONV2_KER_DIM * CONV2_OUT_CH] = CONV2_WT; +static q7_t conv2_bias[CONV2_OUT_CH] = CONV2_BIAS; + +static q7_t conv3_wt[CONV3_IM_CH * CONV3_KER_DIM * CONV3_KER_DIM * CONV3_OUT_CH] = CONV3_WT; +static q7_t conv3_bias[CONV3_OUT_CH] = CONV3_BIAS; + +static q7_t ip1_wt[IP1_DIM * IP1_OUT] = IP1_WT; +static q7_t ip1_bias[IP1_OUT] = IP1_BIAS; + +/* Here the image_data should be the raw uint8 type RGB image in [RGB, RGB, RGB ... RGB] format */ +uint8_t image_data[CONV1_IM_CH * CONV1_IM_DIM * CONV1_IM_DIM] = IMG_DATA; +q7_t output_data[IP1_OUT]; + +//vector buffer: max(im2col buffer,average pool buffer, fully connected buffer) +q7_t col_buffer[2 * 5 * 5 * 32 * 2]; + +q7_t scratch_buffer[32 * 32 * 10 * 4]; + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("start execution\n"); + /* start the execution */ + + q7_t *img_buffer1 = scratch_buffer; + q7_t *img_buffer2 = img_buffer1 + 32 * 32 * 32; + + /* input pre-processing */ + int mean_data[3] = INPUT_MEAN_SHIFT; + unsigned int scale_data[3] = INPUT_RIGHT_SHIFT; + for (int i=0;i<32*32*3; i+=3) { + img_buffer2[i] = (q7_t)__SSAT( ((((int)image_data[i] - mean_data[0])<<7) + (0x1<<(scale_data[0]-1))) + >> scale_data[0], 8); + img_buffer2[i+1] = (q7_t)__SSAT( ((((int)image_data[i+1] - mean_data[1])<<7) + (0x1<<(scale_data[1]-1))) + >> scale_data[1], 8); + img_buffer2[i+2] = (q7_t)__SSAT( ((((int)image_data[i+2] - mean_data[2])<<7) + (0x1<<(scale_data[2]-1))) + >> scale_data[2], 8); + } + + // conv1 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_RGB(img_buffer2, CONV1_IM_DIM, CONV1_IM_CH, conv1_wt, CONV1_OUT_CH, CONV1_KER_DIM, CONV1_PADDING, + CONV1_STRIDE, conv1_bias, CONV1_BIAS_LSHIFT, CONV1_OUT_RSHIFT, img_buffer1, CONV1_OUT_DIM, + (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV1_OUT_DIM * CONV1_OUT_DIM * CONV1_OUT_CH); + + // pool1 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV1_OUT_DIM, CONV1_OUT_CH, POOL1_KER_DIM, + POOL1_PADDING, POOL1_STRIDE, POOL1_OUT_DIM, NULL, img_buffer2); + + // conv2 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV2_IM_DIM, CONV2_IM_CH, conv2_wt, CONV2_OUT_CH, CONV2_KER_DIM, + CONV2_PADDING, CONV2_STRIDE, conv2_bias, CONV2_BIAS_LSHIFT, CONV2_OUT_RSHIFT, img_buffer1, + CONV2_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV2_OUT_DIM * CONV2_OUT_DIM * CONV2_OUT_CH); + + // pool2 img_buffer1 -> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV2_OUT_DIM, CONV2_OUT_CH, POOL2_KER_DIM, + POOL2_PADDING, POOL2_STRIDE, POOL2_OUT_DIM, col_buffer, img_buffer2); + +// conv3 img_buffer2 -> img_buffer1 + arm_convolve_HWC_q7_fast(img_buffer2, CONV3_IM_DIM, CONV3_IM_CH, conv3_wt, CONV3_OUT_CH, CONV3_KER_DIM, + CONV3_PADDING, CONV3_STRIDE, conv3_bias, CONV3_BIAS_LSHIFT, CONV3_OUT_RSHIFT, img_buffer1, + CONV3_OUT_DIM, (q15_t *) col_buffer, NULL); + + arm_relu_q7(img_buffer1, CONV3_OUT_DIM * CONV3_OUT_DIM * CONV3_OUT_CH); + + // pool3 img_buffer-> img_buffer2 + arm_maxpool_q7_HWC(img_buffer1, CONV3_OUT_DIM, CONV3_OUT_CH, POOL3_KER_DIM, + POOL3_PADDING, POOL3_STRIDE, POOL3_OUT_DIM, col_buffer, img_buffer2); + + arm_fully_connected_q7_opt(img_buffer2, ip1_wt, IP1_DIM, IP1_OUT, IP1_BIAS_LSHIFT, IP1_OUT_RSHIFT, ip1_bias, + output_data, (q15_t *) img_buffer1); + + arm_softmax_q7(output_data, 10, output_data); + + for (int i = 0; i < 10; i++) + { + printf("%d: %d\n", i, output_data[i]); + } + + return 0; +} diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvoptx b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvoptx new file mode 100644 index 0000000..fe91232 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvoptx @@ -0,0 +1,745 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>ARMCM0</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>10000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM0_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <ScvdPack> + <Filename>C:\KEIL_V5\ARM\PACK\Keil\ARM_Compiler\1.3.3\EventRecorder.scvd</Filename> + <Type>Keil.ARM_Compiler.1.3.3</Type> + <SubType>1</SubType> + </ScvdPack> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>1</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + 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<LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + 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<LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + 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<HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM7_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <MemoryWindow1> + <Mm> + <WinNumber>1</WinNumber> + <SubType>0</SubType> + <ItemText>img_buffer2</ItemText> + <AccSizeX>0</AccSizeX> + </Mm> + </MemoryWindow1> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>1</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Group> + <GroupName>Source Files</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>8</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>.\arm_nnexamples_cifar10.cpp</PathWithFileName> + <FilenameWithoutPath>arm_nnexamples_cifar10.cpp</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Documentation</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>.\readme.txt</PathWithFileName> + <FilenameWithoutPath>readme.txt</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>::CMSIS</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + + <Group> + <GroupName>::Compiler</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + + <Group> + <GroupName>::Device</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + +</ProjectOpt> diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvprojx b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvprojx new file mode 100644 index 0000000..bdcfd87 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.uvprojx @@ -0,0 +1,1856 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>ARMCM0</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>ARMCM0</Device> + <Vendor>ARM</Vendor> + <PackID>ARM.CMSIS.5.3.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> + <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(10000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Flash\NEW_DEVICE.flm))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:ARMCM0$Device\Include\ARMCM0.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:ARMCM0$SVD\ARMCM0.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + 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name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0"> + <instance index="0" removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/> + <targetInfos/> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0"> + <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/> + <targetInfos/> + </file> + <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\startup_ARMCM7.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\system_ARMCM7.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + </targetInfos> + </file> + </files> + </RTE> + +</Project> diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h new file mode 100644 index 0000000..c600c5a --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h @@ -0,0 +1,6 @@ +/* Here are two different test images */ + +//#define IMG_DATA {158,112,49,159,111,47,165,116,51,166,118,53,160,112,46,156,109,41,162,115,47,159,113,45,158,111,44,159,113,41,161,116,41,160,111,52,161,111,49,166,117,41,169,117,45,170,119,44,167,117,40,162,113,38,160,111,39,160,112,43,156,109,44,149,107,45,150,107,45,148,106,43,149,107,44,143,101,39,140,98,43,141,97,41,143,97,38,137,95,36,126,91,36,116,85,33,152,112,51,151,110,40,159,114,45,166,116,56,162,112,49,160,113,43,164,117,47,162,114,45,163,116,46,156,110,38,155,111,41,159,110,54,163,113,52,170,119,41,171,117,40,171,115,33,169,115,30,160,111,33,154,112,41,151,115,50,145,110,53,139,104,55,140,102,52,141,100,48,149,105,50,147,102,46,145,102,45,142,97,38,143,98,34,136,95,31,125,91,32,119,88,34,151,110,47,151,109,33,158,111,36,167,111,48,160,106,42,163,115,44,165,117,45,165,117,45,163,115,43,162,115,43,158,114,48,157,109,57,161,111,51,166,115,38,167,114,37,169,113,35,170,116,39,159,114,47,145,111,54,121,96,49,110,90,52,98,78,50,101,77,47,114,85,50,120,86,48,134,96,55,143,103,51,140,99,39,142,99,35,139,98,34,130,95,34,120,89,33,155,107,40,155,110,32,160,109,31,174,112,44,167,110,43,167,117,46,169,120,48,169,119,48,165,115,44,165,117,45,167,123,57,191,146,95,177,130,75,157,111,41,162,115,47,164,114,54,158,112,58,149,111,67,104,80,47,103,87,65,98,90,76,92,90,84,80,75,66,74,63,50,86,70,52,83,62,39,113,85,45,132,98,46,140,102,43,140,101,39,136,99,39,127,94,36,155,107,41,156,114,48,161,115,49,170,114,47,169,114,43,163,113,40,169,120,47,166,116,44,164,113,41,164,116,42,173,128,59,246,214,164,195,156,107,151,114,56,146,111,60,142,108,71,111,80,50,78,53,31,85,69,56,113,103,98,112,110,111,106,114,118,97,102,105,93,94,93,74,72,67,84,78,70,85,73,47,105,83,45,128,96,48,138,101,46,133,94,36,129,93,36,148,109,54,133,104,64,130,100,57,147,112,53,161,115,44,165,113,39,167,116,41,167,115,41,163,111,37,165,116,39,163,118,42,180,138,85,157,122,78,128,102,58,97,75,43,66,50,31,69,58,43,66,56,45,89,83,76,118,113,110,122,121,120,119,122,122,114,116,116,94,96,96,99,100,97,91,91,86,58,58,47,67,58,37,108,84,49,140,105,58,138,98,44,134,95,40,127,100,57,109,95,80,47,37,17,88,74,28,153,117,48,170,118,43,168,115,40,170,118,43,169,117,42,166,116,37,164,120,39,147,107,52,129,98,59,127,108,75,100,87,70,68,67,57,78,83,72,72,75,64,83,84,74,132,130,121,146,142,132,124,118,108,105,99,90,107,102,94,115,111,103,85,83,77,63,71,69,46,47,39,79,61,36,132,98,58,141,99,48,134,93,39,131,115,90,99,96,92,42,43,38,70,64,41,143,111,56,167,117,42,165,114,36,168,116,39,171,119,49,161,113,51,140,109,51,120,94,49,130,110,77,144,131,107,116,106,93,88,87,79,91,95,88,85,88,82,77,77,69,124,118,107,163,153,140,136,124,112,102,93,81,106,98,88,100,93,84,85,81,74,54,60,58,49,53,49,57,47,32,107,83,50,138,103,51,136,97,39,170,161,144,103,105,105,54,58,59,124,121,113,153,124,82,161,113,43,163,117,41,166,122,50,165,121,66,174,135,95,113,89,59,125,105,78,157,141,121,156,143,128,121,111,101,86,80,74,82,81,77,84,85,82,80,78,73,81,71,61,138,125,112,146,135,123,113,103,93,87,79,70,83,77,69,86,82,76,71,73,67,56,57,53,40,35,27,74,59,35,133,106,59,137,103,45,180,176,163,134,139,143,94,100,105,154,154,149,174,149,112,158,116,51,156,116,47,153,118,60,207,180,146,237,214,198,207,180,166,156,131,119,174,153,145,148,131,125,125,110,107,93,85,79,86,84,79,74,74,71,59,57,53,76,68,58,137,125,112,143,133,122,133,124,114,106,98,89,86,81,74,87,85,78,84,85,78,75,76,71,50,49,43,40,30,15,95,75,44,132,103,57,183,183,175,108,116,122,142,151,158,165,169,168,177,156,122,155,112,50,159,118,51,122,89,47,213,197,179,237,224,226,220,191,188,164,135,131,183,159,155,156,137,132,125,108,104,120,111,104,78,76,69,80,80,77,45,44,40,91,85,77,175,165,154,157,147,137,155,147,138,107,100,92,87,83,77,103,102,96,88,88,79,78,79,73,59,59,59,41,36,33,59,46,31,104,81,46,188,191,189,100,108,116,135,144,153,170,175,178,187,167,136,166,120,59,173,123,55,134,93,44,117,95,80,194,182,188,199,171,164,170,142,133,185,161,151,189,171,159,134,119,106,117,107,95,102,98,89,84,84,79,38,38,34,125,121,113,210,201,192,160,152,142,146,139,130,93,89,82,83,80,75,94,93,88,104,104,94,85,87,81,73,75,78,55,53,55,62,55,48,76,56,26,189,194,194,90,96,105,127,134,144,175,180,185,174,156,133,166,123,68,178,123,53,159,109,47,97,68,44,168,154,152,168,144,126,137,114,94,186,166,148,216,202,183,160,149,129,123,113,98,120,114,105,115,114,109,50,50,47,150,147,140,194,187,178,155,149,140,123,118,111,91,88,83,84,83,79,84,84,80,95,95,85,86,87,81,84,87,89,73,73,73,79,74,64,73,55,24,189,192,193,93,95,103,152,154,163,185,188,192,119,110,98,136,106,66,173,124,58,167,116,50,103,72,39,147,132,120,145,125,103,167,149,127,189,174,155,226,216,200,180,172,157,141,131,117,126,117,107,117,114,109,71,71,68,154,152,147,186,181,174,149,144,136,114,110,104,87,85,80,80,80,76,72,73,70,80,80,72,99,100,94,100,101,99,90,88,81,97,89,69,94,73,34,194,196,196,108,107,112,168,167,172,186,186,188,105,109,109,99,89,67,156,119,62,167,122,55,100,74,34,115,106,88,138,123,103,198,185,169,190,180,169,172,165,159,145,140,140,154,143,134,146,136,125,103,100,95,71,71,70,152,152,149,179,175,170,137,13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3,71,107,133,49,89,114,31,77,105,27,71,105,38,82,117,49,93,128,56,100,135,58,102,137,53,92,128,56,94,131,60,99,137,57,99,139,53,97,138,50,95,137,45,94,136,39,88,131,33,83,125,42,91,133,62,112,154,79,132,179,73,131,181,56,116,168,38,97,146,13,64,108,40,85,127,61,116,168,49,102,148,35,85,132,43,91,143,39,90,139,42,92,134,44,88,125,40,81,112,42,85,115,27,72,104,23,67,102,30,74,109,27,71,106,29,73,108,36,80,115,47,86,120,56,95,128,62,101,135,66,109,144,75,119,156,69,113,152,49,95,134,43,88,127,43,88,127,60,105,144,85,130,170,109,156,197,93,145,190,60,115,164,26,82,130,29,82,126,20,64,107,54,107,160,56,105,149,45,89,132,43,86,134,40,89,134,40,92,132,40,87,123,38,81,115,36,79,114,26,69,105,22,66,101,29,73,108,25,69,104,29,73,108,19,63,98,18,58,89,32,70,100,47,87,118,61,104,137,74,119,152,66,111,145,53,96,131,52,95,130,45,87,123,67,109,145,89,131,167,105,146,182,89,135,175,48,99,145,24,77,124,34,84,129,21,67,110} + + +#define IMG_DATA {235,235,235,231,231,231,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,233,232,233,233,231,233,232,231,233,231,233,233,230,233,232,232,232,234,232,231,234,232,232,232,233,233,230,232,233,231,233,233,233,232,232,232,232,232,232,232,232,232,233,233,233,233,233,233,232,232,232,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,236,237,234,233,236,234,233,236,236,234,234,236,234,234,235,237,234,234,238,235,236,237,236,236,235,236,236,234,236,236,236,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,235,235,235,237,237,237,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,234,234,236,233,231,236,234,231,235,235,234,234,235,236,227,230,233,231,235,238,231,233,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,238,238,238,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,234,233,233,230,232,232,231,228,230,232,223,226,231,186,192,197,209,216,219,207,210,213,228,228,230,236,235,235,234,234,234,234,234,234,234,234,234,234,234,234,235,235,235,235,235,235,235,235,235,237,237,237,234,234,234,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,234,234,234,234,234,234,235,235,235,235,235,235,236,238,236,233,237,237,219,225,230,203,210,219,163,172,179,195,205,208,214,218,221,230,229,232,237,235,237,235,235,235,235,235,235,235,235,235,235,236,236,236,236,236,236,236,236,236,236,236,239,239,238,236,235,235,236,235,235,236,235,235,236,235,235,236,235,235,235,236,235,235,235,235,234,234,234,235,235,235,237,236,236,237,236,236,234,235,236,232,233,234,235,237,237,229,231,232,208,216,218,194,205,210,185,198,207,174,188,200,165,179,189,184,196,202,207,215,220,226,228,232,236,235,237,236,236,235,236,236,235,236,236,235,236,236,236,237,237,237,237,237,237,237,237,237,228,229,229,228,227,228,232,230,231,231,228,230,234,232,233,237,236,236,237,237,235,236,237,235,237,235,236,237,235,236,239,236,237,239,237,238,225,229,230,224,228,229,233,237,238,221,226,228,183,197,204,161,180,190,159,180,191,154,176,190,144,163,177,143,159,171,156,169,177,198,206,211,233,238,239,236,237,234,235,236,233,235,235,235,235,236,236,236,238,237,237,237,237,239,237,238,212,220,222,224,230,233,230,234,238,227,232,234,229,234,234,234,237,236,237,238,235,238,237,236,239,237,238,239,237,238,239,236,237,240,238,239,201,204,203,219,222,221,233,236,235,214,218,218,193,204,210,185,201,210,184,201,211,173,191,203,165,182,196,159,174,187,162,176,185,186,199,204,229,239,240,234,239,238,233,238,237,233,238,238,234,239,238,236,239,238,237,239,238,238,238,238,216,234,241,221,236,243,225,238,246,225,239,243,227,240,240,231,238,237,236,237,235,238,236,235,238,236,237,238,236,237,237,237,237,239,239,239,197,198,196,220,221,218,233,234,231,230,231,229,209,213,217,209,216,222,219,228,235,208,218,227,209,221,234,210,224,235,217,233,240,218,235,241,225,240,243,228,238,240,228,239,240,230,240,240,230,240,239,235,240,239,237,240,239,238,238,238,118,140,149,119,138,148,124,142,153,136,155,161,172,188,191,225,234,233,235,236,233,237,234,232,236,233,234,235,235,235,235,237,236,233,237,235,214,216,214,226,228,226,232,234,232,236,237,236,228,230,232,227,230,235,231,236,241,225,232,239,225,237,247,217,233,243,201,219,226,185,204,211,172,189,195,167,179,186,167,180,185,186,199,201,223,235,235,235,241,239,236,240,239,238,240,239,109,130,141,103,121,133,108,125,137,111,127,137,146,159,165,222,229,231,227,228,225,229,226,224,236,232,233,234,234,234,231,236,234,230,237,235,229,234,235,231,235,236,232,237,238,230,235,236,231,236,238,231,237,240,229,237,241,223,232,238,191,206,213,164,184,191,146,165,172,137,156,163,134,149,159,128,140,153,121,133,143,149,162,166,216,228,229,234,241,239,235,240,238,237,240,239,195,212,224,188,202,215,199,211,224,200,211,223,209,217,227,223,227,231,213,213,211,211,209,206,216,213,214,220,222,222,219,226,225,210,221,219,209,219,223,211,221,225,216,225,230,220,229,233,225,234,237,226,236,239,225,237,241,218,231,237,183,204,208,175,198,203,181,200,207,178,194,202,186,197,211,170,178,196,142,151,164,185,195,202,219,230,233,231,240,238,234,241,239,236,240,239,193,207,222,191,202,217,202,211,224,214,217,234,223,225,241,214,219,227,203,208,208,171,174,174,177,180,183,207,213,214,174,184,188,98,112,121,93,114,126,101,121,132,111,129,139,122,138,147,137,152,161,153,167,174,202,216,220,223,236,237,218,232,235,220,233,238,223,234,240,217,226,233,221,228,237,212,219,229,196,203,212,222,230,237,219,227,234,221,230,233,232,239,242,235,241,242,113,130,152,111,125,147,113,125,141,125,131,151,138,145,165,170,182,193,191,201,205,190,199,204,208,219,226,216,230,234,158,172,183,54,71,92,45,70,91,49,73,91,53,73,90,66,84,98,102,114,129,159,168,179,221,227,233,234,239,241,233,237,241,227,231,237,223,228,233,207,211,217,202,208,212,211,218,220,212,219,223,199,206,214,179,186,196,188,197,205,211,221,227,221,231,234,61,81,108,69,86,114,63,79,100,68,85,102,123,141,155,139,155,164,151,157,164,195,200,207,214,228,234,206,223,228,163,180,190,103,121,138,95,112,131,101,117,135,138,151,168,181,192,207,207,212,223,221,222,232,219,219,227,205,203,212,183,186,195,158,166,174,147,154,163,131,138,147,125,133,140,130,139,144,136,146,152,133,142,151,128,137,147,138,153,160,182,197,203,197,212,216,40,53,77,58,70,94,85,98,116,127,144,153,132,151,156,96,107,110,119,115,118,163,158,161,173,180,182,184,194,197,182,194,198,181,193,200,183,194,202,198,209,217,218,228,236,200,210,217,174,181,186,159,165,172,145,150,159,132,136,149,116,125,138,98,111,123,94,106,118,99,111,123,105,118,128,107,121,130,122,135,145,138,151,161,150,164,174,157,174,184,188,206,213,185,203,208,13,15,35,26,29,47,134,140,151,206,216,220,138,150,150,118,123,123,141,133,134,172,162,162,181,181,180,207,209,211,220,224,225,228,234,233,224,234,232,230,241,240,226,238,238,176,189,190,144,159,163,138,154,162,142,158,170,145,163,177,154,171,187,149,165,182,149,165,182,154,171,187,157,174,189,160,177,191,173,190,204,187,204,217,190,207,218,178,196,208,165,183,193,157,175,183,5,5,24,58,62,79,200,207,217,225,232,239,197,205,212,199,207,211,212,212,218,226,224,229,229,230,237,233,236,246,232,238,245,230,238,239,209,221,220,223,238,239,221,238,241,210,228,234,198,217,228,180,200,214,193,216,230,188,213,229,189,212,231,194,214,234,192,212,232,184,204,224,172,193,212,171,191,209,161,181,197,144,165,179,136,156,169,131,146,161,128,143,158,138,154,165,39,45,71,145,155,179,190,204,222,186,196,216,184,197,217,192,211,229,194,211,230,194,208,227,194,206,227,191,203,228,192,207,228,190,207,221,177,193,207,180,198,215,154,176,193,147,169,188,145,161,184,156,171,195,146,163,186,113,133,156,114,137,161,132,157,180,126,150,173,111,135,158,92,115,138,91,112,135,93,114,133,94,116,131,105,125,140,121,133,151,129,141,158,129,142,156,122,135,161,162,179,207,143,160,194,137,154,189,131,152,187,128,152,190,127,150,192,130,150,193,131,150,192,128,147,190,127,147,189,129,149,189,129,149,188,124,145,186,104,126,163,100,122,154,102,120,154,118,134,170,112,128,163,94,109,145,94,112,148,94,117,153,87,112,144,83,103,136,80,97,130,83,103,134,93,111,139,101,117,141,108,121,144,115,125,146,121,133,148,130,144,156,73,87,109,76,90,113,77,90,122,80,93,127,84,98,134,87,102,142,87,102,147,90,105,150,94,111,152,102,119,160,107,124,165,113,131,172,115,137,181,118,136,186,118,132,180,120,133,175,115,136,172,110,133,168,106,127,163,100,119,155,95,109,148,85,101,139,79,97,132,80,92,127,80,94,129,77,100,133,80,100,129,82,98,122,92,104,126,113,119,138,125,135,146,136,149,156,13,25,41,3,11,25,9,16,35,18,26,48,18,26,52,21,25,56,20,25,58,22,30,61,26,36,62,34,43,70,42,51,77,48,59,87,52,69,106,60,75,121,66,77,126,70,79,126,71,87,127,72,88,126,67,81,120,60,72,112,55,67,106,53,68,104,53,69,103,57,69,102,57,71,105,57,78,110,72,89,115,87,100,119,104,113,128,120,124,136,130,136,141,137,146,149,36,46,55,11,16,20,8,13,19,32,44,53,36,45,58,22,25,41,8,11,30,3,8,24,1,4,17,0,2,15,0,2,15,0,4,20,6,13,42,5,18,56,1,19,60,3,23,62,13,29,71,24,38,81,21,33,77,21,31,76,21,38,78,22,44,79,30,50,83,39,58,90,57,70,101,85,90,118,113,115,138,123,123,138,116,115,125,122,123,128,134,139,137,153,160,158,35,41,45,26,27,26,13,19,18,27,41,41,71,81,84,70,70,76,49,50,57,27,31,37,15,15,21,5,5,11,2,2,7,0,0,7,17,17,35,57,64,91,31,50,78,10,36,62,4,30,60,4,30,62,7,30,63,14,35,69,25,43,74,41,55,83,62,71,99,86,97,123,122,124,146,144,131,149,132,120,135,114,105,114,117,111,116,132,134,133,146,152,146,172,179,175,16,15,17,13,10,9,4,10,8,3,12,11,45,44,46,65,52,57,54,43,47,36,33,35,18,18,20,4,4,7,2,2,4,0,1,3,7,8,15,118,117,134,161,158,179,131,128,148,112,112,131,105,105,125,105,103,124,109,105,127,118,107,126,138,115,133,154,126,144,151,126,141,127,106,116,105,86,91,106,94,97,120,116,116,129,130,129,142,147,144,164,172,165,184,194,190,40,40,35,12,10,7,0,3,3,0,4,4,12,6,7,30,12,17,32,12,17,21,10,12,7,6,7,2,1,3,2,1,2,3,2,3,0,0,2,68,58,64,182,128,146,205,130,148,196,127,144,194,123,141,195,119,137,187,113,129,172,110,122,150,96,106,123,75,83,103,66,69,95,71,70,104,93,88,122,118,113,129,132,126,132,141,135,152,162,158,171,182,176,185,197,194,69,77,64,26,29,21,1,1,1,1,1,2,4,1,0,12,2,5,18,3,9,12,2,5,4,1,2,2,0,0,2,0,0,4,0,1,1,1,1,32,12,11,153,45,59,203,47,68,195,46,67,191,48,69,179,50,67,155,49,59,119,42,49,91,38,42,81,48,46,94,77,71,117,110,102,125,126,116,125,128,120,129,135,128,144,153,147,162,176,171,173,187,183,184,198,196,83,94,82,47,52,43,1,1,1,2,1,2,2,0,0,5,1,2,7,1,5,4,0,2,1,0,0,1,0,0,1,0,0,3,0,0,1,2,0,27,3,2,142,25,38,205,32,54,198,25,46,169,25,43,121,25,36,85,29,34,74,41,39,85,66,56,102,92,82,121,113,105,128,124,115,122,126,115,121,127,118,132,139,131,147,157,150,165,179,174,176,191,187,186,201,199,92,102,93,54,60,50,6,7,3,3,2,1,2,2,0,1,3,1,1,3,3,1,2,2,1,1,1,1,0,0,1,0,0,1,1,1,0,3,2,15,1,0,102,19,28,157,31,47,117,17,23,74,13,12,56,27,22,74,58,55,99,90,81,115,115,99,122,126,111,124,124,112,123,123,113,125,130,119,128,135,126,136,145,137,148,159,151,162,176,171,177,192,188,188,202,201,87,99,89,43,51,37,19,23,11,11,12,4,8,10,2,5,11,4,2,10,4,2,7,2,3,4,1,3,4,1,3,4,1,2,3,2,0,6,6,4,5,2,42,13,13,71,21,24,53,27,25,57,50,41,80,77,62,113,98,82,132,113,101,134,126,113,123,126,112,116,125,111,120,128,115,131,138,126,139,148,137,143,154,145,156,168,161,169,184,179,182,197,193,188,202,201,82,96,82,46,57,36,36,44,22,31,35,17,27,30,15,22,28,15,17,26,13,16,23,12,18,21,12,19,21,13,20,22,14,19,23,15,19,27,20,23,31,21,37,40,27,64,55,45,87,70,67,104,88,81,116,102,85,128,112,88,139,121,105,131,122,110,117,122,107,115,127,112,123,133,119,131,139,127,139,149,138,148,160,151,159,172,164,174,189,183,185,200,196,187,202,200,85,101,83,62,75,48,58,67,38,55,61,37,51,56,35,47,53,33,46,53,34,48,55,38,49,55,40,51,56,41,53,58,44,55,62,46,59,67,45,68,71,48,81,84,59,104,96,74,116,103,83,127,109,92,133,116,97,127,121,97,127,127,107,118,124,106,114,125,108,122,131,117,129,136,123,136,145,133,141,152,141,149,162,153,158,171,163,168,183,178,180,195,191,186,200,199} diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h new file mode 100644 index 0000000..09d0ca3 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h @@ -0,0 +1,43 @@ +#define CONV1_IM_DIM 32 +#define CONV1_IM_CH 3 +#define CONV1_KER_DIM 5 +#define CONV1_PADDING 2 +#define CONV1_STRIDE 1 +#define CONV1_OUT_CH 32 +#define CONV1_OUT_DIM 32 + +#define POOL1_KER_DIM 3 +#define POOL1_STRIDE 2 +#define POOL1_PADDING 0 +#define POOL1_OUT_DIM 16 + +#define CONV2_IM_DIM 16 +#define CONV2_IM_CH 32 +#define CONV2_KER_DIM 5 +#define CONV2_PADDING 2 +#define CONV2_STRIDE 1 +#define CONV2_OUT_CH 16 +#define CONV2_OUT_DIM 16 + +#define POOL2_KER_DIM 3 +#define POOL2_STRIDE 2 +#define POOL2_PADDING 0 +#define POOL2_OUT_DIM 8 + +#define CONV3_IM_DIM 8 +#define CONV3_IM_CH 16 +#define CONV3_KER_DIM 5 +#define CONV3_PADDING 2 +#define CONV3_STRIDE 1 +#define CONV3_OUT_CH 32 +#define CONV3_OUT_DIM 8 + +#define POOL3_KER_DIM 3 +#define POOL3_STRIDE 2 +#define POOL3_PADDING 0 +#define POOL3_OUT_DIM 4 + +#define IP1_DIM 4*4*32 +#define IP1_IM_DIM 4 +#define IP1_IM_CH 32 +#define IP1_OUT 10 diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h new file mode 100644 index 0000000..8d92d21 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h @@ -0,0 +1,26 @@ +#define CONV1_WT {-9,-1,2,6,-4,6,4,-11,8,-9,-11,10,-12,5,15,11,-1,-1,33,-25,-18,47,-35,-23,25,-27,-5,0,-4,9,2,-5,0,34,-25,-21,55,-40,-33,34,-32,-16,5,-7,2,-21,16,14,-4,5,3,14,-10,-7,3,-10,-2,-8,5,8,-29,23,12,-25,15,8,-15,4,7,-16,5,8,-13,17,12,2,-4,-1,-1,-10,9,6,-4,21,11,0,12,-10,-9,-4,13,10,12,19,11,27,0,-5,11,-21,-26,-28,-7,3,-15,16,14,26,-22,-25,-8,-29,-24,-23,0,6,-13,13,25,0,-21,-18,-3,-21,-19,-13,11,14,4,13,18,-4,6,16,-1,-10,-14,-7,12,9,5,13,8,-4,9,10,-9,-4,7,-3,7,7,-12,7,3,0,-1,-7,2,-8,-5,9,-3,6,-4,7,-10,-25,7,-7,-7,10,2,14,-4,2,17,-9,5,-3,7,-10,-25,4,-10,-8,0,0,16,-7,11,25,-14,13,4,7,-12,-23,5,-16,-17,8,0,11,2,13,21,-11,9,-3,2,-9,-9,-3,-14,-11,1,-1,6,-6,6,14,-1,16,11,7,3,-14,21,6,-6,17,13,4,1,7,-3,-6,2,2,27,13,-5,18,0,-7,-6,-4,2,-24,-11,0,-18,-8,6,24,8,-14,11,-6,-8,-8,0,12,-22,-2,13,-15,-3,7,29,6,-16,10,-6,-4,-12,-7,11,-26,-14,3,-10,-8,0,16,5,-8,-5,-5,3,-15,-2,23,-17,-5,17,1,1,12,10,3,-5,-7,-18,-7,-3,-4,2,3,6,4,4,2,-7,17,20,12,-23,-27,-15,-3,3,6,5,15,6,-2,2,-5,22,22,11,-26,-30,-19,-6,-5,3,10,12,6,2,1,-3,20,14,4,-15,-26,-18,0,-9,1,14,8,6,1,-7,-9,8,11,6,-10,-13,-11,-4,-4,8,2,5,17,-9,0,11,-9,-11,21,6,13,39,-7,1,30,2,12,36,-11,-1,28,-2,-25,-6,6,-16,-6,-9,-34,-24,3,-17,-15,2,-20,-11,0,-13,-11,25,13,6,0,-15,-20,16,7,-11,7,-3,-10,-5,-2,-6,14,22,12,-16,-5,-12,7,23,7,-10,5,-2,-10,-1,-9,7,21,8,-19,-2,-13,2,21,3,-15,9,-2,-4,-2,-2,-12,2,13,-19,1,6,0,16,-1,5,8,-28,11,-2,-4,-10,-1,21,-30,-4,22,-8,14,9,11,14,-21,20,-9,-23,0,-4,19,-28,-9,31,-30,-1,12,3,14,-11,30,3,-24,3,-8,6,-22,-9,31,-29,2,26,-5,11,8,24,2,-36,24,3,-9,-6,-17,4,-8,-8,12,1,-1,5,3,-12,15,-6,-2,-1,0,15,-11,-18,6,-18,-10,6,3,6,-3,3,-12,13,-14,-1,43,-23,-3,52,-16,-11,28,-8,4,-6,5,-11,16,-6,-20,32,-28,-24,38,-31,-22,20,-16,5,-13,7,-2,5,3,-6,17,-10,-8,22,-13,-5,13,0,11,-16,14,-3,-14,6,3,-4,4,4,-2,2,-3,-9,5,2,1,-2,-10,-6,-3,-17,-2,1,-19,2,1,-14,8,11,14,3,7,1,-13,-13,2,-1,-3,-9,0,-5,-18,4,0,18,3,9,15,-10,-8,10,-12,-18,5,-3,-16,-10,0,-14,5,4,14,14,-1,10,16,-6,-2,14,-1,-12,8,2,-18,-13,-1,17,-2,2,24,-4,-3,17,8,-1,12,9,-6,-3,-2,-9,3,-2,-13,-1,-5,-17,-5,-7,-16,-7,-8,-14,-9,3,-9,-1,0,-13,-7,4,-9,-7,3,-6,-8,-2,-4,-7,5,-7,-4,1,-8,-11,10,6,-3,14,12,-1,6,10,-2,0,-12,-16,-3,-9,-19,0,1,-12,9,12,-2,1,10,-1,10,4,-8,6,3,-11,11,14,1,12,19,8,3,16,9,-7,-1,4,-11,-1,3,1,12,8,7,15,13,-5,-2,4,-7,-5,1,-8,-3,2,1,10,9,-1,8,9,-11,-9,-2,0,-1,6,-14,-13,-6,1,3,10,3,4,11,-1,-5,5,7,4,10,-14,-17,-10,-12,-13,-6,-11,-14,-6,1,-6,1,2,-1,1,-5,-7,-3,-2,-4,1,-11,-13,-9,-12,-16,-12,-2,-1,-2,-9,-5,-4,-7,-3,3,-1,-3,8,9,-2,1,8,11,13,5,14,17,1,10,17,-1,3,18,0,-6,0,-1,0,3,4,13,16,-1,8,14,-4,2,14,-16,-20,-14,-3,-3,0,13,21,25,5,11,14,-5,-2,9,1,-5,2,-6,-9,-14,-7,-4,-8,-10,-9,-13,-10,-12,-12,7,-1,-2,-5,2,-14,-5,3,-6,1,9,3,-8,3,-1,-9,2,0,-12,-4,-21,6,17,8,17,28,22,-5,6,2,-15,-8,-7,8,21,-3,2,20,-5,-1,16,-8,7,17,3,0,6,1,11,26,0,-22,-4,-33,-36,-16,-40,-2,14,1,2,10,5,1,17,-10,-16,3,-22,-22,-1,-14,-9,10,6,-7,7,7,10,-8,5,-3,-4,-1,-7,-7,-7,1,0,-2,-7,11,9,5,-2,2,12,14,16,12,7,2,0,-9,-23,-14,-8,-23,-1,-11,-14,-7,-9,-7,14,11,7,44,35,19,34,38,12,1,3,9,-6,-4,8,-32,-28,-19,-41,-45,-37,-14,-17,-17,-7,4,-3,-5,8,8,3,16,21,8,14,24,-3,-5,6,-11,-15,-18,-8,-12,-12,-6,-14,-8,9,-6,1,16,3,11,3,3,-8,-5,0,-6,-13,-13,-13,-6,-15,-15,6,-5,-4,9,16,5,1,14,5,-4,7,-1,-12,-11,-18,0,-6,-12,5,14,0,-1,13,2,2,18,6,-9,-4,-16,0,-3,-17,4,12,0,-1,13,2,0,16,6,-6,1,-9,-5,-8,-19,18,-1,-4,16,-2,-6,18,-1,-4,9,-4,1,-12,-13,-4,9,-3,-9,6,-4,-14,15,5,-2,-5,-5,-1,-20,-9,-3,16,2,-5,12,3,-7,15,7,1,-12,-7,-2,-15,-2,2,18,7,-1,10,2,-5,-1,-8,-8,-18,-15,-7,-2,7,9,-15,-15,-17,-7,-6,-7,-12,-12,-6,-17,-12,-6,9,14,12,13,7,6,3,-3,2,-6,-7,1,-7,-4,3,-11,-12,-6,12,11,6,-4,-3,-2,-15,-12,-4,-7,-4,3,-9,-9,-4,15,17,12,-3,1,2,-18,-13,-6,4,5,10,6,1,5,9,14,8,-6,1,3,-21,-15,-7,-2,-1,5,4,-1,2,4,17,14,-4,4,9,-24,-20,-11,-7,-7,3,-2,-6,1,5,9,-10,6,9,-12,12,11,-7,4,1,-15,11,9,-6,25,15,5,21,13,5,23,14,7,13,2,-3,17,10,6,-1,-10,-2,-20,-21,-14,-11,-11,-2,-11,-12,-3,-16,-15,-3,-4,-14,6,-16,-19,-1,-3,-2,13,-1,-3,12,-6,-10,8,0,-5,10,-11,-10,4,-4,-1,8,-11,-5,3,-6,-1,8,-8,-15,0,-3,0,9,4,11,14,-3,3,4,-15,-9,-6,-12,-14,-1,-18,-8,-1,-26,-12,-8,-28,-12,-9,-30,-13,-8,10,-1,-6,15,17,5,11,22,8,15,24,8,17,25,12,10,-5,-9,4,4,-5,1,10,1,2,4,-8,6,7,-7,5,-10,-6,-1,-5,-3,3,8,10,1,4,-2,-1,0,-8,2,-8,3,0,-6,9,1,-2,-8,6,1,-3,1,-10,6,5,-6,7,-8,-12,0,11,17,-4,-7,-1,-12,1,-2,9,11,2,17,-35,-32,-21,38,52,20,-27,-17,-30,4,2,17,18,10,19,-44,-34,-34,43,59,28,-25,-17,-31,6,0,16,10,4,18,-31,-27,-22,27,31,16,-10,-9,-16,3,-6,6,-2,-11,15,10,0,14,-2,-8,-8,0,-7,-7,13,0,11,2,-7,3,10,4,3,0,-2,-14,-1,-1,-16,-1,3,-6,8,-4,3,12,4,2,4,1,-17,7,10,-8,0,10,-2,-3,-15,0,10,4,8,-10,-13,-24,-7,-2,-16,0,8,-3,-6,-6,7,7,11,13,2,9,-6,-4,11,-15,2,22,0,2,-4,-2,-10,-12,-5,24,15,25,-1,-4,-2,-11,-1,-3,7,11,5,-16,-17,-23,-29,-35,-30,53,45,54,-11,-9,-12,-3,5,4,44,39,36,-45,-51,-51,-19,-28,-16,25,24,28,-15,0,-12,7,1,2,44,42,40,-36,-41,-41,5,0,3,-1,18,5,-17,-15,-15,7,8,14,11,3,4,1,-11,-8,10,-1,-2,-5,-10,-3,6,6,10,5,9,9,-6,3,0,-14,-21,-16,-40,-39,-26,0,4,16,15,20,24,-14,-7,-5,3,-5,1,-13,-12,0,-16,-11,6,4,7,20,-11,-9,-1,11,-4,7,14,7,22,-14,-14,5,-7,-6,12,-4,-9,4,18,-6,5,14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+ +#define CONV1_BIAS {-49,-18,-7,-20,-12,-15,7,2,-10,-84,-72,-65,-53,-6,-87,-63,-64,-28,-28,-4,-3,-10,-52,-15,-5,-7,-31,-44,-102,-19,-5,-65} + +#define CONV2_WT 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+ +#define CONV2_BIAS {55,50,34,43,-37,35,-21,10,35,-53,-76,7,14,-1,92,20} + +#define CONV3_WT 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+ +#define CONV3_BIAS {18,36,-46,-45,64,8,13,-19,28,1,14,-57,23,20,-2,32,48,-11,85,73,-7,52,125,33,125,13,92,-72,89,-1,11,70} + +#define IP1_WT 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34,-1,-20} + +#define IP1_BIAS {30,-121,-51,77,40,20,46,-35,28,-33} + +#define CONV1_BIAS_LSHIFT 6 +#define CONV1_OUT_RSHIFT 9 +#define CONV2_BIAS_LSHIFT 4 +#define CONV2_OUT_RSHIFT 9 +#define CONV3_BIAS_LSHIFT 1 +#define CONV3_OUT_RSHIFT 7 +#define IP1_BIAS_LSHIFT 1 +#define IP1_OUT_RSHIFT 8 +#define INPUT_MEAN_SHIFT {125,123,114} +#define INPUT_RIGHT_SHIFT {8,8,8} diff --git a/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt new file mode 100644 index 0000000..774fef8 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_cifar10 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/NN/Examples/ARM/arm_nn_examples/gru/EventRecorderStub.scvd b/NN/Examples/ARM/arm_nn_examples/gru/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/EventRecorderStub.scvd @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="utf-8"?> + +<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd"> + +<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component--> + <events> + </events> + +</component_viewer> diff --git a/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h b/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..ddf354d --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,44 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// <h>Event Recorder + +// <o>Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 <131072=>131072 <262144=>262144 <524288=>524288 +// <1048576=>1048576 +// <i>Configure size of Event Record Buffer (each record is 16 bytes) +// <i>Must be 2^n (min=8, max=1048576) +#define EVENT_RECORD_COUNT 64U + +// <o>Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// <i>Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 1 + +// <h>SysTick Configuration +// <i>Configure values when Time Stamp Source is set to SysTick + +// <o>SysTick Input Clock Frequency [Hz] <1-1000000000> +// <i>Defines SysTick input clock (typical identical with processor clock) +#define SYSTICK_CLOCK 100000000U + +// <o>SysTick Interrupt Period [us] <1-1000000000> +// <i>Defines time period of the SysTick timer interrupt +#define SYSTICK_PERIOD_US 1000U + +// </h> + +// </h> + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..b3b3076 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_EVR /* Compiler I/O: STDOUT EVR */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..2df6879 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..f29db07 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..6cd8e76 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,22 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_gru' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp new file mode 100644 index 0000000..340dc33 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp @@ -0,0 +1,221 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_gru.cpp +* +* Description: Gated Recurrent Unit Example +* +* Target Processor: Cortex-M4/Cortex-M7 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of Arm LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +/** + * @ingroup groupExamples + */ + +/** + * @defgroup GRUExample Gated Recurrent Unit Example + * + * \par Description: + * \par + * Demonstrates a gated recurrent unit (GRU) example with the use of fully-connected, + * Tanh/Sigmoid activation functions. + * + * \par Model definition: + * \par + * GRU is a type of recurrent neural network (RNN). It contains two sigmoid gates and one hidden + * state. + * \par + * The computation can be summarized as: + * <pre>z[t] = sigmoid( W_z ⋅ {h[t-1],x[t]} ) + * r[t] = sigmoid( W_r ⋅ {h[t-1],x[t]} ) + * n[t] = tanh( W_n ⋅ [r[t] × {h[t-1], x[t]} ) + * h[t] = (1 - z[t]) × h[t-1] + z[t] × n[t] </pre> + * \image html GRU.gif "Gate Recurrent Unit Diagram" + * + * \par Variables Description: + * \par + * \li \c update_gate_weights, \c reset_gate_weights, \c hidden_state_weights are weights corresponding to update gate (W_z), reset gate (W_r), and hidden state (W_n). + * \li \c update_gate_bias, \c reset_gate_bias, \c hidden_state_bias are layer bias arrays + * \li \c test_input1, \c test_input2, \c test_history are the inputs and initial history + * + * \par + * The buffer is allocated as: + * \par + * | reset | input | history | update | hidden_state | + * \par + * In this way, the concatination is automatically done since (reset, input) and (input, history) + * are physically concatinated in memory. + * \par + * The ordering of the weight matrix should be adjusted accordingly. + * + * + * + * \par CMSIS DSP Software Library Functions Used: + * \par + * - arm_fully_connected_mat_q7_vec_q15_opt() + * - arm_nn_activations_direct_q15() + * - arm_mult_q15() + * - arm_offset_q15() + * - arm_sub_q15() + * - arm_copy_q15() + * + * <b> Refer </b> + * \link arm_nnexamples_gru.cpp \endlink + * + */ + +#include <stdio.h> +#include <stdlib.h> +#include <math.h> +#include "arm_nnexamples_gru_test_data.h" +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif +#endif + +#define DIM_HISTORY 32 +#define DIM_INPUT 32 +#define DIM_VEC 64 + +#define USE_X4 + +#ifndef USE_X4 +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X2; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X2; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X2; +#else +static q7_t update_gate_weights[DIM_VEC * DIM_HISTORY] = UPDATE_GATE_WEIGHT_X4; +static q7_t reset_gate_weights[DIM_VEC * DIM_HISTORY] = RESET_GATE_WEIGHT_X4; +static q7_t hidden_state_weights[DIM_VEC * DIM_HISTORY] = HIDDEN_STATE_WEIGHT_X4; +#endif + +static q7_t update_gate_bias[DIM_HISTORY] = UPDATE_GATE_BIAS; +static q7_t reset_gate_bias[DIM_HISTORY] = RESET_GATE_BIAS; +static q7_t hidden_state_bias[DIM_HISTORY] = HIDDEN_STATE_BIAS; + +static q15_t test_input1[DIM_INPUT] = INPUT_DATA1; +static q15_t test_input2[DIM_INPUT] = INPUT_DATA2; +static q15_t test_history[DIM_HISTORY] = HISTORY_DATA; + +q15_t scratch_buffer[DIM_HISTORY * 4 + DIM_INPUT]; + +void gru_example(q15_t * scratch_input, uint16_t input_size, uint16_t history_size, + q7_t * weights_update, q7_t * weights_reset, q7_t * weights_hidden_state, + q7_t * bias_update, q7_t * bias_reset, q7_t * bias_hidden_state) +{ + q15_t *reset = scratch_input; + q15_t *input = scratch_input + history_size; + q15_t *history = scratch_input + history_size + input_size; + q15_t *update = scratch_input + 2 * history_size + input_size; + q15_t *hidden_state = scratch_input + 3 * history_size + input_size; + + // reset gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_reset, input_size + history_size, history_size, 0, 15, bias_reset, + reset, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_reset, input_size + history_size, history_size, 0, 15, + bias_reset, reset, NULL); +#endif + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(reset, history_size, 0, ARM_SIGMOID); + arm_mult_q15(history, reset, reset, history_size); + + // update gate calculation + // the range of the output can be adjusted with bias_shift and output_shift +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(input, weights_update, input_size + history_size, history_size, 0, 15, + bias_update, update, NULL); +#endif + + // sigmoid function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(update, history_size, 0, ARM_SIGMOID); + + // hidden state calculation +#ifndef USE_X4 + arm_fully_connected_mat_q7_vec_q15(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#else + arm_fully_connected_mat_q7_vec_q15_opt(reset, weights_hidden_state, input_size + history_size, history_size, 0, 15, + bias_hidden_state, hidden_state, NULL); +#endif + + // tanh function, the size of the integer bit-width should be consistent with out_shift + arm_nn_activations_direct_q15(hidden_state, history_size, 0, ARM_TANH); + arm_mult_q15(update, hidden_state, hidden_state, history_size); + + // we calculate z - 1 here + // so final addition becomes substraction + arm_offset_q15(update, 0x8000, update, history_size); + // multiply history + arm_mult_q15(history, update, update, history_size); + // calculate history_out + arm_sub_q15(hidden_state, update, history, history_size); + + return; +} + +int main() +{ + #ifdef RTE_Compiler_EventRecorder + EventRecorderInitialize (EventRecordAll, 1); // initialize and start Event Recorder + #endif + + printf("Start GRU execution\n"); + int input_size = DIM_INPUT; + int history_size = DIM_HISTORY; + + // copy over the input data + arm_copy_q15(test_input1, scratch_buffer + history_size, input_size); + arm_copy_q15(test_history, scratch_buffer + history_size + input_size, history_size); + + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete first iteration on GRU\n"); + + arm_copy_q15(test_input2, scratch_buffer + history_size, input_size); + gru_example(scratch_buffer, input_size, history_size, + update_gate_weights, reset_gate_weights, hidden_state_weights, + update_gate_bias, reset_gate_bias, hidden_state_bias); + printf("Complete second iteration on GRU\n"); + + return 0; +} diff --git a/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvoptx b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvoptx new file mode 100644 index 0000000..8aa1a94 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvoptx @@ -0,0 +1,737 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>ARMCM0</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>10000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM0_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + 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<Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <ScvdPack> + <Filename>C:\KEIL_V5\ARM\PACK\Keil\ARM_Compiler\1.3.3\EventRecorder.scvd</Filename> + <Type>Keil.ARM_Compiler.1.3.3</Type> + <SubType>1</SubType> + </ScvdPack> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>1</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + 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<CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + 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+ <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM7_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile></sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Group> + <GroupName>Source Files</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>1</GroupNumber> + <FileNumber>1</FileNumber> + <FileType>8</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>.\arm_nnexamples_gru.cpp</PathWithFileName> + <FilenameWithoutPath>arm_nnexamples_gru.cpp</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>Documentation</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>0</RteFlg> + <File> + <GroupNumber>2</GroupNumber> + <FileNumber>2</FileNumber> + <FileType>5</FileType> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <bDave2>0</bDave2> + <PathWithFileName>.\readme.txt</PathWithFileName> + <FilenameWithoutPath>readme.txt</FilenameWithoutPath> + <RteFlg>0</RteFlg> + <bShared>0</bShared> + </File> + </Group> + + <Group> + <GroupName>::CMSIS</GroupName> + <tvExp>0</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + + <Group> + <GroupName>::Compiler</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + + <Group> + <GroupName>::Device</GroupName> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <cbSel>0</cbSel> + <RteFlg>1</RteFlg> + </Group> + +</ProjectOpt> diff --git a/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvprojx b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvprojx new file mode 100644 index 0000000..801893e --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.uvprojx @@ -0,0 +1,1856 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd"> + + <SchemaVersion>2.1</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Targets> + <Target> + <TargetName>ARMCM0</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>ARMCM0</Device> + <Vendor>ARM</Vendor> + <PackID>ARM.CMSIS.5.3.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> + <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(10000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Flash\NEW_DEVICE.flm))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:ARMCM0$Device\Include\ARMCM0.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:ARMCM0$SVD\ARMCM0.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\ARMCM0_debug\</OutputDirectory> + <OutputName>arm_nnexample_gru</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\ARMCM0_debug\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> </SimDllArguments> + <SimDlgDll>DARMCM1.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM0</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments> </TargetDllArguments> + <TargetDlgDll>TARMCM1.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M0"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <nSecure>0</nSecure> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + <vShortEn>1</vShortEn> + <vShortWch>1</vShortWch> + <v6Lto>0</v6Lto> + <v6WtE>0</v6WtE> + <v6Rtti>0</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define>ARM_MATH_CM0</Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>1</interw> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <thumb>0</thumb> + <SplitLS>0</SplitLS> + <SwStkChk>0</SwStkChk> + <NoWarn>0</NoWarn> + <uSurpInc>0</uSurpInc> + <useXO>0</useXO> + <uClangAs>0</uClangAs> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + <LDads> + <umfTarg>0</umfTarg> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <noStLib>0</noStLib> + <RepFail>1</RepFail> + <useFile>0</useFile> + <TextAddressRange>0x00000000</TextAddressRange> + <DataAddressRange>0x20000000</DataAddressRange> + <pXoBase></pXoBase> + <ScatterFile></ScatterFile> + <IncludeLibs></IncludeLibs> + <IncludeLibsPath></IncludeLibsPath> + <Misc></Misc> + <LinkerInputFile></LinkerInputFile> + <DisabledWarnings></DisabledWarnings> + </LDads> + </TargetArmAds> + </TargetOption> + <Groups> + <Group> + <GroupName>Source Files</GroupName> + <Files> + <File> + <FileName>arm_nnexamples_gru.cpp</FileName> + <FileType>8</FileType> + <FilePath>.\arm_nnexamples_gru.cpp</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>Documentation</GroupName> + <Files> + <File> + <FileName>readme.txt</FileName> + <FileType>5</FileType> + <FilePath>.\readme.txt</FilePath> + </File> + </Files> + </Group> + <Group> + <GroupName>::CMSIS</GroupName> + </Group> + <Group> + <GroupName>::Compiler</GroupName> + <GroupOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>2</AlwaysBuild> + <GenerateAssemblyFile>2</GenerateAssemblyFile> + <AssembleAssemblyFile>2</AssembleAssemblyFile> + <PublicsOnly>2</PublicsOnly> + <StopOnExitCode>11</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <GroupArmAds> + <Cads> + <interw>2</interw> + <Optim>0</Optim> + <oTime>2</oTime> + <SplitLS>2</SplitLS> + <OneElfS>2</OneElfS> + <Strict>2</Strict> + <EnumInt>2</EnumInt> + <PlainCh>2</PlainCh> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <wLevel>0</wLevel> + <uThumb>2</uThumb> + <uSurpInc>2</uSurpInc> + <uC99>2</uC99> + <useXO>2</useXO> + <v6Lang>0</v6Lang> + <v6LangP>0</v6LangP> + <vShortEn>2</vShortEn> + <vShortWch>2</vShortWch> + <v6Lto>2</v6Lto> + <v6WtE>2</v6WtE> + <v6Rtti>2</v6Rtti> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Cads> + <Aads> + <interw>2</interw> + <Ropi>2</Ropi> + <Rwpi>2</Rwpi> + <thumb>2</thumb> + <SplitLS>2</SplitLS> + <SwStkChk>2</SwStkChk> + <NoWarn>2</NoWarn> + <uSurpInc>2</uSurpInc> + <useXO>2</useXO> + <uClangAs>2</uClangAs> + <VariousControls> + <MiscControls></MiscControls> + <Define></Define> + <Undefine></Undefine> + <IncludePath></IncludePath> + </VariousControls> + </Aads> + </GroupArmAds> + </GroupOption> + </Group> + <Group> + <GroupName>::Device</GroupName> + </Group> + </Groups> + </Target> + <Target> + <TargetName>ARMCM3</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>ARMCM3</Device> + <Vendor>ARM</Vendor> + <PackID>ARM.CMSIS.5.3.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> + <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(10000000) ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Flash\NEW_DEVICE.flm))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:ARMCM3$Device\Include\ARMCM3.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:ARMCM3$SVD\ARMCM3.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\ARMCM3_debug\</OutputDirectory> + <OutputName>arm_nnexample_gru</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\ARMCM3_debug\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopA1X>0</nStopA1X> + <nStopA2X>0</nStopA2X> + </AfterMake> + <SelectedForBatchBuild>0</SelectedForBatchBuild> + <SVCSIdString></SVCSIdString> + </TargetCommonOption> + <CommonProperty> + <UseCPPCompiler>0</UseCPPCompiler> + <RVCTCodeConst>0</RVCTCodeConst> + <RVCTZI>0</RVCTZI> + <RVCTOtherData>0</RVCTOtherData> + <ModuleSelection>0</ModuleSelection> + <IncludeInBuild>1</IncludeInBuild> + <AlwaysBuild>0</AlwaysBuild> + <GenerateAssemblyFile>0</GenerateAssemblyFile> + <AssembleAssemblyFile>0</AssembleAssemblyFile> + <PublicsOnly>0</PublicsOnly> + <StopOnExitCode>3</StopOnExitCode> + <CustomArgument></CustomArgument> + <IncludeLibraryModules></IncludeLibraryModules> + <ComprImg>1</ComprImg> + </CommonProperty> + <DllOption> + <SimDllName>SARMCM3.DLL</SimDllName> + <SimDllArguments> </SimDllArguments> + <SimDlgDll>DCM.DLL</SimDlgDll> + <SimDlgDllArguments>-pCM3</SimDlgDllArguments> + <TargetDllName>SARMCM3.DLL</TargetDllName> + <TargetDllArguments></TargetDllArguments> + <TargetDlgDll>TCM.DLL</TargetDlgDll> + <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments> + </DllOption> + <DebugOption> + <OPTHX> + <HexSelection>1</HexSelection> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + <Oh166RecLen>16</Oh166RecLen> + </OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3>"" ()</Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + <AdsLszi>1</AdsLszi> + <AdsLtoi>1</AdsLtoi> + <AdsLsun>1</AdsLsun> + <AdsLven>1</AdsLven> + <AdsLsxf>1</AdsLsxf> + <RvctClst>0</RvctClst> + <GenPPlst>0</GenPPlst> + <AdsCpuType>"Cortex-M3"</AdsCpuType> + <RvctDeviceName></RvctDeviceName> + <mOS>0</mOS> + <uocRom>0</uocRom> + <uocRam>0</uocRam> + <hadIROM>1</hadIROM> + <hadIRAM>1</hadIRAM> + <hadXRAM>0</hadXRAM> + <uocXRam>0</uocXRam> + <RvdsVP>0</RvdsVP> + <hadIRAM2>0</hadIRAM2> + <hadIROM2>0</hadIROM2> + <StupSel>8</StupSel> + <useUlib>0</useUlib> + <EndSel>0</EndSel> + <uLtcg>0</uLtcg> + <nSecure>0</nSecure> + <RoSelD>3</RoSelD> + <RwSelD>3</RwSelD> + <CodeSel>0</CodeSel> + <OptFeed>0</OptFeed> + <NoZi1>0</NoZi1> + <NoZi2>0</NoZi2> + <NoZi3>0</NoZi3> + <NoZi4>0</NoZi4> + <NoZi5>0</NoZi5> + <Ro1Chk>0</Ro1Chk> + <Ro2Chk>0</Ro2Chk> + <Ro3Chk>0</Ro3Chk> + <Ir1Chk>1</Ir1Chk> + <Ir2Chk>0</Ir2Chk> + <Ra1Chk>0</Ra1Chk> + <Ra2Chk>0</Ra2Chk> + <Ra3Chk>0</Ra3Chk> + <Im1Chk>1</Im1Chk> + <Im2Chk>0</Im2Chk> + <OnChipMemories> + <Ocm1> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm1> + <Ocm2> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm2> + <Ocm3> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm3> + <Ocm4> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm4> + <Ocm5> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm5> + <Ocm6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </Ocm6> + <IRAM> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </IRAM> + <IROM> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </IROM> + <XRAM> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </XRAM> + <OCR_RVCT1> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT1> + <OCR_RVCT2> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT2> + <OCR_RVCT3> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT3> + <OCR_RVCT4> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x80000</Size> + </OCR_RVCT4> + <OCR_RVCT5> + <Type>1</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT5> + <OCR_RVCT6> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT6> + <OCR_RVCT7> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT7> + <OCR_RVCT8> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT8> + <OCR_RVCT9> + <Type>0</Type> + <StartAddress>0x20000000</StartAddress> + <Size>0x20000</Size> + </OCR_RVCT9> + <OCR_RVCT10> + <Type>0</Type> + <StartAddress>0x0</StartAddress> + <Size>0x0</Size> + </OCR_RVCT10> + </OnChipMemories> + <RvctStartVector></RvctStartVector> + </ArmAdsMisc> + <Cads> + <interw>1</interw> + <Optim>1</Optim> + <oTime>0</oTime> + <SplitLS>0</SplitLS> + <OneElfS>0</OneElfS> + <Strict>0</Strict> + <EnumInt>0</EnumInt> + <PlainCh>0</PlainCh> + <Ropi>0</Ropi> + <Rwpi>0</Rwpi> + <wLevel>0</wLevel> + <uThumb>0</uThumb> + <uSurpInc>0</uSurpInc> + <uC99>1</uC99> + <useXO>0</useXO> + <v6Lang>1</v6Lang> + <v6LangP>1</v6LangP> + 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</OPTHX> + </DebugOption> + <Utilities> + <Flash1> + <UseTargetDll>1</UseTargetDll> + <UseExternalTool>0</UseExternalTool> + <RunIndependent>0</RunIndependent> + <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging> + <Capability>1</Capability> + <DriverSelection>4096</DriverSelection> + </Flash1> + <bUseTDR>1</bUseTDR> + <Flash2>BIN\UL2CM3.DLL</Flash2> + <Flash3></Flash3> + <Flash4></Flash4> + <pFcarmOut></pFcarmOut> + <pFcarmGrp></pFcarmGrp> + <pFcArmRoot></pFcArmRoot> + <FcArmLst>0</FcArmLst> + </Utilities> + <TargetArmAds> + <ArmAdsMisc> + <GenerateListings>0</GenerateListings> + <asHll>1</asHll> + <asAsm>1</asAsm> + <asMacX>1</asMacX> + <asSyms>1</asSyms> + <asFals>1</asFals> + <asDbgD>1</asDbgD> + <asForm>1</asForm> + <ldLst>0</ldLst> + <ldmm>1</ldmm> + <ldXref>1</ldXref> + <BigEnd>0</BigEnd> + <AdsALst>1</AdsALst> + <AdsACrf>1</AdsACrf> + <AdsANop>0</AdsANop> + <AdsANot>0</AdsANot> + <AdsLLst>1</AdsLLst> + <AdsLmap>1</AdsLmap> + <AdsLcgr>1</AdsLcgr> + <AdsLsym>1</AdsLsym> + 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</Group> + <Group> + <GroupName>::Compiler</GroupName> + </Group> + <Group> + <GroupName>::Device</GroupName> + </Group> + </Groups> + </Target> + <Target> + <TargetName>ARMCM7_SP</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <pCCUsed>5060300::V5.06 update 3 (build 300)::ARMCC</pCCUsed> + <uAC6>0</uAC6> + <TargetOption> + <TargetCommonOption> + <Device>ARMCM7_SP</Device> + <Vendor>ARM</Vendor> + <PackID>ARM.CMSIS.5.3.0</PackID> + <PackURL>http://www.keil.com/pack/</PackURL> + <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ESEL ELITTLE</Cpu> + <FlashUtilSpec></FlashUtilSpec> + <StartupFile></StartupFile> + <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll> + <DeviceId>0</DeviceId> + <RegisterFile>$$Device:ARMCM7_SP$Device\ARM\ARMCM7\Include\ARMCM7_SP.h</RegisterFile> + <MemoryEnv></MemoryEnv> + <Cmp></Cmp> + <Asm></Asm> + <Linker></Linker> + <OHString></OHString> + <InfinionOptionDll></InfinionOptionDll> + <SLE66CMisc></SLE66CMisc> + <SLE66AMisc></SLE66AMisc> + <SLE66LinkerMisc></SLE66LinkerMisc> + <SFDFile>$$Device:ARMCM7_SP$Device\ARM\SVD\ARMCM7.svd</SFDFile> + <bCustSvd>0</bCustSvd> + <UseEnv>0</UseEnv> + <BinPath></BinPath> + <IncludePath></IncludePath> + <LibPath></LibPath> + <RegisterFilePath></RegisterFilePath> + <DBRegisterFilePath></DBRegisterFilePath> + <TargetStatus> + <Error>0</Error> + <ExitCodeStop>0</ExitCodeStop> + <ButtonStop>0</ButtonStop> + <NotGenerated>0</NotGenerated> + <InvalidFlash>1</InvalidFlash> + </TargetStatus> + <OutputDirectory>.\ARMCM7_debug\</OutputDirectory> + <OutputName>arm_nnexample_gru</OutputName> + <CreateExecutable>1</CreateExecutable> + <CreateLib>0</CreateLib> + <CreateHexFile>0</CreateHexFile> + <DebugInformation>1</DebugInformation> + <BrowseInformation>1</BrowseInformation> + <ListingPath>.\ARMCM7_debug\</ListingPath> + <HexFormatSelection>1</HexFormatSelection> + <Merge32K>0</Merge32K> + <CreateBatchFile>0</CreateBatchFile> + <BeforeCompile> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopU1X>0</nStopU1X> + <nStopU2X>0</nStopU2X> + </BeforeCompile> + <BeforeMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + <UserProg2Dos16Mode>0</UserProg2Dos16Mode> + <nStopB1X>0</nStopB1X> + <nStopB2X>0</nStopB2X> + </BeforeMake> + <AfterMake> + <RunUserProg1>0</RunUserProg1> + <RunUserProg2>0</RunUserProg2> + <UserProg1Name></UserProg1Name> + <UserProg2Name></UserProg2Name> + <UserProg1Dos16Mode>0</UserProg1Dos16Mode> + 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condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\startup_ARMCM7.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\system_ARMCM7.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + </targetInfos> + </file> + </files> + </RTE> + +</Project> diff --git a/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h new file mode 100644 index 0000000..4fd2bb0 --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h @@ -0,0 +1,23 @@ +#define UPDATE_GATE_WEIGHT_X2 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+ +#define UPDATE_GATE_WEIGHT_X4 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+ +#define RESET_GATE_WEIGHT_X2 {65,-28,-36,70,67,55,86,-53,23,25,-19,59,67,43,-92,48,94,-113,60,-58,24,76,-15,-19,15,36,-74,115,-59,3,34,-43,21,-125,-45,127,92,-5,-65,-103,-83,51,42,109,-51,-39,-97,-64,-4,57,79,-42,88,-4,-108,83,-4,20,86,82,-87,95,12,-69,28,30,-97,-13,-33,-48,75,119,18,31,-83,-59,-114,-21,127,34,-27,-26,-47,86,-83,-49,8,29,-48,-31,-94,-59,-49,-36,0,28,-64,113,65,-8,47,-55,-49,112,-40,-39,-100,-42,32,82,27,-78,-105,3,19,88,15,-121,-120,7,-9,-107,-23,104,114,66,113,-102,-90,24,80,-34,106,48,-91,-11,22,-96,-82,75,26,-42,59,-45,23,78,79,-76,6,20,63,-118,-125,-42,111,-80,-79,-59,-121,-79,83,49,-95,-49,81,15,-11,-54,-45,64,-30,-49,81,-57,71,91,113,-46,-63,-4,-96,-95,-27,5,-52,35,67,112,58,-62,48,112,106,80,-19,103,4,-32,-118,-74,12,13,-126,-20,-5,115,-74,-30,123,-74,-66,11,-99,-16,-102,-100,-81,-20,-24,92,-79,-31,44,-24,-85,-123,5,-52,-111,73,29,28,-19,18,23,-112,-32,-52,-38,99,-59,-52,-31,87,124,28,-42,-39,81,-87,-24,16,47,20,36,1,-70,121,124,13,1,30,112,87,-86,11,36,-18,74,-104,-100,-14,0,-24,28,-53,53,66,-63,-109,-10,-50,-15,63,34,82,-59,85,-44,105,-10,-27,99,5,-105,-69,-75,2,-47,-66,71,-30,73,-11,-45,93,47,-37,-34,-8,90,-106,103,112,65,-100,-25,-13,38,74,54,27,-81,-8,19,49,94,118,-121,-116,120,-71,-87,36,-65,-112,8,-59,-106,-40,-16,68,87,-109,53,12,-7,9,6,67,78,8,-42,-123,79,-93,-102,-40,12,-66,-109,47,15,-8,-5,51,-62,111,8,-66,-82,-102,120,68,-67,9,-73,-69,-79,56,-36,-10,-69,-99,-2,-11,-66,76,37,4,92,1,-89,74,85,-124,-25,40,106,-102,42,-19,-30,0,-70,82,84,106,-84,48,16,37,33,-114,38,-29,-117,51,101,26,56,127,-81,-76,38,-124,103,-25,54,-21,-112,40,102,3,63,36,-54,16,-18,114,39,5,105,83,117,-92,-5,-14,-102,-87,-48,-77,-19,-82,-55,119,-95,-43,97,126,-48,-50,-97,-25,-102,-53,47,111,66,-82,-16,-38,76,-15,23,20,88,-19,125,-90,107,-31,102,107,30,-111,71,38,26,43,-85,82,29,-99,126,-109,21,-42,-107,-115,-123,30,-46,39,4,-19,-44,-69,86,41,4,33,57,-110,95,-22,123,71,1,119,77,90,105,81,-68,74,-38,-109,6,-82,-20,-115,-104,38,27,-44,82,-107,99,-41,-28,-55,100,10,-42,7,91,56,-91,113,-91,70,-66,-48,-18,109,-27,42,-89,-20,-63,-41,77,-13,73,10,-74,-51,88,28,50,-5,7,92,18,-98,-41,-14,8,-16,99,30,-109,7,52,110,-120,-17,33,53,1,106,-99,-14,-93,-46,-60,7,-54,100,91,93,89,-84,118,58,-84,38,57,-24,-25,22,-52,119,-85,-75,-79,60,-97,1,-13,54,-43,98,-92,65,37,-110,64,21,-18,-111,-9,86,90,42,-71,-29,86,-10,-15,-20,106,-45,-22,44,105,55,-61,-89,-119,31,93,-97,-35,9,-113,86,-113,22,-68,-29,-36,-123,98,79,34,-29,71,44,49,56,93,4,63,-3,45,12,54,-96,27,-55,-72,84,69,27,-28,-111,-57,-41,92,-106,-90,55,105,-60,94,34,94,-1,112,-86,-55,-58,68,-65,37,110,-107,-62,66,61,-69,-52,27,-61,70,-56,-116,-101,-103,127,-98,-79,25,-117,40,33,111,10,-3,-65,1,84,-41,5,-93,-85,-96,78,54,43,70,77,-53,-71,-38,48,103,-88,115,94,20,-5,-125,-7,-61,30,-25,-57,-42,-100,63,-114,40,-53,123,50,-7,121,75,67,75,3,-38,-101,-44,-46,54,38,-22,4,18,102,-126,44,86,-10,-1,118,98,102,-125,74,32,18,74,73,72,64,47,105,-72,5,73,98,9,39,18,10,-68,81,-128,-89,27,-51,51,16,119,-71,-53,51,-84,107,-116,7,73,106,20,52,-85,-74,-103,-18,29,-13,73,106,-92,107,-115,5,65,83,-79,-7,98,-42,-33,82,-64,75,-32,100,-67,-122,84,43,-111,114,-99,46,12,99,43,50,-24,-88,-60,111,68,64,54,-105,-120,119,68,5,51,63,89,-57,-75,-25,-35,-28,42,-64,101,-103,-35,-99,-96,-18,-64,-94,-46,89,-65,-38,-1,-97,127,-67,84,-18,86,115,60,-78,-109,-61,-93,-67,-87,-80,124,26,-9,111,115,-88,-71,-86,-71,-65,-15,108,-25,111,9,86,-115,-55,-23,57,27,103,108,-28,65,86,68,114,62,126,-4,33,-34,-123,87,-76,-104,-126,26,-13,44,108,105,12,-35,-58,3,-5,-32,91,49,89,88,37,38,119,-125,-48,37,53,85,-73,67,116,-116,-127,103,127,-115,92,-35,-83,-45,25,-96,-13,-90,41,-27,105,119,85,27,-3,-64,93,17,-53,104,-70,-43,65,45,-90,61,-31,-49,-99,84,46,93,-37,84,-79,13,-59,-76,62,19,-11,-96,-104,-3,-8,-78,92,98,50,-7,-39,-82,37,-126,127,-113,67,94,115,-9,-33,-57,26,-67,9,28,-8,81,-98,-10,84,34,111,-95,127,75,38,-7,-2,-71,-62,-72,99,-74,25,123,114,51,-28,103,-110,43,113,7,58,75,-95,-52,19,-112,101,26,65,-115,-91,85,-5,-45,110,-103,-34,-69,50,-15,-19,-110,-44,-7,-112,-93,29,50,-84,-55,-41,11,19,-31,-47,-62,-12,-105,-47,68,-124,-47,-113,-55,30,25,55,-14,85,-66,-5,-105,62,-27,-89,-124,-84,112,34,52,25,104,32,-30,84,-46,-38,60,-2,-107,-95,-86,-25,117,60,-121,32,84,8,-88,-1,91,-46,-76,81,44,79,105,-105,82,20,59,-115,96,21,-113,19,92,122,76,36,-112,78,16,38,73,69,54,97,41,-49,78,-71,-69,95,-85,117,10,-98,25,72,126,47,-17,4,-44,-32,-16,-12,105,76,4,-82,-91,-21,-117,30,-67,46,-8,-125,84,-51,94,0,-60,127,99,43,60,16,55,-16,-121,-61,-115,38,25,17,35,23,68,9,-107,-44,118,119,43,99,-95,40,42,-70,54,19,92,-36,82,-35,122,-96,54,-29,-50,100,-79,-71,-99,-60,-2,-100,41,97,-93,-58,-123,126,-102,81,-5,83,110,-50,58,-86,41,-126,43,-49,98,-59,94,-91,115,16,-3,-58,-30,-109,110,-114,124,22,-88,-79,-29,-100,54,-33,23,-1,-77,52,-126,114,70,-50,90,82,-13,-25,-125,16,48,101,-93,19,-103,67,-1,-32,28,-72,-26,73,45,-22,83,-68,-61,89,57,-37,90,16,-38,-124,47,-5,-113,81,71,-30,-46,-18,-52,-104,-40,49,-101,106,38,6,125,-70,25,-88,-50,-77,-12,53,110,-84,23,-109,-53,112,2,88,101,-55,-10,-72,123,-35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+ +#define RESET_GATE_WEIGHT_X4 {65,28,-28,30,-90,106,24,80,-36,-97,70,-13,80,-19,-34,103,67,-33,55,-48,106,4,48,-32,86,75,-53,119,-91,-118,-11,-74,23,18,25,31,22,12,-96,13,-19,-83,59,-59,-82,-126,75,-20,67,-114,43,-21,26,-5,-42,115,-92,127,48,34,59,-74,-45,-30,94,-27,-113,-26,23,123,78,-74,60,-47,-58,86,79,-66,-76,11,24,-83,76,-49,6,-99,20,-16,-15,8,-19,29,63,-102,-118,-100,15,-48,36,-31,-125,-81,-42,-20,-74,-94,115,-59,111,-24,-80,92,-59,-49,3,-36,-79,-79,-59,-31,34,0,-43,28,-121,44,-79,-24,21,-64,-125,113,83,-85,49,-123,-45,65,127,-8,-95,5,-49,-52,92,47,-5,-55,81,-111,15,73,-65,-49,-103,112,-11,29,-54,28,-83,-40,51,-39,-45,-19,64,18,42,-100,109,-42,-30,23,-49,-112,-51,32,-39,82,81,-32,-57,-52,-97,27,-64,-78,71,-38,91,99,-4,-105,57,3,113,-59,-46,-52,79,19,-42,88,-63,-31,-4,87,88,15,-4,-121,-96,124,-95,28,-108,-120,83,7,-27,-42,5,-39,-4,-9,20,-107,-52,81,35,-87,86,-23,82,104,67,-24,112,16,-87,114,95,66,58,47,-62,20,12,113,-69,-102,48,36,112,1,-70,54,121,27,-2,-102,-11,-87,124,-81,13,-8,-66,-48,76,-77,1,19,30,49,37,-19,4,-82,112,94,87,118,92,-55,1,119,-86,-121,11,-116,-89,-95,74,-43,36,120,-18,-71,85,97,-124,126,74,-87,-104,36,-25,-48,40,-50,-100,-65,-14,-112,106,-97,-102,-25,0,8,-24,-59,42,-102,-19,-53,28,-106,-53,-40,-30,47,0,111,53,-16,66,68,-70,66,82,-82,-63,87,-109,-109,84,-16,106,-38,-10,53,-50,12,-84,76,48,-15,-15,-7,63,9,16,23,37,20,34,6,82,67,33,88,-114,-19,-59,78,85,8,38,125,-29,-90,-44,-42,105,-123,-117,107,51,-31,-10,79,-27,-93,101,102,26,107,99,-102,5,-40,56,30,127,-111,-105,12,-69,-66,-81,71,-76,38,-75,-109,2,47,38,26,-124,43,-47,15,-66,-8,103,-85,-25,82,71,-5,-30,51,54,29,-21,-99,73,-62,-11,111,-112,126,40,-109,-45,8,93,-66,102,21,3,-42,47,-82,-37,-102,63,-107,36,-115,-34,120,-8,68,-54,-123,16,30,90,-67,-106,9,-18,-46,114,39,103,-73,112,-69,39,4,5,-19,65,-79,-100,56,105,-44,83,-69,-25,-36,-13,-10,117,86,-92,41,38,-69,74,-99,-5,4,-14,33,57,-41,-110,-14,-15,68,-20,-65,95,8,-22,-16,106,37,-45,110,123,99,71,30,-22,-107,44,-62,1,-109,119,7,105,66,55,61,77,52,90,110,-61,-69,-89,-52,105,-120,81,-17,-119,27,31,-61,-68,33,74,53,93,70,-97,-56,-38,1,-109,106,-35,-116,9,-101,6,-99,-82,-14,-113,-103,86,127,-20,-93,-115,-46,-113,-98,22,-79,-104,-60,38,7,-68,25,-29,-117,27,-54,-44,100,-36,40,-123,33,82,91,-107,93,98,111,79,10,99,89,-41,-84,34,-3,-29,-65,-28,118,-55,58,71,1,44,84,100,-84,10,38,49,-41,56,5,-42,57,7,-24,93,-93,4,-85,91,-25,56,22,63,-96,-3,78,-91,-52,113,119,45,54,12,43,-91,-85,70,-75,54,70,-96,77,-66,-79,-48,60,27,-53,-55,-71,-18,-97,109,1,-72,-38,84,48,-27,-13,42,54,69,103,27,-88,-89,-43,-20,98,-28,115,-111,94,-63,-92,-41,65,-57,20,-41,-5,77,37,-13,-110,92,-125,-106,-7,73,64,10,21,-90,-61,55,30,-74,-18,-51,-111,105,-25,-60,-57,88,-9,28,86,94,-42,34,-100,50,90,-5,42,94,63,-1,-114,7,-71,92,-29,112,40,-86,-53,18,86,-98,-10,-55,123,-58,50,-7,-103,121,-18,-46,-35,89,-58,75,29,67,-13,-65,3,-38,-5,75,73,3,106,-1,-32,-97,91,-38,-92,-101,107,127,49,-67,89,-44,-115,-46,5,84,88,-18,37,54,65,38,83,86,38,115,119,-22,-79,4,-7,60,-125,-78,-48,18,98,102,-42,-109,37,-61,53,-126,-33,44,82,-93,85,-67,-73,86,-64,-10,75,-87,67,-80,116,-1,-32,118,100,124,-116,26,-127,98,-67,102,-122,-9,103,111,127,-125,84,74,43,115,-115,-88,92,32,-111,18,114,-71,-35,-86,-83,74,-99,73,46,-71,-45,-65,25,72,12,64,99,-15,-96,108,-13,47,43,105,50,-25,-90,111,41,-72,-24,5,-88,9,-27,86,105,73,-60,98,111,-115,119,-55,85,9,68,39,64,-23,27,57,-3,18,54,10,-105,27,-64,103,93,-68,-120,81,119,108,17,-28,-53,-128,68,-89,5,65,104,86,-70,27,51,-51,63,68,-43,114,65,51,89,16,-57,62,45,126,-90,119,-75,-71,-25,-4,61,33,-31,-53,-35,51,-28,-34,-49,-123,-99,-84,42,107,-64,87,84,-76,46,-116,101,7,-103,-104,93,-126,-37,73,-35,106,-99,26,84,-13,-79,20,-96,52,-18,44,13,108,-59,-85,-64,-74,-94,105,-76,12,62,19,-115,-11,-91,117,-67,60,46,-96,85,-104,-5,-121,-8,32,-125,-3,-45,-8,110,84,84,8,-51,-78,-103,92,-34,-88,94,-1,0,98,-69,50,50,91,-60,-46,127,-7,-15,-39,-19,-76,99,81,43,-82,-110,37,-44,44,60,79,16,-126,-7,127,-112,105,55,-105,-16,-113,-93,67,29,82,-121,20,-61,94,50,115,-84,59,-115,-115,38,-9,-55,-33,-41,96,25,21,17,-57,11,26,19,-113,35,19,23,-67,-31,9,-47,92,68,122,9,28,-62,-8,-12,76,-107,36,-44,81,-105,-98,-47,-112,118,78,119,-10,68,84,-124,16,43,38,99,34,-47,111,-113,73,-95,69,40,-95,-55,127,30,54,42,97,-70,75,25,38,55,41,54,-49,19,-7,-14,-2,85,78,92,-71,-36,-71,-66,-62,-5,-69,82,95,-35,-72,-105,99,62,-85,122,117,-96,-74,-27,25,-89,10,54,-98,-29,123,-124,114,-84,25,-50,72,100,51,112,-28,34,126,-79,47,-71,103,52,-110,25,-17,-99,4,-60,43,104,113,32,-44,-2,-32,-100,7,-30,58,84,-16,41,-12,97,75,-46,-95,-38,105,-93,76,-58,-52,60,19,-2,4,-123,-82,126,-112,-107,101,-95,-91,-102,-21,81,26,-86,65,-25,-117,-5,30,83,110,-38,-50,-124,57,-31,-16,13,58,47,-86,-5,114,71,-98,63,41,-113,-126,81,101,-126,81,107,43,71,-49,-30,34,115,-83,-100,98,-46,-59,-18,-8,27,3,39,94,-52,-91,-104,-27,10,5,75,115,-40,16,49,110,-128,-24,58,-3,-101,-58,106,-80,103,9,-104,-30,38,-109,6,85,126,-108,-59,110,125,-114,-70,96,31,-93,89,124,25,22,-88,-34,-67,76,97,-88,-50,-79,-77,-107,-96,71,-69,-29,-12,-100,53,84,87,-98,19,5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+ +#define HIDDEN_STATE_WEIGHT_X2 {-3,-33,59,21,117,70,0,44,108,108,-47,-80,-118,34,88,-91,-123,-108,8,51,26,82,-80,107,-100,-69,97,-90,17,19,63,111,-40,-125,110,24,58,-69,26,-31,-65,-37,-47,-41,-109,106,-100,108,-99,108,116,104,86,-50,-45,10,-53,112,34,96,-10,-39,-32,-25,69,102,-2,-4,-25,121,-1,-28,-48,-100,0,-128,60,-73,42,-32,118,-88,-113,-112,-113,70,-98,118,95,77,-52,123,-99,72,26,-102,-32,120,113,22,6,-68,84,-33,103,66,111,60,-76,33,10,25,-43,93,41,-79,110,13,67,107,-113,90,58,64,-125,79,-85,-18,76,80,-59,11,-18,-74,15,-102,99,-19,117,99,65,-50,-108,-121,-9,-104,33,94,-95,110,-48,-97,76,36,1,-58,86,-115,45,-88,38,51,123,-23,-20,-43,-37,15,91,-85,-88,6,-96,58,78,13,23,1,-43,62,-70,-108,44,30,74,90,79,-80,-20,71,-21,0,60,19,-59,-52,44,-14,77,92,-69,121,-123,-27,119,-84,79,87,24,85,118,1,-51,-96,60,102,-6,15,96,120,-109,6,35,11,-119,-109,-18,16,-112,91,-126,71,-29,121,-21,-120,37,57,-117,-39,93,56,-73,-104,77,-107,-52,111,-61,-4,44,-119,67,72,-66,36,-127,-113,-124,123,21,98,84,86,76,23,78,7,-127,-4,1,-46,-107,59,-21,53,-65,-99,-15,-98,53,-31,7,64,7,105,51,-75,50,-52,48,101,-126,-120,5,34,3,81,-39,70,41,112,25,30,79,-6,107,-11,-97,92,-84,67,49,107,60,101,-37,27,-91,-61,-96,120,-113,87,-46,68,64,102,-86,-60,13,-71,56,-105,90,-9,-35,27,103,120,39,23,-39,-1,-85,-95,-6,119,-41,-2,-69,102,102,-119,-3,-11,-125,-111,40,-115,-41,-117,-44,-7,83,123,-21,23,99,-107,43,100,-99,-3,89,3,-113,103,47,-94,-69,-38,-28,-37,49,-117,-49,-126,17,-98,37,92,55,-116,-70,-50,77,120,47,124,78,114,67,-48,6,-42,-115,85,116,-114,-46,-50,-13,70,-101,110,-55,20,-51,125,-19,-9,-15,46,30,-27,-123,114,-50,-30,-72,76,-83,71,47,-45,74,102,44,108,-26,108,-113,-43,110,-91,37,-69,76,-33,106,-76,-96,20,-117,63,-33,-5,11,-121,-51,63,-56,59,-16,-33,114,74,124,73,99,-50,51,-71,118,106,30,-92,26,-40,119,-121,2,-45,9,0,-5,-2,-89,88,-11,-85,-60,19,81,-96,75,82,-40,124,89,-36,-117,-100,-2,-34,112,101,39,-101,-106,60,59,-126,-32,96,68,-53,87,20,54,-24,46,-95,65,-112,22,60,122,-22,-106,-124,97,-37,-86,95,-110,-8,44,58,-12,-120,-45,-86,-32,-86,-94,-14,15,29,-8,-114,71,70,-93,-69,100,-123,-18,-47,-12,127,104,-102,93,-11,-73,121,87,-79,-92,46,92,-108,-107,79,121,-71,-89,16,-11,-52,72,-114,-32,-60,-9,-57,-4,10,-81,-22,68,74,76,-68,-127,96,-84,69,-3,-26,-106,-3,-87,-65,105,109,122,-103,31,-108,-86,-5,-39,85,88,67,-82,0,-25,93,61,-62,5,-54,-114,-51,-9,-114,20,49,-26,38,19,39,-103,33,-120,37,-97,32,-89,119,111,-124,-99,78,-49,-128,76,-18,-12,-109,96,90,-73,-104,59,-59,-92,123,55,54,-120,-80,-48,-16,-95,96,36,118,-119,-58,93,45,-43,-75,64,38,-2,-72,-111,22,-89,-75,-120,-42,45,108,59,-105,40,27,32,-66,121,-22,-71,-9,118,124,60,-96,47,4,14,-27,64,70,47,-91,-70,1,-44,94,-46,53,4,23,-124,-92,-95,83,-49,-81,40,-80,48,0,39,1,-113,32,40,-21,-1,-110,102,1,-74,-51,40,108,-35,-36,89,84,123,-48,-115,-115,83,-61,114,-127,-61,114,100,-82,-45,60,87,60,19,86,97,-68,40,-66,75,86,-32,-128,88,-57,-27,77,3,-27,43,-39,-62,66,5,-82,45,-104,-78,34,57,96,89,-90,66,-10,37,-110,-30,82,-58,13,94,12,115,35,117,0,80,61,-7,107,-104,-21,21,-70,-93,-94,-51,-61,39,-62,64,-82,-109,76,84,58,-47,-100,52,46,-51,88,91,8,-47,108,-80,25,-58,111,-59,-83,-75,92,98,110,54,106,65,-47,-120,-5,90,-123,101,-61,-85,-93,109,88,0,8,59,86,56,126,17,-26,58,-101,-25,35,0,-123,-3,-56,112,-128,8,17,-52,88,31,-3,105,-56,68,-1,-94,96,-19,10,-22,-88,-10,119,-44,19,42,75,-86,18,-107,89,-82,-120,76,40,84,-122,29,33,-47,17,-50,-13,23,-66,-46,85,-29,-110,42,-68,8,99,-93,-29,101,16,52,-13,127,0,86,-117,-92,-70,-32,-27,127,-123,1,34,-13,92,114,-11,29,-103,-121,-54,20,73,16,74,108,16,-61,89,50,-30,-14,116,44,-31,16,96,24,-51,7,39,-87,-69,-61,-98,61,-46,113,85,-95,103,67,99,-66,-45,-42,-70,96,104,5,-111,69,-25,99,-118,23,109,11,4,-41,-94,73,100,96,6,90,-75,-25,79,-13,-43,-6,-12,51,12,40,124,-56,81,-8,59,-60,-26,-54,33,122,85,53,-99,125,19,-26,94,41,-5,46,-48,-70,-10,41,102,-1,-98,-9,15,29,46,-66,-118,-53,45,119,-127,94,53,-58,90,124,5,-110,-98,-80,-77,77,29,19,105,-121,92,9,-124,50,-119,59,40,67,104,-12,13,103,101,47,-51,34,-66,-101,-117,112,-5,118,-48,-60,-114,38,-71,2,51,114,80,115,-5,116,20,16,-47,-19,30,24,-68,7,-30,-3,-64,-7,-34,-12,44,34,-91,-97,116,112,-99,108,-75,17,26,-14,-61,80,22,-7,34,47,-93,45,106,121,78,43,-97,39,-99,-68,-72,-7,64,-49,-82,-127,78,-64,48,18,15,126,-125,-111,-69,-111,10,-46,111,-75,123,-44,-67,-31,-96,-67,-53,-53,-106,67,-101,23,62,30,9,-114,-12,-57,-38,-78,95,-10,-3,110,88,123,-26,78,-125,114,53,10,-57,26,38,-51,73,92,-124,79,15,75,-62,109,-113,-67,1,35,52,-36,55,7,111,-43,109,101,88,122,-21,-32,-87,59,16,-122,-109,-118,17,-22,-39,53,-105,77,90,-24,-65,43,-27,113,30,-117,-30,106,37,55,59,54,-70,99,99,-73,120,97,-39,-88,-54,101,51,-76,70,-121,-68,23,-73,-31,75,-8,-63,-123,-93,96,-81,99,-95,28,-36,55,-104,32,-64,41,-97,95,-89,126,-26,-25,126,2,-26,-54,110,-86,110,74,-3,-110,56,-60,-49,117,-82,-55,-103,-112,70,-85,85,-63,82,7,75,-61,90,32,35,-115,72,73,-121,63,-84,-52,-29,-59,-4,29,64,119,127,58,-117,48,126,120,-115,-15,-10,27,27,-81,117,-5,121,-72,113,31,-13,10,27,-106,-51,81,-96,-22,19,-78,6,71,-34,123,118,75,-23,-72,-97,111,-121,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+ +#define HIDDEN_STATE_WEIGHT_X4 {-3,69,-33,102,76,60,80,19,59,-2,21,-4,-59,-59,11,-52,117,-25,70,121,-18,44,-74,-14,0,-1,44,-28,15,77,-102,92,108,-48,108,-100,99,-69,-19,121,-47,0,-80,-128,117,-123,99,-27,-118,60,34,-73,65,119,-50,-84,88,42,-91,-32,-108,79,-121,87,-123,118,-108,-88,-9,24,-104,85,8,-113,51,-112,33,118,94,1,26,-113,82,70,-95,-51,110,-96,-80,-98,107,118,-48,60,-97,102,-100,95,-69,77,76,-6,36,15,97,-52,-90,123,1,96,-58,120,17,-99,19,72,86,-109,-115,6,63,26,111,-102,45,35,-88,11,-40,-32,-125,120,38,-119,51,-109,110,113,24,22,123,-18,-23,16,58,6,-69,-68,-20,-112,-43,91,26,84,-31,-33,-37,-126,15,71,-65,103,-37,66,91,-29,-85,121,-47,111,-41,60,-88,-21,6,-120,-109,-76,106,33,-96,37,58,57,-100,10,108,25,78,-117,13,-39,-99,-43,108,93,23,93,1,56,116,41,104,-79,-43,-73,62,-104,86,110,-50,13,-70,77,-108,-107,-45,67,10,107,44,-52,30,111,-53,-113,112,90,74,-61,90,-4,34,58,96,64,79,44,-80,-119,-10,-125,-39,79,-20,67,71,72,-32,-85,-25,-18,-21,-66,0,36,-127,-96,-113,120,49,76,-117,-33,-124,-113,123,87,-49,106,-126,-76,21,-46,98,68,17,-96,-98,20,84,64,86,102,37,-117,92,63,76,-86,23,-60,55,-33,-116,-5,78,13,7,-71,-70,11,-50,-121,-127,56,-4,-105,77,-51,120,63,1,90,-46,-9,47,-56,124,59,-107,-35,59,27,78,-16,114,-33,-21,103,53,120,67,114,-48,74,-65,39,-99,23,6,124,-42,73,-15,-39,-98,-1,-115,99,85,-50,53,-85,-31,-95,116,51,-114,-71,7,-6,64,119,-46,118,-50,106,7,-41,105,-2,-13,30,70,-92,51,-69,-75,102,-101,26,110,-40,50,102,-52,-119,-55,119,20,-121,48,-3,101,-11,-51,2,125,-45,-126,-125,-120,-111,-19,9,-9,0,5,40,34,-115,-15,-5,46,-2,3,-41,81,-117,30,-89,-27,88,-39,-44,70,-7,-123,-11,114,-85,41,83,112,123,-50,-60,-30,19,25,-21,30,23,-72,81,76,-96,79,99,-6,-107,-83,75,71,82,107,43,-11,100,47,-40,-45,124,-97,-99,92,-3,74,89,102,-36,-84,89,67,3,44,-117,108,-100,49,-113,107,103,-26,-2,108,-34,60,47,101,-94,-113,112,-43,101,-37,-69,27,-38,110,39,-91,-101,-91,-28,-61,-37,37,-106,-69,60,59,121,-126,-71,-97,47,32,4,-32,-89,96,16,-89,14,119,-27,68,-11,-53,-52,111,64,-124,70,87,72,20,-114,-99,47,78,-91,54,-32,-24,-60,-49,-70,-128,1,46,-9,-95,-57,76,-44,-18,94,65,-4,-112,10,-12,-46,-109,53,22,-81,60,-22,96,4,90,23,122,68,-22,74,-73,-124,-104,-92,-106,76,-124,-68,59,-95,-59,83,97,-127,-37,96,-92,-49,123,-81,-86,-84,95,69,55,40,54,-80,-110,-3,-8,-26,-120,48,-80,0,44,-106,58,-3,-48,39,-16,1,-12,-87,-120,-65,-95,-113,96,32,-45,105,-86,109,36,40,118,-21,-32,122,-86,-103,-119,-1,-58,-110,-94,31,-14,-108,93,102,45,1,15,-86,29,-5,-43,-74,-75,-51,-8,-39,-114,85,64,40,38,108,71,88,70,67,-2,-35,-72,-36,-93,-82,-69,0,-111,89,22,84,100,-25,-123,93,-89,123,-75,-48,-18,61,-47,-62,-120,-115,-42,-115,-12,5,127,-54,45,83,108,-61,104,-114,-102,-51,59,114,-105,-127,93,-9,-11,-114,40,-61,27,114,-73,20,121,49,32,100,-66,-82,87,-26,-79,38,121,-45,-22,60,-92,19,46,39,-71,87,-9,60,92,-103,-108,33,118,19,124,86,-107,-120,79,37,60,97,-96,-68,40,-51,-66,88,-10,-61,119,89,75,91,86,8,-44,50,19,-30,-32,-47,-128,108,42,-14,75,116,88,-80,-57,25,-86,44,18,-31,-27,-58,77,111,-107,16,89,96,3,-59,-27,-83,-82,24,-120,-51,43,-75,-39,92,76,7,40,39,-62,98,66,110,84,-87,-122,-69,5,54,-82,106,29,-61,33,-98,45,65,-104,-47,-47,61,17,-46,-78,-120,34,-5,-50,113,-13,85,57,90,96,-123,23,-95,-66,103,89,101,-90,-61,-46,67,85,99,66,-85,-10,-93,-29,-66,-110,-45,37,109,-110,88,42,-42,-68,-70,-30,0,82,8,8,96,99,104,-58,59,13,86,-93,5,-29,-111,94,56,12,126,101,69,16,-25,115,17,35,-26,52,99,-13,-118,117,58,0,-101,127,23,0,109,80,-25,61,35,86,11,-117,4,-7,0,107,-123,-92,-41,-70,-94,-104,-3,-21,-56,-32,73,-27,100,21,112,-70,-128,127,96,-123,6,-93,8,-94,17,1,90,34,-75,-51,-52,-61,88,-13,-25,92,79,39,31,-62,-3,114,-13,-11,-43,64,105,-82,-56,29,-6,-103,-12,-109,68,76,-1,-121,51,-54,12,84,-94,58,96,20,40,73,124,-47,-19,-100,10,16,-56,74,81,52,-22,46,-88,108,-8,16,59,-60,-101,-26,-117,-127,-36,78,55,-54,112,33,-5,-64,7,48,111,122,118,85,-48,18,-43,15,109,53,-60,-99,-114,126,101,-125,88,125,38,19,-71,-111,122,-69,-21,-26,2,94,51,-111,-32,10,-87,41,114,-5,80,-46,59,111,16,46,115,-48,-5,-75,-122,123,-109,-70,116,-10,20,-44,-118,-67,17,41,16,102,-47,-31,-22,-96,-39,-1,-19,-98,30,-67,53,-53,-105,-9,24,15,-68,-53,77,-106,90,29,7,46,-30,67,-24,-101,-65,-66,-3,-118,-64,23,43,62,-27,-53,-7,45,-34,30,113,9,30,119,-12,-127,44,-114,-117,-12,-30,94,34,53,-91,-57,106,-38,37,-58,-97,90,116,-78,55,95,59,124,112,5,-99,-10,54,-3,-70,-110,108,-98,-75,110,99,88,99,-80,17,-77,26,123,-73,-26,120,77,-14,29,-61,78,97,-125,-39,19,80,105,22,114,-88,53,-54,-121,-7,92,34,10,101,-57,51,9,47,-124,-93,26,-76,38,70,50,45,-119,106,-51,-121,73,-68,59,121,40,78,92,23,-124,-73,67,43,104,-97,79,-31,15,75,-12,39,13,-99,75,-8,-62,-63,103,-68,101,-72,109,-123,-113,-93,47,-7,-51,64,-67,96,1,-81,34,-49,-66,-82,35,99,52,-95,28,27,-36,27,-93,-15,52,-68,55,-81,-104,117,67,-3,53,102,32,-5,-64,121,-31,-10,19,-123,41,-72,-97,113,45,-10,-111,-71,95,31,-89,-13,36,-111,39,86,126,10,-26,27,-91,48,-77,-45,-25,-106,126,-51,104,101,71,81,2,81,-26,-96,7,-114,-44,-94,-54,-22,110,19,-76,77,3,-127,-86,-78,110,6,-62,-96,121,-100,74,71,-3,-34,43,86,37,109,-110,123,56,118,-7,-33,-96,15,-60,75,-49,-23,-6,-34,57,60,117,-72,-82,-97,-104,88,30,-86,-55,111,-103,-121,-126,-63,-94,-103,-112,0,70,80,118,-46,-44,101,-85,28,85,52,91,-127,29,-88,-63,95,82,59,124,90,-86,-37,7,-116,75,72,-13,82,55,-125,-61,80,90,-75,41,-28,-41,-6,32,-62,35,88,91,61,-112,-104,-115,23,72,-102,-25,77,103,0,73,13,-121,6,81,-52,-70,59,63,113,-84,-85,-112,-9,113,-82,-52,98,-29,45,-25,59,-73,-78,-59,-96,-4,-32,-82,79,16,80,29,94,64,-7,67,-77,-5,-125,119,12,127,-9,104,-95,56,16,58,86,-117,18,66,26,-115,-55,48,59,126,-15,-90,-16,-126,15,120,75,-115,13,106,-76,80,-9,-15,-70,-10,50,-78,56,-51,110,85,-29,-102,20,15,-56,-73,-64,-23,-66,-12,-80,-128,-6,-121,-103,-6,-122,-97,40,46,-36,30,-2,-34,-2,32,116,-93,-59,-109,34,-79,126,-95,-120,-15,-40,-86,-64,71,-48,126,124,-2,-39,75,-64,127,57,30,-107,1,-74,-32,-105,-112,104,-115,80,-27,50,-86,-86,75,-13,-8,81,-13,-66,-38,-14,125,118,103,33,48,-71,10,35,-118,88,65,119,-36,-116,-107,-20,-43,-110,107,33,-27,15,-48,-119,46,-35,96,-75,88,-12,-7,90,-41,-6,-87,89,-88,-117,98,-29,-64,-41,-18,99,-83,13,61,-8,126,46,82,127,-81,-75,20,57,10,-36,81,54,-123,67,18,124,45,-55,95,50,-41,-38,-127,66,61,24,9,51,-55,113,-66,-80,28,49,-113,-71,24,113,-107,105,-71,37,47,-117,73,45,30,-74,117,114,26,6,-42,-80,-74,108,-81,110,73,88,124,-24,-43,-3,49,84,-55,-30,-125,36,102,62,-126,-45,-33,-50,98,-8,6,109,62,113,-84,-12,32,-40,24,-101,-87,-57,-56,59,-123,106,32,12,-71,-18,97,49,113,-47,105,-113,49,99,-124,-124,-81,-118,117,-12,-76,46,-9,-48,-41,-3,-54,-86,97,88,119,-82,-113,-52,-126,-93,-23,-121,127,-97,-28,-24,31,-62,-119,52,-93,75,7,33,-101,-67,67,-45,39,74,-83,127,-115,-66,4,-6,-18,-29,29,-23,68,-123,-103,31,24,117,49,8,-70,41,1,20,71,99,-40,-21,-116,-30,93,66,95,27,63,117,-49,20,-113,-92,-7,127,115,-85,97,-39,34,-67,-10,-53,123,-87,119,2,-77,68,-74,-66,22,96,-13,-12,96,-26,86,35,47,-128,-4,83,52,114,-2,-84,-14,67,-94,-53,-45,-74,-71,-94,94,-101,-122,3,-48,-14,124,-43,56,-3,58,-22,-97,-106,1,-32,57,-16,-127,51,23,-67,-59,-27,-60,125,-46,-125,-117,28,-74,29,29,-76,94,25,58,-32,-31,-101,-105,42,49,101,-115,-60,114,-55,-72,101,94,35,-14,-6,-115,-101,20,-36,-8,103,77,-42,82,61,104,85,35,-71,100,111,67,107,-90,-24,19,6,117,-87,-16,-67,-26,26,24,105,-64,102,105,-36,-7,60,109,112,-19,119,59,-81,10,-91,-9,69,124,-54,124,52,80,13,-105,21,-116,-114,-33,5,0,10,126,-93,22,-26,-115,115,94,22,105,-111,30,-7,102,44,63,0,85,-38,91,-30,98,-21,43,4,-63,-34,-124,-67,38,33,-2,45,-32,-86,12,-92,-38,29,39,121,-119,-42,-23,-30,-106,3,-12,-54,-108,7} + +#define UPDATE_GATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define RESET_GATE_BIAS {-77,67,-93,-3,98,59,-121,33,49,50,41,91,-115,-33,71,47,-70,45,89,-115,72,106,-22,100,97,-100,-95,108,-33,3,14,30} + +#define HIDDEN_STATE_BIAS {-85,78,113,70,33,38,8,114,70,-35,-67,65,31,-24,-70,-124,-89,104,124,-122,111,61,-87,75,-61,-98,83,-69,-63,45,-11,103} + +#define INPUT_DATA1 {-367,-338,0,-89,453,-413,-343,-16,42,418,201,274,-352,477,-290,-92,266,-49,342,453,-398,247,-153,328,217,342,85,69,-38,351,73,128} + +#define INPUT_DATA2 {280,41,-322,61,315,350,504,-227,-221,-483,352,252,455,-236,344,364,-378,229,-187,-498,295,357,-511,58,-349,-458,-420,-66,-400,-379,477,-60} + +#define HISTORY_DATA {-38,53,105,-79,-463,51,-343,-226,-435,-282,218,441,-299,-215,-109,335,340,-471,-109,273,33,-245,-469,170,-26,-59,192,-119,76,-6,236,-145} diff --git a/NN/Examples/ARM/arm_nn_examples/gru/para_gen.py b/NN/Examples/ARM/arm_nn_examples/gru/para_gen.py new file mode 100644 index 0000000..e2f053b --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/para_gen.py @@ -0,0 +1,183 @@ +#!/usr/bin/env python + +# +# This is a simple script to generate and convert weights +# from regular ordering to specific ordering used by +# q7_x4 or q7_q15_x4 +# + + +import numpy as np + +def convert_to_x4_weights(weights): + [r, h, w, c] = weights.shape + weights = np.reshape(weights, (r, h*w*c)) + num_of_rows = r + num_of_cols = h*w*c + new_weights = np.copy(weights) + new_weights = np.reshape(new_weights, (r*h*w*c)) + counter = 0 + for i in range(int(num_of_rows)/4): + # we only need to do the re-ordering for every 4 rows + row_base = 4*i + for j in range (int(num_of_cols)/4): + # for each 4 entries + column_base = 4*j + new_weights[counter] = weights[row_base ][column_base ] + new_weights[counter+1] = weights[row_base+1][column_base ] + new_weights[counter+2] = weights[row_base ][column_base+2] + new_weights[counter+3] = weights[row_base+1][column_base+2] + new_weights[counter+4] = weights[row_base+2][column_base ] + new_weights[counter+5] = weights[row_base+3][column_base ] + new_weights[counter+6] = weights[row_base+2][column_base+2] + new_weights[counter+7] = weights[row_base+3][column_base+2] + + new_weights[counter+8] = weights[row_base ][column_base+1] + new_weights[counter+9] = weights[row_base+1][column_base+1] + new_weights[counter+10] = weights[row_base ][column_base+3] + new_weights[counter+11] = weights[row_base+1][column_base+3] + new_weights[counter+12] = weights[row_base+2][column_base+1] + new_weights[counter+13] = weights[row_base+3][column_base+1] + new_weights[counter+14] = weights[row_base+2][column_base+3] + new_weights[counter+15] = weights[row_base+3][column_base+3] + counter = counter + 16 + # the remaining ones are in order + for j in range((int)(num_of_cols-num_of_cols%4), int(num_of_cols)): + new_weights[counter] = weights[row_base][j] + new_weights[counter+1] = weights[row_base+1][j] + new_weights[counter+2] = weights[row_base+2][j] + new_weights[counter+3] = weights[row_base+3][j] + counter = counter + 4 + return new_weights + +def convert_q7_q15_weights(weights): + [r, h, w, c] = weights.shape + weights = np.reshape(weights, (r, h*w*c)) + num_of_rows = r + num_of_cols = h*w*c + new_weights = np.copy(weights) + new_weights = np.reshape(new_weights, (r*h*w*c)) + counter = 0 + for i in range(int(num_of_rows)/4): + # we only need to do the re-ordering for every 4 rows + row_base = 4*i + for j in range (int(num_of_cols)/2): + # for each 2 entries + column_base = 2*j + new_weights[counter] = weights[row_base ][column_base ] + new_weights[counter+1] = weights[row_base+1][column_base ] + new_weights[counter+2] = weights[row_base ][column_base+1] + new_weights[counter+3] = weights[row_base+1][column_base+1] + new_weights[counter+4] = weights[row_base+2][column_base ] + new_weights[counter+5] = weights[row_base+3][column_base ] + new_weights[counter+6] = weights[row_base+2][column_base+1] + new_weights[counter+7] = weights[row_base+3][column_base+1] + + counter = counter + 8 + # the remaining ones are in order + for j in range((int)(num_of_cols-num_of_cols%2), int(num_of_cols)): + new_weights[counter] = weights[row_base][j] + new_weights[counter+1] = weights[row_base+1][j] + new_weights[counter+2] = weights[row_base+2][j] + new_weights[counter+3] = weights[row_base+3][j] + counter = counter + 4 + return new_weights + + +vec_dim = 64 +row_dim = 32 + +update_weight = np.zeros((row_dim,vec_dim), dtype=int) +reset_weight = np.zeros((row_dim,vec_dim), dtype=int) +hidden_weight = np.zeros((row_dim,vec_dim), dtype=int) + +update_bias = np.zeros((row_dim), dtype=int) +reset_bias = np.zeros((row_dim), dtype=int) +hidden_bias = np.zeros((row_dim), dtype=int) + +input_data1 = np.zeros((vec_dim-row_dim), dtype=int) +input_data2 = np.zeros((vec_dim-row_dim), dtype=int) +history_data = np.zeros((row_dim), dtype=int) + +outfile = open("arm_nnexamples_gru_test_data.h", "w") + +for i in range(row_dim): + for j in range(vec_dim): + update_weight[i][j] = np.random.randint(256)-128 + reset_weight[i][j] = np.random.randint(256)-128 + hidden_weight[i][j] = np.random.randint(256)-128 + +for i in range(row_dim): + update_bias[i] = np.random.randint(256)-128 + reset_bias[i] = np.random.randint(256)-128 + hidden_bias[i] = np.random.randint(256)-128 + history_data[i] = np.random.randint(2**10)-2**9 + +for i in range(vec_dim-row_dim): + input_data1[i] = np.random.randint(2**10)-2**9 + input_data2[i] = np.random.randint(2**10)-2**9 + +weight = np.reshape(update_weight, (row_dim, vec_dim, 1, 1)) +new_weight = convert_to_x4_weights(weight) + +outfile.write("#define UPDATE_GATE_WEIGHT_X2 {") +weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_q7_q15_weights(weight) +outfile.write("#define UPDATE_GATE_WEIGHT_X4 {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +weight = np.reshape(reset_weight, (row_dim, vec_dim, 1, 1)) +new_weight = convert_to_x4_weights(weight) + +outfile.write("#define RESET_GATE_WEIGHT_X2 {") +weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_q7_q15_weights(weight) +outfile.write("#define RESET_GATE_WEIGHT_X4 {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +weight = np.reshape(hidden_weight, (row_dim, vec_dim, 1, 1)) +new_weight = convert_to_x4_weights(weight) + +outfile.write("#define HIDDEN_STATE_WEIGHT_X2 {") +weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_q7_q15_weights(weight) +outfile.write("#define HIDDEN_STATE_WEIGHT_X4 {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +outfile.write("#define UPDATE_GATE_BIAS {") +update_bias.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +outfile.write("#define RESET_GATE_BIAS {") +reset_bias.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +outfile.write("#define HIDDEN_STATE_BIAS {") +update_bias.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +outfile.write("#define INPUT_DATA1 {") +input_data1.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +outfile.write("#define INPUT_DATA2 {") +input_data2.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + + +outfile.write("#define HISTORY_DATA {") +history_data.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + + + +outfile.close() diff --git a/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/NN/Examples/ARM/arm_nn_examples/gru/readme.txt new file mode 100644 index 0000000..fdfe60f --- /dev/null +++ b/NN/Examples/ARM/arm_nn_examples/gru/readme.txt @@ -0,0 +1,4 @@ +CMSIS NN Lib example arm_nnexample_gru0 for + Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/NN/Include/arm_nn_tables.h b/NN/Include/arm_nn_tables.h new file mode 100644 index 0000000..d56d82c --- /dev/null +++ b/NN/Include/arm_nn_tables.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_tables.h + * Description: Extern declaration for NN tables + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_NN_TABLES_H +#define _ARM_NN_TABLES_H + +#include "arm_math.h" + +/** +* @brief tables for various activation functions +* +*/ + +extern const q15_t sigmoidTable_q15[256]; +extern const q7_t sigmoidTable_q7[256]; + +extern const q7_t tanhTable_q7[256]; +extern const q15_t tanhTable_q15[256]; + + /** + * @brief 2-way tables for various activation functions + * + * 2-way table, H table for value larger than 1/4 + * L table for value smaller than 1/4, H table for remaining + * We have this only for the q15_t version. It does not make + * sense to have it for q7_t type + */ +extern const q15_t sigmoidHTable_q15[192]; +extern const q15_t sigmoidLTable_q15[128]; + +extern const q15_t sigmoidLTable_q15[128]; +extern const q15_t sigmoidHTable_q15[192]; + +#endif /* ARM_NN_TABLES_H */ diff --git a/NN/Include/arm_nnfunctions.h b/NN/Include/arm_nnfunctions.h new file mode 100644 index 0000000..c6ec83a --- /dev/null +++ b/NN/Include/arm_nnfunctions.h @@ -0,0 +1,1010 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnfunctions.h + * Description: Public header file for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS NN Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS NN software library, + * a collection of efficient neural network kernels developed to maximize the + * performance and minimize the memory footprint of neural networks on Cortex-M processor cores. + * + * The library is divided into a number of functions each covering a specific category: + * - Neural Network Convolution Functions + * - Neural Network Activation Functions + * - Fully-connected Layer Functions + * - Neural Network Pooling Functions + * - Softmax Functions + * - Neural Network Support Functions + * + * The library has separate functions for operating on different weight and activation data + * types including 8-bit integers (q7_t) and 16-bit integers (q15_t). The descrition of the + * kernels are included in the function description. The implementation details are also + * described in this paper [1]. + * + * Block Diagram + * -------- + * \image html CMSIS-NN-OVERVIEW.PNG + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - ARM_MATH_DSP: + * + * Define macro ARM_MATH_DSP, If the silicon supports DSP instructions. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_NN_TRUNCATE: + * + * Define macro ARM_NN_TRUNCATE to use floor instead of round-to-the-nearest-int for the computation. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2018 Arm Limited. All rights reserved. + * + * [1] CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs https://arxiv.org/abs/1801.06601 + */ + +/** + * @defgroup groupNN Neural Network Functions + * These functions perform basic operations for neural network layers. + */ + +#ifndef _ARM_NNFUNCTIONS_H +#define _ARM_NNFUNCTIONS_H + +#include "arm_nnsupportfunctions.h" +#include "arm_nn_tables.h" + +#define USE_INTRINSIC + +//#define ARM_NN_TRUNCATE /* This config the rounding model to floor or round to the nearest int */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup NNConv Neural Network Convolution Functions + * + * Perform convolution layer + * + * The convolution is implemented in 2 steps: im2col and GEMM + * + * im2col is a process of converting each patch of image data into + * a column. After im2col, the convolution is computed as matrix-matrix + * multiplication. + * + * To reduce the memory footprint, the im2col is performed partially. + * Each iteration, only a few column (i.e., patches) are generated and + * computed with GEMM kernels similar to CMSIS-DSP arm_mat_mult functions. + * + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + */ + + arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function implement convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for + * second half of MobileNets after depthwise separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 version of convolution for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + + arm_status arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + + arm_status + arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + + arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB); + + /** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + +/** + * @defgroup FC Fully-connected Layer Functions + * + * Perform fully-connected layer + * + * Fully-connected layer is basically a matrix-vector multiplication + * with bias. The matrix is the weights and the input/output vectors + * are the activation values. Supported {weight, activation} precisions + * include {8-bit, 8-bit}, {16-bit, 16-bit}, and {8-bit, 16-bit}. + * + * Here we have two types of kernel functions. The basic function + * implements the function using regular GEMV approach. The opt functions + * operates with weights in interleaved formats. + * + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + */ + + arm_status arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer); + +/** + * @brief Matrix-Multiplication Kernels for Convolution + * + * These functions are used within convolution layer functions for + * matrix multiplication. + * + * The implementation is similar to CMSIS-DSP arm_mat_mult functions + * with one Q7 and one Q15 operands. The Q15 operand is the im2col + * output which is always with 2 columns. + * + */ + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + */ + + q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut); + +#ifdef __cplusplus +} +#endif + +/* + * Other functions + * These layers are typically not timing critical + * Basic implementation is supported here + */ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @defgroup Acti Neural Network Activation Functions + * + * Perform activation layers, including ReLU (Rectified Linear Unit), + * sigmoid and tanh + * + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q7(q7_t * data, uint16_t size); + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + */ + + void arm_relu_q15(q15_t * data, uint16_t size); + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + */ + + void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, + arm_nn_activation_type type); + +/** + * @defgroup Pooling Neural Network Pooling Functions + * + * Perform pooling functions, including max pooling and average pooling + * + */ + + /** + * @brief Q7 max pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + + /** + * @brief Q7 average pooling function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + */ + + void arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const uint16_t dim_im_out, + q7_t * bufferA, + q7_t * Im_out); + +/** + * @defgroup Softmax Softmax Functions + * + * EXP(2) based softmax function + * + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out); + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + */ + + void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/NN/Include/arm_nnsupportfunctions.h b/NN/Include/arm_nnsupportfunctions.h new file mode 100644 index 0000000..8460190 --- /dev/null +++ b/NN/Include/arm_nnsupportfunctions.h @@ -0,0 +1,202 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nnsupportfunctions.h + * Description: Public header file of support functions for CMSIS NN Library + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#ifndef _ARM_NNSUPPORTFUNCTIONS_H_ +#define _ARM_NNSUPPORTFUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_common_tables.h" +//#include <cstring> + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @brief Union for SIMD access of Q31/Q15/Q7 types + */ +union arm_nnword +{ + q31_t word; + /**< Q31 type */ + q15_t half_words[2]; + /**< Q15 type */ + q7_t bytes[4]; + /**< Q7 type */ +}; + +/** + * @brief Struct for specifying activation function types + * + */ +typedef enum +{ + ARM_SIGMOID = 0, + /**< Sigmoid activation function */ + ARM_TANH = 1, + /**< Tanh activation function */ +} arm_nn_activation_type; + +/** + * @defgroup nndata_convert Neural Network Data Conversion Functions + * + * Perform data type conversion in-between neural network operations + * + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize); + +#if defined (ARM_MATH_DSP) + +/** + * @brief read and expand one Q7 word into two Q15 words + */ + +__STATIC_FORCEINLINE void *read_and_pad(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; + q31_t inAbuf1 = __SXTB16(__ROR(inA, 8)); + q31_t inAbuf2 = __SXTB16(inA); + +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __PKHTB(inAbuf1, inAbuf2, 16); + *out1 = __PKHBT(inAbuf2, inAbuf1, 16); +#else + *out1 = __PKHTB(inAbuf1, inAbuf2, 16); + *out2 = __PKHBT(inAbuf2, inAbuf1, 16); +#endif + + return source; +} + +/** + * @brief read and expand one Q7 word into two Q15 words with reordering + */ + +__STATIC_FORCEINLINE void *read_and_pad_reordered(void *source, q31_t * out1, q31_t * out2) +{ + q31_t inA = *__SIMD32(source)++; +#ifndef ARM_MATH_BIG_ENDIAN + *out2 = __SXTB16(__ROR(inA, 8)); + *out1 = __SXTB16(inA); +#else + *out1 = __SXTB16(__ROR(inA, 8)); + *out2 = __SXTB16(inA); +#endif + + return source; +} +#endif + +/** + * @defgroup NNBasicMath Basic Math Functions for Neural Network Computation + * + * Basic Math Functions for Neural Network Computation + * + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize); + +/** + * @brief defition to adding rouding offset + */ +#ifndef ARM_NN_TRUNCATE + #define NN_ROUND(out_shift) ( 0x1 << (out_shift - 1) ) +#else + #define NN_ROUND(out_shift) 0 +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h new file mode 100644 index 0000000..4459a74 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM0/RTE_Components.h @@ -0,0 +1,20 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_cifar10' + * Target: 'ARMCM0' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM0.h" + + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h new file mode 100644 index 0000000..f12e4f3 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM3' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM3.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h new file mode 100644 index 0000000..d4542f5 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM4_FP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h new file mode 100644 index 0000000..97ef09a --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h @@ -0,0 +1,26 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'arm_nnexamples_nn_test' + * Target: 'ARMCM7_SP' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM7_SP.h" + +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +#define RTE_Compiler_IO_TTY /* Compiler I/O: TTY */ + #define RTE_Compiler_IO_TTY_ITM /* Compiler I/O: TTY ITM */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c new file mode 100644 index 0000000..0089709 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c new file mode 100644 index 0000000..e355ebf --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void +arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) + +{ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } +} + + diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c new file mode 100644 index 0000000..560cd23 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..1e2d19e --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c @@ -0,0 +1,78 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { +#ifndef ARM_NN_TRUNCATE + conv_out = ((q31_t) (bias[i]) << bias_shift) + (0x1 << (out_shift - 1)); +#else + conv_out = bias[i] << bias_shift; +#endif + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c new file mode 100644 index 0000000..1672a4e --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += Im_in[(in_row * dim_im_in + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c new file mode 100644 index 0000000..6ebd1f0 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ) +{ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output +#ifndef ARM_NN_TRUNCATE + int conv_out = (bias[i_ch_out] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int conv_out = bias[i_ch_out] << bias_shift; +#endif + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c new file mode 100644 index 0000000..09dd653 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c new file mode 100644 index 0000000..8fc74d4 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c new file mode 100644 index 0000000..2118f99 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 1; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c new file mode 100644 index 0000000..99ab4d9 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c new file mode 100644 index 0000000..567f964 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + q31_t sum = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum2 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum3 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); + q31_t sum4 = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + q31_t sum = *pBias++ << bias_shift; + q31_t sum2 = *pBias++ << bias_shift; + q31_t sum3 = *pBias++ << bias_shift; + q31_t sum4 = *pBias++ << bias_shift; +#endif + + uint16_t colCnt = dim_vec >> 2; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + pA = pV; +#ifndef ARM_NN_TRUNCATE + int ip_out = (*pBias++ << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = *pBias++ << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c new file mode 100644 index 0000000..f59f3db --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer) +{ + for (int i = 0; i < num_of_rows; i++) + { +#ifndef ARM_NN_TRUNCATE + int ip_out = (bias[i] << bias_shift) + (0x1 << (out_shift - 1)); +#else + int ip_out = bias[i] << bias_shift; +#endif + for (int j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c new file mode 100644 index 0000000..2cc6b72 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_nn_mult_q7_ref(q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q7_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 8); +#else + pDst[i] = (q7_t)__SSAT(product >> out_shift, 8); +#endif + } +} + +void arm_nn_mult_q15_ref(q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) { + uint16_t i; + +for (i = 0; i < blockSize; i++) + { + q31_t product = pSrcA[i] * pSrcB[i]; +#ifndef ARM_NN_TRUNCATE + pDst[i] = (q15_t)__SSAT((product + (0x1 << (out_shift - 1)))>>out_shift, 16); +#else + pDst[i] = (q15_t)__SSAT(product >> out_shift, 16); +#endif + + + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c new file mode 100644 index 0000000..9a4adb2 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ref_functions.h" + +void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } +} + +void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out) +{ + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c new file mode 100644 index 0000000..323fc11 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +void arm_relu_q7_ref(q7_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} + +void arm_relu_q15_ref(q15_t * data, uint16_t size) +{ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } +} diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h new file mode 100644 index 0000000..74b79f8 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h @@ -0,0 +1,7 @@ +#define IP2_WEIGHT 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+ +#define IP4_WEIGHT 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+ +#define IP4_q7_q15_WEIGHT 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+ +#define IP4_WEIGHT_Q15 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diff --git a/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h new file mode 100644 index 0000000..4a0647a --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h @@ -0,0 +1,250 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _REF_FUNCTIONS_H_ +#define _REF_FUNCTIONS_H_ + +#include "arm_math.h" +#include "arm_nnfunctions.h" +//#include "arm_nnsupportfunctions.h" +#include "fully_connected_testing_weights.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* + * + * Convolution reference implemenation + * + */ + + void arm_convolve_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + + void arm_convolve_HWC_q15_ref(const q15_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q15_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q15_t * bias, // bias + const uint16_t bias_shift, const uint16_t out_shift, q15_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_convolve_HWC_q15_nonsquare_ref(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB); + + void arm_depthwise_separable_conv_HWC_q7_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimention + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel, // filter kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out, // output image dimension + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + void arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(const q7_t * Im_in, // input image + const uint16_t dim_im_in_x, // input image dimention x + const uint16_t dim_im_in_y, // input image dimention y + const uint16_t ch_im_in, // number of input image channels + const q7_t * wt, // kernel weights + const uint16_t ch_im_out, // number of filters, i.e., output image channels + const uint16_t dim_kernel_x, // filter kernel size x + const uint16_t dim_kernel_y, // filter kernel size y + const uint16_t padding_x, // padding sizes x + const uint16_t padding_y, // padding sizes y + const uint16_t stride_x, // stride x + const uint16_t stride_y, // stride y + const q7_t * bias, // bias + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + q7_t * Im_out, // output image + const uint16_t dim_im_out_x, // output image dimension x + const uint16_t dim_im_out_y, // output image dimension y + q15_t * bufferA, //buffer space for input + q7_t * bufferB //buffer space for output + ); + +/* + * + * Fully-connected reference implemenation + * + */ + + void arm_fully_connected_q7_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q7_opt_ref(const q7_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q7_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_q15_opt_ref(const q15_t * pV, // pointer to vector + const q15_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q15_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + + void arm_fully_connected_mat_q7_vec_q15_opt_ref(const q15_t * pV, // pointer to vector + const q7_t * pM, // pointer to matrix + const uint16_t dim_vec, // length of the vector + const uint16_t num_of_rows, // numCol of A + const uint16_t bias_shift, // amount of left-shift for bias + const uint16_t out_shift, // amount of right-shift for output + const q7_t * bias, q15_t * pOut, // output operand + q15_t * vec_buffer); + +/* + * + * Pooling reference implemenation + * + */ + + void arm_avepool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + + void arm_maxpool_q7_HWC_ref(const q7_t * Im_in, // input image + const uint16_t dim_im_in, // input image dimension + const uint16_t ch_im_in, // number of input image channels + const uint16_t dim_kernel, // window kernel size + const uint16_t padding, // padding sizes + const uint16_t stride, // stride + const uint16_t dim_im_out, // output image dimension + q7_t * bufferA, // a buffer for local storage + q7_t * Im_out); + +/* + * + * Other reference implemenation + * + */ + + void arm_relu_q7_ref(q7_t * data, uint16_t size); + + void arm_relu_q15_ref(q15_t * data, uint16_t size); + + void arm_nn_mult_q7_ref(q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, const uint16_t out_shift, uint32_t blockSize); + + void arm_nn_mult_q15_ref(q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, const uint16_t out_shift, uint32_t blockSize); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp new file mode 100644 index 0000000..5cf72a2 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp @@ -0,0 +1,801 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2018 Arm Limited. All rights reserved. +* +* +* Project: CMSIS NN Library +* Title: arm_nnexamples_nn_test.cpp +* +* Description: Example code for NN kernel testing. +* +* Target Processor: Cortex-M cores +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#include "arm_nnexamples_nn_test.h" + +//#define TEST_SIGMOID +//#define TEST_TANH +#define TEST_POOL +#define TEST_RELU +#define TEST_IP +#define TEST_CONV +#define TEST_NONSQUARE +#define TEST_NNMULT + +int test_index = 0; +q7_t test_flags[50]; +bool test_pass; + +int main() +{ + printf("start tests\n"); + + srand(1); + + // common pointers for testing data + q7_t *test1; + q15_t *test2; + q7_t *test3; + q15_t *test4; + + for (test_index = 0; test_index<50; test_index++) { + test_flags[test_index] = -1; + } + test_index = 0; + +#ifdef TEST_NNMULT +#define NNMULT_DIM 128 + test1 = new q7_t[NNMULT_DIM*2]; + test2 = new q15_t[NNMULT_DIM*2]; + test3 = new q7_t[NNMULT_DIM*2]; + test4 = new q15_t[NNMULT_DIM*2]; + + q7_t * mult_out_q7 = test3; + q7_t * mult_ref_q7 = test3 + NNMULT_DIM; + q15_t * mult_out_q15 = test4; + q15_t * mult_ref_q15 = test4 + NNMULT_DIM; + + for (int i=0;i<NNMULT_DIM*2;i++) { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + } + + // Test q7 + arm_nn_mult_q7(test1, test1+NNMULT_DIM, mult_out_q7, 5, NNMULT_DIM); + + arm_nn_mult_q7_ref(test1, test1+NNMULT_DIM, mult_ref_q7, 5, NNMULT_DIM); + + verify_results_q7(mult_out_q7, mult_ref_q7, NNMULT_DIM); + + arm_nn_mult_q7(test1, test1+NNMULT_DIM, mult_out_q7, 9, NNMULT_DIM); + + arm_nn_mult_q7_ref(test1, test1+NNMULT_DIM, mult_ref_q7, 9, NNMULT_DIM); + + verify_results_q7(mult_out_q7, mult_ref_q7, NNMULT_DIM); + + // Test q15 + arm_nn_mult_q15(test2, test2+NNMULT_DIM, mult_out_q15, 13, NNMULT_DIM); + + arm_nn_mult_q15_ref(test2, test2+NNMULT_DIM, mult_ref_q15, 13, NNMULT_DIM); + + verify_results_q15(mult_out_q15, mult_ref_q15, NNMULT_DIM); + + arm_nn_mult_q15(test2, test2+NNMULT_DIM, mult_out_q15, 18, NNMULT_DIM); + + arm_nn_mult_q15_ref(test2, test2+NNMULT_DIM, mult_ref_q15, 18, NNMULT_DIM); + + verify_results_q15(mult_out_q15, mult_ref_q15, NNMULT_DIM); + +#endif + +#ifdef TEST_SIGMOID + +#define SIGMOID_DIM 128 + + /* This part tests the running of sigmoid functions */ + + test1 = new q7_t[SIGMOID_DIM]; + test2 = new q15_t[SIGMOID_DIM]; + test3 = new q7_t[SIGMOID_DIM]; + test4 = new q15_t[SIGMOID_DIM]; + + srand(1); + + for (int i = 0; i < SIGMOID_DIM; i++) + { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + arm_nn_activations_direct_q7(test3, SIGMOID_DIM, 3, ARM_SIGMOID); + + for (int i = 0; i < SIGMOID_DIM; i++) + { + printf("in: %d out: %d\n", test1[i], test3[i]); + } + + printf("start testing q15_t sigmoid\n\n"); + + arm_nn_activations_direct_q15(test4, SIGMOID_DIM, 3, ARM_SIGMOID); + + for (int i = 0; i < SIGMOID_DIM; i++) + { + printf("in: %d out: %d\n", test2[i], test4[i]); + } + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_TANH + +#define TANH_DIM 128 + + /* This part tests the running of sigmoid functions */ + + test1 = new q7_t[TANH_DIM]; + test2 = new q15_t[TANH_DIM]; + test3 = new q7_t[TANH_DIM]; + test4 = new q15_t[TANH_DIM]; + + srand(1); + + for (int i = 0; i < TANH_DIM; i++) + { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + arm_nn_activations_direct_q7(test3, TANH_DIM, 3, ARM_TANH); + + printf("start testing q7_t tanh\n\n"); + + for (int i = 0; i < TANH_DIM; i++) + { + printf("in: %d out: %d\n", test1[i], test3[i]); + } + + printf("start testing q15_t tanh\n\n"); + + arm_nn_activations_direct_q15(test4, TANH_DIM, 3, ARM_TANH); + + for (int i = 0; i < TANH_DIM; i++) + { + printf("in: %d out: %d\n", test2[i], test4[i]); + } + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_POOL + +#define POOL_IM_DIM 32 +#define POOL_IM_CH 8 + + test1 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH * 2]; + test2 = new q15_t[POOL_IM_DIM * POOL_IM_CH]; + test3 = new q7_t[POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH]; + + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + test1[i] = (rand() % 256 - 128); + } + + q7_t *img_in = test1 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; + q7_t *pool_out_ref = test3; + q7_t *pool_out_opt = test3 + POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH / 2; + + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + test3[i] = 0; + } + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + img_in[i] = test1[i]; + } + + initialize_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + + printf("Start maxpool reference implementation\n"); + + arm_maxpool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_ref); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + img_in[i] = test1[i]; + } + + printf("Start maxpool opt implementation\n"); + + arm_maxpool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_opt); + + verify_results_q7(pool_out_ref, pool_out_opt, POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + img_in[i] = test1[i]; + } + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + img_in[i] = test1[i]; + } + + printf("Start avepool ref implementation\n"); + + arm_avepool_q7_HWC_ref(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_ref); + + // copy over the img input + for (int i = 0; i < POOL_IM_DIM * POOL_IM_DIM * POOL_IM_CH; i++) + { + img_in[i] = test1[i]; + } + + printf("Start avepool opt implementation\n"); + + arm_avepool_q7_HWC(img_in, POOL_IM_DIM, POOL_IM_CH, 3, 0, 2, POOL_IM_DIM / 2, (q7_t *) test2, pool_out_opt); + + // special check here + bool if_ave_pool_match = true; + for (int i = 0; i < POOL_IM_DIM / 2 * POOL_IM_DIM / 2 * POOL_IM_CH; i++) + { + // we tolerate at most difference of 1 here because of rounding errors + if (pool_out_ref[i] - pool_out_opt[i] >= 2 || pool_out_opt[i] - pool_out_ref[i] >= 2) + { + printf("Output mismatch at %d, expected %d, actual %d\n", i, pool_out_ref[i], pool_out_opt[i]); + if_ave_pool_match = false; + } + } + if (if_ave_pool_match == true) + { + printf("Outputs match.\n"); + } + + delete[]test1; + delete[]test2; + delete[]test3; + +#endif + +#ifdef TEST_RELU + +#define RELU_DIM 127 + + test1 = new q7_t[RELU_DIM]; + test2 = new q15_t[RELU_DIM]; + test3 = new q7_t[RELU_DIM]; + test4 = new q15_t[RELU_DIM]; + + for (int i = 0; i < RELU_DIM; i++) + { + test1[i] = (rand() % 256 - 128); + test2[i] = (rand() % 65536 - 32768); + test3[i] = test1[i]; + test4[i] = test2[i]; + } + + q7_t *relu_ref_data_q7 = test1; + q7_t *relu_opt_data_q7 = test3; + q15_t *relu_ref_data_q15 = test2; + q15_t *relu_opt_data_q15 = test4; + + printf("Start ref relu q7 implementation\n"); + + arm_relu_q7_ref(relu_ref_data_q7, RELU_DIM); + + printf("Start opt relu q7 implementation\n"); + + arm_relu_q7(relu_opt_data_q7, RELU_DIM); + + verify_results_q7(relu_ref_data_q7, relu_opt_data_q7, RELU_DIM); + + printf("Start ref relu q15 implementation\n"); + + arm_relu_q15_ref(relu_ref_data_q15, RELU_DIM); + + printf("Start opt relu q15 implementation\n"); + + arm_relu_q15(relu_opt_data_q15, RELU_DIM); + + verify_results_q15(relu_ref_data_q15, relu_opt_data_q15, RELU_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_IP + +#define IP_ROW_DIM 127 +#define IP_COL_DIM 127 + + q7_t ip_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q7_t ip_q7_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT; + q7_t ip_q7_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_q7_q15_WEIGHT; + q15_t ip_q15_weights[IP_ROW_DIM * IP_COL_DIM] = IP2_WEIGHT; + q15_t ip_q15_opt_weights[IP_ROW_DIM * IP_COL_DIM] = IP4_WEIGHT_Q15; + + test1 = new q7_t[IP_COL_DIM + IP_ROW_DIM]; + test2 = new q15_t[IP_COL_DIM]; + test3 = new q7_t[IP_ROW_DIM * 3]; + test4 = new q15_t[IP_COL_DIM + IP_ROW_DIM * 2]; + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test1[i] = rand() % 256 - 100; + } + for (int i = 0; i < IP_ROW_DIM * 3; i++) + { + test3[i] = 0; + } + + q7_t *ip_bias_q7 = test1 + IP_COL_DIM; + + q7_t *ip_out_q7_ref = test3; + q7_t *ip_out_q7_opt = test3 + IP_ROW_DIM; + q7_t *ip_out_q7_opt_fast = test3 + 2 * IP_ROW_DIM; + q15_t *ip_out_q15_ref = test4 + IP_COL_DIM; + q15_t *ip_out_q15_opt = test4 + IP_COL_DIM + IP_ROW_DIM; + + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + initialize_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start ref q7 implementation\n"); + + arm_fully_connected_q7_ref(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_ref, test2); + + printf("Start q7 implementation\n"); + + arm_fully_connected_q7(test1, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt, IP_ROW_DIM); + + printf("Start q7 ref opt implementation\n"); + + arm_fully_connected_q7_opt_ref(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q7_opt_fast, test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + printf("Start q7 opt implementation\n"); + + arm_fully_connected_q7_opt(test1, ip_q7_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q7_opt_fast, + test2); + + verify_results_q7(ip_out_q7_ref, ip_out_q7_opt_fast, IP_ROW_DIM); + + for (int i = 0; i < IP_ROW_DIM + IP_COL_DIM; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q15 implementation\n"); + + arm_fully_connected_q15_ref(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_ref, NULL); + + printf("Start q15 implementation\n"); + + arm_fully_connected_q15(test4, ip_q15_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q15 implementation\n"); + + arm_fully_connected_q15_opt_ref(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, + NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q15 implementation\n"); + + arm_fully_connected_q15_opt(test4, ip_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, test2, ip_out_q15_opt, NULL); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + initialize_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_ref(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_ref, + test2); + + printf("Start q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15(test4, ip_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, ip_out_q15_opt, + test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start ref opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt_ref(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + printf("Start opt q7_q15 implementation\n"); + + arm_fully_connected_mat_q7_vec_q15_opt(test4, ip_q7_q15_opt_weights, IP_COL_DIM, IP_ROW_DIM, 1, 7, ip_bias_q7, + ip_out_q15_opt, test2); + + verify_results_q15(ip_out_q15_ref, ip_out_q15_opt, IP_ROW_DIM); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + +#ifdef TEST_NONSQUARE + +/* Use RCONV to differential with square CONV */ + +#define RCONV_IM_DIM_X 10 +#define RCONV_IM_DIM_Y 8 +#define RCONV_IM_CH 4 +#define RCONV_KER_DIM_X 5 +#define RCONV_KER_DIM_Y 3 +#define RCONV_STRIDE_X 1 +#define RCONV_STRIDE_Y 1 +#define RCONV_PADDING_X 2 +#define RCONV_PADDING_Y 1 +#define RCONV_OUT_CH 4 +#define RCONV_OUT_DIM_X 10 +#define RCONV_OUT_DIM_Y 8 + + test1 = new q7_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; + test2 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH]; + test3 = + new q7_t[RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + q7_t *rconv_weight_q7 = test1; + q7_t *rconv_bias_q7 = test1 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + q15_t *rconv_buf = test2; + + q7_t *rconv_im_in_q7 = test3; + q7_t *rconv_im_out_ref_q7 = test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q7_t *rconv_im_out_opt_q7 = + test3 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare opt implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q7 nonsquare ref implementation\n"); + arm_convolve_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q7 nonsquare basic implementation\n"); + arm_convolve_HWC_q7_basic_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + initialize_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start 1x1 conv q7 nonsquare fast implementation\n"); + arm_convolve_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start 1x1 conv q7 nonsquare dedicated function implementation\n"); + arm_convolve_1x1_HWC_q7_fast_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q7, + RCONV_OUT_CH, 1, 1, 0, 0, RCONV_STRIDE_X, + RCONV_STRIDE_Y, rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start depthwise separable conv q7 nonsquare ref implementation\n"); + arm_depthwise_separable_conv_HWC_q7_ref_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_ref_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start depthwise separable conv q7 nonsquare opt implementation\n"); + arm_depthwise_separable_conv_HWC_q7_nonsquare(rconv_im_in_q7, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, + rconv_weight_q7, RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, + RCONV_PADDING_X, RCONV_PADDING_Y, RCONV_STRIDE_X, RCONV_STRIDE_Y, + rconv_bias_q7, 1, 7, rconv_im_out_opt_q7, RCONV_OUT_DIM_X, + RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q7(rconv_im_out_ref_q7, rconv_im_out_opt_q7, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + + test2 = new q15_t[RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH]; // weights + bias + test4 = new q15_t[2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH //buffer + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH]; // i/o + + for (int i = 0; i < RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH + RCONV_OUT_CH; i++) + { + test2[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH + + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH + 2 * RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + i++) + { + test4[i] = rand() % 256 - 100; + } + + q15_t *rconv_weight_q15 = test2; + q15_t *rconv_bias_q15 = test2 + RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH * RCONV_OUT_CH; + + rconv_buf = test4; + + q15_t *rconv_im_in_q15 = test4 + 2 * RCONV_KER_DIM_Y * RCONV_KER_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_ref_q15 = rconv_im_in_q15 + RCONV_IM_DIM_Y * RCONV_IM_DIM_X * RCONV_IM_CH; + q15_t *rconv_im_out_opt_q15 = rconv_im_out_ref_q15 + RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH; + + initialize_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + printf("start conv q15 nonsquare ref implementation\n"); + arm_convolve_HWC_q15_nonsquare_ref(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_ref_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + printf("start conv q5 nonsquare opt implementation\n"); + arm_convolve_HWC_q15_fast_nonsquare(rconv_im_in_q15, RCONV_IM_DIM_X, RCONV_IM_DIM_Y, RCONV_IM_CH, rconv_weight_q15, + RCONV_OUT_CH, RCONV_KER_DIM_X, RCONV_KER_DIM_Y, RCONV_PADDING_X, RCONV_PADDING_Y, + RCONV_STRIDE_X, RCONV_STRIDE_Y, rconv_bias_q15, 1, 7, rconv_im_out_opt_q15, + RCONV_OUT_DIM_X, RCONV_OUT_DIM_Y, rconv_buf, NULL); + + verify_results_q15(rconv_im_out_ref_q15, rconv_im_out_opt_q15, RCONV_OUT_DIM_Y * RCONV_OUT_DIM_X * RCONV_OUT_CH); + + delete [] test2; + delete [] test4; +#endif + +#ifdef TEST_CONV + +#define CONV_IM_DIM 16 +#define CONV_IM_CH 16 +#define CONV_KER_DIM 5 +#define CONV_OUT_CH 16 +#define CONV_OUT_DIM 16 + + test1 = new q7_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test2 = + new q15_t[CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH]; + test3 = new q7_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + test4 = new q15_t[CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH]; + + for (int i = 0; i < CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test1[i] = rand() % 256 - 100; + } + + for (int i = 0; + i < + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + CONV_OUT_CH; i++) + { + test2[i] = (rand() % 65536 - 32768); + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test3[i] = rand() % 256 - 100; + } + + for (int i = 0; i < CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + 2 * CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; i++) + { + test4[i] = (rand() % 65536 - 32768); + } + + q7_t *conv_weight_q7 = test1; + q7_t *conv_bias_q7 = test1 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q15_t *conv_weight_q15 = test2; + q15_t *conv_buf = test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + q15_t *conv_bias_q15 = + test2 + CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH + + 2 * CONV_KER_DIM * CONV_KER_DIM * CONV_IM_CH * CONV_OUT_CH; + + q7_t *conv_im_in_q7 = test3; + q7_t *conv_im_out_ref_q7 = test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q7_t *conv_im_out_opt_q7 = + test3 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + q15_t *conv_im_in_q15 = test4; + q15_t *conv_im_out_ref_q15 = test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH; + q15_t *conv_im_out_opt_q15 = + test4 + CONV_IM_DIM * CONV_IM_DIM * CONV_IM_CH + CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH; + + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 ref implementation\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 fast implementation\n"); + + arm_convolve_HWC_q7_fast(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing with RGB + printf("start q7 ref implementation for RGB\n"); + + arm_convolve_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 basic implementation for RGB\n"); + + arm_convolve_HWC_q7_basic(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 RGB implementation for RGB\n"); + + arm_convolve_HWC_q7_RGB(conv_im_in_q7, CONV_IM_DIM, 3, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // testing q15 + initialize_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 ref implementation\n"); + + arm_convolve_HWC_q15_ref(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_ref_q15, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q15 basic implementation\n"); + + arm_convolve_HWC_q15_basic(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q15 fast implementation\n"); + + arm_convolve_HWC_q15_fast(conv_im_in_q15, CONV_IM_DIM, CONV_IM_CH, conv_weight_q15, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q15, 0, 15, conv_im_out_opt_q15, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q15(conv_im_out_ref_q15, conv_im_out_opt_q15, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + // depthwise separable conv + initialize_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + printf("start q7 depthwise_separable_conv ref implementation\n"); + + arm_depthwise_separable_conv_HWC_q7_ref(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_ref_q7, + CONV_OUT_DIM, conv_buf, NULL); + + printf("start q7 depthwise_separable_conv implementation\n"); + + arm_depthwise_separable_conv_HWC_q7(conv_im_in_q7, CONV_IM_DIM, CONV_IM_CH, conv_weight_q7, + CONV_OUT_CH, CONV_KER_DIM, 2, 1, conv_bias_q7, 1, 7, conv_im_out_opt_q7, + CONV_OUT_DIM, conv_buf, NULL); + + verify_results_q7(conv_im_out_ref_q7, conv_im_out_opt_q7, CONV_OUT_DIM * CONV_OUT_DIM * CONV_OUT_CH); + + delete[]test1; + delete[]test2; + delete[]test3; + delete[]test4; + +#endif + + test_pass = true; + test_index = 0; + while (test_flags[test_index] != -1) { + if (test_flags[test_index]) { + test_pass = false; + } + test_index ++; + } + if (test_pass) { + printf("All tests passed\n"); + } else { + printf("Test failed passed\n"); + } + + return 0; +} diff --git a/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h new file mode 100644 index 0000000..264b755 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h @@ -0,0 +1,78 @@ +#ifndef _MAIN_H_ +#define _MAIN_H_ + +#include <stdio.h> +#include <stdlib.h> +#include <math.h> + +#include "arm_math.h" + +#include "arm_nnfunctions.h" +#include "ref_functions.h" + +extern int test_index; +extern q7_t test_flags[50]; + +void initialize_results_q7(q7_t * ref, q7_t * opt, int length) +{ + arm_fill_q7(0, ref, length); + arm_fill_q7(37, opt, length); +} + +void initialize_results_q15(q15_t * ref, q15_t * opt, int length) +{ + arm_fill_q15(0, ref, length); + arm_fill_q15(0x5F5, opt, length); +} + +void verify_results_q7(q7_t * ref, q7_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +void verify_results_q15(q15_t * ref, q15_t * opt, int length) +{ + + bool if_match = true; + + for (int i = 0; i < length; i++) + { + if (ref[i] != opt[i]) + { + printf("Output mismatch at %d, expected %d, actual %d\r\n", i, ref[i], opt[i]); + + if_match = false; + } + } + + if (if_match == true) + { + printf("Outputs match.\r\n\r\n"); + test_flags[test_index++] = 0; + } else { + test_flags[test_index++] = 1; + } + +} + +#endif diff --git a/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.ini b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.ini new file mode 100644 index 0000000..071a116 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.ini @@ -0,0 +1,26 @@ +/* This file automatically runs the tests and extract out results */ + +FUNC void check_results (void) +{ + if (test_pass) { + exec("LOG > NN_TEST.log"); + printf("Test passed\n"); + exec("LOG OFF"); + } else { + exec("LOG > NN_TEST.log"); + printf("Test failed\n"); + exec("D test_flags"); + exec("LOG OFF"); + } +} + + + +RESET /* Reset the target processor */ +LOG OFF /* Turn off Logging by default. */ + +G + +check_results() + +EXIT
\ No newline at end of file diff --git a/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.uvoptx b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.uvoptx new file mode 100644 index 0000000..bcc0ff2 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.uvoptx @@ -0,0 +1,1622 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no" ?> +<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd"> + + <SchemaVersion>1.0</SchemaVersion> + + <Header>### uVision Project, (C) Keil Software</Header> + + <Extensions> + <cExt>*.c</cExt> + <aExt>*.s*; *.src; *.a*</aExt> + <oExt>*.obj; *.o</oExt> + <lExt>*.lib</lExt> + <tExt>*.txt; *.h; *.inc</tExt> + <pExt>*.plm</pExt> + <CppX>*.cpp</CppX> + <nMigrate>0</nMigrate> + </Extensions> + + <DaveTm> + <dwLowDateTime>0</dwLowDateTime> + <dwHighDateTime>0</dwHighDateTime> + </DaveTm> + + <Target> + <TargetName>ARMCM3</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>10000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM3_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile>.\arm_nnexamples_nn_test.ini</sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMCM4_FP</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>100000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM4_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile>.\arm_nnexamples_nn_test.ini</sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=341,284,717,520,0)(1009=-1,-1,-1,-1,0)(1012=347,325,822,639,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>1</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>1</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMCM7_SP</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM7_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile>.\arm_nnexamples_nn_test.ini</sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM7_SP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <MemoryWindow1> + <Mm> + <WinNumber>1</WinNumber> + <SubType>0</SubType> + <ItemText>0x20000700</ItemText> + <AccSizeX>0</AccSizeX> + </Mm> + </MemoryWindow1> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>0</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>0</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMCM4b_FP</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>100000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM4_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>1</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + <uSim>1</uSim> + <uTrg>0</uTrg> + <sLdApp>1</sLdApp> + <sGomain>1</sGomain> + <sRbreak>1</sRbreak> + <sRwatch>1</sRwatch> + <sRmem>1</sRmem> + <sRfunc>1</sRfunc> + <sRbox>1</sRbox> + <tLdApp>1</tLdApp> + <tGomain>1</tGomain> + <tRbreak>1</tRbreak> + <tRwatch>1</tRwatch> + <tRmem>1</tRmem> + <tRfunc>0</tRfunc> + <tRbox>1</tRbox> + <tRtrace>0</tRtrace> + <sRSysVw>1</sRSysVw> + <tRSysVw>1</tRSysVw> + <sRunDeb>0</sRunDeb> + <sLrtime>0</sLrtime> + <bEvRecOn>1</bEvRecOn> + <nTsel>0</nTsel> + <sDll></sDll> + <sDllPa></sDllPa> + <sDlgDll></sDlgDll> + <sDlgPa></sDlgPa> + <sIfile>.\arm_nnexamples_nn_test.ini</sIfile> + <tDll></tDll> + <tDllPa></tDllPa> + <tDlgDll></tDlgDll> + <tDlgPa></tDlgPa> + <tIfile></tIfile> + <pMon>BIN\UL2CM3.DLL</pMon> + </DebugOpt> + <TargetDriverDllRegistry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMRTXEVENTFLAGS</Key> + <Name>-L70 -Z18 -C0 -M0 -T1</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>UL2CM3</Key> + <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>DLGDARM</Key> + <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=341,284,717,520,0)(1009=-1,-1,-1,-1,0)(1012=347,325,822,639,0)</Name> + </SetRegEntry> + <SetRegEntry> + <Number>0</Number> + <Key>ARMDBGFLAGS</Key> + <Name>-T0</Name> + </SetRegEntry> + </TargetDriverDllRegistry> + <Breakpoint/> + <Tracepoint> + <THDelay>0</THDelay> + </Tracepoint> + <DebugFlag> + <trace>0</trace> + <periodic>0</periodic> + <aLwin>1</aLwin> + <aCover>0</aCover> + <aSer1>0</aSer1> + <aSer2>0</aSer2> + <aPa>0</aPa> + <viewmode>1</viewmode> + <vrSel>0</vrSel> + <aSym>0</aSym> + <aTbox>0</aTbox> + <AscS1>0</AscS1> + <AscS2>0</AscS2> + <AscS3>0</AscS3> + <aSer3>0</aSer3> + <eProf>1</eProf> + <aLa>0</aLa> + <aPa1>0</aPa1> + <AscS4>0</AscS4> + <aSer4>0</aSer4> + <StkLoc>1</StkLoc> + <TrcWin>0</TrcWin> + <newCpu>0</newCpu> + <uProt>0</uProt> + </DebugFlag> + <LintExecutable></LintExecutable> + <LintConfigFile></LintConfigFile> + <bLintAuto>0</bLintAuto> + <bAutoGenD>0</bAutoGenD> + <LntExFlags>0</LntExFlags> + <pMisraName></pMisraName> + <pszMrule></pszMrule> + <pSingCmds></pSingCmds> + <pMultCmds></pMultCmds> + <pMisraNamep></pMisraNamep> + <pszMrulep></pszMrulep> + <pSingCmdsp></pSingCmdsp> + <pMultCmdsp></pMultCmdsp> + </TargetOption> + </Target> + + <Target> + <TargetName>ARMCM7b_SP</TargetName> + <ToolsetNumber>0x4</ToolsetNumber> + <ToolsetName>ARM-ADS</ToolsetName> + <TargetOption> + <CLKADS>12000000</CLKADS> + <OPTTT> + <gFlags>1</gFlags> + <BeepAtEnd>1</BeepAtEnd> + <RunSim>0</RunSim> + <RunTarget>1</RunTarget> + <RunAbUc>0</RunAbUc> + </OPTTT> + <OPTHX> + <HexSelection>1</HexSelection> + <FlashByte>65535</FlashByte> + <HexRangeLowAddress>0</HexRangeLowAddress> + <HexRangeHighAddress>0</HexRangeHighAddress> + <HexOffset>0</HexOffset> + </OPTHX> + <OPTLEX> + <PageWidth>79</PageWidth> + <PageLength>66</PageLength> + <TabStop>8</TabStop> + <ListingPath>.\ARMCM7_debug\</ListingPath> + </OPTLEX> + <ListingPage> + <CreateCListing>1</CreateCListing> + <CreateAListing>1</CreateAListing> + <CreateLListing>1</CreateLListing> + <CreateIListing>0</CreateIListing> + <AsmCond>1</AsmCond> + <AsmSymb>1</AsmSymb> + <AsmXref>0</AsmXref> + <CCond>1</CCond> + <CCode>0</CCode> + <CListInc>0</CListInc> + <CSymb>0</CSymb> + <LinkerCodeListing>0</LinkerCodeListing> + </ListingPage> + <OPTXL> + <LMap>1</LMap> + <LComments>1</LComments> + <LGenerateSymbols>1</LGenerateSymbols> + <LLibSym>1</LLibSym> + <LLines>1</LLines> + <LLocSym>1</LLocSym> + <LPubSym>1</LPubSym> + <LXref>0</LXref> + <LExpSel>0</LExpSel> + </OPTXL> + <OPTFL> + <tvExp>1</tvExp> + <tvExpOptDlg>0</tvExpOptDlg> + <IsCurrentTarget>0</IsCurrentTarget> + </OPTFL> + <CpuCode>7</CpuCode> + <DebugOpt> + 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removed="1">RTE\Device\ARMCM4\startup_ARMCM4.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/> + <targetInfos/> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0"> + <instance index="0" removed="1">RTE\Device\ARMCM4\system_ARMCM4.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.2.0"/> + <targetInfos/> + </file> + <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + <targetInfo name="ARMCM4_FP_truncate"/> + <targetInfo name="ARMCM4b_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM4 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM4_FP"/> + <targetInfo name="ARMCM4_FP_truncate"/> + <targetInfo name="ARMCM4b_FP"/> + </targetInfos> + </file> + <file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM7\Source\ARM\startup_ARMCM7.s" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\startup_ARMCM7.s</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + <targetInfo name="ARMCM7b_SP"/> + </targetInfos> + </file> + <file attr="config" category="sourceC" name="Device\ARM\ARMCM7\Source\system_ARMCM7.c" version="1.0.0"> + <instance index="0">RTE\Device\ARMCM7_SP\system_ARMCM7.c</instance> + <component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM7 CMSIS"/> + <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.3.0"/> + <targetInfos> + <targetInfo name="ARMCM7_SP"/> + <targetInfo name="ARMCM7b_SP"/> + </targetInfos> + </file> + </files> + </RTE> + +</Project> diff --git a/NN/NN_Lib_Tests/nn_test/readme.txt b/NN/NN_Lib_Tests/nn_test/readme.txt new file mode 100644 index 0000000..2e9e171 --- /dev/null +++ b/NN/NN_Lib_Tests/nn_test/readme.txt @@ -0,0 +1,4 @@ +CMSIS DSP_Lib example arm_nnexample_nn_test for + Cortex-M3, Cortex-M4 and Cortex-M7. + +The example is configured for uVision Simulator. diff --git a/NN/Scripts/NNFunctions/fully_connected_opt_weight_generation.py b/NN/Scripts/NNFunctions/fully_connected_opt_weight_generation.py new file mode 100644 index 0000000..0319e83 --- /dev/null +++ b/NN/Scripts/NNFunctions/fully_connected_opt_weight_generation.py @@ -0,0 +1,146 @@ +#!/usr/bin/env python + +import numpy as np + +def convert_to_x4_q7_weights(weights): + [r, h, w, c] = weights.shape + weights = np.reshape(weights, (r, h*w*c)) + num_of_rows = r + num_of_cols = h*w*c + new_weights = np.copy(weights) + new_weights = np.reshape(new_weights, (r*h*w*c)) + counter = 0 + for i in range(int(num_of_rows)/4): + # we only need to do the re-ordering for every 4 rows + row_base = 4*i + for j in range (int(num_of_cols)/4): + # for each 4 entries + column_base = 4*j + new_weights[counter] = weights[row_base ][column_base ] + new_weights[counter+1] = weights[row_base+1][column_base ] + new_weights[counter+2] = weights[row_base ][column_base+2] + new_weights[counter+3] = weights[row_base+1][column_base+2] + new_weights[counter+4] = weights[row_base+2][column_base ] + new_weights[counter+5] = weights[row_base+3][column_base ] + new_weights[counter+6] = weights[row_base+2][column_base+2] + new_weights[counter+7] = weights[row_base+3][column_base+2] + + new_weights[counter+8] = weights[row_base ][column_base+1] + new_weights[counter+9] = weights[row_base+1][column_base+1] + new_weights[counter+10] = weights[row_base ][column_base+3] + new_weights[counter+11] = weights[row_base+1][column_base+3] + new_weights[counter+12] = weights[row_base+2][column_base+1] + new_weights[counter+13] = weights[row_base+3][column_base+1] + new_weights[counter+14] = weights[row_base+2][column_base+3] + new_weights[counter+15] = weights[row_base+3][column_base+3] + counter = counter + 16 + # the remaining ones are in order + for j in range((int)(num_of_cols-num_of_cols%4), int(num_of_cols)): + new_weights[counter] = weights[row_base][j] + new_weights[counter+1] = weights[row_base+1][j] + new_weights[counter+2] = weights[row_base+2][j] + new_weights[counter+3] = weights[row_base+3][j] + counter = counter + 4 + return new_weights + +def convert_to_x4_q15_weights(weights): + [r, h, w, c] = weights.shape + weights = np.reshape(weights, (r, h*w*c)) + num_of_rows = r + num_of_cols = h*w*c + new_weights = np.copy(weights) + new_weights = np.reshape(new_weights, (r*h*w*c)) + counter = 0 + for i in range(int(num_of_rows)/4): + # we only need to do the re-ordering for every 4 rows + row_base = 4*i + for j in range (int(num_of_cols)/2): + # for each 2 entries + column_base = 2*j + new_weights[counter] = weights[row_base ][column_base ] + new_weights[counter+1] = weights[row_base ][column_base+1] + new_weights[counter+2] = weights[row_base+1][column_base ] + new_weights[counter+3] = weights[row_base+1][column_base+1] + new_weights[counter+4] = weights[row_base+2][column_base ] + new_weights[counter+5] = weights[row_base+2][column_base+1] + new_weights[counter+6] = weights[row_base+3][column_base ] + new_weights[counter+7] = weights[row_base+3][column_base+1] + + counter = counter + 8 + # the remaining ones are in order + for j in range((int)(num_of_cols-num_of_cols%2), int(num_of_cols)): + new_weights[counter] = weights[row_base][j] + new_weights[counter+1] = weights[row_base+1][j] + new_weights[counter+2] = weights[row_base+2][j] + new_weights[counter+3] = weights[row_base+3][j] + counter = counter + 4 + return new_weights + +def convert_q7_q15_weights(weights): + [r, h, w, c] = weights.shape + weights = np.reshape(weights, (r, h*w*c)) + num_of_rows = r + num_of_cols = h*w*c + new_weights = np.copy(weights) + new_weights = np.reshape(new_weights, (r*h*w*c)) + counter = 0 + for i in range(int(num_of_rows)/4): + # we only need to do the re-ordering for every 4 rows + row_base = 4*i + for j in range (int(num_of_cols)/2): + # for each 2 entries + column_base = 2*j + new_weights[counter] = weights[row_base ][column_base ] + new_weights[counter+1] = weights[row_base+1][column_base ] + new_weights[counter+2] = weights[row_base ][column_base+1] + new_weights[counter+3] = weights[row_base+1][column_base+1] + new_weights[counter+4] = weights[row_base+2][column_base ] + new_weights[counter+5] = weights[row_base+3][column_base ] + new_weights[counter+6] = weights[row_base+2][column_base+1] + new_weights[counter+7] = weights[row_base+3][column_base+1] + + counter = counter + 8 + # the remaining ones are in order + for j in range((int)(num_of_cols-num_of_cols%2), int(num_of_cols)): + new_weights[counter] = weights[row_base][j] + new_weights[counter+1] = weights[row_base+1][j] + new_weights[counter+2] = weights[row_base+2][j] + new_weights[counter+3] = weights[row_base+3][j] + counter = counter + 4 + return new_weights + +# input dimensions +vec_dim = 127 +row_dim = 127 + +weight = np.zeros((row_dim,vec_dim), dtype=int) + +# generate random inputs +for i in range(row_dim): + for j in range(vec_dim): + weight[i][j] = np.random.randint(256)-128 + +weight = np.reshape(weight, (row_dim, vec_dim, 1, 1)) + +outfile = open("../Ref_Implementations/fully_connected_testing_weights.h", "w") +outfile.write("#define IP2_WEIGHT {") +weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_to_x4_q7_weights(weight) +outfile.write("#define IP4_WEIGHT {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_q7_q15_weights(weight) +outfile.write("#define IP4_q7_q15_WEIGHT {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + +new_weight = convert_to_x4_q15_weights(weight) +outfile.write("#define IP4_WEIGHT_Q15 {") +new_weight.tofile(outfile,sep=",",format="%d") +outfile.write("}\n\n") + + +outfile.close() diff --git a/NN/Scripts/NNFunctions/table_gen.py b/NN/Scripts/NNFunctions/table_gen.py new file mode 100644 index 0000000..5db6d3e --- /dev/null +++ b/NN/Scripts/NNFunctions/table_gen.py @@ -0,0 +1,116 @@ +#!/usr/bin/python + +import math + +class Table(object): + + def __init__(self, table_entry=256, table_range=8): + self.table_entry = table_entry + self.table_range = table_range + pass + + def sigmoid(self, x): + return 1 / (1 + math.exp(-1*x)) + + def tanh(self, x): + return (math.exp(2*x)-1) / (math.exp(2*x)+1) + + def fp2q7(self, x): + x_int = math.floor(x*(2**7)+0.5) + if x_int >= 128 : + x_int = 127 + if x_int < -128 : + x_int = -128 + if x_int >= 0 : + return x_int + else : + return 0x100 + x_int + + def fp2q15(self, x): + x_int = math.floor(x*(2**15)+0.5) + if x_int >= 2**15 : + x_int = 2**15-1 + if x_int < -1*2**15 : + x_int = -1*2**15 + if x_int >= 0 : + return x_int + else : + return 0x10000 + x_int + + def table_gen(self): + outfile = open("NNCommonTable.c", "wb") + + outfile.write("/*\n * Common tables for NN\n *\n *\n *\n *\n */\n\n#include \"arm_math.h\"\n#include \"NNCommonTable.h\"\n\n/*\n * Table for sigmoid\n */\n") + + for function_type in ["sigmoid", "tanh"]: + for data_type in [7, 15]: + out_type = "q"+str(data_type)+"_t" + act_func = getattr(self, function_type) + quan_func = getattr(self, 'fp2q'+str(data_type)) + + # unified table + outfile.write('const %s %sTable_q%d[%d] = {\n' % (out_type, function_type, data_type, self.table_entry) ) + for i in range(self.table_entry): + # convert into actual value + if i < self.table_entry/2: + value_q7 = self.table_range * (i) + else: + value_q7 = self.table_range * (i - self.table_entry) + + if data_type == 7: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%02x, ' % (quan_func(act_func(float(value_q7)/self.table_entry)))) + else: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%04x, ' % (quan_func(act_func(float(value_q7)/self.table_entry)))) + if i % 8 == 7: + outfile.write("\n") + outfile.write("};\n\n") + + for data_type in [15]: + out_type = "q"+str(data_type)+"_t" + act_func = getattr(self, function_type) + quan_func = getattr(self, 'fp2q'+str(data_type)) + + # H-L tables + outfile.write('const %s %sLTable_q%d[%d] = {\n' % (out_type, function_type, data_type, self.table_entry/2)) + for i in range(self.table_entry/2): + # convert into actual value, max value is 16*self.table_entry/4 / 4 + # which is equivalent to self.table_entry / self.table_entry/2 = 2, i.e., 1/4 of 8 + if i < self.table_entry/4: + value_q7 = self.table_range * i / 4 + else: + value_q7 = self.table_range * (i - self.table_entry/2) / 4 + if data_type == 7: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%02x, ' % (quan_func(act_func(float(value_q7)/(self.table_entry/2))))) + else: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%04x, ' % (quan_func(act_func(float(value_q7)/(self.table_entry/2))))) + if i % 8 == 7: + outfile.write("\n") + outfile.write("};\n\n") + + outfile.write('const %s %sHTable_q%d[%d] = {\n' % (out_type, function_type, data_type, 3*self.table_entry/4)) + for i in range(3 * self.table_entry/4): + # convert into actual value, tageting range (2, 8) + if i < 3*self.table_entry/8 : + value_q7 = self.table_range * ( i + self.table_entry/8 ) + else: + value_q7 = self.table_range * ( i + self.table_entry/8 - self.table_entry) + if data_type == 7: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%02x, ' % (quan_func(act_func(float(value_q7)/self.table_entry)))) + else: + #outfile.write('%f, ' % (act_func(float(value_q7)/256))) + outfile.write('0x%04x, ' % (quan_func(act_func(float(value_q7)/self.table_entry)))) + if i % 8 == 7: + outfile.write("\n") + outfile.write("};\n\n") + + outfile.close() + + +mytable = Table(table_entry=256, table_range=16) + +mytable.table_gen() diff --git a/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/NN/Source/ActivationFunctions/arm_nn_activations_q15.c new file mode 100644 index 0000000..9c64e2a --- /dev/null +++ b/NN/Source/ActivationFunctions/arm_nn_activations_q15.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q15.c + * Description: Q15 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q15(q15_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q15_t *pIn = data; + q15_t *pOut = data; + uint16_t shift_size = 8 + 3 - int_width; + uint32_t bit_mask = 0x7FF >> int_width; + uint32_t full_frac = bit_mask + 1; + const q15_t *lookup_table; + + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q15; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q15; + break; + } + + while (i) + { + q15_t out; + q15_t in = *pIn++; + q15_t frac = (uint32_t) in & bit_mask; + q15_t value = lookup_table[__USAT(in >> shift_size, 8)]; + q15_t value2 = lookup_table[__USAT(1 + (in >> shift_size), 8)]; + + /* doing the interpolation here for better accuracy */ + out = ((q31_t) (full_frac - frac) * value + (q31_t) value2 * frac) >> shift_size; + + *pOut++ = out; + i--; + } + +} + +/** + * @} end of Acti group + */ diff --git a/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/NN/Source/ActivationFunctions/arm_nn_activations_q7.c new file mode 100644 index 0000000..1ca429f --- /dev/null +++ b/NN/Source/ActivationFunctions/arm_nn_activations_q7.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_activations_q7.c + * Description: Q7 neural network activation function using direct table look-up + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 neural network activation function using direct table look-up + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @param[in] int_width bit-width of the integer part, assume to be smaller than 3 + * @param[in] type type of activation functions + * @return none. + * + * @details + * + * This is the direct table look-up approach. + * + * Assume here the integer part of the fixed-point is <= 3. + * More than 3 just not making much sense, makes no difference with + * saturation followed by any of these activation functions. + */ + +void arm_nn_activations_direct_q7(q7_t * data, uint16_t size, uint16_t int_width, arm_nn_activation_type type) +{ + uint16_t i = size; + q7_t *pIn = data; + q7_t *pOut = data; + q7_t in; + q7_t out; + uint16_t shift_size = 3 - int_width; + const q7_t *lookup_table; + switch (type) + { + case ARM_SIGMOID: + lookup_table = sigmoidTable_q7; + break; + case ARM_TANH: + default: + lookup_table = tanhTable_q7; + break; + } + while (i) + { + in = *pIn++; + out = lookup_table[(uint8_t) (in >> shift_size)]; + *pOut++ = out; + i--; + } +} + +/** + * @} end of Acti group + */ diff --git a/NN/Source/ActivationFunctions/arm_relu_q15.c b/NN/Source/ActivationFunctions/arm_relu_q15.c new file mode 100644 index 0000000..571d51c --- /dev/null +++ b/NN/Source/ActivationFunctions/arm_relu_q15.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q15.c + * Description: Q15 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q15 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q15(q15_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 1; + q15_t *pIn = data; + q15_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80008000, 15); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB16(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + if (size & 0x1) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/NN/Source/ActivationFunctions/arm_relu_q7.c b/NN/Source/ActivationFunctions/arm_relu_q7.c new file mode 100644 index 0000000..013325c --- /dev/null +++ b/NN/Source/ActivationFunctions/arm_relu_q7.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_relu_q7.c + * Description: Q7 version of ReLU + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Acti + * @{ + */ + + /** + * @brief Q7 RELU function + * @param[in,out] data pointer to input + * @param[in] size number of elements + * @return none. + * + * @details + * + * Optimized relu with QSUB instructions. + * + */ + +void arm_relu_q7(q7_t * data, uint16_t size) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + uint16_t i = size >> 2; + q7_t *pIn = data; + q7_t *pOut = data; + q31_t in; + q31_t buf; + q31_t mask; + + while (i) + { + in = *__SIMD32(pIn)++; + + /* extract the first bit */ + buf = __ROR(in & 0x80808080, 7); + + /* if MSB=1, mask will be 0xFF, 0x0 otherwise */ + mask = __QSUB8(0x00000000, buf); + + *__SIMD32(pOut)++ = in & (~mask); + i--; + } + + i = size & 0x3; + while (i) + { + if (*pIn < 0) + { + *pIn = 0; + } + pIn++; + i--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i; + + for (i = 0; i < size; i++) + { + if (data[i] < 0) + data[i] = 0; + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Acti group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..2f4133c --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_1x1_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of 1x1 convolution (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 version of 1x1 convolution (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is optimized for convolution with 1x1 kernel size (i.e., dim_kernel_x=1 + * and dim_kernel_y=1). It can be used for the second half of MobileNets [1] after depthwise + * separable convolution. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + * + * [1] MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications + * https://arxiv.org/abs/1704.04861 + */ + +arm_status arm_convolve_1x1_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ch_out; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_out_y * dim_im_in_x + i_out_x) * ch_im_in, pBuffer, + ch_im_in); + pBuffer += ch_im_in; + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + q31_t sum = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0 || dim_kernel_x != 1 || dim_kernel_y != 1 + || padding_x != 0 || padding_y != 0 || stride_x != 1 || stride_y != 1) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_y + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c new file mode 100644 index 0000000..00b5aa5 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_basic.c + * Description: Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q15_basic(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + uint16_t im2col_out_pixel_index = 0; + q15_t *pBuffer = bufferA; + q15_t *pOut = Im_out; + q15_t *im_buffer = bufferA; + const q15_t *pA; + int i; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + pA = wt; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = im_buffer; + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA)++; + q31_t inB2 = *__SIMD32(pB)++; + + sum = __SMLAD(inA1, inB1, sum); + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q15_t) __SSAT((sum >> out_shift), 16); + pOut++; + } + + /* counter reset */ + pBuffer = im_buffer; + im2col_out_pixel_index++; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c new file mode 100644 index 0000000..c9873c1 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c @@ -0,0 +1,255 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast(const q15_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel * dim_kernel; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel * dim_kernel; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel * dim_kernel; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c new file mode 100644 index 0000000..0274202 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q15_fast.c + * Description: Fast Q15 version of convolution + * + * $Date: 24. May 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q15 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in is multiple of 2 + * + * ch_im_out is multipe of 2 + * + */ + +arm_status +arm_convolve_HWC_q15_fast_nonsquare(const q15_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q15_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q15_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q15_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + q15_t *pBuffer = bufferA; + q15_t *im_buffer = bufferA; + q15_t *pOut = Im_out; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* arm_copy_q15((q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q15_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, sizeof(q15_t)*ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (i_out_x & 0x1) + { + int i; + /* initialize the matrix pointers for A */ + const q15_t *pA = wt; + + /* set up the second output pointers */ + q15_t *pOut2 = pOut + ch_im_out; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + q15_t *pB = im_buffer; + const q15_t *pB2 = pB + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* aling the second pointer for A */ + const q15_t *pA2 = pA + ch_im_in * dim_kernel_y * dim_kernel_x; + + /* init the sum with bias */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)bias[i + 1] << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 1; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA1 = *__SIMD32(pA)++; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inA2 = *__SIMD32(pA2)++; + q31_t inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA1, inB1, sum); + sum2 = __SMLAD(inA1, inB2, sum2); + sum3 = __SMLAD(inA2, inB1, sum3); + sum4 = __SMLAD(inA2, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x1; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q15_t) __SSAT(sum >> out_shift, 16); + *pOut++ = (q15_t) __SSAT(sum3 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum2 >> out_shift, 16); + *pOut2++ = (q15_t) __SSAT(sum4 >> out_shift, 16); + + /* skip the row computed with A2 */ + pA += ch_im_in * dim_kernel_y * dim_kernel_x; + } /* for over ch_im_out */ + + pOut += ch_im_out; + /* counter reset */ + pBuffer = im_buffer; + } + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 2 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel_x * dim_kernel_y + (m * dim_kernel_x + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q15_t) __SSAT((conv_out >> out_shift), 16); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c new file mode 100644 index 0000000..42bfb1f --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_RGB.c + * Description: Q7 version of convolution for RGB image + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Q7 convolution function for RGB image + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in equals 3 + * + * This kernel is written exclusively for convolution with ch_im_in + * equals 3. This applies on the first layer of CNNs which has input + * image with RGB format. + */ + +arm_status +arm_convolve_HWC_q7_RGB(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, const uint16_t dim_im_out, q15_t * bufferA, q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + // This part implements the im2col function + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Equivalent to arm_fill_q15(0, pBuffer, ch_im_in) with assumption: ch_im_in = 3 */ + *__SIMD32(pBuffer) = 0x0; + *(pBuffer + 2) = 0; + pBuffer += 3; + } else + { + /* + * Equivalent to: + * arm_q7_to_q15_no_shift( (q7_t*)Im_in+(i_ker_y*dim_im_in+i_ker_x)*3, pBuffer, 3); + */ + + const q7_t *pPixel = Im_in + (i_ker_y * dim_im_in + i_ker_x) * 3; + q31_t buf = *__SIMD32(pPixel); + + union arm_nnword top; + union arm_nnword bottom; + + top.word = __SXTB16(buf); + bottom.word = __SXTB16(__ROR(buf, 8)); + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * little-endian, | omit | 3rd | 2nd | 1st | + * MSB LSB + * top | 3rd | 1st |; bottom | omit | 2nd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = top.word; + * *(pBuffer+2) = bottom.half_words[0]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = top.half_words[0]; + *__SIMD32(pBuffer) = __PKHBT(bottom.word, top.word, 0); +#else + /* + * big-endian, | 1st | 2nd | 3rd | omit | + * MSB LSB + * top | 2nd | omit |; bottom | 1st | 3rd | + * + * version 1, need to swap 2nd and 3rd weight + * *__SIMD32(pBuffer) = bottom.word; + * *(pBuffer+2) = top.half_words[1]; + * + * version 2, no weight shuffling required + */ + *pBuffer++ = bottom.half_words[0]; + *__SIMD32(pBuffer) = __PKHTB(top.word, bottom.word, 0); +#endif + pBuffer += 2; + } + } + } + + if (pBuffer == bufferA + 2 * 3 * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + 3 * dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = 3 * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = 3 * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + // check if number of input channels is 3 + if (ch_im_in != 3) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + /* if-for implementation */ + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c new file mode 100644 index 0000000..a926086 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * This basic version is designed to work for any input tensor and weight + * dimension. + */ + +arm_status +arm_convolve_HWC_q7_basic(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c new file mode 100644 index 0000000..b426b92 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_basic.c + * Description: Q7 version of convolution + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Basic Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns <code>ARM_MATH_SUCCESS</code> + */ + +arm_status arm_convolve_HWC_q7_basic_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + /* This part implements the im2col function */ + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* Filling 0 for out-of-bound paddings */ + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + /* Copying the pixel data to column */ + arm_q7_to_q15_no_shift((q7_t *) + Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* Computation is filed for every 2 columns */ + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_y * dim_kernel_x) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15(wt, bufferA, + ch_im_out, + ch_im_in * + dim_kernel_y * dim_kernel_x, bias_shift, out_shift, bias, pOut); + + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* left-over because odd number of output pixels */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + /* Load the accumulator with bias first */ + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + + /* Point to the beging of the im2col buffer */ + q15_t *pB = bufferA; + + /* Each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_y * dim_kernel_x >> 2; + + while (colCnt) + { + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel_y * dim_kernel_x & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + } + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + // if-for implementation + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c new file mode 100644 index 0000000..7b59d79 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast.c + * Description: Fast Q7 version of convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + + /** + * @brief Fast Q7 convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in is multiple of 4 ( because of the SIMD32 read and swap ) + * + * ch_im_out is multipe of 2 ( bacause 2x2 mat_mult kernel ) + * + * The im2col converts the Q7 tensor input into Q15 column, which is stored in + * bufferA. There is reordering happenning during this im2col process with + * arm_q7_to_q15_reordered_no_shift. For every four elements, the second and + * third elements are swapped. + * + * The computation kernel arm_nn_mat_mult_kernel_q7_q15_reordered does the + * GEMM computation with the reordered columns. + * + * To speed-up the determination of the padding condition, we split the + * computation into 3x3 parts, i.e., {top, mid, bottom} X {left, mid, right}. + * This reduces the total number of boundary condition checks and improves + * the data copying performance. + */ + +arm_status +arm_convolve_HWC_q7_fast(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out - padding; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out - padding; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + + (i_ker_y * + dim_im_in + + i_out_x * + stride - padding) * ch_im_in, pBuffer, ch_im_in * dim_kernel); + pBuffer += ch_im_in * dim_kernel; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift + ((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel * dim_kernel) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, + bufferA, + ch_im_out, + ch_im_in + * + dim_kernel * dim_kernel, bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)bias[i] << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel * dim_kernel >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = ch_im_in * dim_kernel * dim_kernel & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + uint16_t i, j, k, l, m, n; + int conv_out; + signed char in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out; j++) + { + for (k = 0; k < dim_im_out; k++) + { + conv_out = (bias[i] << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel; m++) + { + for (n = 0; n < dim_kernel; n++) + { + // if-for implementation + in_row = stride * j + m - padding; + in_col = stride * k + n - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += + Im_in[(in_row * dim_im_in + in_col) * ch_im_in + + l] * wt[i * ch_im_in * dim_kernel * dim_kernel + (m * dim_kernel + + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c new file mode 100644 index 0000000..f2aa4a2 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c @@ -0,0 +1,379 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_convolve_HWC_q7_fast_nonsquare.c + * Description: Fast Q7 version of convolution (non-sqaure shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Fast Q7 convolution function (non-sqaure shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding size x + * @param[in] padding_y padding size y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 4 + * ch_im_out is multiple of 2 + */ + +arm_status arm_convolve_HWC_q7_fast_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x, i_ker_y, i_ker_x; + + /* ----------------------- + * Here we use bufferA as q15_t internally as computation are done with q15_t level + * im2col are done to output in q15_t format from q7_t input + */ + + q15_t *pBuffer = bufferA; + q7_t *pOut = Im_out; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + /* + * Here we split the entire matrix into three regions depending on the padding situation + * Top: i_out_y from 0 to padding - 1 + * Middle: i_out_y from padding to dim_im_out-padding-1 + * Bottom: i_out_y from dim_im_out-padding to dim_im_out-1 + */ + + /* top part */ + for (i_out_y = 0; i_out_y < padding_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* middle part, here we also divide the x into left, mid and right */ + for (; i_out_y < dim_im_out_y - padding_y; i_out_y++) + { + + /* left part */ + for (i_out_x = 0; i_out_x < padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* mid part */ + for (; i_out_x < dim_im_out_x - padding_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + + (i_ker_y * dim_im_in_x + i_out_x * stride_x - padding_x) * ch_im_in, + pBuffer, ch_im_in * dim_kernel_x); + pBuffer += ch_im_in * dim_kernel_x; + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + + /* right part */ + for (; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + for (; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* This part implements the im2col function */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q15(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, sizeof(q15_t)*ch_im_in); + } else + { + arm_q7_to_q15_reordered_no_shift((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, + pBuffer, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + if (pBuffer == bufferA + 2 * ch_im_in * dim_kernel_x * dim_kernel_y) + { + pOut = + arm_nn_mat_mult_kernel_q7_q15_reordered(wt, bufferA, ch_im_out, ch_im_in * dim_kernel_x * dim_kernel_y, + bias_shift, out_shift, bias, pOut); + /* counter reset */ + pBuffer = bufferA; + } + } + } + + /* check if there is left-over for compute */ + if (pBuffer != bufferA) + { + const q7_t *pA = wt; + int i; + for (i = 0; i < ch_im_out; i++) + { + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q15_t *pB = bufferA; + /* basically each time it process 4 entries */ + uint16_t colCnt = ch_im_in * dim_kernel_x * dim_kernel_y >> 2; + + while (colCnt) + { + + q31_t inA1, inA2; + q31_t inB1, inB2; + + pA = (const q7_t *)read_and_pad_reordered((void *)pA, &inA1, &inA2); + + inB1 = *__SIMD32(pB)++; + sum = __SMLAD(inA1, inB1, sum); + inB2 = *__SIMD32(pB)++; + sum = __SMLAD(inA2, inB2, sum); + + colCnt--; + } + colCnt = (ch_im_in * dim_kernel_y * dim_kernel_x) & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + sum += inA1 * inB1; + colCnt--; + } + *pOut = (q7_t) __SSAT((sum >> out_shift), 8); + pOut++; + + } + + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i, j, k, l, m, n; + int conv_out; + int in_row, in_col; + + if (ch_im_in % 4 != 0 || ch_im_out % 2 != 0) + { + /* check if the input dimension meets the constraints */ + return ARM_MATH_SIZE_MISMATCH; + } + + for (i = 0; i < ch_im_out; i++) + { + for (j = 0; j < dim_im_out_y; j++) + { + for (k = 0; k < dim_im_out_x; k++) + { + conv_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (m = 0; m < dim_kernel_y; m++) + { + for (n = 0; n < dim_kernel_x; n++) + { + /* if-for implementation */ + in_row = stride_y * j + m - padding_y; + in_col = stride_x * k + n - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + for (l = 0; l < ch_im_in; l++) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + l] * + wt[i * ch_im_in * dim_kernel_y * dim_kernel_x + (m * dim_kernel_x + n) * ch_im_in + l]; + } + } + } + } + Im_out[i + (j * dim_im_out_x + k) * ch_im_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c b/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c new file mode 100644 index 0000000..68ebeb8 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c @@ -0,0 +1,418 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7.c + * Description: Q7 depthwise separable convolution function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*ch_im_in*dim_kernel*dim_kernel + * + * bufferB size: 0 + * + * <b>Input dimension constraints:</b> + * + * ch_im_in equals ch_im_out + * + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + */ + +arm_status arm_depthwise_separable_conv_HWC_q7(const q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride - padding; i_ker_y < i_out_y * stride - padding + dim_kernel; i_ker_y++) + { + for (i_ker_x = i_out_x * stride - padding; i_ker_x < i_out_x * stride - padding + dim_kernel; i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in || i_ker_x < 0 || i_ker_x >= dim_im_in) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel * dim_kernel) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + /* + * r0 r1 r2 r3 r4 r5 + * inA1, inA2, inB1, inB2, opA, opB + */ + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] + "+r"(sum),[sum2] "+r"(sum2), + [sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB), + [pA] "+r"(pA):[colCnt] + "r"(colCnt),[ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel * dim_kernel) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel * dim_kernel); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + /* clear counter and pointers */ + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out, i_ker_x, i_ker_y; + int conv_out; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel; i_ker_x++) + { + int in_row = stride * i_out_y + i_ker_y - padding; + int in_col = stride * i_out_x + i_ker_x - padding; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in && in_col < dim_im_in) + { + conv_out += + Im_in[(in_row * + dim_im_in + + in_col) * + ch_im_in + + i_ch_out] * wt[(i_ker_y * dim_kernel + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out + + i_out_x) * ch_im_out + i_ch_out] = (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c b/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c new file mode 100644 index 0000000..397f233 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c @@ -0,0 +1,411 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_depthwise_separable_conv_HWC_q7_nonsquare.c + * Description: Q7 depthwise separable convolution function (non-square shape) + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup NNConv + * @{ + */ + +/** + * @brief Q7 depthwise separable convolution function (non-square shape) + * @param[in] Im_in pointer to input tensor + * @param[in] dim_im_in_x input tensor dimention x + * @param[in] dim_im_in_y input tensor dimention y + * @param[in] ch_im_in number of input tensor channels + * @param[in] wt pointer to kernel weights + * @param[in] ch_im_out number of filters, i.e., output tensor channels + * @param[in] dim_kernel_x filter kernel size x + * @param[in] dim_kernel_y filter kernel size y + * @param[in] padding_x padding sizes x + * @param[in] padding_y padding sizes y + * @param[in] stride_x convolution stride x + * @param[in] stride_y convolution stride y + * @param[in] bias pointer to bias + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in,out] Im_out pointer to output tensor + * @param[in] dim_im_out_x output tensor dimension x + * @param[in] dim_im_out_y output tensor dimension y + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] bufferB pointer to buffer space for output + * @return The function returns either + * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking. + * + * This function is the version with full list of optimization tricks, but with + * some contraints: + * ch_im_in is multiple of 2 + * ch_im_out is multiple of 2 + */ + +arm_status arm_depthwise_separable_conv_HWC_q7_nonsquare(const q7_t * Im_in, + const uint16_t dim_im_in_x, + const uint16_t dim_im_in_y, + const uint16_t ch_im_in, + const q7_t * wt, + const uint16_t ch_im_out, + const uint16_t dim_kernel_x, + const uint16_t dim_kernel_y, + const uint16_t padding_x, + const uint16_t padding_y, + const uint16_t stride_x, + const uint16_t stride_y, + const q7_t * bias, + const uint16_t bias_shift, + const uint16_t out_shift, + q7_t * Im_out, + const uint16_t dim_im_out_x, + const uint16_t dim_im_out_y, + q15_t * bufferA, + q7_t * bufferB) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + +/* + * Implementation: + * There are 3 nested loop here: + * Inner loop: calculate each output value with MAC instruction over an accumulator + * Mid loop: loop over different output channel + * Outer loop: loop over different output (x, y) + * + */ + + int16_t i_out_y, i_out_x; + int16_t i_ker_y, i_ker_x; + q7_t *colBuffer = (q7_t *) bufferA; + q7_t *pBuffer = colBuffer; + const q7_t *pBias = bias; + q7_t *pOut = Im_out; + uint16_t rowCnt; + uint16_t row_shift; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + /* we first do im2col here */ + for (i_ker_y = i_out_y * stride_y - padding_y; i_ker_y < i_out_y * stride_y - padding_y + dim_kernel_y; + i_ker_y++) + { + for (i_ker_x = i_out_x * stride_x - padding_x; i_ker_x < i_out_x * stride_x - padding_x + dim_kernel_x; + i_ker_x++) + { + if (i_ker_y < 0 || i_ker_y >= dim_im_in_y || i_ker_x < 0 || i_ker_x >= dim_im_in_x) + { + /* arm_fill_q7(0, pBuffer, ch_im_in); */ + memset(pBuffer, 0, ch_im_in); + } else + { + /* arm_copy_q7((q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, pBuffer, ch_im_in); */ + memcpy(pBuffer, (q7_t *) Im_in + (i_ker_y * dim_im_in_x + i_ker_x) * ch_im_in, ch_im_in); + } + pBuffer += ch_im_in; + } + } + + /* we will do the computation here for each channel */ + rowCnt = ch_im_out >> 2; + row_shift = 0; + pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = (dim_kernel_x * dim_kernel_y) >> 1; + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + row_shift += 4; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHTB(opB, inB1, 16); + inB1 = __PKHBT(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHTB(opB, inA1, 16); + inA1 = __PKHBT(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum3 = __SMLAD(opA, opB, sum3); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum4 = __SMLAD(opA, opB, sum4); + colCnt--; + } +#else + + while (colCnt) + { + q31_t inA1, inA2, inB1, inB2, opA, opB; + + inB1 = *__SIMD32(pB); + pB += ch_im_in; + opB = *__SIMD32(pB); + pB += ch_im_in; + inB2 = __PKHBT(opB, inB1, 16); + inB1 = __PKHTB(inB1, opB, 16); + inA1 = *__SIMD32(pA); + pA += ch_im_in; + opB = *__SIMD32(pA); + pA += ch_im_in; + inA2 = __PKHBT(opB, inA1, 16); + inA1 = __PKHTB(inA1, opB, 16); + opA = __SXTB16(inA1); + opB = __SXTB16(inB1); + sum2 = __SMLAD(opA, opB, sum2); + opA = __SXTB16(__ROR(inA1, 8)); + opB = __SXTB16(__ROR(inB1, 8)); + sum = __SMLAD(opA, opB, sum); + opA = __SXTB16(inA2); + opB = __SXTB16(inB2); + sum4 = __SMLAD(opA, opB, sum4); + opA = __SXTB16(__ROR(inA2, 8)); + opB = __SXTB16(__ROR(inB2, 8)); + sum3 = __SMLAD(opA, opB, sum3); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + +#ifndef ARM_MATH_BIG_ENDIAN + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhtb r3, r5, r2, ASR #16\n" + "pkhbt r2, r2, r5, LSL #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhtb r1, r5, r0, ASR #16\n" + "pkhbt r0, r0, r5, LSL #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum], r4, r5, %[sum]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#else + // r0 r1 r2 r3 r4 r5 + // inA1, inA2, inB1, inB2, opA, opB + asm volatile ("COL_LOOP:\n" + "ldr.w r2, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "ldr.w r5, [%[pB], #0]\n" + "add.w %[pB], %[pB], %[ch_im_in]\n" + "pkhbt r3, r5, r2, LSL #16\n" + "pkhtb r2, r2, r5, ASR #16\n" + "ldr.w r0, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "ldr.w r5, [%[pA], #0]\n" + "add.w %[pA], %[pA], %[ch_im_in]\n" + "pkhbt r1, r5, r0, LSL #16\n" + "pkhtb r0, r0, r5, ASR #16\n" + "sxtb16 r4, r0\n" + "sxtb16 r5, r2\n" + "smlad %[sum2], r4, r5, %[sum2]\n" + "mov.w r4, r0, ror #8\n" + "mov.w r5, r2, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum], r4, r5, %[sum]\n" + "sxtb16 r4, r1\n" + "sxtb16 r5, r3\n" + "smlad %[sum4], r4, r5, %[sum4]\n" + "mov.w r4, r1, ror #8\n" + "mov.w r5, r3, ror #8\n" + "sxtb16 r4, r4\n" + "sxtb16 r5, r5\n" + "smlad %[sum3], r4, r5, %[sum3]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP\n":[sum] "+r"(sum),[sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt), + [ch_im_in] "r"(ch_im_in):"r0", "r1", "r2", "r3", "r4", "r5"); +#endif /*ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = (dim_kernel_x * dim_kernel_y) & 0x1; + while (colCnt) + { + union arm_nnword inA, inB; + inA.word = *__SIMD32(pA); + pA += ch_im_in; + inB.word = *__SIMD32(pB); + pB += ch_im_in; + sum += inA.bytes[0] * inB.bytes[0]; + sum2 += inA.bytes[1] * inB.bytes[1]; + sum3 += inA.bytes[2] * inB.bytes[2]; + sum4 += inA.bytes[3] * inB.bytes[3]; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = ch_im_out & 0x3; + while (rowCnt) + { + q7_t *pB = colBuffer + row_shift; + const q7_t *pA = wt + row_shift; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = (dim_kernel_x * dim_kernel_y); + + row_shift += 1; + + while (colCnt) + { + q7_t A1 = *pA; + q7_t B1 = *pB; + pA += ch_im_in; + pB += ch_im_in; + sum += A1 * B1; + + colCnt--; + } + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + rowCnt--; + } + + // clear counter and pointers + pBuffer = colBuffer; + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + int i_out_y, i_out_x, i_ch_out; + int i_ker_y, i_ker_x; + + /* do some checking here, basically ch_im_in == ch_im_out */ + if (ch_im_in != ch_im_out) + { + return ARM_MATH_SIZE_MISMATCH; + } + + for (i_out_y = 0; i_out_y < dim_im_out_y; i_out_y++) + { + for (i_out_x = 0; i_out_x < dim_im_out_x; i_out_x++) + { + for (i_ch_out = 0; i_ch_out < ch_im_out; i_ch_out++) + { + // for each output + int conv_out = ((q31_t)(bias[i_ch_out]) << bias_shift) + NN_ROUND(out_shift); + for (i_ker_y = 0; i_ker_y < dim_kernel_y; i_ker_y++) + { + for (i_ker_x = 0; i_ker_x < dim_kernel_x; i_ker_x++) + { + int in_row = stride_y * i_out_y + i_ker_y - padding_y; + int in_col = stride_x * i_out_x + i_ker_x - padding_x; + if (in_row >= 0 && in_col >= 0 && in_row < dim_im_in_y && in_col < dim_im_in_x) + { + conv_out += Im_in[(in_row * dim_im_in_x + in_col) * ch_im_in + i_ch_out] * + wt[(i_ker_y * dim_kernel_x + i_ker_x) * ch_im_out + i_ch_out]; + } + } + } + Im_out[(i_out_y * dim_im_out_x + i_out_x) * ch_im_out + i_ch_out] = + (q7_t) __SSAT((conv_out >> out_shift), 8); + } + } + } + +#endif /* ARM_MATH_DSP */ + + + /* Return to application */ + return ARM_MATH_SUCCESS; + +} + +/** + * @} end of NNConv group + */ diff --git a/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c new file mode 100644 index 0000000..a4adc5d --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15.c + * Description: Matrix-multiplication function for convolution + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + + /** + * @brief Matrix-multiplication function for convolution + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function does the matrix multiplication with weight matrix + * and 2 columns from im2col. + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + const q7_t *pBias = bias; + + uint16_t rowCnt = ch_im_out >> 1; + /* this loop over rows in A */ + while (rowCnt) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + rowCnt--; + } /* for over ch_im_out */ + + /* compute left-over row if any */ + if (ch_im_out & 0x1) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* load the bias */ + q31_t sum = ((q31_t)(*pBias) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + while (colCnt) + { + q31_t inA11, inA12; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad((void *)pA, &inA11, &inA12); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + + colCnt--; + } + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + colCnt--; + } + + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + } + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ + +} diff --git a/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c new file mode 100644 index 0000000..deef7c6 --- /dev/null +++ b/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mat_mult_kernel_q7_q15_reordered.c + * Description: Matrix-multiplication function for convolution with reordered columns + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" +#include "arm_math.h" + + /** + * @brief Matrix-multiplication function for convolution with reordered columns + * @param[in] pA pointer to operand A + * @param[in] pInBuffer pointer to operand B, always conssists of 2 vectors + * @param[in] ch_im_out numRow of A + * @param[in] numCol_A numCol of A + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias the bias + * @param[in,out] pOut pointer to output + * @return The function returns the incremented output pointer + * + * @details + * + * This function assumes that data in pInBuffer are reordered + */ + +q7_t *arm_nn_mat_mult_kernel_q7_q15_reordered(const q7_t * pA, + const q15_t * pInBuffer, + const uint16_t ch_im_out, + const uint16_t numCol_A, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut) +{ + +#if defined (ARM_MATH_DSP) + /* set up the second output pointers */ + q7_t *pOut2 = pOut + ch_im_out; + int i; + + /* this loop over rows in A */ + for (i = 0; i < ch_im_out; i += 2) + { + /* setup pointers for B */ + const q15_t *pB = pInBuffer; + const q15_t *pB2 = pB + numCol_A; + + /* align the second pointer for A */ + const q7_t *pA2 = pA + numCol_A; + + /* init the sum with bias */ + q31_t sum = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(bias[i + 1]) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = numCol_A >> 2; + /* accumulate over the vector */ + while (colCnt) + { + q31_t inA11, inA12, inA21, inA22; + q31_t inB1 = *__SIMD32(pB)++; + q31_t inB2 = *__SIMD32(pB2)++; + + pA = (q7_t *) read_and_pad_reordered((void *)pA, &inA11, &inA12); + pA2 = (q7_t *) read_and_pad_reordered((void *)pA2, &inA21, &inA22); + + sum = __SMLAD(inA11, inB1, sum); + sum2 = __SMLAD(inA11, inB2, sum2); + sum3 = __SMLAD(inA21, inB1, sum3); + sum4 = __SMLAD(inA21, inB2, sum4); + + inB1 = *__SIMD32(pB)++; + inB2 = *__SIMD32(pB2)++; + + sum = __SMLAD(inA12, inB1, sum); + sum2 = __SMLAD(inA12, inB2, sum2); + sum3 = __SMLAD(inA22, inB1, sum3); + sum4 = __SMLAD(inA22, inB2, sum4); + + colCnt--; + } /* while over colCnt */ + colCnt = numCol_A & 0x3; + while (colCnt) + { + q7_t inA1 = *pA++; + q15_t inB1 = *pB++; + q7_t inA2 = *pA2++; + q15_t inB2 = *pB2++; + + sum += inA1 * inB1; + sum2 += inA1 * inB2; + sum3 += inA2 * inB1; + sum4 += inA2 * inB2; + colCnt--; + } /* while over colCnt */ + *pOut++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pOut++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pOut2++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + /* skip the row computed with A2 */ + pA += numCol_A; + } /* for over ch_im_out */ + + pOut += ch_im_out; + + /* return the new output pointer with offset */ + return pOut; +#else + /* To be completed */ + return NULL; +#endif /* ARM_MATH_DSP */ +} diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c new file mode 100644 index 0000000..2746967 --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c @@ -0,0 +1,199 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15.c + * Description: Mixed Q15-Q7 fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + + /*adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c new file mode 100644 index 0000000..7be156f --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_mat_q7_vec_q15_opt.c + * Description: Mixed Q15-Q7 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Mixed Q15-Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: 0 + * + * Q7_Q15 version of the fully connected layer + * + * Weights are in q7_t and Activations are in q15_t + * + * Limitation: x4 version requires weight reordering to work + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a12 | a22 | a31 | a41 | a32 | a42 | + * + * | a13 | a23 | a14 | a24 | a33 | a43 | a34 | a44 | + * + * | a15 | a25 | a16 | a26 | a35 | a45 | a36 | a46 | + * + * The column left over will be in-order. + * which is: + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a12 | a22 | a31 | a41 | + * + * | a32 | a42 | a13 | a23 | a14 | a24 | + * + * | a33 | a43 | a34 | a44 | a15 | a25 | + * + * | a16 | a26 | a35 | a45 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + */ + +arm_status +arm_fully_connected_mat_q7_vec_q15_opt(const q15_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q15_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q15_t *pO = pOut; + const q7_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } + +#else + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } + +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r1, [%[pB]], #8\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + colCnt--; + } + + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c new file mode 100644 index 0000000..c3e7cf2 --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15.c + * Description: Q15 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: 0 + * + */ + +arm_status +arm_fully_connected_q15(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + const q15_t *pB2 = pB + dim_vec; + q15_t *pO = pOut; + const q15_t *pA; + const q15_t *pBias = bias; + uint16_t rowCnt = num_of_rows >> 1; + + /* this loop loops over different output */ + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV1, inM1, inM2; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + inM2 = *__SIMD32(pB2)++; + sum2 = __SMLAD(inV1, inM2, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2>> out_shift), 16)); + + /* adjust the pointers and counters */ + pB = pB + dim_vec; + rowCnt --; + } + + rowCnt = num_of_rows & 0x1; + + while (rowCnt) { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) { + q31_t inV1, inM1; + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + inV1 = *__SIMD32(pA)++; + inM1 = *__SIMD32(pB)++; + sum = __SMLAD(inV1, inM1, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while(colCnt) { + q15_t inV = *pA++; + q15_t inM = *pB++; + + sum += inV * inM; + + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt --; + } + +#else + int i, j; + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q15_t) __SSAT((ip_out >> out_shift), 16); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to application */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c new file mode 100644 index 0000000..f7a3915 --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c @@ -0,0 +1,332 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q15_opt.c + * Description: Q15 opt fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q15 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: 0 + * + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original matrix looks like this: + * + * | a11 | a12 | a13 | + * + * | a21 | a22 | a23 | + * + * | a31 | a32 | a33 | + * + * | a41 | a42 | a43 | + * + * | a51 | a52 | a53 | + * + * | a61 | a62 | a63 | + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | + * + * Remaining rows are kept the same original order. + * + * So the stored weight matrix looks like this: + * + * + * | a11 | a12 | a21 | a22 | a31 | a32 | a41 | a42 | + * + * | a13 | a23 | a33 | a43 | a51 | a52 | a53 | a61 | + * + * | a62 | a63 | + */ + +arm_status +arm_fully_connected_q15_opt(const q15_t * pV, + const q15_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q15_t * bias, + q15_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q15_t *pB = pM; + q15_t *pO = pOut; + const q15_t *pBias = bias; + const q15_t *pA = pV; + + uint16_t rowCnt = num_of_rows >> 2; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + +#ifdef USE_INTRINSIC + + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + sum = __SMLAD(inV, inM11, sum); + inM12 = *__SIMD32(pB)++; + sum2 = __SMLAD(inV, inM12, sum2); + inM13 = *__SIMD32(pB)++; + sum3 = __SMLAD(inV, inM13, sum3); + inM14 = *__SIMD32(pB)++; + sum4 = __SMLAD(inV, inM14, sum4); + colCnt--; + } + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #4\n" + "ldr.w r0, [%[pB]], #16\n" + "smlad %[sum], r4, r0, %[sum]\n" + "ldr.w r1, [%[pB] , #-12]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r2, [%[pB] , #-8]\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "ldr.w r3, [%[pB] , #-4]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x1; + while (colCnt) + { + + q15_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB++; + q15_t inM3 = *pB++; + q15_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum2 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum3 >> out_shift), 16)); + *pO++ = (q15_t) (__SSAT((sum4 >> out_shift), 16)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q31_t inV1, inV2, inM1, inM2; + + inM1 = *__SIMD32(pB)++; + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM1, sum); + + inM2 = *__SIMD32(pB)++; + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM2, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q15_t) (__SSAT((sum >> out_shift), 16)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q15_t *pB = pM; + const q15_t *pA; + q15_t *pO = pOut; + const q15_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 1; + + pA = pV; + while (colCnt) + { + q15_t inA1 = *pA++; + q15_t inA2 = *pA++; + + q15_t inB1 = *pB++; + q15_t inB2 = *pB++; + sum += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum2 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum3 += inA1 * inB1 + inA2 * inB2; + + inB1 = *pB++; + inB2 = *pB++; + sum4 += inA1 * inB1 + inA2 * inB2; + + colCnt--; + } + colCnt = dim_vec & 0x1; + while (colCnt) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + colCnt--; + } + *pO++ = (q15_t) __SSAT((sum >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum2 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum3 >> out_shift), 16); + *pO++ = (q15_t) __SSAT((sum4 >> out_shift), 16); + + rowCnt--; + } + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q15_t inA = *pA++; + q15_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q15_t) __SSAT((ip_out >> out_shift), 16); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c new file mode 100644 index 0000000..d8efc04 --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 basic fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: dim_vec + * + * This basic function is designed to work with regular weight + * matrix without interleaving. + * + */ + +arm_status +arm_fully_connected_q7(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, const q7_t * bias, q7_t * pOut, q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + const q7_t *pB2; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 1; + + /* expand the vector into the buffer */ + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + pB2 = pB + dim_vec; + + while (colCnt) + { + q31_t inV, inM11, inM12, inM21, inM22; + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + pB2 = (q7_t *) read_and_pad_reordered((void *)pB2, &inM21, &inM22); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM11, sum); + sum2 = __SMLAD(inV, inM21, sum2); + + inV = *__SIMD32(pA)++; + + sum = __SMLAD(inV, inM12, sum); + sum2 = __SMLAD(inV, inM22, sum2); + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + q15_t inM2 = *pB2++; + + sum += inV * inM; + sum2 += inV * inM2; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + + /* adjust the pointers and counters */ + pB += dim_vec; + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x1; + + while (rowCnt) + { + uint16_t colCnt = dim_vec >> 2; + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inV = *pA++; + q15_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + int i, j; + + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + for (i = 0; i < num_of_rows; i++) + { + int ip_out = ((q31_t)(bias[i]) << bias_shift) + NN_ROUND(out_shift); + for (j = 0; j < dim_vec; j++) + { + ip_out += pV[j] * pM[i * dim_vec + j]; + } + pOut[i] = (q7_t) __SSAT((ip_out >> out_shift), 8); + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c new file mode 100644 index 0000000..e3d0874 --- /dev/null +++ b/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c @@ -0,0 +1,484 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_fully_connected_q7_opt.c + * Description: Q7 basic fully-connected layer function + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup FC + * @{ + */ + + /** + * @brief Q7 opt fully-connected layer function + * @param[in] pV pointer to input vector + * @param[in] pM pointer to matrix weights + * @param[in] dim_vec length of the vector + * @param[in] num_of_rows number of rows in weight matrix + * @param[in] bias_shift amount of left-shift for bias + * @param[in] out_shift amount of right-shift for output + * @param[in] bias pointer to bias + * @param[in,out] pOut pointer to output vector + * @param[in,out] vec_buffer pointer to buffer space for input + * @return The function returns <code>ARM_MATH_SUCCESS</code> + * + * @details + * + * <b>Buffer size:</b> + * + * vec_buffer size: dim_vec + * + * This opt function is designed to work with interleaved weight + * matrix. The vector input is assumed in q7_t format, we call + * arm_q7_to_q15_no_shift_shuffle function to expand into + * q15_t format with certain weight re-ordering, refer to the function + * comments for more details. + * Here we use only one pointer to read 4 rows in the weight + * matrix. So if the original q7_t matrix looks like this: + * + * | a11 | a12 | a13 | a14 | a15 | a16 | a17 | + * + * | a21 | a22 | a23 | a24 | a25 | a26 | a27 | + * + * | a31 | a32 | a33 | a34 | a35 | a36 | a37 | + * + * | a41 | a42 | a43 | a44 | a45 | a46 | a47 | + * + * | a51 | a52 | a53 | a54 | a55 | a56 | a57 | + * + * | a61 | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + * We operates on multiple-of-4 rows, so the first four rows becomes + * + * | a11 | a21 | a13 | a23 | a31 | a41 | a33 | a43 | + * + * | a12 | a22 | a14 | a24 | a32 | a42 | a34 | a44 | + * + * | a15 | a25 | a35 | a45 | a16 | a26 | a36 | a46 | + * + * So within the kernel, we first read the re-ordered vector in as: + * + * | b1 | b3 | and | b2 | b4 | + * + * the four q31_t weights will look like + * + * | a11 | a13 |, | a21 | a23 |, | a31 | a33 |, | a41 | a43 | + * + * | a12 | a14 |, | a22 | a24 |, | a32 | a34 |, | a42 | a44 | + * + * The column left over will be in-order. + * which is: + * + * | a17 | a27 | a37 | a47 | + * + * For the left-over rows, we do 1x1 computation, so the data remains + * as its original order. + * + * So the stored weight matrix looks like this: + * + * | a11 | a21 | a13 | a23 | a31 | a41 | + * + * | a33 | a43 | a12 | a22 | a14 | a24 | + * + * | a32 | a42 | a34 | a44 | a15 | a25 | + * + * | a35 | a45 | a16 | a26 | a36 | a46 | + * + * | a17 | a27 | a37 | a47 | a51 | a52 | + * + * | a53 | a54 | a55 | a56 | a57 | a61 | + * + * | a62 | a63 | a64 | a65 | a66 | a67 | + * + * + */ + +arm_status +arm_fully_connected_q7_opt(const q7_t * pV, + const q7_t * pM, + const uint16_t dim_vec, + const uint16_t num_of_rows, + const uint16_t bias_shift, + const uint16_t out_shift, + const q7_t * bias, + q7_t * pOut, + q15_t * vec_buffer) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + const q7_t *pB = pM; + q7_t *pO = pOut; + const q7_t *pBias = bias; + q15_t *pA; + uint16_t rowCnt = num_of_rows >> 2; + + arm_q7_to_q15_reordered_no_shift(pV, vec_buffer, dim_vec); + + while (rowCnt) + { + + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + +#ifdef USE_INTRINSIC + +#ifndef ARM_MATH_BIG_ENDIAN + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM11, inV, sum); + sum2 = __SMLAD(inM12, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM13, inV, sum3); + sum4 = __SMLAD(inM14, inV, sum4); + colCnt--; + } +#else + while (colCnt) + { + q31_t inM11, inM12, inM13, inM14; + q31_t inV; + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + + inV = *__SIMD32(pA)++; + inM11 = *__SIMD32(pB)++; + inM12 = __SXTB16(__ROR(inM11, 8)); + inM11 = __SXTB16(inM11); + sum = __SMLAD(inM12, inV, sum); + sum2 = __SMLAD(inM11, inV, sum2); + inM13 = *__SIMD32(pB)++; + inM14 = __SXTB16(__ROR(inM13, 8)); + inM13 = __SXTB16(inM13); + sum3 = __SMLAD(inM14, inV, sum3); + sum4 = __SMLAD(inM13, inV, sum4); + colCnt--; + } +#endif /* ARM_MATH_BIG_ENDIAN */ + +#else + + /* + * register needed: + * loop counter: colCnt + * accumulators: sum, sum2, sum3, sum4 + * pointers: pB, pA + * weight data: inM11, inM12, inM13, inM14 + * activation data: inV + */ + +#ifndef ARM_MATH_BIG_ENDIAN + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r1, %[sum]\n" + "smlad %[sum2], r4, r0, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r3, %[sum3]\n" + "smlad %[sum4], r4, r2, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#else + asm volatile ("COL_LOOP_%=:\n" + "ldr.w r4, [%[pA]], #8\n" + "ldr.w r1, [%[pB]], #16\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-12]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "ldr.w r4, [%[pA], #-4]\n" + "ldr.w r1, [%[pB], #-8]\n" + "mov.w r0, r1, ror #8\n" + "sxtb16 r0, r0\n" + "sxtb16 r1, r1\n" + "smlad %[sum], r4, r0, %[sum]\n" + "smlad %[sum2], r4, r1, %[sum2]\n" + "ldr.w r3, [%[pB], #-4]\n" + "mov.w r2, r3, ror #8\n" + "sxtb16 r2, r2\n" + "sxtb16 r3, r3\n" + "smlad %[sum3], r4, r2, %[sum3]\n" + "smlad %[sum4], r4, r3, %[sum4]\n" + "subs %[colCnt], #1\n" + "bne COL_LOOP_%=\n":[sum] "+r"(sum), + [sum2] "+r"(sum2),[sum3] "+r"(sum3), + [sum4] "+r"(sum4),[pB] "+r"(pB),[pA] "+r"(pA):[colCnt] "r"(colCnt):"r0", "r1", "r2", "r3", "r4"); +#endif /* ARM_MATH_BIG_ENDIAN */ + +#endif /* USE_INTRINSIC */ + + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + q7_t inM2 = *pB++; + q7_t inM3 = *pB++; + q7_t inM4 = *pB++; + + sum += inV * inM; + sum2 += inV * inM2; + sum3 += inV * inM3; + sum4 += inV * inM4; + colCnt--; + } /* while over colCnt */ + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum2 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum3 >> out_shift), 8)); + *pO++ = (q7_t) (__SSAT((sum4 >> out_shift), 8)); + + /* adjust the pointers and counters */ + rowCnt--; + } + + /* left-over part of the rows */ + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + uint16_t colCnt = dim_vec >> 2; + + pA = vec_buffer; + + while (colCnt) + { + q31_t inV1, inV2, inM11, inM12; + + pB = (q7_t *) read_and_pad_reordered((void *)pB, &inM11, &inM12); + + inV1 = *__SIMD32(pA)++; + sum = __SMLAD(inV1, inM11, sum); + + inV2 = *__SIMD32(pA)++; + sum = __SMLAD(inV2, inM12, sum); + + colCnt--; + } + + /* left-over of the vector */ + colCnt = dim_vec & 0x3; + while (colCnt) + { + q15_t inV = *pA++; + q7_t inM = *pB++; + sum += inV * inM; + colCnt--; + } + + *pO++ = (q7_t) (__SSAT((sum >> out_shift), 8)); + + rowCnt--; + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + uint16_t rowCnt = num_of_rows >> 2; + const q7_t *pB = pM; + const q7_t *pA; + q7_t *pO = pOut; + const q7_t *pBias = bias; + + while (rowCnt) + { + q31_t sum = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum2 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum3 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + q31_t sum4 = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + uint16_t colCnt = dim_vec >> 2; + + pA = pV; + + while (colCnt) + { + q7_t inA1 = *pA++; + q7_t inA3 = *pA++; + q7_t inA2 = *pA++; + q7_t inA4 = *pA++; + + q7_t inB1 = *pB++; + q7_t inB3 = *pB++; + q7_t inB2 = *pB++; + q7_t inB4 = *pB++; + + sum += inA1 * inB1 + inA2 * inB2; + sum2 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA1 * inB1 + inA2 * inB2; + sum4 += inA1 * inB3 + inA2 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum += inA3 * inB1 + inA4 * inB2; + sum2 += inA3 * inB3 + inA4 * inB4; + + inB1 = *pB++; + inB3 = *pB++; + inB2 = *pB++; + inB4 = *pB++; + + sum3 += inA3 * inB1 + inA4 * inB2; + sum4 += inA3 * inB3 + inA4 * inB4; + + colCnt--; + } + colCnt = dim_vec & 0x3; + while (colCnt) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + sum += inA * inB; + inB = *pB++; + sum2 += inA * inB; + inB = *pB++; + sum3 += inA * inB; + inB = *pB++; + sum4 += inA * inB; + + colCnt--; + } + *pO++ = (q7_t) __SSAT((sum >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum2 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum3 >> out_shift), 8); + *pO++ = (q7_t) __SSAT((sum4 >> out_shift), 8); + + rowCnt--; + } + + rowCnt = num_of_rows & 0x3; + + while (rowCnt) + { + int ip_out = ((q31_t)(*pBias++) << bias_shift) + NN_ROUND(out_shift); + + int j; + + pA = pV; + for (j = 0; j < dim_vec; j++) + { + q7_t inA = *pA++; + q7_t inB = *pB++; + ip_out += inA * inB; + } + *pO++ = (q7_t) __SSAT((ip_out >> out_shift), 8); + + rowCnt--; + } + +#endif /* ARM_MATH_DSP */ + + /* Return to ARM_MATH_SUCCESS */ + return (ARM_MATH_SUCCESS); + +} + +/** + * @} end of FC group + */ diff --git a/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c new file mode 100644 index 0000000..5a60459 --- /dev/null +++ b/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q15.c + * Description: Q15 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_nn_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ + q15_t out1, out2, out3, out4; /* temporary output variables */ + q31_t mul1, mul2, mul3, mul4; /* temporary variables */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* read two samples at a time from sourceA */ + inA1 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB1 = *__SIMD32(pSrcB)++; + /* read two samples at a time from sourceA */ + inA2 = *__SIMD32(pSrcA)++; + /* read two samples at a time from sourceB */ + inB2 = *__SIMD32(pSrcB)++; + + /* multiply mul = sourceA * sourceB */ + mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16)); + mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1); + mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16)); + mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2); + + /* saturate result to 16 bit */ + out1 = (q15_t) __SSAT((mul1 + NN_ROUND(out_shift)) >> out_shift, 16); + out2 = (q15_t) __SSAT((mul2 + NN_ROUND(out_shift)) >> out_shift, 16); + out3 = (q15_t) __SSAT((mul3 + NN_ROUND(out_shift)) >> out_shift, 16); + out4 = (q15_t) __SSAT((mul4 + NN_ROUND(out_shift)) >> out_shift, 16); + + /* store the result */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16); + *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ + diff --git a/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c new file mode 100644 index 0000000..3735c04 --- /dev/null +++ b/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nn_mult_q7.c + * Description: Q7 vector multiplication with variable output shifts + * + * $Date: 13. July 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup NNBasicMath + * @{ + */ + +/** + * @brief Q7 vector multiplication with variable output shifts + * @param[in] *pSrcA pointer to the first input vector + * @param[in] *pSrcB pointer to the second input vector + * @param[out] *pDst pointer to the output vector + * @param[in] out_shift amount of right-shift for output + * @param[in] blockSize number of samples in each vector + * @return none. + * + * <b>Scaling and Overflow Behavior:</b> + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_nn_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + const uint16_t out_shift, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#if defined (ARM_MATH_DSP) + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2U; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4U; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #if defined (ARM_MATH_DSP) */ + + + while (blkCnt > 0U) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++) + NN_ROUND(out_shift)) >> out_shift), 8); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of NNBasicMath group + */ diff --git a/NN/Source/NNSupportFunctions/arm_nntables.c b/NN/Source/NNSupportFunctions/arm_nntables.c new file mode 100644 index 0000000..c28f1a6 --- /dev/null +++ b/NN/Source/NNSupportFunctions/arm_nntables.c @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_nntables.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @brief tables for various activation functions + * + * This file include the declaration of common tables. + * Most of them are used for activation functions + * + * Assumption: + * Unified table: input is 3.x format, i.e, range of [-8, 8) + * sigmoid(8) = 0.9996646498695336 + * tanh(8) = 0.9999997749296758 + * The accuracy here should be good enough + * + * 2-stage HL table: + * + * The entire input range is divided into two parts: + * + * Low range table: 0x000x xxxx or 0x111x xxxx + * table entry will be the binary number excluding the first + * two digits, i.e., 0x0x xxxx or 0x1x xxxx + * + * + * + * High range table 0x0010 0000 -- 0x0111 1111 + * 0x1000 0000 -- 0x1101 1111 + * + * For positive numbers, table entry will be + * 0x0010 0000 -- 0x0111 1111 minus 0x0010 0000 + * i.e., 0x0000 0000 - 0x0101 11111 + * + * same thing for the negative numbers, table entry will be + * 0x1000 0000 -- 0x1101 1111 minux 0x0010 0000 + * i.e., 0x0110 0000 - 0x1011 1111 + */ + +const q7_t sigmoidTable_q7[256] = { + 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e, + 0x50, 0x52, 0x53, 0x55, 0x57, 0x59, 0x5a, 0x5c, + 0x5e, 0x5f, 0x61, 0x62, 0x63, 0x65, 0x66, 0x67, + 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, + 0x71, 0x72, 0x72, 0x73, 0x74, 0x74, 0x75, 0x76, + 0x76, 0x77, 0x77, 0x78, 0x78, 0x79, 0x79, 0x7a, + 0x7a, 0x7a, 0x7b, 0x7b, 0x7b, 0x7c, 0x7c, 0x7c, + 0x7c, 0x7c, 0x7d, 0x7d, 0x7d, 0x7d, 0x7d, 0x7e, + 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7e, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, + 0x02, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x04, + 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x06, + 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, + 0x0a, 0x0a, 0x0b, 0x0c, 0x0c, 0x0d, 0x0e, 0x0e, + 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, + 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, + 0x22, 0x24, 0x26, 0x27, 0x29, 0x2b, 0x2d, 0x2e, + 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e, +}; + +const q15_t sigmoidTable_q15[256] = { + 0x4000, 0x4200, 0x43ff, 0x45fc, 0x47f5, 0x49eb, 0x4bdc, 0x4dc8, + 0x4fad, 0x518a, 0x5360, 0x552c, 0x56ef, 0x58a8, 0x5a57, 0x5bfb, + 0x5d93, 0x5f20, 0x60a1, 0x6216, 0x637f, 0x64db, 0x662b, 0x676f, + 0x68a6, 0x69d2, 0x6af1, 0x6c05, 0x6d0d, 0x6e09, 0x6efb, 0x6fe2, + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, + 0x0f42, 0x101e, 0x1105, 0x11f7, 0x12f3, 0x13fb, 0x150f, 0x162e, + 0x175a, 0x1891, 0x19d5, 0x1b25, 0x1c81, 0x1dea, 0x1f5f, 0x20e0, + 0x226d, 0x2405, 0x25a9, 0x2758, 0x2911, 0x2ad4, 0x2ca0, 0x2e76, + 0x3053, 0x3238, 0x3424, 0x3615, 0x380b, 0x3a04, 0x3c01, 0x3e00, +}; + +const q15_t sigmoidLTable_q15[128] = { + 0x4000, 0x4100, 0x4200, 0x42ff, 0x43ff, 0x44fd, 0x45fc, 0x46f9, + 0x47f5, 0x48f1, 0x49eb, 0x4ae5, 0x4bdc, 0x4cd3, 0x4dc8, 0x4ebb, + 0x4fad, 0x509c, 0x518a, 0x5276, 0x5360, 0x5447, 0x552c, 0x560f, + 0x56ef, 0x57cd, 0x58a8, 0x5981, 0x5a57, 0x5b2a, 0x5bfb, 0x5cc9, + 0x5d93, 0x5e5b, 0x5f20, 0x5fe2, 0x60a1, 0x615d, 0x6216, 0x62cc, + 0x637f, 0x642e, 0x64db, 0x6584, 0x662b, 0x66ce, 0x676f, 0x680c, + 0x68a6, 0x693d, 0x69d2, 0x6a63, 0x6af1, 0x6b7c, 0x6c05, 0x6c8a, + 0x6d0d, 0x6d8d, 0x6e09, 0x6e84, 0x6efb, 0x6f70, 0x6fe2, 0x7051, + 0x0f42, 0x0faf, 0x101e, 0x1090, 0x1105, 0x117c, 0x11f7, 0x1273, + 0x12f3, 0x1376, 0x13fb, 0x1484, 0x150f, 0x159d, 0x162e, 0x16c3, + 0x175a, 0x17f4, 0x1891, 0x1932, 0x19d5, 0x1a7c, 0x1b25, 0x1bd2, + 0x1c81, 0x1d34, 0x1dea, 0x1ea3, 0x1f5f, 0x201e, 0x20e0, 0x21a5, + 0x226d, 0x2337, 0x2405, 0x24d6, 0x25a9, 0x267f, 0x2758, 0x2833, + 0x2911, 0x29f1, 0x2ad4, 0x2bb9, 0x2ca0, 0x2d8a, 0x2e76, 0x2f64, + 0x3053, 0x3145, 0x3238, 0x332d, 0x3424, 0x351b, 0x3615, 0x370f, + 0x380b, 0x3907, 0x3a04, 0x3b03, 0x3c01, 0x3d01, 0x3e00, 0x3f00, +}; + +const q15_t sigmoidHTable_q15[192] = { + 0x70be, 0x7190, 0x7258, 0x7316, 0x73cc, 0x7478, 0x751b, 0x75b7, + 0x764a, 0x76d6, 0x775b, 0x77d8, 0x784f, 0x78c0, 0x792a, 0x798f, + 0x79ee, 0x7a48, 0x7a9d, 0x7aed, 0x7b39, 0x7b80, 0x7bc4, 0x7c03, + 0x7c3f, 0x7c78, 0x7cad, 0x7ce0, 0x7d0f, 0x7d3c, 0x7d66, 0x7d8d, + 0x7db3, 0x7dd6, 0x7df7, 0x7e16, 0x7e33, 0x7e4f, 0x7e69, 0x7e81, + 0x7e98, 0x7eae, 0x7ec2, 0x7ed5, 0x7ee7, 0x7ef8, 0x7f08, 0x7f17, + 0x7f25, 0x7f32, 0x7f3e, 0x7f4a, 0x7f55, 0x7f5f, 0x7f69, 0x7f72, + 0x7f7b, 0x7f83, 0x7f8a, 0x7f91, 0x7f98, 0x7f9e, 0x7fa4, 0x7faa, + 0x7faf, 0x7fb4, 0x7fb8, 0x7fbd, 0x7fc1, 0x7fc5, 0x7fc8, 0x7fcc, + 0x7fcf, 0x7fd2, 0x7fd5, 0x7fd7, 0x7fda, 0x7fdc, 0x7fde, 0x7fe0, + 0x7fe2, 0x7fe4, 0x7fe6, 0x7fe7, 0x7fe9, 0x7fea, 0x7feb, 0x7fed, + 0x7fee, 0x7fef, 0x7ff0, 0x7ff1, 0x7ff2, 0x7ff3, 0x7ff4, 0x7ff4, + 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x0010, 0x0011, + 0x0012, 0x0013, 0x0015, 0x0016, 0x0017, 0x0019, 0x001a, 0x001c, + 0x001e, 0x0020, 0x0022, 0x0024, 0x0026, 0x0029, 0x002b, 0x002e, + 0x0031, 0x0034, 0x0038, 0x003b, 0x003f, 0x0043, 0x0048, 0x004c, + 0x0051, 0x0056, 0x005c, 0x0062, 0x0068, 0x006f, 0x0076, 0x007d, + 0x0085, 0x008e, 0x0097, 0x00a1, 0x00ab, 0x00b6, 0x00c2, 0x00ce, + 0x00db, 0x00e9, 0x00f8, 0x0108, 0x0119, 0x012b, 0x013e, 0x0152, + 0x0168, 0x017f, 0x0197, 0x01b1, 0x01cd, 0x01ea, 0x0209, 0x022a, + 0x024d, 0x0273, 0x029a, 0x02c4, 0x02f1, 0x0320, 0x0353, 0x0388, + 0x03c1, 0x03fd, 0x043c, 0x0480, 0x04c7, 0x0513, 0x0563, 0x05b8, + 0x0612, 0x0671, 0x06d6, 0x0740, 0x07b1, 0x0828, 0x08a5, 0x092a, + 0x09b6, 0x0a49, 0x0ae5, 0x0b88, 0x0c34, 0x0cea, 0x0da8, 0x0e70, +}; + +const q7_t tanhTable_q7[256] = { + 0x00, 0x08, 0x10, 0x18, 0x1f, 0x27, 0x2e, 0x35, + 0x3b, 0x41, 0x47, 0x4c, 0x51, 0x56, 0x5a, 0x5e, + 0x61, 0x65, 0x68, 0x6a, 0x6d, 0x6f, 0x71, 0x72, + 0x74, 0x75, 0x76, 0x78, 0x78, 0x79, 0x7a, 0x7b, + 0x7b, 0x7c, 0x7c, 0x7d, 0x7d, 0x7e, 0x7e, 0x7e, + 0x7e, 0x7e, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, + 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x81, + 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x81, 0x82, + 0x82, 0x82, 0x82, 0x82, 0x83, 0x83, 0x84, 0x84, + 0x85, 0x85, 0x86, 0x87, 0x88, 0x88, 0x8a, 0x8b, + 0x8c, 0x8e, 0x8f, 0x91, 0x93, 0x96, 0x98, 0x9b, + 0x9f, 0xa2, 0xa6, 0xaa, 0xaf, 0xb4, 0xb9, 0xbf, + 0xc5, 0xcb, 0xd2, 0xd9, 0xe1, 0xe8, 0xf0, 0xf8, +}; + +const q15_t tanhTable_q15[256] = { + 0x0000, 0x07fd, 0x0feb, 0x17b9, 0x1f59, 0x26bf, 0x2ddf, 0x34ae, + 0x3b27, 0x4142, 0x46fd, 0x4c56, 0x514d, 0x55e2, 0x5a1a, 0x5df6, + 0x617c, 0x64b0, 0x6797, 0x6a37, 0x6c95, 0x6eb5, 0x709e, 0x7254, + 0x73dc, 0x753a, 0x7672, 0x7788, 0x787f, 0x795b, 0x7a1e, 0x7acb, + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, + 0x849b, 0x8535, 0x85e2, 0x86a5, 0x8781, 0x8878, 0x898e, 0x8ac6, + 0x8c24, 0x8dac, 0x8f62, 0x914b, 0x936b, 0x95c9, 0x9869, 0x9b50, + 0x9e84, 0xa20a, 0xa5e6, 0xaa1e, 0xaeb3, 0xb3aa, 0xb903, 0xbebe, + 0xc4d9, 0xcb52, 0xd221, 0xd941, 0xe0a7, 0xe847, 0xf015, 0xf803, +}; + +const q15_t tanhLTable_q15[128] = { + 0x0000, 0x0400, 0x07fd, 0x0bf7, 0x0feb, 0x13d7, 0x17b9, 0x1b90, + 0x1f59, 0x2314, 0x26bf, 0x2a58, 0x2ddf, 0x3151, 0x34ae, 0x37f6, + 0x3b27, 0x3e40, 0x4142, 0x442c, 0x46fd, 0x49b6, 0x4c56, 0x4edd, + 0x514d, 0x53a3, 0x55e2, 0x580a, 0x5a1a, 0x5c13, 0x5df6, 0x5fc4, + 0x617c, 0x6320, 0x64b0, 0x662d, 0x6797, 0x68f0, 0x6a37, 0x6b6e, + 0x6c95, 0x6dac, 0x6eb5, 0x6fb0, 0x709e, 0x717f, 0x7254, 0x731e, + 0x73dc, 0x7490, 0x753a, 0x75da, 0x7672, 0x7701, 0x7788, 0x7807, + 0x787f, 0x78f0, 0x795b, 0x79bf, 0x7a1e, 0x7a77, 0x7acb, 0x7b1b, + 0x849b, 0x84e5, 0x8535, 0x8589, 0x85e2, 0x8641, 0x86a5, 0x8710, + 0x8781, 0x87f9, 0x8878, 0x88ff, 0x898e, 0x8a26, 0x8ac6, 0x8b70, + 0x8c24, 0x8ce2, 0x8dac, 0x8e81, 0x8f62, 0x9050, 0x914b, 0x9254, + 0x936b, 0x9492, 0x95c9, 0x9710, 0x9869, 0x99d3, 0x9b50, 0x9ce0, + 0x9e84, 0xa03c, 0xa20a, 0xa3ed, 0xa5e6, 0xa7f6, 0xaa1e, 0xac5d, + 0xaeb3, 0xb123, 0xb3aa, 0xb64a, 0xb903, 0xbbd4, 0xbebe, 0xc1c0, + 0xc4d9, 0xc80a, 0xcb52, 0xceaf, 0xd221, 0xd5a8, 0xd941, 0xdcec, + 0xe0a7, 0xe470, 0xe847, 0xec29, 0xf015, 0xf409, 0xf803, 0xfc00, +}; + +const q15_t tanhHTable_q15[192] = { + 0x7b65, 0x7bee, 0x7c66, 0x7cd1, 0x7d30, 0x7d84, 0x7dce, 0x7e0f, + 0x7e49, 0x7e7d, 0x7eaa, 0x7ed2, 0x7ef5, 0x7f14, 0x7f30, 0x7f48, + 0x7f5e, 0x7f71, 0x7f82, 0x7f91, 0x7f9e, 0x7fa9, 0x7fb3, 0x7fbc, + 0x7fc4, 0x7fcb, 0x7fd1, 0x7fd7, 0x7fdc, 0x7fe0, 0x7fe4, 0x7fe7, + 0x7fea, 0x7fed, 0x7fef, 0x7ff1, 0x7ff3, 0x7ff4, 0x7ff6, 0x7ff7, + 0x7ff8, 0x7ff9, 0x7ffa, 0x7ffa, 0x7ffb, 0x7ffc, 0x7ffc, 0x7ffd, + 0x7ffd, 0x7ffd, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, 0x8000, + 0x8000, 0x8000, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, 0x8001, + 0x8001, 0x8001, 0x8001, 0x8002, 0x8002, 0x8002, 0x8002, 0x8003, + 0x8003, 0x8003, 0x8004, 0x8004, 0x8005, 0x8006, 0x8006, 0x8007, + 0x8008, 0x8009, 0x800a, 0x800c, 0x800d, 0x800f, 0x8011, 0x8013, + 0x8016, 0x8019, 0x801c, 0x8020, 0x8024, 0x8029, 0x802f, 0x8035, + 0x803c, 0x8044, 0x804d, 0x8057, 0x8062, 0x806f, 0x807e, 0x808f, + 0x80a2, 0x80b8, 0x80d0, 0x80ec, 0x810b, 0x812e, 0x8156, 0x8183, + 0x81b7, 0x81f1, 0x8232, 0x827c, 0x82d0, 0x832f, 0x839a, 0x8412, +}; diff --git a/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c new file mode 100644 index 0000000..264e760 --- /dev/null +++ b/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_no_shift.c + * Description: Converts the elements of the Q7 vector to Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * \par Description: + * + * The equation used for the conversion process is: + * + * <pre> + * pDst[n] = (q15_t) pSrc[n]; 0 <= n < blockSize. + * </pre> + * + */ + +void arm_q7_to_q15_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + q31_t out1, out2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + + out2 = __PKHTB(in1, in2, 16); + out1 = __PKHBT(in2, in1, 16); + +#else + + out1 = __PKHTB(in1, in2, 16); + out2 = __PKHBT(in2, in1, 16); + +#endif + + *__SIMD32(pDst)++ = out1; + *__SIMD32(pDst)++ = out2; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of nndata_convert group + */ diff --git a/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c b/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c new file mode 100644 index 0000000..7d29aa4 --- /dev/null +++ b/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_q7_to_q15_reordered_no_shift.c + * Description: Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_nnsupportfunctions.h" + +/** + * @ingroup groupSupport + */ + +/** + * @addtogroup nndata_convert + * @{ + */ + +/** + * @brief Converts the elements of the Q7 vector to reordered Q15 vector without left-shift + * @param[in] *pSrc points to the Q7 input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none. + * + * @details + * + * This function does the q7 to q15 expansion with re-ordering + * + * <pre> + * | A1 | A2 | A3 | A4 | + * + * 0 7 8 15 16 23 24 31 + * </pre> + * + * is converted into: + * + * <pre> + * | A1 | A3 | and | A2 | A4 | + * + * 0 15 16 31 0 15 16 31 + * </pre> + * + * + * This looks strange but is natural considering how sign-extension is done at + * assembly level. + * + * The expansion of other other oprand will follow the same rule so that the end + * results are the same. + * + * The tail (i.e., last (N % 4) elements) will still be in original order. + * + */ + +void arm_q7_to_q15_reordered_no_shift(const q7_t * pSrc, q15_t * pDst, uint32_t blockSize) +{ + const q7_t *pIn = pSrc; /* Src pointer */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0_FAMILY + q31_t in; + q31_t in1, in2; + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + in = *__SIMD32(pIn)++; + + /* rotatate in by 8 and extend two q7_t values to q15_t values */ + in1 = __SXTB16(__ROR(in, 8)); + + /* extend remainig two q7_t values to q15_t values */ + in2 = __SXTB16(in); + +#ifndef ARM_MATH_BIG_ENDIAN + *__SIMD32(pDst)++ = in2; + *__SIMD32(pDst)++ = in1; +#else + *__SIMD32(pDst)++ = in1; + *__SIMD32(pDst)++ = in2; +#endif + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Loop over blockSize number of values */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0_FAMILY */ + + while (blkCnt > 0u) + { + /* C = (q15_t) A << 8 */ + /* convert from q7 to q15 and then store the results in the destination buffer */ + *pDst++ = (q15_t) * pIn++; + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of q7_to_x group + */ diff --git a/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c b/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c new file mode 100644 index 0000000..b451f5e --- /dev/null +++ b/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c @@ -0,0 +1,448 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_pool_q7_HWC.c + * Description: Pooling function implementations + * + * $Date: 17. January 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +#if defined (ARM_MATH_DSP) + +/** + * @brief A few utility functions used by pooling functions + * + * + */ + +static void buffer_scale_back_q15_to_q7(q15_t * buffer, q7_t * target, uint16_t length, uint16_t scale) +{ + int i; + + for (i = 0; i < length; i++) + { + target[i] = (q7_t) (buffer[i] / scale); + } +} + +static void compare_and_replace_if_larger_q7(q7_t * base, // base data + q7_t * target, // compare target + const uint16_t length // data length + ) +{ + q7_t *pIn = base; + q7_t *pCom = target; + union arm_nnword in; + union arm_nnword com; + uint16_t cnt = length >> 2; + + while (cnt > 0u) + { + in.word = *__SIMD32(pIn); + com.word = *__SIMD32(pCom)++; + + // if version + if (com.bytes[0] > in.bytes[0]) + in.bytes[0] = com.bytes[0]; + if (com.bytes[1] > in.bytes[1]) + in.bytes[1] = com.bytes[1]; + if (com.bytes[2] > in.bytes[2]) + in.bytes[2] = com.bytes[2]; + if (com.bytes[3] > in.bytes[3]) + in.bytes[3] = com.bytes[3]; + + *__SIMD32(pIn)++ = in.word; + + cnt--; + } +} + +static void accumulate_q7_to_q15(q15_t * base, q7_t * target, const uint16_t length) +{ + q15_t *pCnt = base; + q7_t *pV = target; + q31_t v1, v2, vo1, vo2; + uint16_t cnt = length >> 2; + q31_t in; + + while (cnt > 0u) + { + q31_t value = *__SIMD32(pV)++; + v1 = __SXTB16(__ROR(value, 8)); + v2 = __SXTB16(value); +#ifndef ARM_MATH_BIG_ENDIAN + + vo2 = __PKHTB(v1, v2, 16); + vo1 = __PKHBT(v2, v1, 16); + +#else + + vo1 = __PKHTB(v1, v2, 16); + vo2 = __PKHBT(v2, v1, 16); + +#endif + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo1, in); + + in = *__SIMD32(pCnt); + *__SIMD32(pCnt)++ = __QADD16(vo2, in); + + cnt--; + } + cnt = length & 0x3; + while (cnt > 0u) + { + *pCnt++ += *pV++; + cnt--; + } +} + +#endif // ARM_MATH_DSP + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Pooling + * @{ + */ + + /** + * @brief Q7 max pooling function + * @param[in, out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 0 + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_maxpool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + int16_t i_x, i_y; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + /* arm_copy_q7(win_start, target, ch_im_in); */ + memmove(target, win_start, ch_im_in); + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + compare_and_replace_if_larger_q7(target, win_start, ch_im_in); + } + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + /* arm_copy_q7(row_start, target, dim_im_out * ch_im_in); */ + memmove(target, row_start, dim_im_out * ch_im_in); + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + compare_and_replace_if_larger_q7(target, row_start, dim_im_out * ch_im_in); + } + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int max = -129; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + if (Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)] > max) + { + max = Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + } + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = max; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + + /** + * @brief Q7 average pooling function + * @param[in,out] Im_in pointer to input tensor + * @param[in] dim_im_in input tensor dimention + * @param[in] ch_im_in number of input tensor channels + * @param[in] dim_kernel filter kernel size + * @param[in] padding padding sizes + * @param[in] stride convolution stride + * @param[in] dim_im_out output tensor dimension + * @param[in,out] bufferA pointer to buffer space for input + * @param[in,out] Im_out pointer to output tensor + * @return none. + * + * @details + * + * <b>Buffer size:</b> + * + * bufferA size: 2*dim_im_out*ch_im_in + * + * The pooling function is implemented as split x-pooling then + * y-pooling. + * + * This pooling function is input-destructive. Input data is undefined + * after calling this function. + * + */ + +void +arm_avepool_q7_HWC(q7_t * Im_in, + const uint16_t dim_im_in, + const uint16_t ch_im_in, + const uint16_t dim_kernel, + const uint16_t padding, + const uint16_t stride, const uint16_t dim_im_out, q7_t * bufferA, q7_t * Im_out) +{ + +#if defined (ARM_MATH_DSP) + /* Run the following code for Cortex-M4 and Cortex-M7 */ + + q15_t *buffer = (q15_t *) bufferA; + int16_t i_x, i_y; + int16_t count = 0; + + /* first does the pooling along x axis */ + for (i_y = 0; i_y < dim_im_in; i_y++) + { + + for (i_x = 0; i_x < dim_im_out; i_x++) + { + /* for each output pixel */ + q7_t *target = Im_in + (i_y * dim_im_in + i_x) * ch_im_in; + q7_t *win_start; + q7_t *win_stop; + if (i_x * stride - padding < 0) + { + win_start = target; + } else + { + win_start = Im_in + (i_y * dim_im_in + i_x * stride - padding) * ch_im_in; + } + + if (i_x * stride - padding + dim_kernel >= dim_im_in) + { + win_stop = Im_in + (i_y * dim_im_in + dim_im_in) * ch_im_in; + } else + { + win_stop = Im_in + (i_y * dim_im_in + i_x * stride - padding + dim_kernel) * ch_im_in; + } + + /* first step is to copy over initial data */ + arm_q7_to_q15_no_shift(win_start, buffer, ch_im_in); + count = 1; + + /* start the max operation from the second part */ + win_start += ch_im_in; + for (; win_start < win_stop; win_start += ch_im_in) + { + accumulate_q7_to_q15(buffer, win_start, ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, ch_im_in, count); + } + } + + /* then does the pooling along y axis */ + for (i_y = 0; i_y < dim_im_out; i_y++) + { + /* for each output row */ + q7_t *target = Im_out + i_y * dim_im_out * ch_im_in; + q7_t *row_start; + q7_t *row_end; + /* setting the starting row */ + if (i_y * stride - padding < 0) + { + row_start = Im_in; + } else + { + row_start = Im_in + (i_y * stride - padding) * dim_im_in * ch_im_in; + } + /* setting the stopping row */ + if (i_y * stride - padding + dim_kernel >= dim_im_in) + { + row_end = Im_in + dim_im_in * dim_im_in * ch_im_in; + } else + { + row_end = Im_in + (i_y * stride - padding + dim_kernel) * dim_im_in * ch_im_in; + } + + /* copy over the first row */ + arm_q7_to_q15_no_shift(row_start, buffer, dim_im_out * ch_im_in); + count = 1; + + /* move over to next row */ + row_start += ch_im_in * dim_im_in; + + for (; row_start < row_end; row_start += dim_im_in * ch_im_in) + { + accumulate_q7_to_q15(buffer, row_start, dim_im_out * ch_im_in); + count++; + } + buffer_scale_back_q15_to_q7(buffer, target, dim_im_out * ch_im_in, count); + } + +#else + /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */ + + int16_t i_ch_in, i_x, i_y; + int16_t k_x, k_y; + + for (i_ch_in = 0; i_ch_in < ch_im_in; i_ch_in++) + { + for (i_y = 0; i_y < dim_im_out; i_y++) + { + for (i_x = 0; i_x < dim_im_out; i_x++) + { + int sum = 0; + int count = 0; + for (k_y = i_y * stride - padding; k_y < i_y * stride - padding + dim_kernel; k_y++) + { + for (k_x = i_x * stride - padding; k_x < i_x * stride - padding + dim_kernel; k_x++) + { + if (k_y >= 0 && k_x >= 0 && k_y < dim_im_in && k_x < dim_im_in) + { + sum += Im_in[i_ch_in + ch_im_in * (k_x + k_y * dim_im_in)]; + count++; + } + } + } + Im_out[i_ch_in + ch_im_in * (i_x + i_y * dim_im_out)] = sum / count; + } + } + } + +#endif /* ARM_MATH_DSP */ + +} + +/** + * @} end of Pooling group + */ diff --git a/NN/Source/SoftmaxFunctions/arm_softmax_q15.c b/NN/Source/SoftmaxFunctions/arm_softmax_q15.c new file mode 100644 index 0000000..abc2737 --- /dev/null +++ b/NN/Source/SoftmaxFunctions/arm_softmax_q15.c @@ -0,0 +1,120 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q15.c + * Description: Q15 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q15 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical e based softmax, we use + * 2-based softmax, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q15(const q15_t * vec_in, const uint16_t dim_vec, q15_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q31_t base; + base = -1 * 0x100000; + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* we ignore really small values + * anyway, they will be 0 after shrinking + * to q15_t + */ + base = base - 16; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 32) / sum */ + int64_t div_base = 0x100000000LL; + int output_base = (int32_t)(div_base / sum); + + /* Final confidence will be output_base >> ( 17 - (vec_in[i] - base) ) + * so 32768 (0x1<<15) -> 100% confidence when sum = 0x1 << 16, output_base = 0x1 << 16 + * and vec_in[i]-base = 16 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 17+base-vec[i] will be 1 */ + shift = (uint8_t)__USAT(17+base-vec_in[i], 5); + p_out[i] = (q15_t) __SSAT((output_base >> shift), 16); + } else + { + p_out[i] = 0; + } + } + +} + +/** + * @} end of Softmax group + */ diff --git a/NN/Source/SoftmaxFunctions/arm_softmax_q7.c b/NN/Source/SoftmaxFunctions/arm_softmax_q7.c new file mode 100644 index 0000000..a4e2548 --- /dev/null +++ b/NN/Source/SoftmaxFunctions/arm_softmax_q7.c @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------- + * Project: CMSIS NN Library + * Title: arm_softmax_q7.c + * Description: Q7 softmax function + * + * $Date: 20. February 2018 + * $Revision: V.1.0.0 + * + * Target Processor: Cortex-M cores + * + * -------------------------------------------------------------------- */ + +#include "arm_math.h" +#include "arm_nnfunctions.h" + +/** + * @ingroup groupNN + */ + +/** + * @addtogroup Softmax + * @{ + */ + + /** + * @brief Q7 softmax function + * @param[in] vec_in pointer to input vector + * @param[in] dim_vec input vector dimention + * @param[out] p_out pointer to output vector + * @return none. + * + * @details + * + * Here, instead of typical natural logarithm e based softmax, we use + * 2-based softmax here, i.e.,: + * + * y_i = 2^(x_i) / sum(2^x_j) + * + * The relative output will be different here. + * But mathematically, the gradient will be the same + * with a log(2) scaling factor. + * + */ + +void arm_softmax_q7(const q7_t * vec_in, const uint16_t dim_vec, q7_t * p_out) +{ + q31_t sum; + int16_t i; + uint8_t shift; + q15_t base; + base = -257; + + /* We first search for the maximum */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + base = vec_in[i]; + } + } + + /* + * So the base is set to max-8, meaning + * that we ignore really small values. + * anyway, they will be 0 after shrinking to q7_t. + */ + base = base - 8; + + sum = 0; + + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + shift = (uint8_t)__USAT(vec_in[i] - base, 5); + sum += 0x1 << shift; + } + } + + /* This is effectively (0x1 << 20) / sum */ + int output_base = 0x100000 / sum; + + /* + * Final confidence will be output_base >> ( 13 - (vec_in[i] - base) ) + * so 128 (0x1<<7) -> 100% confidence when sum = 0x1 << 8, output_base = 0x1 << 12 + * and vec_in[i]-base = 8 + */ + for (i = 0; i < dim_vec; i++) + { + if (vec_in[i] > base) + { + /* Here minimum value of 13+base-vec_in[i] will be 5 */ + shift = (uint8_t)__USAT(13+base-vec_in[i], 5); + p_out[i] = (q7_t) __SSAT((output_base >> shift), 8); + } else { + p_out[i] = 0; + } + } +} + +/** + * @} end of Softmax group + */ |