Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-11-29 | pcb: Fix a bunch of kicady layout errors | jaseg | 28 | -10926/+10986 |
2018-11-29 | Some small fixes, add silk artwork | jaseg | 33 | -14137/+165325 |
2018-11-27 | pcb: Add BOM | jaseg | 11 | -10/+3645 |
2018-11-27 | pcb: Add project info to silk and do gerber export | jaseg | 14 | -621/+78194 |
2018-11-22 | PCB silk: hide testpoint references | jaseg | 1 | -77/+77 |
2018-11-22 | Further PCB cleanup, initial silk cleanup | jaseg | 4 | -4188/+4740 |
2018-11-21 | Some cleanups | jaseg | 5 | -5176/+5594 |
2018-11-21 | Initial PCB draft | jaseg | 8 | -1656/+32396 |
2018-11-17 | Initial schematic commit | jaseg | 9 | -0/+5500 |