Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-11-29 | pcb: Fix a bunch of kicady layout errors | jaseg | 1 | -704/+706 |
2018-11-29 | Some small fixes, add silk artwork | jaseg | 1 | -2171/+2140 |
2018-11-27 | pcb: Add project info to silk and do gerber export | jaseg | 1 | -271/+290 |
2018-11-22 | PCB silk: hide testpoint references | jaseg | 1 | -77/+77 |
2018-11-22 | Further PCB cleanup, initial silk cleanup | jaseg | 1 | -2096/+2361 |
2018-11-21 | Some cleanups | jaseg | 1 | -2269/+2458 |
2018-11-21 | Initial PCB draft | jaseg | 1 | -1/+12282 |
2018-11-17 | Initial schematic commit | jaseg | 1 | -0/+1 |