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path: root/pcb/securehid.kicad_pcb
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2018-11-27pcb: Add project info to silk and do gerber exportjaseg1-271/+290
2018-11-22PCB silk: hide testpoint referencesjaseg1-77/+77
2018-11-22Further PCB cleanup, initial silk cleanupjaseg1-2096/+2361
2018-11-21Some cleanupsjaseg1-2269/+2458
2018-11-21Initial PCB draftjaseg1-1/+12282
2018-11-17Initial schematic commitjaseg1-0/+1