Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2018-11-29 | Add system diagram for traditional system | jaseg | 2 | -771/+7762 |
2018-11-29 | Add directions writeup | jaseg | 9 | -0/+17262 |
2018-11-29 | pcb: Fix a bunch of kicady layout errors | jaseg | 28 | -10926/+10986 |
2018-11-29 | Some small fixes, add silk artwork | jaseg | 33 | -14137/+165325 |
2018-11-27 | pcb: Add BOM | jaseg | 11 | -10/+3645 |
2018-11-27 | pcb: Add project info to silk and do gerber export | jaseg | 14 | -621/+78194 |
2018-11-22 | PCB silk: hide testpoint references | jaseg | 1 | -77/+77 |
2018-11-22 | Further PCB cleanup, initial silk cleanup | jaseg | 4 | -4188/+4740 |
2018-11-21 | Some cleanups | jaseg | 5 | -5176/+5594 |
2018-11-21 | Initial PCB draft | jaseg | 9 | -1663/+32398 |
2018-11-19 | Add old architecture documents | jaseg | 6 | -0/+284 |
2018-11-17 | Initial schematic commit | jaseg | 27 | -2602/+5500 |
2017-07-31 | Boot, UART working | jaseg | 7 | -115/+367 |
2017-07-30 | USB HID host code import | jaseg | 11 | -324/+1388 |
2017-07-30 | Initial commit, blink working | jaseg | 10 | -0/+1293 |