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authorjaseg <git@jaseg.net>2018-11-27 11:37:35 +0900
committerjaseg <git@jaseg.net>2018-11-27 11:37:35 +0900
commitad86b136490b231d14891c9fe936ac38ea940553 (patch)
tree047c9ddc5576d93a27f61339dccf27d683df7550 /pcb/sym-lib-table
parent2de3660f50d26a19955522bc77b02f2bed780de9 (diff)
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pcb: Add project info to silk and do gerber export
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