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authorjaseg <git@jaseg.net>2018-11-22 10:17:35 +0900
committerjaseg <git@jaseg.net>2018-11-22 10:17:35 +0900
commit47f48bea909e1d8dafb471b67e3a2335a5d8a93d (patch)
tree793c19477ead43930e4e09bced3be2c0923cf404 /pcb/securehid.bak
parent07ae18740e453a3a5b4911a89dbcd94facb94ee2 (diff)
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Further PCB cleanup, initial silk cleanup
Diffstat (limited to 'pcb/securehid.bak')
-rw-r--r--pcb/securehid.bak30
1 files changed, 26 insertions, 4 deletions
diff --git a/pcb/securehid.bak b/pcb/securehid.bak
index 4041ec0..3de2792 100644
--- a/pcb/securehid.bak
+++ b/pcb/securehid.bak
@@ -4034,10 +4034,10 @@ Wire Wire Line
Wire Wire Line
1950 1250 2750 1250
$Comp
-L Connector:TestPoint_Alt TP?
+L Connector:TestPoint_Alt TP81
U 1 1 5BFF0539
P 14400 3500
-F 0 "TP?" V 14400 3800 50 0000 C CNN
+F 0 "TP81" V 14400 3800 50 0000 C CNN
F 1 "TestPoint_Alt" V 14504 3574 50 0001 C CNN
F 2 "TestPoint:TestPoint_Pad_1.0x1.0mm" H 14600 3500 50 0001 C CNN
F 3 "~" H 14600 3500 50 0001 C CNN
@@ -4045,10 +4045,10 @@ F 3 "~" H 14600 3500 50 0001 C CNN
0 -1 -1 0
$EndComp
$Comp
-L Connector:TestPoint_Alt TP?
+L Connector:TestPoint_Alt TP82
U 1 1 5C0015E1
P 14400 3600
-F 0 "TP?" V 14400 3900 50 0000 C CNN
+F 0 "TP82" V 14400 3900 50 0000 C CNN
F 1 "TestPoint_Alt" V 14504 3674 50 0001 C CNN
F 2 "TestPoint:TestPoint_Pad_1.0x1.0mm" H 14600 3600 50 0001 C CNN
F 3 "~" H 14600 3600 50 0001 C CNN
@@ -4069,4 +4069,26 @@ Wire Wire Line
Connection ~ 14400 3650
Wire Wire Line
14400 3650 15100 3650
+$Comp
+L Connector:TestPoint_Alt TP?
+U 1 1 5C13B94B
+P 14400 3700
+F 0 "TP?" V 14400 4000 50 0000 C CNN
+F 1 "TestPoint_Alt" V 14504 3774 50 0001 C CNN
+F 2 "TestPoint:TestPoint_Pad_1.0x1.0mm" H 14600 3700 50 0001 C CNN
+F 3 "~" H 14600 3700 50 0001 C CNN
+ 1 14400 3700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L power:GNDA #PWR?
+U 1 1 5C14109B
+P 14400 3700
+F 0 "#PWR?" H 14400 3450 50 0001 C CNN
+F 1 "GNDA" H 14405 3527 50 0000 C CNN
+F 2 "" H 14400 3700 50 0001 C CNN
+F 3 "" H 14400 3700 50 0001 C CNN
+ 1 14400 3700
+ 1 0 0 -1
+$EndComp
$EndSCHEMATC