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authorjaseg <git@jaseg.net>2018-11-29 10:18:56 +0900
committerjaseg <git@jaseg.net>2018-11-29 10:18:56 +0900
commit8e1bf42f397407695667b24a44055b0c60a2ef04 (patch)
tree05cff52594fd452d2d6a327a4dc448a4e6ec5d9c /pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod
parent9e50656e353d5aedf8b99c06113d0ae69aa97602 (diff)
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Some small fixes, add silk artwork
Diffstat (limited to 'pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod')
-rw-r--r--pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod30
1 files changed, 30 insertions, 0 deletions
diff --git a/pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod b/pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod
new file mode 100644
index 0000000..666f138
--- /dev/null
+++ b/pcb/footprints.pretty/microusb_ali_dovetail.kicad_mod
@@ -0,0 +1,30 @@
+(module microusb_ali_dovetail (layer F.Cu) (tedit 5BFF34EF)
+ (fp_text reference REF** (at 6.3 -3.4) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value microusb_ali_dovetail (at 0 -5.8) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -3.9 -5.6) (end 3.9 -5.6) (layer F.CrtYd) (width 0.5))
+ (fp_line (start 3.9 -5.6) (end 3.9 0) (layer F.CrtYd) (width 0.5))
+ (fp_line (start 3.9 0) (end -3.9 0) (layer F.CrtYd) (width 0.5))
+ (fp_line (start -3.9 0) (end -3.9 -5.6) (layer F.CrtYd) (width 0.5))
+ (fp_line (start -3.9 -5.6) (end -3.9 0) (layer F.SilkS) (width 0.5))
+ (fp_line (start -3.9 0) (end 3.9 0) (layer F.SilkS) (width 0.5))
+ (fp_line (start 3.9 0) (end 3.9 -5.6) (layer F.SilkS) (width 0.5))
+ (fp_line (start 3.9 -5.6) (end -3.9 -5.6) (layer F.SilkS) (width 0.5))
+ (fp_line (start -3.9 -4.2) (end 3.9 -4.2) (layer F.SilkS) (width 0.5))
+ (fp_line (start 3.9 -5.6) (end 2.5 -4.2) (layer F.SilkS) (width 0.5))
+ (fp_line (start -3.9 -5.6) (end -2.5 -4.2) (layer F.SilkS) (width 0.5))
+ (fp_line (start -2.2 -3.4) (end -2.2 -2.2) (layer F.SilkS) (width 0.5))
+ (fp_line (start 2.2 -3.4) (end 2.2 -2.2) (layer F.SilkS) (width 0.5))
+ (pad 6 thru_hole oval (at -3.625 -2.65) (size 1.5 2) (drill 1.1) (layers *.Cu *.Mask))
+ (pad 6 thru_hole oval (at -2.425 0) (size 1 1.5) (drill 0.7) (layers *.Cu *.Mask))
+ (pad 6 thru_hole oval (at 2.425 0) (size 1 1.5) (drill 0.7) (layers *.Cu *.Mask))
+ (pad 6 thru_hole oval (at 3.625 -2.65) (size 1.5 2) (drill 1.1) (layers *.Cu *.Mask))
+ (pad 3 smd rect (at 0 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask))
+ (pad 2 smd rect (at 0.65 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask))
+ (pad 1 smd rect (at 1.3 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask))
+ (pad 4 smd rect (at -0.65 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask))
+ (pad 5 smd rect (at -1.3 0) (size 0.4 1.35) (layers F.Cu F.Paste F.Mask))
+)