Initial commit, blink working

10 files changed, 1293 insertions, 0 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..6b57994
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,7 @@
+*.o
+*.elf
+*.lst
+*.hex
+*.map
+*.bin
+*.expand
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..e1d6d0a
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,57 @@
+# put your *.o targets here, make should handle the rest!
+CUBE_PATH 		?= $(wildcard ~)/resource/STM32CubeF4
+CMSIS_PATH 		?= $(CUBE_PATH)/Drivers/CMSIS
+CMSIS_DEV_PATH  ?= $(CMSIS_PATH)/Device/ST/STM32F4xx
+HAL_PATH   		?= $(CUBE_PATH)/Drivers/STM32F4xx_HAL_Driver
+
+CC      := arm-none-eabi-gcc
+LD      := arm-none-eabi-ld
+OBJCOPY := arm-none-eabi-objcopy
+OBJDUMP := arm-none-eabi-objdump
+SIZE    := arm-none-eabi-size
+
+CFLAGS  = -Wall -std=gnu11 -Os -fdump-rtl-expand
+CFLAGS += -mlittle-endian -mcpu=cortex-m4 -mthumb
+CFLAGS += -ffunction-sections -fdata-sections
+LDFLAGS = -nostartfiles
+LDFLAGS += -Wl,-Map=main.map -nostdlib
+LDFLAGS += -Wl,--gc-sections 
+LIBS = -lgcc
+#LIBS += -lrdimon
+
+CFLAGS += -DSTM32F407xx
+
+LDFLAGS += -Tstm32_flash.ld
+CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig
+LDFLAGS += -L$(CMSIS_PATH)/Lib/GCC
+
+###################################################
+
+.PHONY: program clean
+
+all: main.elf main.pdf
+
+%.o: %.c
+	$(CC) -c $(CFLAGS) -o $@ $^
+
+%.o: %.s
+	$(CC) -c $(CFLAGS) -o $@ $^
+
+%.dot: %.elf
+	r2 -a arm -qc 'aa;agC' $< 2>/dev/null >$@
+
+main.elf: main.o startup_stm32f407xx.o system_stm32f4xx.c $(HAL_PATH)/Src/stm32f4xx_ll_utils.o
+	$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $^ $(LIBS)
+	$(OBJCOPY) -O ihex $@ $(@:.elf=.hex)
+	$(OBJCOPY) -O binary $@ $(@:.elf=.bin)
+	$(OBJDUMP) -St $@ >$(@:.elf=.lst)
+	$(SIZE) $@
+	
+program: main.elf openocd.cfg
+	openocd -f openocd.cfg -c "program $< verify reset exit"
+
+clean:
+	rm -f **.o
+	rm -f main.elf main.hex main.bin main.map main.lst
+	rm -f **.expand
+
diff --git a/base.c b/base.c
new file mode 100644
index 0000000..8c9de6f
--- /dev/null
+++ b/base.c
@@ -0,0 +1,20 @@
+
+#include <unistd.h>
+
+int __errno = 0;
+void *_impure_ptr = NULL;
+
+void __sinit(void) {
+}
+
+void memset(void *s, int c, size_t n) {
+    char *end = (char *)s + n;
+    for (char *p = (char *)s; p < end; p++)
+        *p = (char)c;
+}
+
+size_t strlen(const char *s) {
+    const char *start = s;
+    while (*s++);
+    return s - start - 1;
+}
diff --git a/main.c b/main.c
new file mode 100644
index 0000000..eb093c4
--- /dev/null
+++ b/main.c
@@ -0,0 +1,82 @@
+
+#include <stm32f407xx.h>
+#include <stdint.h>
+#include <system_stm32f4xx.h>
+#include <stm32f4xx_ll_utils.h>
+#include <stm32f4xx_ll_spi.h>
+#include <string.h>
+#include <unistd.h>
+/* 
+ * Part number: STM32F030F4C6
+ */
+
+void _init(void) {}
+
+void tick(void) {
+    for(int i=0; i<50; i++)
+        __asm__("nop");
+}
+
+int main(void) {
+    /*
+    RCC->CR |= RCC_CR_HSEON;
+    while (!(RCC->CR&RCC_CR_HSERDY));
+    RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk;
+    RCC->CFGR |= (2<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV;
+    RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_Msk;
+    RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2;
+    RCC->CR |= RCC_CR_PLLON;
+    while (!(RCC->CR&RCC_CR_PLLRDY));
+    RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
+    SystemCoreClockUpdate();
+    */
+
+    LL_Init1msTick(SystemCoreClock);
+
+    RCC->AHB1ENR  |= RCC_AHB1ENR_GPIOAEN;
+
+    GPIOA->MODER |=
+        (1<<GPIO_MODER_MODER5_Pos)|
+        (1<<GPIO_MODER_MODER6_Pos)|
+        (1<<GPIO_MODER_MODER7_Pos);
+
+    /* Set shift register IO GPIO output speed */
+    GPIOA->OSPEEDR |=
+        (2<<GPIO_OSPEEDR_OSPEED5_Pos)|
+        (2<<GPIO_OSPEEDR_OSPEED6_Pos)|
+        (2<<GPIO_OSPEEDR_OSPEED7_Pos);
+
+    GPIOA->BSRR = GPIO_BSRR_BR_5;
+    GPIOA->BSRR = GPIO_BSRR_BR_6;
+    GPIOA->BSRR = GPIO_BSRR_BR_7;
+    while (42) {
+        for (int i=0; i<10000; i++)
+            tick();
+        GPIOA->BSRR = GPIO_BSRR_BS_5;
+        GPIOA->BSRR = GPIO_BSRR_BS_6;
+        GPIOA->BSRR = GPIO_BSRR_BS_7;
+        for (int i=0; i<10000; i++)
+            tick();
+        GPIOA->BSRR = GPIO_BSRR_BR_5;
+        GPIOA->BSRR = GPIO_BSRR_BR_6;
+        GPIOA->BSRR = GPIO_BSRR_BR_7;
+    }
+}
+
+void NMI_Handler(void) {
+}
+
+void HardFault_Handler(void) {
+    for(;;);
+}
+
+void SVC_Handler(void) {
+}
+
+
+void PendSV_Handler(void) {
+}
+
+void SysTick_Handler(void) {
+}
+
diff --git a/mapparse.py b/mapparse.py
new file mode 100644
index 0000000..c1f460a
--- /dev/null
+++ b/mapparse.py
@@ -0,0 +1,129 @@
+
+import re
+from collections import defaultdict, namedtuple
+
+Section = namedtuple('Section', ['name', 'offset', 'objects'])
+ObjectEntry = namedtuple('ObjectEntry', ['filename', 'object', 'offset', 'size'])
+FileEntry = namedtuple('FileEntry', ['section', 'object', 'offset', 'length'])
+
+class Memory:
+    def __init__(self, name, origin, length, attrs=''):
+        self.name, self.origin, self.length, self.attrs = name, origin, length, attrs
+        self.sections = {}
+        self.files = defaultdict(lambda: [])
+        self.totals = defaultdict(lambda: 0)
+
+    def add_toplevel(self, name, offx, length):
+        self.sections[name] = Section(offx, length, [])
+
+    def add_obj(self, name, offx, length, fn, obj):
+        base_section, sep, subsec = name[1:].partition('.')
+        base_section = '.'+base_section
+        if base_section in self.sections:
+            sec = secname, secoffx, secobjs = self.sections[base_section]
+            secobjs.append(ObjectEntry(fn, obj, offx, length))
+        else:
+            sec = None
+        self.files[fn].append(FileEntry(sec, obj, offx, length))
+        self.totals[fn] += length
+
+class MapFile:
+    def __init__(self, s):
+        self._lines = s.splitlines()
+        self.memcfg = {}
+        self.defaultmem = Memory('default', 0, 0xffffffffffffffff)
+        self._parse()
+
+    def __getitem__(self, offx_or_name):
+        ''' Lookup a memory area by name or address '''
+        if offx_or_name in self.memcfg:
+            return self.memcfg[offx_or_name]
+
+        elif isinstance(offx_or_name, int):
+            for mem in self.memcfg.values():
+                if mem.origin <= offx_or_name < mem.origin+mem.length:
+                    return mem
+            else:
+                return self.defaultmem
+
+        raise ValueError('Invalid argument type for indexing')
+
+    def _skip(self, regex):
+        matcher = re.compile(regex)
+        for l in self:
+            if matcher.match(l):
+                break
+
+    def __iter__(self):
+        while self._lines:
+            yield self._lines.pop(0)
+
+    def _parse(self):
+        self._skip('^Memory Configuration')
+
+        # Parse memory segmentation info
+        self._skip('^Name')
+        for l in self:
+            if not l:
+                break
+            name, origin, length, *attrs = l.split()
+            if not name.startswith('*'):
+                self.memcfg[name] = Memory(name, int(origin, 16), int(length, 16), attrs[0] if attrs else '')
+
+        # Parse section information
+        toplevel_m = re.compile('^(\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)')
+        secondlevel_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\s+(0x[0-9a-fA-F]+)\s+(0x[0-9a-fA-F]+)\s+(.*)$')
+        secondlevel_linebreak_m = re.compile('^ (\.[a-zA-Z0-9_.]+)\n')
+        filelike = re.compile('^(/?[^()]*\.[a-zA-Z0-9-_]+)(\(.*\))?')
+        linebreak_section = None
+        for l in self:
+            # Toplevel section
+            match = toplevel_m.match(l)
+            if match:
+                name, offx, length = match.groups()
+                offx, length = int(offx, 16), int(length, 16)
+                self[offx].add_toplevel(name, offx, length)
+
+            match = secondlevel_linebreak_m.match(l)
+            if match:
+                linebreak_section, = match.groups()
+                continue
+
+            if linebreak_section:
+                l = ' {} {}'.format(linebreak_section, l)
+                linebreak_section = None
+
+            # Second-level section
+            match = secondlevel_m.match(l)
+            if match:
+                name, offx, length, misc = match.groups()
+                match = filelike.match(misc)
+                if match:
+                    fn, obj = match.groups()
+                    obj = obj.strip('()') if obj else None
+                    offx, length = int(offx, 16), int(length, 16)
+                    self[offx].add_obj(name, offx, length, fn, obj)
+
+
+if __name__ == '__main__':
+    import argparse
+    parser = argparse.ArgumentParser(description='Parser GCC map file')
+    parser.add_argument('mapfile', type=argparse.FileType('r'), help='The GCC .map file to parse')
+    parser.add_argument('-m', '--memory', type=str, help='The memory segments to print, comma-separated')
+    args = parser.parse_args()
+    mf = MapFile(args.mapfile.read())
+    args.mapfile.close()
+
+    mems = args.memory.split(',') if args.memory else mf.memcfg.keys()
+
+    for name in mems:
+        mem = mf.memcfg[name]
+        print('Symbols by file for memory', name)
+        for tot, fn in reversed(sorted( (tot, fn) for fn, tot in mem.totals.items() )):
+            print('    {:>8} {}'.format(tot, fn))
+            for length, offx, sec, obj in reversed(sorted(( (length, offx, sec, obj) for sec, obj, offx, length in
+                mem.files[fn] ), key=lambda e: e[0] )):
+                name = sec.name if sec else None
+                print('       {:>8} {:>#08x} {}'.format(length, offx, obj))
+        #print('{:>16} 0x{:016x} 0x{:016x} ({:>24}) {}'.format(name, origin, length, length, attrs))
+
diff --git a/mapvis.py b/mapvis.py
new file mode 100644
index 0000000..4a71222
--- /dev/null
+++ b/mapvis.py
@@ -0,0 +1,25 @@
+#!/usr/bin/env python3
+
+from matplotlib import pyplot as plt
+
+f, ax = plt.subplots(1, figsize=(3, 8))
+bar_width = 1
+
+ax.bar([-bar_width/2], top, bottom=bottom, width=bar_width, label='foo')
+ax.set_xticks([0], [filename])
+ax.set_ylabel('Memory usage (B)')
+ax.set_xlabel('')
+
+ax.set_xlim([-bar_width/2, bar_width/2])
+ax.set_ylim([0, mem_max])
+
+if __name__ == '__main__':
+    import argparse
+    import mapparse
+    parser = argparse.ArgumentParser(description='Visualize program memory usage using GCC map file')
+    parser.add_argument('mapfile', type=argparse.FileType('r'), description='Input GCC .map file')
+    args = parser.parse_args()
+
+    mapping = mapparse.MapFile(args.mapfile.read())
+    mapping.
+
diff --git a/openocd.cfg b/openocd.cfg
new file mode 100644
index 0000000..91a1deb
--- /dev/null
+++ b/openocd.cfg
@@ -0,0 +1,14 @@
+telnet_port 4444
+gdb_port 3333
+
+interface jlink
+
+adapter_khz 1000
+transport select swd
+
+source /usr/share/openocd/scripts/target/stm32f4x.cfg
+
+init
+#arm semihosting enable
+
+#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME
diff --git a/startup_stm32f407xx.s b/startup_stm32f407xx.s
new file mode 100644
index 0000000..b9c68ed
--- /dev/null
+++ b/startup_stm32f407xx.s
@@ -0,0 +1,523 @@
+/**

+  ******************************************************************************

+  * @file      startup_stm32f407xx.s

+  * @author    MCD Application Team

+  * @version   V1.4.4

+  * @date      17-February-2017

+  * @brief     STM32F407xx Devices vector table for GCC based toolchain. 

+  *            This module performs:

+  *                - Set the initial SP

+  *                - Set the initial PC == Reset_Handler,

+  *                - Set the vector table entries with the exceptions ISR address

+  *                - Branches to main in the C library (which eventually

+  *                  calls main()).

+  *            After Reset the Cortex-M4 processor is in Thread mode,

+  *            priority is Privileged, and the Stack is set to Main.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>

+  *

+  * Redistribution and use in source and binary forms, with or without modification,

+  * are permitted provided that the following conditions are met:

+  *   1. Redistributions of source code must retain the above copyright notice,

+  *      this list of conditions and the following disclaimer.

+  *   2. Redistributions in binary form must reproduce the above copyright notice,

+  *      this list of conditions and the following disclaimer in the documentation

+  *      and/or other materials provided with the distribution.

+  *   3. Neither the name of STMicroelectronics nor the names of its contributors

+  *      may be used to endorse or promote products derived from this software

+  *      without specific prior written permission.

+  *

+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+  *

+  ******************************************************************************

+  */

+    

+  .syntax unified

+  .cpu cortex-m4

+  .fpu softvfp

+  .thumb

+

+.global  g_pfnVectors

+.global  Default_Handler

+

+/* start address for the initialization values of the .data section. 

+defined in linker script */

+.word  _sidata

+/* start address for the .data section. defined in linker script */  

+.word  _sdata

+/* end address for the .data section. defined in linker script */

+.word  _edata

+/* start address for the .bss section. defined in linker script */

+.word  _sbss

+/* end address for the .bss section. defined in linker script */

+.word  _ebss

+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */

+

+/**

+ * @brief  This is the code that gets called when the processor first

+ *          starts execution following a reset event. Only the absolutely

+ *          necessary set is performed, after which the application

+ *          supplied main() routine is called. 

+ * @param  None

+ * @retval : None

+*/

+

+    .section  .text.Reset_Handler

+  .weak  Reset_Handler

+  .type  Reset_Handler, %function

+Reset_Handler:  

+  ldr   sp, =_estack     /* set stack pointer */

+

+/* Copy the data segment initializers from flash to SRAM */  

+  movs  r1, #0

+  b  LoopCopyDataInit

+

+CopyDataInit:

+  ldr  r3, =_sidata

+  ldr  r3, [r3, r1]

+  str  r3, [r0, r1]

+  adds  r1, r1, #4

+    

+LoopCopyDataInit:

+  ldr  r0, =_sdata

+  ldr  r3, =_edata

+  adds  r2, r0, r1

+  cmp  r2, r3

+  bcc  CopyDataInit

+  ldr  r2, =_sbss

+  b  LoopFillZerobss

+/* Zero fill the bss segment. */  

+FillZerobss:

+  movs  r3, #0

+  str  r3, [r2], #4

+    

+LoopFillZerobss:

+  ldr  r3, = _ebss

+  cmp  r2, r3

+  bcc  FillZerobss

+

+/* Call the clock system intitialization function.*/

+  bl  SystemInit   

+/* Call static constructors */

+    bl __libc_init_array

+/* Call the application's entry point.*/

+  bl  main

+  bx  lr    

+.size  Reset_Handler, .-Reset_Handler

+

+/**

+ * @brief  This is the code that gets called when the processor receives an 

+ *         unexpected interrupt.  This simply enters an infinite loop, preserving

+ *         the system state for examination by a debugger.

+ * @param  None     

+ * @retval None       

+*/

+    .section  .text.Default_Handler,"ax",%progbits

+Default_Handler:

+Infinite_Loop:

+  b  Infinite_Loop

+  .size  Default_Handler, .-Default_Handler

+/******************************************************************************

+*

+* The minimal vector table for a Cortex M3. Note that the proper constructs

+* must be placed on this to ensure that it ends up at physical address

+* 0x0000.0000.

+* 

+*******************************************************************************/

+   .section  .isr_vector,"a",%progbits

+  .type  g_pfnVectors, %object

+  .size  g_pfnVectors, .-g_pfnVectors

+    

+    

+g_pfnVectors:

+  .word  _estack

+  .word  Reset_Handler

+  .word  NMI_Handler

+  .word  HardFault_Handler

+  .word  MemManage_Handler

+  .word  BusFault_Handler

+  .word  UsageFault_Handler

+  .word  0

+  .word  0

+  .word  0

+  .word  0

+  .word  SVC_Handler

+  .word  DebugMon_Handler

+  .word  0

+  .word  PendSV_Handler

+  .word  SysTick_Handler

+  

+  /* External Interrupts */

+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        

+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        

+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            

+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      

+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          

+  .word     RCC_IRQHandler                    /* RCC                          */                                            

+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        

+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          

+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          

+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          

+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          

+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  

+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   

+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   

+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   

+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   

+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   

+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   

+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   

+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         

+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          

+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          

+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          

+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          

+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         

+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         

+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */

+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          

+  .word     TIM2_IRQHandler                   /* TIM2                         */                   

+  .word     TIM3_IRQHandler                   /* TIM3                         */                   

+  .word     TIM4_IRQHandler                   /* TIM4                         */                   

+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          

+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          

+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          

+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            

+  .word     SPI1_IRQHandler                   /* SPI1                         */                   

+  .word     SPI2_IRQHandler                   /* SPI2                         */                   

+  .word     USART1_IRQHandler                 /* USART1                       */                   

+  .word     USART2_IRQHandler                 /* USART2                       */                   

+  .word     USART3_IRQHandler                 /* USART3                       */                   

+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          

+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 

+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       

+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         

+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         

+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */

+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          

+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          

+  .word     FSMC_IRQHandler                   /* FSMC                         */                   

+  .word     SDIO_IRQHandler                   /* SDIO                         */                   

+  .word     TIM5_IRQHandler                   /* TIM5                         */                   

+  .word     SPI3_IRQHandler                   /* SPI3                         */                   

+  .word     UART4_IRQHandler                  /* UART4                        */                   

+  .word     UART5_IRQHandler                  /* UART5                        */                   

+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   

+  .word     TIM7_IRQHandler                   /* TIM7                         */

+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   

+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   

+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   

+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   

+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   

+  .word     ETH_IRQHandler                    /* Ethernet                     */                   

+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     

+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          

+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          

+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          

+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          

+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   

+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   

+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   

+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   

+  .word     USART6_IRQHandler                 /* USART6                       */                    

+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          

+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          

+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   

+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   

+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         

+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   

+  .word     DCMI_IRQHandler                   /* DCMI                         */                   

+  .word     0                                 /* CRYP crypto                  */                   

+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */

+  .word     FPU_IRQHandler                    /* FPU                          */

+                         

+                         

+/*******************************************************************************

+*

+* Provide weak aliases for each Exception handler to the Default_Handler. 

+* As they are weak aliases, any function with the same name will override 

+* this definition.

+* 

+*******************************************************************************/

+   .weak      NMI_Handler

+   .thumb_set NMI_Handler,Default_Handler

+  

+   .weak      HardFault_Handler

+   .thumb_set HardFault_Handler,Default_Handler

+  

+   .weak      MemManage_Handler

+   .thumb_set MemManage_Handler,Default_Handler

+  

+   .weak      BusFault_Handler

+   .thumb_set BusFault_Handler,Default_Handler

+

+   .weak      UsageFault_Handler

+   .thumb_set UsageFault_Handler,Default_Handler

+

+   .weak      SVC_Handler

+   .thumb_set SVC_Handler,Default_Handler

+

+   .weak      DebugMon_Handler

+   .thumb_set DebugMon_Handler,Default_Handler

+

+   .weak      PendSV_Handler

+   .thumb_set PendSV_Handler,Default_Handler

+

+   .weak      SysTick_Handler

+   .thumb_set SysTick_Handler,Default_Handler              

+  

+   .weak      WWDG_IRQHandler                   

+   .thumb_set WWDG_IRQHandler,Default_Handler      

+                  

+   .weak      PVD_IRQHandler      

+   .thumb_set PVD_IRQHandler,Default_Handler

+               

+   .weak      TAMP_STAMP_IRQHandler            

+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler

+            

+   .weak      RTC_WKUP_IRQHandler                  

+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler

+            

+   .weak      FLASH_IRQHandler         

+   .thumb_set FLASH_IRQHandler,Default_Handler

+                  

+   .weak      RCC_IRQHandler      

+   .thumb_set RCC_IRQHandler,Default_Handler

+                  

+   .weak      EXTI0_IRQHandler         

+   .thumb_set EXTI0_IRQHandler,Default_Handler

+                  

+   .weak      EXTI1_IRQHandler         

+   .thumb_set EXTI1_IRQHandler,Default_Handler

+                     

+   .weak      EXTI2_IRQHandler         

+   .thumb_set EXTI2_IRQHandler,Default_Handler 

+                 

+   .weak      EXTI3_IRQHandler         

+   .thumb_set EXTI3_IRQHandler,Default_Handler

+                        

+   .weak      EXTI4_IRQHandler         

+   .thumb_set EXTI4_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream0_IRQHandler               

+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler

+         

+   .weak      DMA1_Stream1_IRQHandler               

+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream2_IRQHandler               

+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream3_IRQHandler               

+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 

+                 

+   .weak      DMA1_Stream4_IRQHandler              

+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream5_IRQHandler               

+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream6_IRQHandler               

+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler

+                  

+   .weak      ADC_IRQHandler      

+   .thumb_set ADC_IRQHandler,Default_Handler

+               

+   .weak      CAN1_TX_IRQHandler   

+   .thumb_set CAN1_TX_IRQHandler,Default_Handler

+            

+   .weak      CAN1_RX0_IRQHandler                  

+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler

+                           

+   .weak      CAN1_RX1_IRQHandler                  

+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler

+            

+   .weak      CAN1_SCE_IRQHandler                  

+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler

+            

+   .weak      EXTI9_5_IRQHandler   

+   .thumb_set EXTI9_5_IRQHandler,Default_Handler

+            

+   .weak      TIM1_BRK_TIM9_IRQHandler            

+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler

+            

+   .weak      TIM1_UP_TIM10_IRQHandler            

+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler

+      

+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      

+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler

+      

+   .weak      TIM1_CC_IRQHandler   

+   .thumb_set TIM1_CC_IRQHandler,Default_Handler

+                  

+   .weak      TIM2_IRQHandler            

+   .thumb_set TIM2_IRQHandler,Default_Handler

+                  

+   .weak      TIM3_IRQHandler            

+   .thumb_set TIM3_IRQHandler,Default_Handler

+                  

+   .weak      TIM4_IRQHandler            

+   .thumb_set TIM4_IRQHandler,Default_Handler

+                  

+   .weak      I2C1_EV_IRQHandler   

+   .thumb_set I2C1_EV_IRQHandler,Default_Handler

+                     

+   .weak      I2C1_ER_IRQHandler   

+   .thumb_set I2C1_ER_IRQHandler,Default_Handler

+                     

+   .weak      I2C2_EV_IRQHandler   

+   .thumb_set I2C2_EV_IRQHandler,Default_Handler

+                  

+   .weak      I2C2_ER_IRQHandler   

+   .thumb_set I2C2_ER_IRQHandler,Default_Handler

+                           

+   .weak      SPI1_IRQHandler            

+   .thumb_set SPI1_IRQHandler,Default_Handler

+                        

+   .weak      SPI2_IRQHandler            

+   .thumb_set SPI2_IRQHandler,Default_Handler

+                  

+   .weak      USART1_IRQHandler      

+   .thumb_set USART1_IRQHandler,Default_Handler

+                     

+   .weak      USART2_IRQHandler      

+   .thumb_set USART2_IRQHandler,Default_Handler

+                     

+   .weak      USART3_IRQHandler      

+   .thumb_set USART3_IRQHandler,Default_Handler

+                  

+   .weak      EXTI15_10_IRQHandler               

+   .thumb_set EXTI15_10_IRQHandler,Default_Handler

+               

+   .weak      RTC_Alarm_IRQHandler               

+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler

+            

+   .weak      OTG_FS_WKUP_IRQHandler         

+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler

+            

+   .weak      TIM8_BRK_TIM12_IRQHandler         

+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler

+         

+   .weak      TIM8_UP_TIM13_IRQHandler            

+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler

+         

+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      

+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler

+      

+   .weak      TIM8_CC_IRQHandler   

+   .thumb_set TIM8_CC_IRQHandler,Default_Handler

+                  

+   .weak      DMA1_Stream7_IRQHandler               

+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler

+                     

+   .weak      FSMC_IRQHandler            

+   .thumb_set FSMC_IRQHandler,Default_Handler

+                     

+   .weak      SDIO_IRQHandler            

+   .thumb_set SDIO_IRQHandler,Default_Handler

+                     

+   .weak      TIM5_IRQHandler            

+   .thumb_set TIM5_IRQHandler,Default_Handler

+                     

+   .weak      SPI3_IRQHandler            

+   .thumb_set SPI3_IRQHandler,Default_Handler

+                     

+   .weak      UART4_IRQHandler         

+   .thumb_set UART4_IRQHandler,Default_Handler

+                  

+   .weak      UART5_IRQHandler         

+   .thumb_set UART5_IRQHandler,Default_Handler

+                  

+   .weak      TIM6_DAC_IRQHandler                  

+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler

+               

+   .weak      TIM7_IRQHandler            

+   .thumb_set TIM7_IRQHandler,Default_Handler

+         

+   .weak      DMA2_Stream0_IRQHandler               

+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler

+               

+   .weak      DMA2_Stream1_IRQHandler               

+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler

+                  

+   .weak      DMA2_Stream2_IRQHandler               

+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler

+            

+   .weak      DMA2_Stream3_IRQHandler               

+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler

+            

+   .weak      DMA2_Stream4_IRQHandler               

+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler

+            

+   .weak      ETH_IRQHandler      

+   .thumb_set ETH_IRQHandler,Default_Handler

+                  

+   .weak      ETH_WKUP_IRQHandler                  

+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler

+            

+   .weak      CAN2_TX_IRQHandler   

+   .thumb_set CAN2_TX_IRQHandler,Default_Handler

+                           

+   .weak      CAN2_RX0_IRQHandler                  

+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler

+                           

+   .weak      CAN2_RX1_IRQHandler                  

+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler

+                           

+   .weak      CAN2_SCE_IRQHandler                  

+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler

+                           

+   .weak      OTG_FS_IRQHandler      

+   .thumb_set OTG_FS_IRQHandler,Default_Handler

+                     

+   .weak      DMA2_Stream5_IRQHandler               

+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler

+                  

+   .weak      DMA2_Stream6_IRQHandler               

+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler

+                  

+   .weak      DMA2_Stream7_IRQHandler               

+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler

+                  

+   .weak      USART6_IRQHandler      

+   .thumb_set USART6_IRQHandler,Default_Handler

+                        

+   .weak      I2C3_EV_IRQHandler   

+   .thumb_set I2C3_EV_IRQHandler,Default_Handler

+                        

+   .weak      I2C3_ER_IRQHandler   

+   .thumb_set I2C3_ER_IRQHandler,Default_Handler

+                        

+   .weak      OTG_HS_EP1_OUT_IRQHandler         

+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler

+               

+   .weak      OTG_HS_EP1_IN_IRQHandler            

+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler

+               

+   .weak      OTG_HS_WKUP_IRQHandler         

+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler

+            

+   .weak      OTG_HS_IRQHandler      

+   .thumb_set OTG_HS_IRQHandler,Default_Handler

+                  

+   .weak      DCMI_IRQHandler            

+   .thumb_set DCMI_IRQHandler,Default_Handler

+                                   

+   .weak      HASH_RNG_IRQHandler                  

+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   

+

+   .weak      FPU_IRQHandler                  

+   .thumb_set FPU_IRQHandler,Default_Handler  

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/stm32_flash.ld b/stm32_flash.ld
new file mode 100644
index 0000000..c54a3b8
--- /dev/null
+++ b/stm32_flash.ld
@@ -0,0 +1,158 @@
+
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20020000;    /* end of RAM */
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200;;      /* required amount of heap  */
+_Min_Stack_Size = 0x400;; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
+CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K
+}
+
+/* Define output sections */
+SECTIONS
+{
+  /* The startup code goes first into FLASH */
+  .isr_vector :
+  {
+    . = ALIGN(4);
+    KEEP(*(.isr_vector)) /* Startup code */
+    . = ALIGN(4);
+  } >FLASH
+
+  /* The program code and other data goes into FLASH */
+  .text :
+  {
+    . = ALIGN(4);
+    *(.text)           /* .text sections (code) */
+    *(.text*)          /* .text* sections (code) */
+    *(.glue_7)         /* glue arm to thumb code */
+    *(.glue_7t)        /* glue thumb to arm code */
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    . = ALIGN(4);
+    _etext = .;        /* define a global symbols at end of code */
+  } >FLASH
+
+  /* Constant data goes into FLASH */
+  .rodata :
+  {
+    . = ALIGN(4);
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    . = ALIGN(4);
+  } >FLASH
+
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+  .ARM : {
+    __exidx_start = .;
+    *(.ARM.exidx*)
+    __exidx_end = .;
+  } >FLASH
+
+  .preinit_array     :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array*))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >FLASH
+  .init_array :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array*))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >FLASH
+  .fini_array :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT(.fini_array.*)))
+    KEEP (*(.fini_array*))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >FLASH
+
+  /* used by the startup to initialize data */
+  _sidata = LOADADDR(.data);
+
+  /* Initialized data sections goes into RAM, load LMA copy after code */
+  .data : 
+  {
+    . = ALIGN(4);
+    _sdata = .;        /* create a global symbol at data start */
+    *(.data)           /* .data sections */
+    *(.data*)          /* .data* sections */
+
+    . = ALIGN(4);
+    _edata = .;        /* define a global symbol at data end */
+  } >RAM AT> FLASH
+
+  _siccmram = LOADADDR(.ccmram);
+
+  /* CCM-RAM section 
+  * 
+  * IMPORTANT NOTE! 
+  * If initialized variables will be placed in this section,
+  * the startup code needs to be modified to copy the init-values.  
+  */
+  .ccmram :
+  {
+    . = ALIGN(4);
+    _sccmram = .;       /* create a global symbol at ccmram start */
+    *(.ccmram)
+    *(.ccmram*)
+    
+    . = ALIGN(4);
+    _eccmram = .;       /* create a global symbol at ccmram end */
+  } >CCMRAM AT> FLASH
+
+  
+  /* Uninitialized data section */
+  . = ALIGN(4);
+  .bss :
+  {
+    /* This is used by the startup in order to initialize the .bss secion */
+    _sbss = .;         /* define a global symbol at bss start */
+    __bss_start__ = _sbss;
+    *(.bss)
+    *(.bss*)
+    *(COMMON)
+
+    . = ALIGN(4);
+    _ebss = .;         /* define a global symbol at bss end */
+    __bss_end__ = _ebss;
+  } >RAM
+
+  /* User_heap_stack section, used to check that there is enough RAM left */
+  ._user_heap_stack :
+  {
+    . = ALIGN(4);
+    PROVIDE ( end = . );
+    PROVIDE ( _end = . );
+    . = . + _Min_Heap_Size;
+    . = . + _Min_Stack_Size;
+    . = ALIGN(4);
+  } >RAM
+
+  
+
+  /* Remove information from the standard libraries */
+  /DISCARD/ :
+  {
+    libc.a ( * )
+    libm.a ( * )
+    libgcc.a ( * )
+  }
+
+  .ARM.attributes 0 : { *(.ARM.attributes) }
+}
+
+
diff --git a/system_stm32f4xx.c b/system_stm32f4xx.c
new file mode 100644
index 0000000..854bc35
--- /dev/null
+++ b/system_stm32f4xx.c
@@ -0,0 +1,278 @@
+/**

+  ******************************************************************************

+  * @file    Demonstrations/Src/system_stm32f4xx.c

+  * @author  MCD Application Team

+  * @version V1.4.4

+  * @date    17-February-2017

+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.

+  *

+  *   This file provides two functions and one global variable to be called from 

+  *   user application:

+  *      - SystemInit(): This function is called at startup just after reset and 

+  *                      before branch to main program. This call is made inside

+  *                      the "startup_stm32f4xx.s" file.

+  *

+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used

+  *                                  by the user application to setup the SysTick 

+  *                                  timer or configure other parameters.

+  *                                     

+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must

+  *                                 be called whenever the core clock is changed

+  *                                 during program execution.

+  *

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

+  *

+  * Redistribution and use in source and binary forms, with or without modification,

+  * are permitted provided that the following conditions are met:

+  *   1. Redistributions of source code must retain the above copyright notice,

+  *      this list of conditions and the following disclaimer.

+  *   2. Redistributions in binary form must reproduce the above copyright notice,

+  *      this list of conditions and the following disclaimer in the documentation

+  *      and/or other materials provided with the distribution.

+  *   3. Neither the name of STMicroelectronics nor the names of its contributors

+  *      may be used to endorse or promote products derived from this software

+  *      without specific prior written permission.

+  *

+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS

+  * @{

+  */

+

+/** @addtogroup stm32f4xx_system

+  * @{

+  */  

+  

+/** @addtogroup STM32F4xx_System_Private_Includes

+  * @{

+  */

+

+#include "stm32f4xx.h"

+

+#if !defined  (HSE_VALUE) 

+  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */

+#endif /* HSE_VALUE */

+

+#if !defined  (HSI_VALUE)

+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/

+#endif /* HSI_VALUE */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_Defines

+  * @{

+  */

+

+/************************* Miscellaneous Configuration ************************/

+

+/*!< Uncomment the following line if you need to relocate your vector Table in

+     Internal SRAM. */

+/* #define VECT_TAB_SRAM */

+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 

+                                   This value must be a multiple of 0x200. */

+/******************************************************************************/

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_Variables

+  * @{

+  */

+  /* This variable is updated in three ways:

+      1) by calling CMSIS function SystemCoreClockUpdate()

+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()

+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 

+         Note: If you use this function to configure the system clock; then there

+               is no need to call the 2 first functions listed above, since SystemCoreClock

+               variable is updated automatically.

+  */

+uint32_t SystemCoreClock = 16000000;

+const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};

+const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32F4xx_System_Private_Functions

+  * @{

+  */

+

+/**

+  * @brief  Setup the microcontroller system

+  *         Initialize the FPU setting, vector table location and External memory 

+  *         configuration.

+  * @param  None

+  * @retval None

+  */

+void SystemInit(void)

+{

+  /* FPU settings ------------------------------------------------------------*/

+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)

+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */

+  #endif

+  /* Reset the RCC clock configuration to the default reset state ------------*/

+  /* Set HSION bit */

+  RCC->CR |= (uint32_t)0x00000001;

+

+  /* Reset CFGR register */

+  RCC->CFGR = 0x00000000;

+

+  /* Reset HSEON, CSSON and PLLON bits */

+  RCC->CR &= (uint32_t)0xFEF6FFFF;

+

+  /* Reset PLLCFGR register */

+  RCC->PLLCFGR = 0x24003010;

+

+  /* Reset HSEBYP bit */

+  RCC->CR &= (uint32_t)0xFFFBFFFF;

+

+  /* Disable all interrupts */

+  RCC->CIR = 0x00000000;

+

+  /* Configure the Vector Table location add offset address ------------------*/

+#ifdef VECT_TAB_SRAM

+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */

+#else

+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */

+#endif

+}

+

+/**

+   * @brief  Update SystemCoreClock variable according to Clock Register Values.

+  *         The SystemCoreClock variable contains the core clock (HCLK), it can

+  *         be used by the user application to setup the SysTick timer or configure

+  *         other parameters.

+  *           

+  * @note   Each time the core clock (HCLK) changes, this function must be called

+  *         to update SystemCoreClock variable value. Otherwise, any configuration

+  *         based on this variable will be incorrect.         

+  *     

+  * @note   - The system frequency computed by this function is not the real 

+  *           frequency in the chip. It is calculated based on the predefined 

+  *           constant and the selected clock source:

+  *             

+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)

+  *                                              

+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)

+  *                          

+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 

+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.

+  *         

+  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value

+  *             16 MHz) but the real value may vary depending on the variations

+  *             in voltage and temperature.   

+  *    

+  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value

+  *              depends on the application requirements), user has to ensure that HSE_VALUE

+  *              is same as the real frequency of the crystal used. Otherwise, this function

+  *              may have wrong result.

+  *                

+  *         - The result of this function could be not correct when using fractional

+  *           value for HSE crystal.

+  *     

+  * @param  None

+  * @retval None

+  */

+void SystemCoreClockUpdate(void)

+{

+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;

+  

+  /* Get SYSCLK source -------------------------------------------------------*/

+  tmp = RCC->CFGR & RCC_CFGR_SWS;

+

+  switch (tmp)

+  {

+    case 0x00:  /* HSI used as system clock source */

+      SystemCoreClock = HSI_VALUE;

+      break;

+    case 0x04:  /* HSE used as system clock source */

+      SystemCoreClock = HSE_VALUE;

+      break;

+    case 0x08:  /* PLL used as system clock source */

+

+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N

+         SYSCLK = PLL_VCO / PLL_P

+         */    

+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;

+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;

+      

+      if (pllsource != 0)

+      {

+        /* HSE used as PLL clock source */

+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

+      }

+      else

+      {

+        /* HSI used as PLL clock source */

+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);

+      }

+

+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;

+      SystemCoreClock = pllvco/pllp;

+      break;

+    default:

+      SystemCoreClock = HSI_VALUE;

+      break;

+  }

+  /* Compute HCLK frequency --------------------------------------------------*/

+  /* Get HCLK prescaler */

+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];

+  /* HCLK frequency */

+  SystemCoreClock >>= tmp;

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+  

+/**

+  * @}

+  */    

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/