From 6002d409143a6726899a4de15c3a6b279a6b1d71 Mon Sep 17 00:00:00 2001
From: jaseg <git@jaseg.net>
Date: Fri, 27 Sep 2019 10:07:38 +0200
Subject: Directory reorg: Put renderer into its own subdir

---
 renderer/support/pogojig/kicad/__init__.py     |  0
 renderer/support/pogojig/kicad/kicad-cache.lib | 21 ++++++++++++++++
 renderer/support/pogojig/kicad/kicad.pro       | 34 ++++++++++++++++++++++++++
 3 files changed, 55 insertions(+)
 create mode 100644 renderer/support/pogojig/kicad/__init__.py
 create mode 100644 renderer/support/pogojig/kicad/kicad-cache.lib
 create mode 100644 renderer/support/pogojig/kicad/kicad.pro

(limited to 'renderer/support/pogojig/kicad')

diff --git a/renderer/support/pogojig/kicad/__init__.py b/renderer/support/pogojig/kicad/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/renderer/support/pogojig/kicad/kicad-cache.lib b/renderer/support/pogojig/kicad/kicad-cache.lib
new file mode 100644
index 0000000..a98cd73
--- /dev/null
+++ b/renderer/support/pogojig/kicad/kicad-cache.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Conn_01x01_Female
+#
+DEF Connector_Conn_01x01_Female J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Connector_Conn_01x01_Female" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*
+$ENDFPLIST
+DRAW
+A 0 0 20 901 -901 1 1 6 N 0 20 0 -20
+P 2 1 1 6 -50 0 -20 0 N
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/renderer/support/pogojig/kicad/kicad.pro b/renderer/support/pogojig/kicad/kicad.pro
new file mode 100644
index 0000000..5cd0983
--- /dev/null
+++ b/renderer/support/pogojig/kicad/kicad.pro
@@ -0,0 +1,34 @@
+update=05/04/2019 20:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+CopperEdgeClearance=0.000000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
-- 
cgit