#include #include #include #include /* * Part number: STM32F030F4C6 */ int main(void) { RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR&RCC_CR_HSERDY)); RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk; RCC->CFGR |= (2<CR |= RCC_CR_PLLON; while (!(RCC->CR&RCC_CR_PLLRDY)); RCC->CFGR |= (2<AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN; RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_ADCEN; GPIOA->MODER |= (3<MODER |= (1<OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_4; /* LED outputs -> open drain */ /* Set shift register IO GPIO output speed */ GPIOA->OSPEEDR |= (3<AFR[0] |= (1<AFR[1] |= (2<BSRR = GPIO_BSRR_BR_1; /* clear output is active low */ /* Configure SPI controller */ /* CPOL=0, CPHA=0, prescaler=8 -> 1MBd */ // SPI1->CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2<CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (0<CR2 = (7<CR1 = TIM_CR1_OPM | TIM_CR1_URS; // TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_URS; TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM; // | TIM_CR1_URS; TIM1->CR2 = 0; //TIM_CR2_CCPC; TIM1->SMCR = 0; TIM1->DIER = 0; TIM1->PSC = 4; // debug /* CH2 - clear/!MR, CH3 - strobe/STCP */ TIM1->CCR2 = 1; TIM1->RCR = 0; TIM1->CCMR1 = (6<CCMR2 = (6<CCER |= TIM_CCER_CC2E | TIM_CCER_CC2NE | TIM_CCER_CC2P | TIM_CCER_CC3E; // TIM1->CCMR1 = (6<CCMR2 = (6<CCER = TIM_CCER_CC2E | TIM_CCER_CC3E; // TIM1->BDTR = TIM_BDTR_MOE; TIM1->DIER = TIM_DIER_UIE; NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 2); TIM1->EGR |= TIM_EGR_UG; for (;;) { GPIOA->ODR ^= GPIO_ODR_6; LL_mDelay(1); } } #define NBITS 4 uint8_t brightness_by_bit[NBITS] = { 0x11, 0x22, 0x44, 0x88 }; /* * 1.00us * 1.64us * 2.84us * 5.36us * 10.4us * 20.4us * 40.4us * 80.8us */ void TIM1_BRK_UP_TRG_COM_IRQHandler(void) { static uint32_t idx = 0; idx = (idx+1)&7; GPIOA->ODR ^= GPIO_ODR_4; TIM1->CCMR1 = (4<DR = 0x88<<8; while (SPI1->SR & SPI_SR_BSY); const uint32_t period_base = 4; /* 1us */ const uint32_t period = period_base<BDTR = TIM_BDTR_MOE | (16<BDTR = TIM_BDTR_MOE | (0<CCR3 = period-1; TIM1->CNT = period-1; TIM1->ARR = period; TIM1->CCMR1 = (6<EGR |= TIM_EGR_UG; TIM1->ARR = 2; TIM1->CR1 |= TIM_CR1_CEN; TIM1->SR &= ~TIM_SR_UIF_Msk; } void NMI_Handler(void) { } void HardFault_Handler(void) { for(;;); } void SVC_Handler(void) { } void PendSV_Handler(void) { } void SysTick_Handler(void) { }