From d5fd0d101240152d14ac3a8c27dbebbc1ce471e4 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 19 Feb 2018 22:04:59 +0000 Subject: spi-master: update to run on the hw1 host board "TRIGGER" is now D0 on the fx2 port "LED" is now D1 on the fx2 port, "SPI MOSI" is now D4 on the fx2 "SPI MISO" is now D5 "SPI CLOCK" is now D6 --- tests/spi-master/main-stm32l1-generic.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'tests/spi-master') diff --git a/tests/spi-master/main-stm32l1-generic.c b/tests/spi-master/main-stm32l1-generic.c index 1763995..38d3525 100644 --- a/tests/spi-master/main-stm32l1-generic.c +++ b/tests/spi-master/main-stm32l1-generic.c @@ -13,10 +13,9 @@ #include "trace.h" #include "hw.h" -//#include "i2c-master.h" #define LED_DISCO_GREEN_PORT GPIOB -#define LED_DISCO_GREEN_PIN GPIO7 +#define LED_DISCO_GREEN_PIN GPIO8 struct hw_detail hw_details = { @@ -28,7 +27,7 @@ struct hw_detail hw_details = { .port_rcc = RCC_GPIOB, .trigger_rcc = RCC_GPIOB, .trigger_port = GPIOB, - .trigger_pin = GPIO11, + .trigger_pin = GPIO9, }; @@ -84,8 +83,21 @@ static void setup(void) int main(void) { + const struct rcc_clock_scale myclock = { + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, + .pll_mul = RCC_CFGR_PLLMUL_MUL4, + .pll_div = RCC_CFGR_PLLDIV_DIV2, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .voltage_scale = PWR_SCALE1, + .flash_waitstates = 1, + .ahb_frequency = 32e6, + .apb1_frequency = 32e6, + .apb2_frequency = 32e6, + }; int i, j; - rcc_clock_setup_pll(&rcc_clock_config[RCC_CLOCK_VRANGE1_HSI_PLL_32MHZ]); + rcc_clock_setup_pll(&myclock); /* green led for ticking */ rcc_periph_clock_enable(RCC_GPIOB); gpio_mode_setup(LED_DISCO_GREEN_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, -- cgit