From bf19c278a6a74a18e00cd576852817400cd6fed9 Mon Sep 17 00:00:00 2001 From: jaseg Date: Sun, 24 Sep 2017 23:16:49 +0200 Subject: Working rainbow code --- olsndot/firmware/Makefile | 9 +- olsndot/firmware/main.c | 250 +++++++++++++++++++++------------------------- 2 files changed, 122 insertions(+), 137 deletions(-) (limited to 'olsndot/firmware') diff --git a/olsndot/firmware/Makefile b/olsndot/firmware/Makefile index cf338eb..625865d 100644 --- a/olsndot/firmware/Makefile +++ b/olsndot/firmware/Makefile @@ -10,13 +10,13 @@ SIZE := arm-none-eabi-size CFLAGS = -Wall -g -std=gnu11 -Os CFLAGS += -mlittle-endian -mcpu=cortex-m0 -march=armv6-m -mthumb -CFLAGS += -ffunction-sections -fdata-sections -CFLAGS += -Wl,--gc-sections -Wl,-Map=main.map +CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections +CFLAGS += -Wl,-Map=main.map # Technically we're using an STM32F030F4, but apart from the TSSOP20 package that one is largely identical to the # STM32F030*6 and there is no separate device header provided for it, so we're faking a *6 device here. This is # even documented in stm32f0xx.h. Thanks ST! -CFLAGS += -DSTM32F030x6 +CFLAGS += -DSTM32F030x6 -DHSE_VALUE=16000000 CFLAGS += -Tstm32_flash.ld CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig @@ -28,6 +28,9 @@ CFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math all: main.elf +cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/core_cm0.h + python3 gen_cmsis_exports.py $^ > $@ + main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c $(HAL_PATH)/Src/stm32f0xx_ll_utils.c $(CC) $(CFLAGS) -o $@ $^ $(OBJCOPY) -O ihex $@ $(@:.elf=.hex) diff --git a/olsndot/firmware/main.c b/olsndot/firmware/main.c index e4b3935..1b3e054 100644 --- a/olsndot/firmware/main.c +++ b/olsndot/firmware/main.c @@ -3,26 +3,72 @@ #include #include #include +#include /* * Part number: STM32F030F4C6 */ #define NBITS 12 void do_transpose(void); -uint32_t brightness[8]; -volatile uint8_t brightness_by_bit[NBITS]; +uint32_t brightness[32]; +volatile uint32_t brightness_by_bit[NBITS]; + +void hsv_set(int idx, int hue, int white) { + int i = hue>>NBITS; + int j = hue & (~(-1<CR |= RCC_CR_HSEON; while (!(RCC->CR&RCC_CR_HSERDY)); - RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk; - RCC->CFGR |= (2<CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk; + RCC->CFGR |= (2< 50.0MHz */ + RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_Msk; + RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2; /* prediv :2 -> 12.5MHz */ RCC->CR |= RCC_CR_PLLON; while (!(RCC->CR&RCC_CR_PLLRDY)); RCC->CFGR |= (2<AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN; RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_ADCEN; @@ -32,26 +78,26 @@ int main(void) { | (1<MODER |= - (1<OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_4; /* LED outputs -> open drain */ + GPIOA->OTYPER |= GPIO_OTYPER_OT_6; /* LED outputs -> open drain */ /* Set shift register IO GPIO output speed */ GPIOA->OSPEEDR |= - (3<OSPEEDR |= + (3<AFR[0] |= (1<AFR[1] |= - (2<AFR[0] |= + (2<BSRR = GPIO_BSRR_BR_1; /* clear output is active low */ - /* Configure SPI controller */ /* CPOL=0, CPHA=0, prescaler=8 -> 1MBd */ -// SPI1->CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (2<CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (0<CR2 = (7<CR2 = (0xf<CR1 = TIM_CR1_OPM | TIM_CR1_URS; -// TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_URS; - TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_OPM; // | TIM_CR1_URS; - TIM1->CR2 = 0; //TIM_CR2_CCPC; - TIM1->SMCR = 0; - TIM1->DIER = 0; + TIM1->CR1 = TIM_CR1_ARPE; // | TIM_CR1_OPM; // | TIM_CR1_URS; TIM1->PSC = 1; // debug /* CH2 - clear/!MR, CH3 - strobe/STCP */ - TIM1->CCR2 = 1; - TIM1->RCR = 0; - TIM1->CCMR1 = (6<CCMR2 = (6<CCER |= TIM_CCER_CC2E | TIM_CCER_CC2NE | TIM_CCER_CC2P | TIM_CCER_CC3E; -// TIM1->CCMR1 = (6<CCMR2 = (6<CCER = TIM_CCER_CC2E | TIM_CCER_CC3E; -// TIM1->BDTR = TIM_BDTR_MOE; + TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE | TIM_CCER_CC3P | TIM_CCER_CC3NP; + TIM1->BDTR = TIM_BDTR_MOE | (8<DIER = TIM_DIER_UIE; + TIM1->ARR = 1; + TIM1->CR1 |= TIM_CR1_CEN; NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 2); @@ -98,88 +133,35 @@ int main(void) { TIM1->EGR |= TIM_EGR_UG; while (42) { - /* - for (uint8_t i=0; i<8; i++) { - brightness[1] = brightness[5] = i; - brightness[2] = brightness[6] = 0; - brightness[3] = brightness[7] = 0; - do_transpose(); - LL_mDelay(500); - } - for (uint8_t i=0; i<8; i++) { - brightness[1] = brightness[5] = 0; - brightness[2] = brightness[6] = i; - brightness[3] = brightness[7] = 0; - do_transpose(); - LL_mDelay(500); - } - for (uint8_t i=0; i<8; i++) { - brightness[1] = brightness[5] = 0; - brightness[2] = brightness[6] = 0; - brightness[3] = brightness[7] = i; - do_transpose(); - LL_mDelay(500); - } - for (uint8_t i=0; i<8; i++) { - brightness[1] = brightness[5] = i; - brightness[2] = brightness[6] = i; - brightness[3] = brightness[7] = i; +#define HUE_MAX ((1<ODR ^= GPIO_ODR_6; + /* generate hsv fade */ + for (int ch=0; ch<8; ch++) { + hue = HUE_MAX * (HUE_OFFX + HUE_AMPLITUDE*sinf(v + ch*CHANNEL_SPACING)); + hue %= HUE_MAX; + hsv_set(ch, hue, WHITE*(1<ODR ^= GPIO_ODR_6; - switch (i) { - case 0: - brightness[1] = brightness[5] = (1<= NBITS) idx = 0; - GPIOA->ODR ^= GPIO_ODR_4; - TIM1->CCMR1 = (4<ODR ^= GPIO_ODR_6; /* LED1 */ - SPI1->DR = brightness_by_bit[idx]<<8; + /* Shift out the current period's data. The shift register clear and strobe lines are handled by the timers + * capture/compare channel 3 complementary outputs. The dead-time generator is used to sequence the clear and strobe + * edges one after another. Since there may be small variations in IRQ service latency it is critical to allow for + * some leeway between the end of this data transmission and strobe and clear. */ + SPI1->DR = (val&0xffff); + while (SPI1->SR & SPI_SR_BSY); + SPI1->DR = (val>>16); while (SPI1->SR & SPI_SR_BSY); - const uint32_t period_base = 4; /* 1us */ - const uint32_t period = period_base<BDTR = TIM_BDTR_MOE | (16<BDTR = TIM_BDTR_MOE | (0<CCR3 = period-1; - TIM1->CNT = period-1; - TIM1->ARR = period; - TIM1->CCMR1 = (6<EGR |= TIM_EGR_UG; - TIM1->ARR = 2; - TIM1->CR1 |= TIM_CR1_CEN; + /* Set up everything for the *next* period. The timer is set to count from 0 to ARR. ARR and CCR3 are pre-loaded, so + * the values written above will only be latched on timer overrun at the end of this period. This is a little + * complicated, but doing it this way has the advantage of keeping both duty cycle and frame rate precisely + * constant. */ + const int period_base = 4; /* 1us */ + const int period = (period_base<ARR = period + timer_cycles_for_spi_transmissions; + TIM1->CCR3 = timer_cycles_for_spi_transmissions; TIM1->SR &= ~TIM_SR_UIF_Msk; } @@ -245,3 +221,9 @@ void PendSV_Handler(void) { void SysTick_Handler(void) { } +/* FIXME */ +void _exit(void) {} +void *__bss_start__; +void *__bss_end__; + +int __errno; -- cgit