From 87c874251fe629b296ead673bb0c09db366dabce Mon Sep 17 00:00:00 2001 From: ↑←↑↓→↓→←↑ Date: Mon, 21 Nov 2016 11:53:33 +0100 Subject: layouting along --- .../led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 olsndot/PCB_Project/Project Logs for olsndot/led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG (limited to 'olsndot/PCB_Project/Project Logs for olsndot/led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG') diff --git a/olsndot/PCB_Project/Project Logs for olsndot/led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG b/olsndot/PCB_Project/Project Logs for olsndot/led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG new file mode 100644 index 0000000..e9ebda0 --- /dev/null +++ b/olsndot/PCB_Project/Project Logs for olsndot/led_drv PCB ECO 11-20-2016 6-36-02 PM.LOG @@ -0,0 +1,4 @@ +Added Component: Designator=R4(6-0805_M) +Added Pin To Net: NetName=VCC Pin=R4-1 +Added Pin To Net: NetName=AVCC Pin=R4-2 +Added Member To Class: ClassName=main Member=Component R4 100 -- cgit