Age | Commit message (Collapse) | Author | Files | Lines |
|
joy. Fixed now against nucleo64 manuals.
|
|
|
|
|
|
|
|
More to go, nno need for the silk and dead shapes, we just needed the
pin spacings
|
|
Fixed boot0 to be tied down, will be programmed via swd.
Added test points for spare pins where easy
Fixed some footprints to make the 3d view pretty.
|
|
|
|
"finish" routing, ignore DRC violations from disconnected usb shield on
pin 6.
Add boot0 jumper pad "just in case" but really kinda dumb, we've got a
debug header on it. Why bother with this?
Change paper size in schema to get more space.
TODO: add silk?
TODO: replace "arduino" shape with just the pinpoints.
|
|
wtf kicad, why aren't my grounds connected?!
|
|
probably need a crystal for usb :)
still needs footrints, will probably be any old 3225 part.
|
|
Spun the host, laid most signal tracks.
todo: vcc, ground pour, then shuffle all LA connectors for ease of
routing.
|
|
|
|
|
|
|
|
|
|
|
|
have I committed enough files for others to even open this?
|
|
Not sure which kicad files are necessary and which are local yet!
Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st
board, giving access to test:
* DAC->ADC (both directions)
* I2C (both directions)
* SPI (both directions)
* Uart (both directions)
a socket for a cheap fx2 based logic analyser will be included, so that
sigrok can be used to capture tests of the actual line states.
|