Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2018-02-20 | hw1: notes from assembling first board. | Karl Palsson | 1 | -7/+14 | |
2018-02-19 | hw1: gitignore gerbers | Karl Palsson | 1 | -0/+12 | |
2018-02-19 | hw1: notes on signal integrity | Karl Palsson | 1 | -0/+41 | |
2018-02-19 | hw1: update to current | Karl Palsson | 6 | -1050/+637 | |
Not really sure, did I forget to checkin after shipping out? Something got updated after a dot update of kicad? revision control of pcbs and schematics still sucks hard. | |||||
2018-02-02 | hw1: add exampe part number for fx2la part number | Karl Palsson | 1 | -0/+1 | |
2017-12-31 | hw1: use explicit 10103594-0001LF part | Karl Palsson | 3 | -439/+447 | |
better fit | |||||
2017-12-29 | hw1: commit with filled pours | Karl Palsson | 1 | -6/+768 | |
2017-12-29 | hw1: termination wat | Karl Palsson | 1 | -766/+7 | |
2017-12-29 | hw1: discover reversed numbering on arduino connectors | Karl Palsson | 3 | -125/+925 | |
joy. Fixed now against nucleo64 manuals. | |||||
2017-12-29 | hw1: more silk cleanup | Karl Palsson | 3 | -192/+197 | |
2017-12-28 | hw1: cleanup silk and start adding labels | Karl Palsson | 1 | -43/+79 | |
2017-12-27 | hw1: shrinking after dropping arduino stuff | Karl Palsson | 1 | -774/+68 | |
2017-12-27 | hw1: drop arduinno style holes and board shape | Karl Palsson | 3 | -987/+994 | |
More to go, nno need for the silk and dead shapes, we just needed the pin spacings | |||||
2017-12-27 | hw1: test points, cleanup 3d view | Karl Palsson | 4 | -212/+376 | |
Fixed boot0 to be tied down, will be programmed via swd. Added test points for spare pins where easy Fixed some footprints to make the 3d view pretty. | |||||
2017-12-17 | new pdf for current schematic | Karl Palsson | 1 | -0/+0 | |
2017-12-17 | "fix" grounds by tracks into pour | Karl Palsson | 3 | -1155/+1380 | |
"finish" routing, ignore DRC violations from disconnected usb shield on pin 6. Add boot0 jumper pad "just in case" but really kinda dumb, we've got a debug header on it. Why bother with this? Change paper size in schema to get more space. TODO: add silk? TODO: replace "arduino" shape with just the pinpoints. | |||||
2017-12-11 | hw1: continued, just intermediate progress save | Karl Palsson | 3 | -282/+1284 | |
wtf kicad, why aren't my grounds connected?! | |||||
2017-11-20 | hw1: add crystal, more commentary | Karl Palsson | 3 | -172/+247 | |
probably need a crystal for usb :) still needs footrints, will probably be any old 3225 part. | |||||
2017-11-19 | hw1: begin routing. | Karl Palsson | 3 | -255/+338 | |
Spun the host, laid most signal tracks. todo: vcc, ground pour, then shuffle all LA connectors for ease of routing. | |||||
2017-11-17 | hw1: apparently _actually_ save the file | Karl Palsson | 1 | -50/+14 | |
2017-11-17 | hw1: add in/out caps to 3v3 | Karl Palsson | 4 | -150/+296 | |
2017-11-17 | git ignore more backups | Karl Palsson | 1 | -0/+2 | |
2017-11-17 | add "klibs" with new regulator | Karl Palsson | 2 | -0/+33 | |
2017-11-17 | gitignore kicad .bak files | Karl Palsson | 1 | -0/+1 | |
2017-11-17 | hw1: schematic "finished" ? | Karl Palsson | 7 | -1223/+1587 | |
have I committed enough files for others to even open this? | |||||
2017-10-07 | WIP: hardware test partner round 1 | Karl Palsson | 23 | -0/+45578 | |
Not sure which kicad files are necessary and which are local yet! Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st board, giving access to test: * DAC->ADC (both directions) * I2C (both directions) * SPI (both directions) * Uart (both directions) a socket for a cheap fx2 based logic analyser will be included, so that sigrok can be used to capture tests of the actual line states. |