olsndot.git - olsndot: 32-channel high fidelity 12V LED tape driver with RS485 control

Age	Commit message (Collapse)	Author	Files	Lines
2017-12-31	hw1: use explicit 10103594-0001LF part	Karl Palsson	1	-6/+6
	better fit
2017-12-29	hw1: discover reversed numbering on arduino connectors	Karl Palsson	1	-68/+68
	joy. Fixed now against nucleo64 manuals.
2017-12-29	hw1: more silk cleanup	Karl Palsson	1	-33/+33

2017-12-27	hw1: drop arduinno style holes and board shape	Karl Palsson	1	-179/+135
	More to go, nno need for the silk and dead shapes, we just needed the pin spacings
2017-12-27	hw1: test points, cleanup 3d view	Karl Palsson	1	-180/+235
	Fixed boot0 to be tied down, will be programmed via swd. Added test points for spare pins where easy Fixed some footprints to make the 3d view pretty.
2017-12-17	"fix" grounds by tracks into pour	Karl Palsson	1	-157/+204
	"finish" routing, ignore DRC violations from disconnected usb shield on pin 6. Add boot0 jumper pad "just in case" but really kinda dumb, we've got a debug header on it. Why bother with this? Change paper size in schema to get more space. TODO: add silk? TODO: replace "arduino" shape with just the pinpoints.
2017-12-11	hw1: continued, just intermediate progress save	Karl Palsson	1	-155/+195
	wtf kicad, why aren't my grounds connected?!
2017-11-19	hw1: begin routing.	Karl Palsson	1	-108/+107
	Spun the host, laid most signal tracks. todo: vcc, ground pour, then shuffle all LA connectors for ease of routing.
2017-11-17	hw1: add in/out caps to 3v3	Karl Palsson	1	-122/+138

2017-11-17	hw1: schematic "finished" ?	Karl Palsson	1	-213/+307
	have I committed enough files for others to even open this?
2017-10-07	WIP: hardware test partner round 1	Karl Palsson	1	-0/+480
	Not sure which kicad files are necessary and which are local yet! Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st board, giving access to test: * DAC->ADC (both directions) * I2C (both directions) * SPI (both directions) * Uart (both directions) a socket for a cheap fx2 based logic analyser will be included, so that sigrok can be used to capture tests of the actual line states.