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2017-12-29hw1: commit with filled poursKarl Palsson1-6/+768
2017-12-29hw1: termination watKarl Palsson1-766/+7
2017-12-29hw1: discover reversed numbering on arduino connectorsKarl Palsson1-54/+854
joy. Fixed now against nucleo64 manuals.
2017-12-29hw1: more silk cleanupKarl Palsson1-141/+144
2017-12-28hw1: cleanup silk and start adding labelsKarl Palsson1-43/+79
2017-12-27hw1: shrinking after dropping arduino stuffKarl Palsson1-774/+68
2017-12-27hw1: drop arduinno style holes and board shapeKarl Palsson1-752/+856
More to go, nno need for the silk and dead shapes, we just needed the pin spacings
2017-12-17"fix" grounds by tracks into pourKarl Palsson1-399/+557
"finish" routing, ignore DRC violations from disconnected usb shield on pin 6. Add boot0 jumper pad "just in case" but really kinda dumb, we've got a debug header on it. Why bother with this? Change paper size in schema to get more space. TODO: add silk? TODO: replace "arduino" shape with just the pinpoints.
2017-12-11hw1: continued, just intermediate progress saveKarl Palsson1-101/+1063
wtf kicad, why aren't my grounds connected?!
2017-11-20hw1: add crystal, more commentaryKarl Palsson1-2/+6
probably need a crystal for usb :) still needs footrints, will probably be any old 3225 part.
2017-11-19hw1: begin routing.Karl Palsson1-139/+222
Spun the host, laid most signal tracks. todo: vcc, ground pour, then shuffle all LA connectors for ease of routing.
2017-11-17hw1: add in/out caps to 3v3Karl Palsson1-3/+75
2017-11-17hw1: schematic "finished" ?Karl Palsson1-122/+838
have I committed enough files for others to even open this?
2017-10-07WIP: hardware test partner round 1Karl Palsson1-0/+447
Not sure which kicad files are necessary and which are local yet! Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st board, giving access to test: * DAC->ADC (both directions) * I2C (both directions) * SPI (both directions) * Uart (both directions) a socket for a cheap fx2 based logic analyser will be included, so that sigrok can be used to capture tests of the actual line states.