Age | Commit message (Collapse) | Author | Files | Lines | |
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2017-11-17 | hw1: add in/out caps to 3v3 | Karl Palsson | 1 | -3/+75 | |
2017-11-17 | hw1: schematic "finished" ? | Karl Palsson | 1 | -122/+838 | |
have I committed enough files for others to even open this? | |||||
2017-10-07 | WIP: hardware test partner round 1 | Karl Palsson | 1 | -0/+447 | |
Not sure which kicad files are necessary and which are local yet! Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st board, giving access to test: * DAC->ADC (both directions) * I2C (both directions) * SPI (both directions) * Uart (both directions) a socket for a cheap fx2 based logic analyser will be included, so that sigrok can be used to capture tests of the actual line states. |