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2018-02-22lib: update to my hacking/stagingKarl Palsson1-0/+0
2018-02-22uart-basic: initial hacks for dut board.Karl Palsson2-0/+104
but oh joy, solder bridges are wrong for serial to hw1 host by defualt :(
2018-02-22oocd: more hacking on local config cruftKarl Palsson1-5/+7
2018-02-21adc-power: stm32l1: make "generic" == hw1 test board.Karl Palsson2-2/+2
* use the trigger pin instead of the led. * use the smaller flash of the part mounted.
2018-02-20hw1: notes from assembling first board.Karl Palsson1-7/+14
2018-02-19spi-master: update to run on the hw1 host boardKarl Palsson1-4/+16
"TRIGGER" is now D0 on the fx2 port "LED" is now D1 on the fx2 port, "SPI MOSI" is now D4 on the fx2 "SPI MISO" is now D5 "SPI CLOCK" is now D6
2018-02-19hw1: gitignore gerbersKarl Palsson1-0/+12
2018-02-19hw1: notes on signal integrityKarl Palsson1-0/+41
2018-02-19hw1: update to currentKarl Palsson6-1050/+637
Not really sure, did I forget to checkin after shipping out? Something got updated after a dot update of kicad? revision control of pcbs and schematics still sucks hard.
2018-02-02hw1: add exampe part number for fx2la part numberKarl Palsson1-0/+1
2017-12-31hw1: use explicit 10103594-0001LF partKarl Palsson3-439/+447
better fit
2017-12-29hw1: commit with filled poursKarl Palsson1-6/+768
2017-12-29hw1: termination watKarl Palsson1-766/+7
2017-12-29hw1: discover reversed numbering on arduino connectorsKarl Palsson3-125/+925
joy. Fixed now against nucleo64 manuals.
2017-12-29hw1: more silk cleanupKarl Palsson3-192/+197
2017-12-28hw1: cleanup silk and start adding labelsKarl Palsson1-43/+79
2017-12-27hw1: shrinking after dropping arduino stuffKarl Palsson1-774/+68
2017-12-27hw1: drop arduinno style holes and board shapeKarl Palsson3-987/+994
More to go, nno need for the silk and dead shapes, we just needed the pin spacings
2017-12-27hw1: test points, cleanup 3d viewKarl Palsson4-212/+376
Fixed boot0 to be tied down, will be programmed via swd. Added test points for spare pins where easy Fixed some footprints to make the 3d view pretty.
2017-12-17new pdf for current schematicKarl Palsson1-0/+0
2017-12-17"fix" grounds by tracks into pourKarl Palsson3-1155/+1380
"finish" routing, ignore DRC violations from disconnected usb shield on pin 6. Add boot0 jumper pad "just in case" but really kinda dumb, we've got a debug header on it. Why bother with this? Change paper size in schema to get more space. TODO: add silk? TODO: replace "arduino" shape with just the pinpoints.
2017-12-11hw1: continued, just intermediate progress saveKarl Palsson3-282/+1284
wtf kicad, why aren't my grounds connected?!
2017-11-20hw1: add crystal, more commentaryKarl Palsson3-172/+247
probably need a crystal for usb :) still needs footrints, will probably be any old 3225 part.
2017-11-19hw1: begin routing.Karl Palsson3-255/+338
Spun the host, laid most signal tracks. todo: vcc, ground pour, then shuffle all LA connectors for ease of routing.
2017-11-17hw1: apparently _actually_ save the fileKarl Palsson1-50/+14
2017-11-17hw1: add in/out caps to 3v3Karl Palsson4-150/+296
2017-11-17git ignore more backupsKarl Palsson1-0/+2
2017-11-17add "klibs" with new regulatorKarl Palsson2-0/+33
2017-11-17gitignore kicad .bak filesKarl Palsson1-0/+1
2017-11-17hw1: schematic "finished" ?Karl Palsson7-1223/+1587
have I committed enough files for others to even open this?
2017-10-26common openocd: use -s to find files from test dirs.Karl Palsson5-4/+18
The sourcing of the common.cfg and the optional local files was failing when invoked from a test directory. Use -s and properly use [find ...] to search paths nicely.
2017-10-26uart-basic: l0: speedup and drop dead codeKarl Palsson1-14/+2
Don't need the HSI48 clocks, that was from a usb demo
2017-10-25uart-basic: add l4Karl Palsson2-0/+103
2017-10-25uart-basic: add functional l0 test code too.Karl Palsson2-0/+116
Really need to get the rcc helpers built up and upstream!
2017-10-24uart-basic: add f0, requires newest code tooKarl Palsson3-1/+91
stupid f072 disco doesn't have usart2 available
2017-10-24basic uart: f4 and f3, prepping tests for usart-v2Karl Palsson6-0/+372
use parity to at least test a little more of the common code
2017-10-07WIP: hardware test partner round 1Karl Palsson23-0/+45578
Not sure which kicad files are necessary and which are local yet! Goal: fixed "host" board (this board) with socket for _any_ Nucleo64 st board, giving access to test: * DAC->ADC (both directions) * I2C (both directions) * SPI (both directions) * Uart (both directions) a socket for a cheap fx2 based logic analyser will be included, so that sigrok can be used to capture tests of the actual line states.
2017-10-05Fix-up repository structurejaseg106-2243/+3
2017-10-05Add .gitignorejaseg1-0/+13
2017-10-05Add source-in-firmware trickjaseg2-1/+15
2017-10-05Add more comments, add LICENSEjaseg2-147/+901
2017-09-26Serial protocol workingjaseg2-8/+144
2017-09-24Merge branch 'master' of github.com:jaseg/led_drvjaseg37-9712/+8194
2017-09-24fw: Add missing filesjaseg3-0/+313
2017-09-24Working rainbow codejaseg3-137/+122
2017-09-01awd-timer-dma: initial commit.Karl Palsson5-0/+293
Had to figure out a few screwups before I got the AWD working properly.
2017-09-01spi-master: trivial: names to match sigrok defaultKarl Palsson1-1/+1
2017-09-01lib: update to my staging 2017.4Karl Palsson1-0/+0
2017-05-30hw: Add BOMjaseg1-0/+0
2017-05-30fw: Basic dimming workingjaseg1-10/+101
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