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AgeCommit message (Expand)AuthorFilesLines
2018-07-17Isolate usb-serial-rs485 treejaseg121-51129/+165
2018-04-17spi-master: functional spi slave on l1 hostKarl Palsson3-29/+29
2018-04-16spi-master-l0: wip:Karl Palsson3-0/+175
2018-04-16adc-power: correctly allow parallel makeKarl Palsson1-2/+2
2018-02-25i2c-master: add parallel make and fix errorsKarl Palsson2-1/+16
2018-02-25adc-power: add parallel parent makefileKarl Palsson4-2/+19
2018-02-25adc-power: drop unused l053 makefile stubKarl Palsson1-43/+0
2018-02-22lib: update to my hacking/stagingKarl Palsson1-0/+0
2018-02-22uart-basic: initial hacks for dut board.Karl Palsson2-0/+104
2018-02-22oocd: more hacking on local config cruftKarl Palsson1-5/+7
2018-02-21adc-power: stm32l1: make "generic" == hw1 test board.Karl Palsson2-2/+2
2018-02-20hw1: notes from assembling first board.Karl Palsson1-7/+14
2018-02-19spi-master: update to run on the hw1 host boardKarl Palsson1-4/+16
2018-02-19hw1: gitignore gerbersKarl Palsson1-0/+12
2018-02-19hw1: notes on signal integrityKarl Palsson1-0/+41
2018-02-19hw1: update to currentKarl Palsson6-1050/+637
2018-02-02hw1: add exampe part number for fx2la part numberKarl Palsson1-0/+1
2017-12-31hw1: use explicit 10103594-0001LF partKarl Palsson3-439/+447
2017-12-29hw1: commit with filled poursKarl Palsson1-6/+768
2017-12-29hw1: termination watKarl Palsson1-766/+7
2017-12-29hw1: discover reversed numbering on arduino connectorsKarl Palsson3-125/+925
2017-12-29hw1: more silk cleanupKarl Palsson3-192/+197
2017-12-28hw1: cleanup silk and start adding labelsKarl Palsson1-43/+79
2017-12-27hw1: shrinking after dropping arduino stuffKarl Palsson1-774/+68
2017-12-27hw1: drop arduinno style holes and board shapeKarl Palsson3-987/+994
2017-12-27hw1: test points, cleanup 3d viewKarl Palsson4-212/+376
2017-12-17new pdf for current schematicKarl Palsson1-0/+0
2017-12-17"fix" grounds by tracks into pourKarl Palsson3-1155/+1380
2017-12-11hw1: continued, just intermediate progress saveKarl Palsson3-282/+1284
2017-11-20hw1: add crystal, more commentaryKarl Palsson3-172/+247
2017-11-19hw1: begin routing.Karl Palsson3-255/+338
2017-11-17hw1: apparently _actually_ save the fileKarl Palsson1-50/+14
2017-11-17hw1: add in/out caps to 3v3Karl Palsson4-150/+296
2017-11-17git ignore more backupsKarl Palsson1-0/+2
2017-11-17add "klibs" with new regulatorKarl Palsson2-0/+33
2017-11-17gitignore kicad .bak filesKarl Palsson1-0/+1
2017-11-17hw1: schematic "finished" ?Karl Palsson7-1223/+1587
2017-10-26common openocd: use -s to find files from test dirs.Karl Palsson5-4/+18
2017-10-26uart-basic: l0: speedup and drop dead codeKarl Palsson1-14/+2
2017-10-25uart-basic: add l4Karl Palsson2-0/+103
2017-10-25uart-basic: add functional l0 test code too.Karl Palsson2-0/+116
2017-10-24uart-basic: add f0, requires newest code tooKarl Palsson3-1/+91
2017-10-24basic uart: f4 and f3, prepping tests for usart-v2Karl Palsson6-0/+372
2017-10-07WIP: hardware test partner round 1Karl Palsson23-0/+45578
2017-09-01awd-timer-dma: initial commit.Karl Palsson5-0/+293
2017-09-01spi-master: trivial: names to match sigrok defaultKarl Palsson1-1/+1
2017-09-01lib: update to my staging 2017.4Karl Palsson1-0/+0
2017-04-24lib: update to my staging 2017.4Karl Palsson1-0/+0
2017-04-05i2c: fix uart notes for f0Karl Palsson1-3/+3
2017-04-05openocd: fix gross tcl syntaxKarl Palsson1-1/+1
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