diff options
Diffstat (limited to 'olsndot/firmware')
| -rw-r--r-- | olsndot/firmware/.gitignore | 13 | ||||
| -rw-r--r-- | olsndot/firmware/LICENSE | 661 | ||||
| -rw-r--r-- | olsndot/firmware/Makefile | 58 | ||||
| -rw-r--r-- | olsndot/firmware/gen_cmsis_exports.py | 30 | ||||
| -rw-r--r-- | olsndot/firmware/main.c | 458 | ||||
| -rw-r--r-- | olsndot/firmware/openocd.cfg | 10 | ||||
| -rw-r--r-- | olsndot/firmware/startup_stm32f030x6.s | 273 | ||||
| -rw-r--r-- | olsndot/firmware/stm32_flash.ld | 127 | ||||
| -rw-r--r-- | olsndot/firmware/system_stm32f0xx.c | 336 |
9 files changed, 0 insertions, 1966 deletions
diff --git a/olsndot/firmware/.gitignore b/olsndot/firmware/.gitignore deleted file mode 100644 index b33e1ea..0000000 --- a/olsndot/firmware/.gitignore +++ /dev/null @@ -1,13 +0,0 @@ -*.elf -*.o -*.map -*.lst -*.hex -*.bin - -cmsis_exports.c -sources.c -sources.tar.xz -sources.tar.xz.zip - -STM32Cube diff --git a/olsndot/firmware/LICENSE b/olsndot/firmware/LICENSE deleted file mode 100644 index be3f7b2..0000000 --- a/olsndot/firmware/LICENSE +++ /dev/null @@ -1,661 +0,0 @@ - GNU AFFERO GENERAL PUBLIC LICENSE - Version 3, 19 November 2007 - - Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/> - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The GNU Affero General Public License is a free, copyleft license for -software and other kinds of works, specifically designed to ensure -cooperation with the community in the case of network server software. - - The licenses for most software and other practical works are designed -to take away your freedom to share and change the works. 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It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - <one line to give the program's name and a brief idea of what it does.> - Copyright (C) <year> <name of author> - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU Affero General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU Affero General Public License for more details. - - You should have received a copy of the GNU Affero General Public License - along with this program. If not, see <https://www.gnu.org/licenses/>. - -Also add information on how to contact you by electronic and paper mail. - - If your software can interact with users remotely through a computer -network, you should also make sure that it provides a way for users to -get its source. For example, if your program is a web application, its -interface could display a "Source" link that leads users to an archive -of the code. There are many ways you could offer source, and different -solutions will be better for different programs; see section 13 for the -specific requirements. - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU AGPL, see -<https://www.gnu.org/licenses/>. diff --git a/olsndot/firmware/Makefile b/olsndot/firmware/Makefile deleted file mode 100644 index ce1d221..0000000 --- a/olsndot/firmware/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# put your *.o targets here, make should handle the rest! -CMSIS_PATH ?= STM32Cube/Drivers/CMSIS -CMSIS_DEV_PATH ?= $(CMSIS_PATH)/Device/ST/STM32F0xx -HAL_PATH ?= STM32Cube/Drivers/STM32F0xx_HAL_Driver - -CC := arm-none-eabi-gcc -OBJCOPY := arm-none-eabi-objcopy -OBJDUMP := arm-none-eabi-objdump -SIZE := arm-none-eabi-size - -CFLAGS = -Wall -g -std=gnu11 -Os -CFLAGS += -mlittle-endian -mcpu=cortex-m0 -march=armv6-m -mthumb -#CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections -CFLAGS += -Wl,-Map=main.map - -# Technically we're using an STM32F030F4, but apart from the TSSOP20 package that one is largely identical to the -# STM32F030*6 and there is no separate device header provided for it, so we're faking a *6 device here. This is -# even documented in stm32f0xx.h. Thanks ST! -CFLAGS += -DSTM32F030x6 -DHSE_VALUE=16000000 - -CFLAGS += -Tstm32_flash.ld -CFLAGS += -I$(CMSIS_DEV_PATH)/Include -I$(CMSIS_PATH)/Include -I$(HAL_PATH)/Inc -Iconfig -CFLAGS += -L$(CMSIS_PATH)/Lib/GCC -larm_cortexM0l_math - -################################################### - -.PHONY: program clean - -all: main.elf - -cmsis_exports.c: $(CMSIS_DEV_PATH)/Include/stm32f030x6.h $(CMSIS_PATH)/Include/core_cm0.h - python3 gen_cmsis_exports.py $^ > $@ - -sources.tar.xz: main.c Makefile - tar -caf $@ $^ - -# don't ask... -sources.tar.xz.zip: sources.tar.xz - zip $@ $^ - -sources.c: sources.tar.xz.zip - xxd -i $< | head -n -1 | sed 's/=/__attribute__((section(".source_tarball"))) =/' > $@ - -main.elf: main.c startup_stm32f030x6.s system_stm32f0xx.c $(HAL_PATH)/Src/stm32f0xx_ll_utils.c cmsis_exports.c sources.o - $(CC) $(CFLAGS) -o $@ $^ - $(OBJCOPY) -O ihex $@ $(@:.elf=.hex) - $(OBJCOPY) -O binary $@ $(@:.elf=.bin) - $(OBJDUMP) -St $@ >$(@:.elf=.lst) - $(SIZE) $@ - -program: main.elf openocd.cfg - openocd -f openocd.cfg -c "program $< verify reset exit" - -clean: - rm -f *.o - rm -f main.elf main.hex main.bin main.map main.lst - rm -f sources.tar.xz sources.tar.xz.zip - diff --git a/olsndot/firmware/gen_cmsis_exports.py b/olsndot/firmware/gen_cmsis_exports.py deleted file mode 100644 index ba3422b..0000000 --- a/olsndot/firmware/gen_cmsis_exports.py +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env python3 -import re -import os - -if __name__ == '__main__': - import argparse - - parser = argparse.ArgumentParser() - parser.add_argument('cmsis_device_header', nargs='+', type=argparse.FileType('rb')) - args = parser.parse_args() - - print('#ifndef __GENERATED_CMSIS_HEADER_EXPORTS__') - print('#define __GENERATED_CMSIS_HEADER_EXPORTS__') - print() - for header in args.cmsis_device_header: - lines = header.readlines() - name = os.path.basename(header.name) - print('#include <{}>'.format(name)) - print() - - print('/* {} */'.format(name)) - for l in lines: - match = re.match(b'^#define (\w+)\s+\W*(\w+_TypeDef|\w+_Type).*$', l) - if match: - inst, typedef = match.groups() - inst, typedef = inst.decode(), typedef.decode() - print('{} *{} = {};'.format(typedef, inst.lower(), inst)) - print() - print('#endif//__GENERATED_CMSIS_HEADER_EXPORTS__') - diff --git a/olsndot/firmware/main.c b/olsndot/firmware/main.c deleted file mode 100644 index a7cbbef..0000000 --- a/olsndot/firmware/main.c +++ /dev/null @@ -1,458 +0,0 @@ -/* OpenStep 2 - * Copyright (C) 2017 Sebastian Götte <code@jaseg.net> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU Affero General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Affero General Public License for more details. - * - * You should have received a copy of the GNU Affero General Public License - * along with this program. If not, see <https://www.gnu.org/licenses/>. - */ - -/* Preliminary remarks. - * - * This code is intended to run on an ARM Cortex-M0 microcontroller made by ST, part number STM32F030F4C6 - * - * Some terminology: - * - * * The term "raw channel" refers to a single output of the 32 outputs provided by the driver board. It corresponds to - * a single color sub-channel of one RGBW output. One RGBW output consists of four raw channels. - * - * * The term "logical channel" refers to one RGBW output of four individual colors handled by a group of four raw - * channels. - */ - -#include <stm32f0xx.h> -#include <stdint.h> -#include <system_stm32f0xx.h> -#include <stm32f0xx_ll_utils.h> -#include <math.h> - -/* Bit count of this device. Note that to change this you will also have to adapt the per-bit timer period lookup table - * below. - */ -#define NBITS 14 - -/* Maximum bit count supported by serial command protocol. The brightness data is assumed to be of this bit width, but - * only the uppermost NBITS bits are used. */ -#define MAX_BITS 16 - -void do_transpose(void); - -/* Right-aligned integer raw channel brightness values like so: - * - * bit index 31 ... 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - * | (MSB) serial data put *here* (LSB) | - * |<-utterly ignored->| |<-----------------MAX_BITS------------------>| - * |<----------------NBITS---------------->| |<>|--ignored - * | (MSB) brightness data (LSB) | |<>|--ignored - */ -uint32_t brightness[32] = { 0 }; - -/* Bit-golfed modulation data generated from the above values by the main loop, ready to be sent out to the shift - * registers. - */ -volatile uint32_t brightness_by_bit[NBITS] = { 0 }; - -/* Global systick timing variables */ -uint32_t sys_time = 0; -uint32_t sys_time_seconds = 0; - -int main(void) { - /* Get all the good clocks and PLLs on this thing up and running. We're running from an external 16MHz crystal, - * which we're first dividing down by 2 to get 8MHz, then PLL'ing up by 4 to get 32MHz as our main system clock. - * - * The busses are all run directly from these 32MHz because why not. - * - * Be careful in mucking around with this code since you can kind of semi-brick the chip if you do it wrong. - */ - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR&RCC_CR_HSERDY)); - RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk; - RCC->CFGR |= (2<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x4 -> 32.0MHz */ - RCC->CFGR2 &= ~RCC_CFGR2_PREDIV_Msk; - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2; /* prediv :2 -> 8.0MHz */ - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR&RCC_CR_PLLRDY)); - RCC->CFGR |= (2<<RCC_CFGR_SW_Pos); - SystemCoreClockUpdate(); - SysTick_Config(SystemCoreClock/1000); /* 1ms interval */ - - - /* Enable all the periphery we need */ - RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN; - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN | RCC_APB2ENR_TIM1EN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_ADCEN; - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - - /* Configure all the GPIOs */ - GPIOA->MODER |= - (3<<GPIO_MODER_MODER0_Pos) /* PA0 - Current measurement analog input */ - | (1<<GPIO_MODER_MODER1_Pos) /* PA1 - RS485 TX enable */ - | (2<<GPIO_MODER_MODER2_Pos) /* PA2 - RS485 TX */ - | (2<<GPIO_MODER_MODER3_Pos) /* PA3 - RS485 RX */ - /* PA4 reserved because */ - | (2<<GPIO_MODER_MODER5_Pos) /* PA5 - Shift register clk/SCLK */ - | (1<<GPIO_MODER_MODER6_Pos) /* PA6 - LED2 open-drain output */ - | (2<<GPIO_MODER_MODER7_Pos) /* PA7 - Shift register data/MOSI */ - | (2<<GPIO_MODER_MODER9_Pos) /* FIXME PA9 - Shift register clear (TIM1_CH2) */ - | (2<<GPIO_MODER_MODER10_Pos);/* PA10 - Shift register strobe (TIM1_CH3) */ - GPIOB->MODER |= - (2<<GPIO_MODER_MODER1_Pos); /* PB1 - Shift register clear (TIM1_CH3N) */ - - - GPIOA->OTYPER |= GPIO_OTYPER_OT_6; /* LED outputs -> open drain */ - - /* Set shift register IO GPIO output speed */ - GPIOA->OSPEEDR |= - (3<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCLK */ - | (3<<GPIO_OSPEEDR_OSPEEDR6_Pos) /* LED1 */ - | (3<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */ - | (3<<GPIO_OSPEEDR_OSPEEDR10_Pos);/* Strobe */ - GPIOB->OSPEEDR |= - (3<<GPIO_OSPEEDR_OSPEEDR1_Pos); /* Clear */ - - /* Alternate function settings */ - GPIOA->AFR[0] |= - (1<<GPIO_AFRL_AFRL2_Pos) /* USART1_TX */ - | (1<<GPIO_AFRL_AFRL3_Pos) /* USART1_RX */ - | (0<<GPIO_AFRL_AFRL5_Pos) /* SPI1_SCK */ - | (0<<GPIO_AFRL_AFRL7_Pos); /* SPI1_MOSI */ - GPIOA->AFR[1] |= - (2<<GPIO_AFRH_AFRH2_Pos); /* TIM1_CH3 */ - GPIOB->AFR[0] |= - (2<<GPIO_AFRL_AFRL1_Pos); /* TIM1_CH3N */ - - /* Configure SPI controller */ - /* CPOL=0, CPHA=0, prescaler=2 -> 16MBd */ - SPI1->CR1 = SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE | SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_SPE | (0<<SPI_CR1_BR_Pos) | SPI_CR1_MSTR; - SPI1->CR2 = (0xf<<SPI_CR2_DS_Pos); - - /* Configure TIM1 for display strobe generation */ - TIM1->CR1 = TIM_CR1_ARPE; - - TIM1->PSC = 1; /* Prescale by 2, resulting in a 16MHz timer frequency and 62.5ns timer step size. */ - /* CH2 - clear/!MR, CH3 - strobe/STCP */ - TIM1->CCMR2 = (6<<TIM_CCMR2_OC3M_Pos) | TIM_CCMR2_OC3PE; - TIM1->CCER |= TIM_CCER_CC3E | TIM_CCER_CC3NE | TIM_CCER_CC3P | TIM_CCER_CC3NP; - TIM1->BDTR = TIM_BDTR_MOE | (1<<TIM_BDTR_DTG_Pos); /* really short dead time */ - TIM1->DIER = TIM_DIER_UIE; /* Enable update (overrun) interrupt */ - TIM1->ARR = 1; - TIM1->CR1 |= TIM_CR1_CEN; - - /* Configure Timer 1 update (overrun) interrupt on NVIC. - * Used only for update (overrun) for strobe timing. */ - NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); - NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn, 2); - - /* Pre-load initial values, kick of first interrupt */ - TIM1->EGR |= TIM_EGR_UG; - - /* Configure TIM3 for USART timeout handing */ - TIM3->CR1 = TIM_CR1_OPM; - TIM3->DIER = TIM_DIER_UIE; - TIM3->PSC = 31; - TIM3->ARR = 1000; - - /* Configure Timer 3 update (overrun) interrupt on NVIC. - * Used only for update (overrun) for USART timeout handling. */ - NVIC_EnableIRQ(TIM3_IRQn); - NVIC_SetPriority(TIM3_IRQn, 2); - - /* Pre-load initial values */ - TIM3->EGR |= TIM_EGR_UG; - - /* Configure UART for RS485 comm */ - /* 8N1, 1MBd */ - USART1->CR1 = /* 8-bit -> M1, M0 clear */ - /* RTOIE clear */ - (8 << USART_CR1_DEAT_Pos) /* 8 sample cycles/1 bit DE assertion time */ - | (8 << USART_CR1_DEDT_Pos) /* 8 sample cycles/1 bit DE assertion time */ - /* CMIF clear */ - /* WAKE clear */ - /* PCE, PS clear */ - | USART_CR1_RXNEIE - /* other interrupts clear */ - | USART_CR1_TE - | USART_CR1_RE; - USART1->CR3 = USART_CR3_DEM; /* RS485 DE enable (output on RTS) */ - USART1->BRR = 32; - USART1->CR1 |= USART_CR1_UE; - - /* Configure USART1 interrupt on NVIC. Used only for RX. */ - NVIC_EnableIRQ(USART1_IRQn); - NVIC_SetPriority(USART1_IRQn, 2); - - /* Idly loop around, occassionally disfiguring some integers. */ - while (42) { - /* Debug output on LED. */ - GPIOA->ODR ^= GPIO_ODR_6; - - /* Bit-mangle the integer brightness data to produce raw modulation data */ - do_transpose(); - - /* Wait a moment */ - for (int k=0; k<10000; k++) - asm volatile("nop"); - } -} - -/* Modulation data bit golfing routine */ -void do_transpose(void) { - /* For each bit value */ - for (uint32_t i=0; i<NBITS; i++) { - uint32_t mask = 1<<i<<(MAX_BITS-NBITS); /* Bit mask for this bit value. */ - uint32_t bv = 0; /* accumulator thing */ - for (uint32_t j=0; j<32; j++) { - if (brightness[j] & mask) - bv |= 1<<j; - } - brightness_by_bit[i] = bv; - } -} - -/* Bit timing base value. This is the lowes bit interval used */ -#define PERIOD_BASE 4 - -/* This value is a constant offset added to every bit period to allow for the timer IRQ handler to execute. This is set - * empirically using a debugger and a logic analyzer. */ -#define TIMER_CYCLES_FOR_SPI_TRANSMISSIONS 120 -/* This is the same as above, but for the reset cycle of the bit period. */ -#define RESET_PERIOD_LENGTH 40 - -/* Defines for brevity */ -#define A TIMER_CYCLES_FOR_SPI_TRANSMISSIONS -#define B PERIOD_BASE - -/* This is a constant offset containing some empirically determined correction values */ -#define C (1 /* reset pulse comp */ - 3 /* analog snafu comp */) - -/* This lookup table maps bit positions to timer period values. This is a lookup table to allow for the compensation for - * non-linear effects of ringing at lower bit durations. - */ -static uint16_t timer_period_lookup[NBITS] = { - /* LSB here */ - A - C + (B<< 0), - A - C + (B<< 1), - A - C + (B<< 2), - A - C + (B<< 3), - A - C + (B<< 4), - A - C + (B<< 5), - A - C + (B<< 6), - A - C + (B<< 7), - A - C + (B<< 8), - A - C + (B<< 9), - A - C + (B<<10), - A - C + (B<<11), - A - C + (B<<12), - A - C + (B<<13), - /* MSB here */ -}; - -/* Don't pollute the global namespace */ -#undef A -#undef B -#undef C - -/* Timer 1 main IRQ handler. This is used only for overflow ("update" or UP event in ST's terminology). */ -void TIM1_BRK_UP_TRG_COM_IRQHandler(void) { - /* The index of the currently active bit. On entry of this function, this is the bit index of the upcoming period. - * On exit it is the index of the *next* period. */ - static int idx = 0; - /* We modulate all outputs simultaneously in n periods, with n being the modulation depth (the number of bits). - * Each period is split into two timer cycles. First, a long one during which the data for the current period is - * shifted out and subsequently latched to the outputs. Then, a short one that is used to reset all outputs in time - * for the next period. - * - * bit value: | <-- least significant, shortest period / most significant, longest period --> | - * bit number: | b0 | b1 | ... | b10 | b11 | - * name: | data cycle | reset cycle | | | | | - * function: | shift data <strobe> wait | | ... | ... | ... | ... | - * duration: | fixed variable | fixed | | | | | - * - * Now, alternate between the two cycles in one phase. - */ - static int clear = 0; - if ((clear = !clear)) { - /* Access bits offset by one as we are setting the *next* period based on idx below. */ - uint32_t val = brightness_by_bit[idx]; - - /* Shift out the current period's data. The shift register clear and strobe lines are handled by the timers - * capture/compare channel 3 complementary outputs. The dead-time generator is used to sequence the clear and strobe - * edges one after another. Since there may be small variations in IRQ service latency it is critical to allow for - * some leeway between the end of this data transmission and strobe and clear. */ - SPI1->DR = (val&0xffff); - while (SPI1->SR & SPI_SR_BSY); - SPI1->DR = (val>>16); - while (SPI1->SR & SPI_SR_BSY); - - /* Increment the bit index for the next cycle */ - idx++; - if (idx >= NBITS) - idx = 0; - - /* Set up the following reset pulse cycle. This cycle is short as it only needs to be long enough for the below - * part of this ISR handler routine to run. */ - TIM1->ARR = RESET_PERIOD_LENGTH; - TIM1->CCR3 = 1; /* This value is fixed to produce a very short reset pulse. IOs, PCB and shift registers all can - easily handle this. */ - } else { - /* Set up everything for the data cycle of the *next* period. The timer is set to count from 0 to ARR. ARR and - * CCR3 are pre-loaded, so the values written above will only be latched on timer overrun at the end of this - * period. This is a little complicated, but doing it this way has the advantage of keeping both duty cycle and - * frame rate precisely constant. */ - TIM1->CCR3 = TIMER_CYCLES_FOR_SPI_TRANSMISSIONS; - TIM1->ARR = timer_period_lookup[idx]; - } - /* Reset the update interrupt flag. This ISR handler routine is only used for timer update events. */ - TIM1->SR &= ~TIM_SR_UIF_Msk; -} - -/* The data format of the serial command interface. - * - * The serial interface uses short packets. Currently, there is only one packet type defined: a "set RGBW" packet, using - * command ID 0x23. The packet starts with the command ID, followed by the addressed channel group, followed by four - * times two bytes of big-endian RGBW channel data. - * - * - */ -union packet { - struct { - uint8_t cmd; /* 0x23 */ - uint8_t step; /* logical channel. The USART_CHANNEL_OFFX is applied on this number below. */ - union { - uint16_t rgbw[4]; - struct { - uint16_t r, g, b, w; - }; - }; - } set_step; - uint8_t data[0]; -}; - -int rxpos = 0; -void TIM3_IRQHandler(void) { - TIM3->SR &= ~TIM_SR_UIF; - /* if (rxpos != sizeof(union packet)) - asm("bkpt"); - */ - rxpos = 0; -} - -/* This macro defines the lowest channel number of this board on the serial command bus. On a shared bus with several - * boards, you would generally assign increasing USART_CHANNEL_OFFX values to each one (0, 8, 16, 24, ...). - * - * Example: Let USART_CHANNEL_OFFX be 8. - * - * /--Command channel number received in command packet (packet.set_step.step) - * | /--USART_OFFX - * | | /--4 raw channels per logical channel (step): R, G, B, W - * | | | /--Raw channel offset for R, G, B, W - * | | | | /--Resulting raw channels for R, G, B, W data received in command packet - * | | | | | - * v v v v v - * - * (8 - 8) * 4 + {0, 1, 2, 3} = {0, 1, 2, 3} - * (9 - 8) * 4 + {0, 1, 2, 3} - * (10 - 8) * 4 + {0, 1, 2, 3} - * (11 - 8) * 4 + {0, 1, 2, 3} - * (12 - 8) * 4 + {0, 1, 2, 3} - * (13 - 8) * 4 + {0, 1, 2, 3} - * (14 - 8) * 4 + {0, 1, 2, 3} - * (15 - 8) * 4 + {0, 1, 2, 3} - */ -#ifndef USART_CHANNEL_OFFX -#define USART_CHANNEL_OFFX 8 -#endif//USART_CHANNEL_OFFX - -#define NCHANNELS (sizeof(brightness)/sizeof(brightness[0])) -void USART1_IRQHandler() { - static union packet rxbuf; - - int isr = USART1->ISR; - USART1->RQR |= USART_RQR_RXFRQ; - /* Overrun detected? */ - if (isr & USART_ISR_ORE) { - USART1->ICR = USART_ICR_ORECF; /* Acknowledge overrun */ - //asm("bkpt"); /* uncomment for debug */ - return; - } - - if (!(isr & USART_ISR_RXNE)) { - //asm("bkpt"); /* uncomment for debug */ - return; - } - - /* Store received data */ - uint8_t data = USART1->RDR; - rxbuf.data[rxpos] = data; - rxpos++; - - /* If we finished receiving a packet, deal with it. */ - if (rxpos == sizeof(union packet)) { - /* Check packet header */ - if (rxbuf.set_step.cmd == 0x23 && - /* bounds-check received channel number. This allows several driver boards to share one common serial bus */ - rxbuf.set_step.step >= USART_CHANNEL_OFFX && - rxbuf.set_step.step < USART_CHANNEL_OFFX+NCHANNELS) { - - /* Calculate raw channel brightness value base address for logical channel */ - uint32_t *out = &brightness[(rxbuf.set_step.step - USART_CHANNEL_OFFX)*4]; - - /* Correct RGBW raw channel ordering per logical channel according to SUB-D pinout used. - * - * (matti) (treppe) - * weiß blau - * rot weiß - * grün rot - * blau grün - */ - out[1] = rxbuf.set_step.rgbw[0]; - out[2] = rxbuf.set_step.rgbw[1]; - out[3] = rxbuf.set_step.rgbw[2]; - out[0] = rxbuf.set_step.rgbw[3]; - } - /* Reset receive data counter */ - rxpos = 0; - } - - /* Reset usart timeout handler */ - TIM3->CNT = 0; - TIM3->CR1 |= TIM_CR1_CEN; -} - -/* Misc IRQ handlers */ -void NMI_Handler(void) { -} - -void HardFault_Handler(void) { - for(;;); -} - -void SVC_Handler(void) { -} - - -void PendSV_Handler(void) { -} - -void SysTick_Handler(void) { - static int n = 0; - sys_time++; - if (n++ == 1000) { - n = 0; - sys_time_seconds++; - } -} - -/* Misc stuff for nostdlib linking */ -void _exit(int status) { while (23); } -void *__bss_start__; -void *__bss_end__; -int __errno; - diff --git a/olsndot/firmware/openocd.cfg b/olsndot/firmware/openocd.cfg deleted file mode 100644 index 2dc74f0..0000000 --- a/olsndot/firmware/openocd.cfg +++ /dev/null @@ -1,10 +0,0 @@ -telnet_port 4444 -gdb_port 3333 - -interface jlink -#adapter_khz 10000 -transport select swd - -source /usr/share/openocd/scripts/target/stm32f0x.cfg - -#flash bank sysflash.alias stm32f0x 0x00000000 0 0 0 $_TARGETNAME diff --git a/olsndot/firmware/startup_stm32f030x6.s b/olsndot/firmware/startup_stm32f030x6.s deleted file mode 100644 index ce81b76..0000000 --- a/olsndot/firmware/startup_stm32f030x6.s +++ /dev/null @@ -1,273 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f030x6.s - * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc - * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 - * @brief STM32F030x4/STM32F030x6 devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2] - adds r2, r2, #4 - - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word 0 /* Reserved */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word 0 /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/olsndot/firmware/stm32_flash.ld b/olsndot/firmware/stm32_flash.ld deleted file mode 100644 index 4a7f88a..0000000 --- a/olsndot/firmware/stm32_flash.ld +++ /dev/null @@ -1,127 +0,0 @@ - -ENTRY(Reset_Handler) - -MEMORY { - FLASH (rx): ORIGIN = 0x08000000, LENGTH = 16K - RAM (xrw): ORIGIN = 0x20000000, LENGTH = 4K -} - -/* highest address of the user mode stack */ -_estack = 0x20001000; - -SECTIONS { - /* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */ - .isr_vector : { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* the program code is stored in the .text section, which goes to Flash */ - .text : { - . = ALIGN(4); - - *(.text) /* normal code */ - *(.text.*) /* -ffunction-sections code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) /* -fdata-sections read only data */ - *(.glue_7) /* TBD - needed ? */ - *(.glue_7t) /* TBD - needed ? */ - - *(.source_tarball) - - /* Necessary KEEP sections (see http://sourceware.org/ml/newlib/2005/msg00255.html) */ - KEEP (*(.init)) - KEEP (*(.fini)) - KEEP (*(.source_tarball)) - - . = ALIGN(4); - _etext = .; - /* This is used by the startup in order to initialize the .data section */ - _sidata = _etext; - } >FLASH - - /* This is the initialized data section - The program executes knowing that the data is in the RAM - but the loader puts the initial values in the FLASH (inidata). - It is one task of the startup to copy the initial values from FLASH to RAM. */ - .data : AT ( _sidata ) { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - _data = . ; - - *(.data) - *(.data.*) - *(.RAMtext) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >RAM - - /* This is the uninitialized data section */ - .bss : { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - _bss = .; - - *(.bss) - *(.bss.*) /* patched by elias - allows the use of -fdata-sections */ - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - } >RAM - - PROVIDE ( end = _ebss); - PROVIDE (_end = _ebss); - - __exidx_start = .; - __exidx_end = .; - - /* after that it's only debugging information. */ - - /* remove the debugging information from the standard libraries */ - /DISCARD/ : { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - Symbols in the DWARF debugging sections are relative to the beginning - of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/olsndot/firmware/system_stm32f0xx.c b/olsndot/firmware/system_stm32f0xx.c deleted file mode 100644 index c578424..0000000 --- a/olsndot/firmware/system_stm32f0xx.c +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.c - * copied from: STM32Cube/Drivers/CMSIS/Device/ST/STM32F0xx/Source/Templates - * @author MCD Application Team - * @version V2.3.1 - * @date 04-November-2016 - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f0xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. This file configures the system clock as follows: - *============================================================================= - * Supported STM32F0xx device - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** @addtogroup STM32F0xx_System_Private_Includes - * @{ - */ - -#include "stm32f0xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI48_VALUE */ -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is - updated automatically. - */ -uint32_t SystemCoreClock = 8000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001U; - -#if defined (STM32F051x8) || defined (STM32F058x8) - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80CU; -#else - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80CU; -#endif /* STM32F051x8 or STM32F058x8 */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFFU; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFFU; - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFFU; - - /* Reset PREDIV[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; - -#if defined (STM32F072xB) || defined (STM32F078xx) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU; -#elif defined (STM32F071xB) - /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFCEACU; -#elif defined (STM32F091xC) || defined (STM32F098xx) - /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; -#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) - /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; -#elif defined (STM32F051x8) || defined (STM32F058xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEACU; -#elif defined (STM32F042x6) || defined (STM32F048xx) - /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU; -#elif defined (STM32F070x6) || defined (STM32F070xB) - /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU; - /* Set default USB clock to PLLCLK, since there is no HSI48 */ - RCC->CFGR3 |= (uint32_t)0x00000080U; -#else - #warning "No target selected" -#endif - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFEU; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ - SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; - } -#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ - || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ - || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ - SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || - STM32F091xC || STM32F098xx || STM32F030xC */ - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - |