/* Megumin LED display firmware
 * Copyright (C) 2018 Sebastian Götte <code@jaseg.net>
 * 
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 * 
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "global.h"

#define RTC_INITIALIZED_REGISTER_HIGH BKP->DR1
#define RTC_INITIALIZED_REGISTER_LOW BKP->DR2
#define REBOOT_REGISTER BKP->DR3

#define DAY_SECONDS (24*3600)

uint32_t pcg32_random_r() {
    // *Really* minimal PCG32 code / (c) 2014 M.E. O'Neill / pcg-random.org
    // Licensed under Apache License 2.0 (NO WARRANTY, etc. see website)
    static uint64_t state = 0xbc422715d3aef60f;
    static uint64_t inc = 0x6605e3bc6d1a869b; 
    uint64_t oldstate = state;
    // Advance internal state
    state = oldstate * 6364136223846793005ULL + (inc|1);
    // Calculate output function (XSH RR), uses old state for max ILP
    uint32_t xorshifted = ((oldstate >> 18u) ^ oldstate) >> 27u;
    uint32_t rot = oldstate >> 59u;
    return (xorshifted >> rot) | (xorshifted << ((-rot) & 31));
}

unsigned char dumb_random() {
    static unsigned char x=0x66, a=0x05, b=0xe3, c=0xbc;
    x++; //x is incremented every round and is not affected by any other variable
    a = (a ^ c ^ x); //note the mix of addition and XOR
    b = (b + a); //And the use of very few instructions
    c = (((c + (b >> 1)) ^ a)); // the AES S-Box Operation ensures an even distributon of entropy
    return (c);
}

void rtc_write(volatile uint32_t *reg, uint32_t val) {
    while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
    RTC->CRL |= RTC_CRL_CNF;

    reg[0] = val>>16;
    reg[1] = val&0xffff;

    RTC->CRL &= ~RTC_CRL_CNF;
    while (!(RTC->CRL & RTC_CRL_RTOFF)) ;
}

void rtc_alarm_reset(void) {
    RTC->CRL &= ~RTC_CRL_ALRF;
}

void rtc_init(void) {
    RTC->CRH = RTC_CRH_ALRIE;

    /* Cold boot config */
    if (((RTC_INITIALIZED_REGISTER_HIGH<<16) | RTC_INITIALIZED_REGISTER_LOW) != COMPILE_TIME) {
        /* RTC clock config */
        RCC->BDCR = RCC_BDCR_RTCEN | (1<<RCC_BDCR_RTCSEL_Pos) | RCC_BDCR_LSEON;
        while (!(RCC->BDCR & RCC_BDCR_LSERDY)) ;

        rtc_write(&RTC->PRLH, 32768-1);
        rtc_write(&RTC->CNTH, COMPILE_TIME);
        RTC_INITIALIZED_REGISTER_HIGH = COMPILE_TIME>>16;
        RTC_INITIALIZED_REGISTER_LOW = COMPILE_TIME&0xffff;
        REBOOT_REGISTER  = 0;
    }

    /* Synchronize RTC registers from backup domain */
    RTC->CRL &= ~RTC_CRL_RSF;
}

void rtc_set_alarm_sec(uint32_t value) {
    rtc_write(&RTC->ALRH, value);
}

uint32_t rtc_time(void) {
    /* Wait for register synchronization after bootup */
    while (!(RTC->CRL & RTC_CRL_RSF)) ;
    return RTC->CNTH<<16 | RTC->CNTL;
}

void rtc_set_alarm_rel_sec(uint32_t value) {
    rtc_set_alarm_sec(rtc_time() + value);
}

int main(void){
    /* We're starting out from HSI@8MHz */
    SystemCoreClockUpdate();
    SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk); /* Disable for now */
    for (int i=0; i<50000; i++)
        asm volatile ("nop");

    /* Turn on lots of neat things */
    RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPBEN;
    RCC->APB1ENR |= RCC_APB1ENR_BKPEN | RCC_APB1ENR_PWREN;
    PWR->CR = PWR_CR_DBP;

    GPIOC->CRH |=
          (0<<GPIO_CRH_CNF13_Pos) | (2<<GPIO_CRH_MODE13_Pos); /* PC13 - LED */
    GPIOB->CRH |=
          (0<<GPIO_CRH_CNF8_Pos) | (2<<GPIO_CRH_MODE8_Pos); /* PB8 - MOSFET */
    GPIOC->ODR |= 1<<13; /* LED */
    GPIOB->ODR &= ~(1<<8); /* MOSFET */

    rtc_init();
    rtc_alarm_reset();
    //NVIC_ClearPendingIRQ(RTC_IRQn);
    NVIC_EnableIRQ(RTC_IRQn);
    NVIC_SetPriority(RTC_IRQn, 1);

    rtc_set_alarm_rel_sec(1);

    //if (!(PWR->CSR & PWR_CSR_WUF)) /* This reset wasn't caused by the RTC alarm */
    REBOOT_REGISTER++;

    //SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
    //SCB->SCR &= (~SCB_SCR_SLEEPONEXIT_Msk) & (~SCB_SCR_SLEEPDEEP_Msk);
    //PWR->CR &= (~PWR_CR_PDDS) & (~PWR_CR_LPDS);
    //PWR->CR |= PWR_CR_CWUF; /* This has 2 cycles latency, thus the NOPs */
    //asm volatile ("nop");
    //asm volatile ("nop");
    while (42)
        asm volatile ("wfi");
}

void RTC_IRQHandler(void) {
    rtc_alarm_reset();
    rtc_set_alarm_rel_sec(1);

    uint32_t now = rtc_time();
    bool switch_on = false;
    if (REBOOT_REGISTER > 1) { /* We have rebooted since initial bring-up */
        /* Give status indication and active output as fail-safe */
        if ((now&3) == 0) {
            GPIOC->ODR &= ~(1<<13);
            for (int i=0; i<5000; i++)
                asm volatile ("nop");
            GPIOC->ODR |= 1<<13;
        }

        switch_on = true;

    } else {
        switch_on = (now >= TARGET_DATE - (DAY_SECONDS*24) && now < TARGET_DATE);
    }

    if (switch_on && (now/2) % 3 == 0) {
        GPIOB->ODR |= 1<<8;

        /* Go to sleep mode to keep GPIO active */
        //PWR->CR &= ~PWR_CR_PDDS;
        //SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); /* Use deep sleep mode */

    } else {
        GPIOB->ODR &= ~(1<<8);

        /* Go to standby mode to reduce power consumption */
        //PWR->CR = PWR_CR_PDDS;
        //SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Use deep sleep mode */
    }

    GPIOC->ODR &= ~(1<<13);
    for (int i=0; i<5000; i++)
        asm volatile ("nop");
    GPIOC->ODR |= 1<<13;
}

void gdb_dump(void) {
    /* debugger hook */
}

void NMI_Handler(void) {
    asm volatile ("bkpt");
}

void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
    asm volatile ("bkpt");
}

void SVC_Handler(void) {
    asm volatile ("bkpt");
}


void PendSV_Handler(void) {
    asm volatile ("bkpt");
}

void SysTick_Handler(void) {
    asm volatile ("bkpt");
}