ARM GAS /tmp/cceoVgjg.s page 1 1 .cpu cortex-m0 2 .eabi_attribute 20, 1 3 .eabi_attribute 21, 1 4 .eabi_attribute 23, 3 5 .eabi_attribute 24, 1 6 .eabi_attribute 25, 1 7 .eabi_attribute 26, 1 8 .eabi_attribute 30, 1 9 .eabi_attribute 34, 0 10 .eabi_attribute 18, 4 11 .file "stm32f0xx_hal_cortex.c" 12 .text 13 .Ltext0: 14 .cfi_sections .debug_frame 15 .section .text.HAL_NVIC_SetPriority,"ax",%progbits 16 .align 1 17 .global HAL_NVIC_SetPriority 18 .syntax unified 19 .code 16 20 .thumb_func 21 .fpu softvfp 23 HAL_NVIC_SetPriority: 24 .LFB40: 25 .file 1 "Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c" 1:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 2:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ****************************************************************************** 3:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @file stm32f0xx_hal_cortex.c 4:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @author MCD Application Team 5:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief CORTEX HAL module driver. 6:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * functionalities of the CORTEX: 8:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * + Peripheral Control functions 10:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 11:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @verbatim 12:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 13:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ##### How to use this driver ##### 14:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 15:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 16:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 17:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** 18:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** =========================================================== 19:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 20:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). 21:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** The Cortex-M0 exceptions are managed by CMSIS functions. 22:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#) Enable and Configure the priority of the selected IRQ Channels. 23:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** The priority can be 0..3. 24:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 25:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** -@- Lower priority values gives higher priority. 26:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** -@- Priority Order: 27:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#@) Lowest priority. 28:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#@) Lowest hardware priority (IRQn position). 29:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 30:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 31:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 32:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 33:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ARM GAS /tmp/cceoVgjg.s page 2 34:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** -@- Negative value of IRQn_Type are not allowed. 35:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 36:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 37:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 38:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** 39:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ======================================================== 40:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 41:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** Setup SysTick Timer for time base. 42:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 43:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which 44:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** is a CMSIS function that: 45:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. 46:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x03). 47:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Resets the SysTick Counter register. 48:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 49:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. 50:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Starts the SysTick Counter. 51:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 52:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 53:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 54:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined 55:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** inside the stm32f0xx_hal_cortex.h file. 56:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 57:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the 58:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 59:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct 60:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 61:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: 62:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 63:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 64:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 65:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF 66:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 67:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** @endverbatim 68:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ****************************************************************************** 69:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @attention 70:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 71:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** *

© Copyright (c) 2016 STMicroelectronics. 72:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * All rights reserved.

73:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 74:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This software component is licensed by ST under BSD 3-Clause license, 75:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * the "License"; You may not use this file except in compliance with the 76:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * License. You may obtain a copy of the License at: 77:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * opensource.org/licenses/BSD-3-Clause 78:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 79:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ****************************************************************************** 80:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 81:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 82:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ 83:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** #include "stm32f0xx_hal.h" 84:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 85:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @addtogroup STM32F0xx_HAL_Driver 86:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ 87:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 88:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 89:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX 90:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief CORTEX CORTEX HAL module driver ARM GAS /tmp/cceoVgjg.s page 3 91:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ 92:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 93:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 94:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED 95:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 96:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Private typedef -----------------------------------------------------------*/ 97:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Private define ------------------------------------------------------------*/ 98:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Private macro -------------------------------------------------------------*/ 99:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ 100:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/ 101:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Exported functions ---------------------------------------------------------*/ 102:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 103:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 104:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ 105:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 106:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 107:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 108:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 109:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Initialization and Configuration functions 110:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 111:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** @verbatim 112:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 113:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### 114:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 115:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 116:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts 117:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** Systick functionalities 118:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 119:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** @endverbatim 120:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ 121:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 122:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 123:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 124:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. 125:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number . 126:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 127:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) 128:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param PreemptPriority The preemption priority for the IRQn channel. 129:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be a value between 0 and 3. 130:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * A lower priority value indicates a higher priority 131:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. 132:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 133:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * no subpriority supported in Cortex M0 based products. 134:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 135:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 136:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 137:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 26 .loc 1 137 0 27 .cfi_startproc 28 @ args = 0, pretend = 0, frame = 0 29 @ frame_needed = 0, uses_anonymous_args = 0 30 .LVL0: 31 0000 70B5 push {r4, r5, r6, lr} 32 .LCFI0: 33 .cfi_def_cfa_offset 16 34 .cfi_offset 4, -16 35 .cfi_offset 5, -12 ARM GAS /tmp/cceoVgjg.s page 4 36 .cfi_offset 6, -8 37 .cfi_offset 14, -4 38 .LVL1: 39 .LBB32: 40 .LBB33: 41 .file 2 "Drivers/CMSIS/Include/core_cm0.h" 1:Drivers/CMSIS/Include/core_cm0.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/core_cm0.h **** * @file core_cm0.h 3:Drivers/CMSIS/Include/core_cm0.h **** * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 4:Drivers/CMSIS/Include/core_cm0.h **** * @version V5.0.5 5:Drivers/CMSIS/Include/core_cm0.h **** * @date 28. May 2018 6:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/core_cm0.h **** /* 8:Drivers/CMSIS/Include/core_cm0.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/core_cm0.h **** * 10:Drivers/CMSIS/Include/core_cm0.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/core_cm0.h **** * 12:Drivers/CMSIS/Include/core_cm0.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/core_cm0.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/core_cm0.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/core_cm0.h **** * 16:Drivers/CMSIS/Include/core_cm0.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/core_cm0.h **** * 18:Drivers/CMSIS/Include/core_cm0.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/core_cm0.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/core_cm0.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/core_cm0.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/core_cm0.h **** * limitations under the License. 23:Drivers/CMSIS/Include/core_cm0.h **** */ 24:Drivers/CMSIS/Include/core_cm0.h **** 25:Drivers/CMSIS/Include/core_cm0.h **** #if defined ( __ICCARM__ ) 26:Drivers/CMSIS/Include/core_cm0.h **** #pragma system_include /* treat file as system include file for MISRA check */ 27:Drivers/CMSIS/Include/core_cm0.h **** #elif defined (__clang__) 28:Drivers/CMSIS/Include/core_cm0.h **** #pragma clang system_header /* treat file as system include file */ 29:Drivers/CMSIS/Include/core_cm0.h **** #endif 30:Drivers/CMSIS/Include/core_cm0.h **** 31:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CORE_CM0_H_GENERIC 32:Drivers/CMSIS/Include/core_cm0.h **** #define __CORE_CM0_H_GENERIC 33:Drivers/CMSIS/Include/core_cm0.h **** 34:Drivers/CMSIS/Include/core_cm0.h **** #include 35:Drivers/CMSIS/Include/core_cm0.h **** 36:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus 37:Drivers/CMSIS/Include/core_cm0.h **** extern "C" { 38:Drivers/CMSIS/Include/core_cm0.h **** #endif 39:Drivers/CMSIS/Include/core_cm0.h **** 40:Drivers/CMSIS/Include/core_cm0.h **** /** 41:Drivers/CMSIS/Include/core_cm0.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 42:Drivers/CMSIS/Include/core_cm0.h **** CMSIS violates the following MISRA-C:2004 rules: 43:Drivers/CMSIS/Include/core_cm0.h **** 44:Drivers/CMSIS/Include/core_cm0.h **** \li Required Rule 8.5, object/function definition in header file.
45:Drivers/CMSIS/Include/core_cm0.h **** Function definitions in header files are used to allow 'inlining'. 46:Drivers/CMSIS/Include/core_cm0.h **** 47:Drivers/CMSIS/Include/core_cm0.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
48:Drivers/CMSIS/Include/core_cm0.h **** Unions are used for effective representation of core registers. 49:Drivers/CMSIS/Include/core_cm0.h **** 50:Drivers/CMSIS/Include/core_cm0.h **** \li Advisory Rule 19.7, Function-like macro defined.
51:Drivers/CMSIS/Include/core_cm0.h **** Function-like macros are used to allow more efficient code. ARM GAS /tmp/cceoVgjg.s page 5 52:Drivers/CMSIS/Include/core_cm0.h **** */ 53:Drivers/CMSIS/Include/core_cm0.h **** 54:Drivers/CMSIS/Include/core_cm0.h **** 55:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* 56:Drivers/CMSIS/Include/core_cm0.h **** * CMSIS definitions 57:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ 58:Drivers/CMSIS/Include/core_cm0.h **** /** 59:Drivers/CMSIS/Include/core_cm0.h **** \ingroup Cortex_M0 60:Drivers/CMSIS/Include/core_cm0.h **** @{ 61:Drivers/CMSIS/Include/core_cm0.h **** */ 62:Drivers/CMSIS/Include/core_cm0.h **** 63:Drivers/CMSIS/Include/core_cm0.h **** #include "cmsis_version.h" 64:Drivers/CMSIS/Include/core_cm0.h **** 65:Drivers/CMSIS/Include/core_cm0.h **** /* CMSIS CM0 definitions */ 66:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C 67:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C 68:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ 69:Drivers/CMSIS/Include/core_cm0.h **** __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL 70:Drivers/CMSIS/Include/core_cm0.h **** 71:Drivers/CMSIS/Include/core_cm0.h **** #define __CORTEX_M (0U) /*!< Cortex-M Core */ 72:Drivers/CMSIS/Include/core_cm0.h **** 73:Drivers/CMSIS/Include/core_cm0.h **** /** __FPU_USED indicates whether an FPU is used or not. 74:Drivers/CMSIS/Include/core_cm0.h **** This core does not support an FPU at all 75:Drivers/CMSIS/Include/core_cm0.h **** */ 76:Drivers/CMSIS/Include/core_cm0.h **** #define __FPU_USED 0U 77:Drivers/CMSIS/Include/core_cm0.h **** 78:Drivers/CMSIS/Include/core_cm0.h **** #if defined ( __CC_ARM ) 79:Drivers/CMSIS/Include/core_cm0.h **** #if defined __TARGET_FPU_VFP 80:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 81:Drivers/CMSIS/Include/core_cm0.h **** #endif 82:Drivers/CMSIS/Include/core_cm0.h **** 83:Drivers/CMSIS/Include/core_cm0.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 84:Drivers/CMSIS/Include/core_cm0.h **** #if defined __ARM_PCS_VFP 85:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 86:Drivers/CMSIS/Include/core_cm0.h **** #endif 87:Drivers/CMSIS/Include/core_cm0.h **** 88:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __GNUC__ ) 89:Drivers/CMSIS/Include/core_cm0.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) 90:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 91:Drivers/CMSIS/Include/core_cm0.h **** #endif 92:Drivers/CMSIS/Include/core_cm0.h **** 93:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __ICCARM__ ) 94:Drivers/CMSIS/Include/core_cm0.h **** #if defined __ARMVFP__ 95:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 96:Drivers/CMSIS/Include/core_cm0.h **** #endif 97:Drivers/CMSIS/Include/core_cm0.h **** 98:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __TI_ARM__ ) 99:Drivers/CMSIS/Include/core_cm0.h **** #if defined __TI_VFP_SUPPORT__ 100:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 101:Drivers/CMSIS/Include/core_cm0.h **** #endif 102:Drivers/CMSIS/Include/core_cm0.h **** 103:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __TASKING__ ) 104:Drivers/CMSIS/Include/core_cm0.h **** #if defined __FPU_VFP__ 105:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 106:Drivers/CMSIS/Include/core_cm0.h **** #endif 107:Drivers/CMSIS/Include/core_cm0.h **** 108:Drivers/CMSIS/Include/core_cm0.h **** #elif defined ( __CSMC__ ) ARM GAS /tmp/cceoVgjg.s page 6 109:Drivers/CMSIS/Include/core_cm0.h **** #if ( __CSMC__ & 0x400U) 110:Drivers/CMSIS/Include/core_cm0.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 111:Drivers/CMSIS/Include/core_cm0.h **** #endif 112:Drivers/CMSIS/Include/core_cm0.h **** 113:Drivers/CMSIS/Include/core_cm0.h **** #endif 114:Drivers/CMSIS/Include/core_cm0.h **** 115:Drivers/CMSIS/Include/core_cm0.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ 116:Drivers/CMSIS/Include/core_cm0.h **** 117:Drivers/CMSIS/Include/core_cm0.h **** 118:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus 119:Drivers/CMSIS/Include/core_cm0.h **** } 120:Drivers/CMSIS/Include/core_cm0.h **** #endif 121:Drivers/CMSIS/Include/core_cm0.h **** 122:Drivers/CMSIS/Include/core_cm0.h **** #endif /* __CORE_CM0_H_GENERIC */ 123:Drivers/CMSIS/Include/core_cm0.h **** 124:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CMSIS_GENERIC 125:Drivers/CMSIS/Include/core_cm0.h **** 126:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CORE_CM0_H_DEPENDANT 127:Drivers/CMSIS/Include/core_cm0.h **** #define __CORE_CM0_H_DEPENDANT 128:Drivers/CMSIS/Include/core_cm0.h **** 129:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus 130:Drivers/CMSIS/Include/core_cm0.h **** extern "C" { 131:Drivers/CMSIS/Include/core_cm0.h **** #endif 132:Drivers/CMSIS/Include/core_cm0.h **** 133:Drivers/CMSIS/Include/core_cm0.h **** /* check device defines and use defaults */ 134:Drivers/CMSIS/Include/core_cm0.h **** #if defined __CHECK_DEVICE_DEFINES 135:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __CM0_REV 136:Drivers/CMSIS/Include/core_cm0.h **** #define __CM0_REV 0x0000U 137:Drivers/CMSIS/Include/core_cm0.h **** #warning "__CM0_REV not defined in device header file; using default!" 138:Drivers/CMSIS/Include/core_cm0.h **** #endif 139:Drivers/CMSIS/Include/core_cm0.h **** 140:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __NVIC_PRIO_BITS 141:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_PRIO_BITS 2U 142:Drivers/CMSIS/Include/core_cm0.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 143:Drivers/CMSIS/Include/core_cm0.h **** #endif 144:Drivers/CMSIS/Include/core_cm0.h **** 145:Drivers/CMSIS/Include/core_cm0.h **** #ifndef __Vendor_SysTickConfig 146:Drivers/CMSIS/Include/core_cm0.h **** #define __Vendor_SysTickConfig 0U 147:Drivers/CMSIS/Include/core_cm0.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 148:Drivers/CMSIS/Include/core_cm0.h **** #endif 149:Drivers/CMSIS/Include/core_cm0.h **** #endif 150:Drivers/CMSIS/Include/core_cm0.h **** 151:Drivers/CMSIS/Include/core_cm0.h **** /* IO definitions (access restrictions to peripheral registers) */ 152:Drivers/CMSIS/Include/core_cm0.h **** /** 153:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines 154:Drivers/CMSIS/Include/core_cm0.h **** 155:Drivers/CMSIS/Include/core_cm0.h **** IO Type Qualifiers are used 156:Drivers/CMSIS/Include/core_cm0.h **** \li to specify the access to peripheral variables. 157:Drivers/CMSIS/Include/core_cm0.h **** \li for automatic generation of peripheral register debug information. 158:Drivers/CMSIS/Include/core_cm0.h **** */ 159:Drivers/CMSIS/Include/core_cm0.h **** #ifdef __cplusplus 160:Drivers/CMSIS/Include/core_cm0.h **** #define __I volatile /*!< Defines 'read only' permissions */ 161:Drivers/CMSIS/Include/core_cm0.h **** #else 162:Drivers/CMSIS/Include/core_cm0.h **** #define __I volatile const /*!< Defines 'read only' permissions */ 163:Drivers/CMSIS/Include/core_cm0.h **** #endif 164:Drivers/CMSIS/Include/core_cm0.h **** #define __O volatile /*!< Defines 'write only' permissions */ 165:Drivers/CMSIS/Include/core_cm0.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ ARM GAS /tmp/cceoVgjg.s page 7 166:Drivers/CMSIS/Include/core_cm0.h **** 167:Drivers/CMSIS/Include/core_cm0.h **** /* following defines should be used for structure members */ 168:Drivers/CMSIS/Include/core_cm0.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ 169:Drivers/CMSIS/Include/core_cm0.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ 170:Drivers/CMSIS/Include/core_cm0.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 171:Drivers/CMSIS/Include/core_cm0.h **** 172:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group Cortex_M0 */ 173:Drivers/CMSIS/Include/core_cm0.h **** 174:Drivers/CMSIS/Include/core_cm0.h **** 175:Drivers/CMSIS/Include/core_cm0.h **** 176:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* 177:Drivers/CMSIS/Include/core_cm0.h **** * Register Abstraction 178:Drivers/CMSIS/Include/core_cm0.h **** Core Register contain: 179:Drivers/CMSIS/Include/core_cm0.h **** - Core Register 180:Drivers/CMSIS/Include/core_cm0.h **** - Core NVIC Register 181:Drivers/CMSIS/Include/core_cm0.h **** - Core SCB Register 182:Drivers/CMSIS/Include/core_cm0.h **** - Core SysTick Register 183:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ 184:Drivers/CMSIS/Include/core_cm0.h **** /** 185:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_register Defines and Type Definitions 186:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions and defines for Cortex-M processor based devices. 187:Drivers/CMSIS/Include/core_cm0.h **** */ 188:Drivers/CMSIS/Include/core_cm0.h **** 189:Drivers/CMSIS/Include/core_cm0.h **** /** 190:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 191:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_CORE Status and Control Registers 192:Drivers/CMSIS/Include/core_cm0.h **** \brief Core Register type definitions. 193:Drivers/CMSIS/Include/core_cm0.h **** @{ 194:Drivers/CMSIS/Include/core_cm0.h **** */ 195:Drivers/CMSIS/Include/core_cm0.h **** 196:Drivers/CMSIS/Include/core_cm0.h **** /** 197:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Application Program Status Register (APSR). 198:Drivers/CMSIS/Include/core_cm0.h **** */ 199:Drivers/CMSIS/Include/core_cm0.h **** typedef union 200:Drivers/CMSIS/Include/core_cm0.h **** { 201:Drivers/CMSIS/Include/core_cm0.h **** struct 202:Drivers/CMSIS/Include/core_cm0.h **** { 203:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ 204:Drivers/CMSIS/Include/core_cm0.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 205:Drivers/CMSIS/Include/core_cm0.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 206:Drivers/CMSIS/Include/core_cm0.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 207:Drivers/CMSIS/Include/core_cm0.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 208:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ 209:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ 210:Drivers/CMSIS/Include/core_cm0.h **** } APSR_Type; 211:Drivers/CMSIS/Include/core_cm0.h **** 212:Drivers/CMSIS/Include/core_cm0.h **** /* APSR Register Definitions */ 213:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_N_Pos 31U /*!< APSR 214:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR 215:Drivers/CMSIS/Include/core_cm0.h **** 216:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_Z_Pos 30U /*!< APSR 217:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR 218:Drivers/CMSIS/Include/core_cm0.h **** 219:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_C_Pos 29U /*!< APSR 220:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR 221:Drivers/CMSIS/Include/core_cm0.h **** 222:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Pos 28U /*!< APSR ARM GAS /tmp/cceoVgjg.s page 8 223:Drivers/CMSIS/Include/core_cm0.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR 224:Drivers/CMSIS/Include/core_cm0.h **** 225:Drivers/CMSIS/Include/core_cm0.h **** 226:Drivers/CMSIS/Include/core_cm0.h **** /** 227:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). 228:Drivers/CMSIS/Include/core_cm0.h **** */ 229:Drivers/CMSIS/Include/core_cm0.h **** typedef union 230:Drivers/CMSIS/Include/core_cm0.h **** { 231:Drivers/CMSIS/Include/core_cm0.h **** struct 232:Drivers/CMSIS/Include/core_cm0.h **** { 233:Drivers/CMSIS/Include/core_cm0.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 234:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 235:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ 236:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ 237:Drivers/CMSIS/Include/core_cm0.h **** } IPSR_Type; 238:Drivers/CMSIS/Include/core_cm0.h **** 239:Drivers/CMSIS/Include/core_cm0.h **** /* IPSR Register Definitions */ 240:Drivers/CMSIS/Include/core_cm0.h **** #define IPSR_ISR_Pos 0U /*!< IPSR 241:Drivers/CMSIS/Include/core_cm0.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR 242:Drivers/CMSIS/Include/core_cm0.h **** 243:Drivers/CMSIS/Include/core_cm0.h **** 244:Drivers/CMSIS/Include/core_cm0.h **** /** 245:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 246:Drivers/CMSIS/Include/core_cm0.h **** */ 247:Drivers/CMSIS/Include/core_cm0.h **** typedef union 248:Drivers/CMSIS/Include/core_cm0.h **** { 249:Drivers/CMSIS/Include/core_cm0.h **** struct 250:Drivers/CMSIS/Include/core_cm0.h **** { 251:Drivers/CMSIS/Include/core_cm0.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 252:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 253:Drivers/CMSIS/Include/core_cm0.h **** uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 254:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ 255:Drivers/CMSIS/Include/core_cm0.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 256:Drivers/CMSIS/Include/core_cm0.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 257:Drivers/CMSIS/Include/core_cm0.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 258:Drivers/CMSIS/Include/core_cm0.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 259:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ 260:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ 261:Drivers/CMSIS/Include/core_cm0.h **** } xPSR_Type; 262:Drivers/CMSIS/Include/core_cm0.h **** 263:Drivers/CMSIS/Include/core_cm0.h **** /* xPSR Register Definitions */ 264:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_N_Pos 31U /*!< xPSR 265:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR 266:Drivers/CMSIS/Include/core_cm0.h **** 267:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_Z_Pos 30U /*!< xPSR 268:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR 269:Drivers/CMSIS/Include/core_cm0.h **** 270:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_C_Pos 29U /*!< xPSR 271:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR 272:Drivers/CMSIS/Include/core_cm0.h **** 273:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_V_Pos 28U /*!< xPSR 274:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR 275:Drivers/CMSIS/Include/core_cm0.h **** 276:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_T_Pos 24U /*!< xPSR 277:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR 278:Drivers/CMSIS/Include/core_cm0.h **** 279:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Pos 0U /*!< xPSR ARM GAS /tmp/cceoVgjg.s page 9 280:Drivers/CMSIS/Include/core_cm0.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR 281:Drivers/CMSIS/Include/core_cm0.h **** 282:Drivers/CMSIS/Include/core_cm0.h **** 283:Drivers/CMSIS/Include/core_cm0.h **** /** 284:Drivers/CMSIS/Include/core_cm0.h **** \brief Union type to access the Control Registers (CONTROL). 285:Drivers/CMSIS/Include/core_cm0.h **** */ 286:Drivers/CMSIS/Include/core_cm0.h **** typedef union 287:Drivers/CMSIS/Include/core_cm0.h **** { 288:Drivers/CMSIS/Include/core_cm0.h **** struct 289:Drivers/CMSIS/Include/core_cm0.h **** { 290:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved0:1; /*!< bit: 0 Reserved */ 291:Drivers/CMSIS/Include/core_cm0.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 292:Drivers/CMSIS/Include/core_cm0.h **** uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ 293:Drivers/CMSIS/Include/core_cm0.h **** } b; /*!< Structure used for bit access */ 294:Drivers/CMSIS/Include/core_cm0.h **** uint32_t w; /*!< Type used for word access */ 295:Drivers/CMSIS/Include/core_cm0.h **** } CONTROL_Type; 296:Drivers/CMSIS/Include/core_cm0.h **** 297:Drivers/CMSIS/Include/core_cm0.h **** /* CONTROL Register Definitions */ 298:Drivers/CMSIS/Include/core_cm0.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT 299:Drivers/CMSIS/Include/core_cm0.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT 300:Drivers/CMSIS/Include/core_cm0.h **** 301:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_CORE */ 302:Drivers/CMSIS/Include/core_cm0.h **** 303:Drivers/CMSIS/Include/core_cm0.h **** 304:Drivers/CMSIS/Include/core_cm0.h **** /** 305:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 306:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 307:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the NVIC Registers 308:Drivers/CMSIS/Include/core_cm0.h **** @{ 309:Drivers/CMSIS/Include/core_cm0.h **** */ 310:Drivers/CMSIS/Include/core_cm0.h **** 311:Drivers/CMSIS/Include/core_cm0.h **** /** 312:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 313:Drivers/CMSIS/Include/core_cm0.h **** */ 314:Drivers/CMSIS/Include/core_cm0.h **** typedef struct 315:Drivers/CMSIS/Include/core_cm0.h **** { 316:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 317:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED0[31U]; 318:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register 319:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RSERVED1[31U]; 320:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * 321:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED2[31U]; 322:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register 323:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED3[31U]; 324:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED4[64U]; 325:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 326:Drivers/CMSIS/Include/core_cm0.h **** } NVIC_Type; 327:Drivers/CMSIS/Include/core_cm0.h **** 328:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_NVIC */ 329:Drivers/CMSIS/Include/core_cm0.h **** 330:Drivers/CMSIS/Include/core_cm0.h **** 331:Drivers/CMSIS/Include/core_cm0.h **** /** 332:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 333:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_SCB System Control Block (SCB) 334:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the System Control Block Registers 335:Drivers/CMSIS/Include/core_cm0.h **** @{ 336:Drivers/CMSIS/Include/core_cm0.h **** */ ARM GAS /tmp/cceoVgjg.s page 10 337:Drivers/CMSIS/Include/core_cm0.h **** 338:Drivers/CMSIS/Include/core_cm0.h **** /** 339:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the System Control Block (SCB). 340:Drivers/CMSIS/Include/core_cm0.h **** */ 341:Drivers/CMSIS/Include/core_cm0.h **** typedef struct 342:Drivers/CMSIS/Include/core_cm0.h **** { 343:Drivers/CMSIS/Include/core_cm0.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 344:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi 345:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED0; 346:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset 347:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 348:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * 349:Drivers/CMSIS/Include/core_cm0.h **** uint32_t RESERVED1; 350:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registe 351:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State 352:Drivers/CMSIS/Include/core_cm0.h **** } SCB_Type; 353:Drivers/CMSIS/Include/core_cm0.h **** 354:Drivers/CMSIS/Include/core_cm0.h **** /* SCB CPUID Register Definitions */ 355:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB 356:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB 357:Drivers/CMSIS/Include/core_cm0.h **** 358:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB 359:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB 360:Drivers/CMSIS/Include/core_cm0.h **** 361:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB 362:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB 363:Drivers/CMSIS/Include/core_cm0.h **** 364:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB 365:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB 366:Drivers/CMSIS/Include/core_cm0.h **** 367:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB 368:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB 369:Drivers/CMSIS/Include/core_cm0.h **** 370:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Interrupt Control State Register Definitions */ 371:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB 372:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB 373:Drivers/CMSIS/Include/core_cm0.h **** 374:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB 375:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB 376:Drivers/CMSIS/Include/core_cm0.h **** 377:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB 378:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB 379:Drivers/CMSIS/Include/core_cm0.h **** 380:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB 381:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB 382:Drivers/CMSIS/Include/core_cm0.h **** 383:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB 384:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB 385:Drivers/CMSIS/Include/core_cm0.h **** 386:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB 387:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB 388:Drivers/CMSIS/Include/core_cm0.h **** 389:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB 390:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB 391:Drivers/CMSIS/Include/core_cm0.h **** 392:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB 393:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ARM GAS /tmp/cceoVgjg.s page 11 394:Drivers/CMSIS/Include/core_cm0.h **** 395:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB 396:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB 397:Drivers/CMSIS/Include/core_cm0.h **** 398:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ 399:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB 400:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB 401:Drivers/CMSIS/Include/core_cm0.h **** 402:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB 403:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB 404:Drivers/CMSIS/Include/core_cm0.h **** 405:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB 406:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB 407:Drivers/CMSIS/Include/core_cm0.h **** 408:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB 409:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB 410:Drivers/CMSIS/Include/core_cm0.h **** 411:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB 412:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB 413:Drivers/CMSIS/Include/core_cm0.h **** 414:Drivers/CMSIS/Include/core_cm0.h **** /* SCB System Control Register Definitions */ 415:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB 416:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB 417:Drivers/CMSIS/Include/core_cm0.h **** 418:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB 419:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB 420:Drivers/CMSIS/Include/core_cm0.h **** 421:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB 422:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB 423:Drivers/CMSIS/Include/core_cm0.h **** 424:Drivers/CMSIS/Include/core_cm0.h **** /* SCB Configuration Control Register Definitions */ 425:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB 426:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB 427:Drivers/CMSIS/Include/core_cm0.h **** 428:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB 429:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB 430:Drivers/CMSIS/Include/core_cm0.h **** 431:Drivers/CMSIS/Include/core_cm0.h **** /* SCB System Handler Control and State Register Definitions */ 432:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB 433:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB 434:Drivers/CMSIS/Include/core_cm0.h **** 435:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_SCB */ 436:Drivers/CMSIS/Include/core_cm0.h **** 437:Drivers/CMSIS/Include/core_cm0.h **** 438:Drivers/CMSIS/Include/core_cm0.h **** /** 439:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 440:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) 441:Drivers/CMSIS/Include/core_cm0.h **** \brief Type definitions for the System Timer Registers. 442:Drivers/CMSIS/Include/core_cm0.h **** @{ 443:Drivers/CMSIS/Include/core_cm0.h **** */ 444:Drivers/CMSIS/Include/core_cm0.h **** 445:Drivers/CMSIS/Include/core_cm0.h **** /** 446:Drivers/CMSIS/Include/core_cm0.h **** \brief Structure type to access the System Timer (SysTick). 447:Drivers/CMSIS/Include/core_cm0.h **** */ 448:Drivers/CMSIS/Include/core_cm0.h **** typedef struct 449:Drivers/CMSIS/Include/core_cm0.h **** { 450:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis ARM GAS /tmp/cceoVgjg.s page 12 451:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 452:Drivers/CMSIS/Include/core_cm0.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * 453:Drivers/CMSIS/Include/core_cm0.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 454:Drivers/CMSIS/Include/core_cm0.h **** } SysTick_Type; 455:Drivers/CMSIS/Include/core_cm0.h **** 456:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Control / Status Register Definitions */ 457:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT 458:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT 459:Drivers/CMSIS/Include/core_cm0.h **** 460:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT 461:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT 462:Drivers/CMSIS/Include/core_cm0.h **** 463:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT 464:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT 465:Drivers/CMSIS/Include/core_cm0.h **** 466:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT 467:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT 468:Drivers/CMSIS/Include/core_cm0.h **** 469:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Reload Register Definitions */ 470:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT 471:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT 472:Drivers/CMSIS/Include/core_cm0.h **** 473:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Current Register Definitions */ 474:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT 475:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT 476:Drivers/CMSIS/Include/core_cm0.h **** 477:Drivers/CMSIS/Include/core_cm0.h **** /* SysTick Calibration Register Definitions */ 478:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT 479:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT 480:Drivers/CMSIS/Include/core_cm0.h **** 481:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT 482:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT 483:Drivers/CMSIS/Include/core_cm0.h **** 484:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT 485:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT 486:Drivers/CMSIS/Include/core_cm0.h **** 487:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_SysTick */ 488:Drivers/CMSIS/Include/core_cm0.h **** 489:Drivers/CMSIS/Include/core_cm0.h **** 490:Drivers/CMSIS/Include/core_cm0.h **** /** 491:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 492:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 493:Drivers/CMSIS/Include/core_cm0.h **** \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible ove 494:Drivers/CMSIS/Include/core_cm0.h **** Therefore they are not covered by the Cortex-M0 header file. 495:Drivers/CMSIS/Include/core_cm0.h **** @{ 496:Drivers/CMSIS/Include/core_cm0.h **** */ 497:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_CoreDebug */ 498:Drivers/CMSIS/Include/core_cm0.h **** 499:Drivers/CMSIS/Include/core_cm0.h **** 500:Drivers/CMSIS/Include/core_cm0.h **** /** 501:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 502:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_bitfield Core register bit field macros 503:Drivers/CMSIS/Include/core_cm0.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). 504:Drivers/CMSIS/Include/core_cm0.h **** @{ 505:Drivers/CMSIS/Include/core_cm0.h **** */ 506:Drivers/CMSIS/Include/core_cm0.h **** 507:Drivers/CMSIS/Include/core_cm0.h **** /** ARM GAS /tmp/cceoVgjg.s page 13 508:Drivers/CMSIS/Include/core_cm0.h **** \brief Mask and shift a bit field value for use in a register bit range. 509:Drivers/CMSIS/Include/core_cm0.h **** \param[in] field Name of the register bit field. 510:Drivers/CMSIS/Include/core_cm0.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. 511:Drivers/CMSIS/Include/core_cm0.h **** \return Masked and shifted value. 512:Drivers/CMSIS/Include/core_cm0.h **** */ 513:Drivers/CMSIS/Include/core_cm0.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) 514:Drivers/CMSIS/Include/core_cm0.h **** 515:Drivers/CMSIS/Include/core_cm0.h **** /** 516:Drivers/CMSIS/Include/core_cm0.h **** \brief Mask and shift a register value to extract a bit filed value. 517:Drivers/CMSIS/Include/core_cm0.h **** \param[in] field Name of the register bit field. 518:Drivers/CMSIS/Include/core_cm0.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. 519:Drivers/CMSIS/Include/core_cm0.h **** \return Masked and shifted bit field value. 520:Drivers/CMSIS/Include/core_cm0.h **** */ 521:Drivers/CMSIS/Include/core_cm0.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) 522:Drivers/CMSIS/Include/core_cm0.h **** 523:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of group CMSIS_core_bitfield */ 524:Drivers/CMSIS/Include/core_cm0.h **** 525:Drivers/CMSIS/Include/core_cm0.h **** 526:Drivers/CMSIS/Include/core_cm0.h **** /** 527:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_core_register 528:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_core_base Core Definitions 529:Drivers/CMSIS/Include/core_cm0.h **** \brief Definitions for base addresses, unions, and structures. 530:Drivers/CMSIS/Include/core_cm0.h **** @{ 531:Drivers/CMSIS/Include/core_cm0.h **** */ 532:Drivers/CMSIS/Include/core_cm0.h **** 533:Drivers/CMSIS/Include/core_cm0.h **** /* Memory mapping of Core Hardware */ 534:Drivers/CMSIS/Include/core_cm0.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas 535:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 536:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 537:Drivers/CMSIS/Include/core_cm0.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas 538:Drivers/CMSIS/Include/core_cm0.h **** 539:Drivers/CMSIS/Include/core_cm0.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct 540:Drivers/CMSIS/Include/core_cm0.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st 541:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc 542:Drivers/CMSIS/Include/core_cm0.h **** 543:Drivers/CMSIS/Include/core_cm0.h **** 544:Drivers/CMSIS/Include/core_cm0.h **** /*@} */ 545:Drivers/CMSIS/Include/core_cm0.h **** 546:Drivers/CMSIS/Include/core_cm0.h **** 547:Drivers/CMSIS/Include/core_cm0.h **** 548:Drivers/CMSIS/Include/core_cm0.h **** /******************************************************************************* 549:Drivers/CMSIS/Include/core_cm0.h **** * Hardware Abstraction Layer 550:Drivers/CMSIS/Include/core_cm0.h **** Core Function Interface contains: 551:Drivers/CMSIS/Include/core_cm0.h **** - Core NVIC Functions 552:Drivers/CMSIS/Include/core_cm0.h **** - Core SysTick Functions 553:Drivers/CMSIS/Include/core_cm0.h **** - Core Register Access Functions 554:Drivers/CMSIS/Include/core_cm0.h **** ******************************************************************************/ 555:Drivers/CMSIS/Include/core_cm0.h **** /** 556:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 557:Drivers/CMSIS/Include/core_cm0.h **** */ 558:Drivers/CMSIS/Include/core_cm0.h **** 559:Drivers/CMSIS/Include/core_cm0.h **** 560:Drivers/CMSIS/Include/core_cm0.h **** 561:Drivers/CMSIS/Include/core_cm0.h **** /* ########################## NVIC functions #################################### */ 562:Drivers/CMSIS/Include/core_cm0.h **** /** 563:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_Core_FunctionInterface 564:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions ARM GAS /tmp/cceoVgjg.s page 14 565:Drivers/CMSIS/Include/core_cm0.h **** \brief Functions that manage interrupts and exceptions via the NVIC. 566:Drivers/CMSIS/Include/core_cm0.h **** @{ 567:Drivers/CMSIS/Include/core_cm0.h **** */ 568:Drivers/CMSIS/Include/core_cm0.h **** 569:Drivers/CMSIS/Include/core_cm0.h **** #ifdef CMSIS_NVIC_VIRTUAL 570:Drivers/CMSIS/Include/core_cm0.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE 571:Drivers/CMSIS/Include/core_cm0.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" 572:Drivers/CMSIS/Include/core_cm0.h **** #endif 573:Drivers/CMSIS/Include/core_cm0.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE 574:Drivers/CMSIS/Include/core_cm0.h **** #else 575:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping 576:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping 577:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ 578:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ 579:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ 580:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ 581:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ 582:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ 583:Drivers/CMSIS/Include/core_cm0.h **** /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ 584:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetPriority __NVIC_SetPriority 585:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetPriority __NVIC_GetPriority 586:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SystemReset __NVIC_SystemReset 587:Drivers/CMSIS/Include/core_cm0.h **** #endif /* CMSIS_NVIC_VIRTUAL */ 588:Drivers/CMSIS/Include/core_cm0.h **** 589:Drivers/CMSIS/Include/core_cm0.h **** #ifdef CMSIS_VECTAB_VIRTUAL 590:Drivers/CMSIS/Include/core_cm0.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE 591:Drivers/CMSIS/Include/core_cm0.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" 592:Drivers/CMSIS/Include/core_cm0.h **** #endif 593:Drivers/CMSIS/Include/core_cm0.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE 594:Drivers/CMSIS/Include/core_cm0.h **** #else 595:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_SetVector __NVIC_SetVector 596:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_GetVector __NVIC_GetVector 597:Drivers/CMSIS/Include/core_cm0.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ 598:Drivers/CMSIS/Include/core_cm0.h **** 599:Drivers/CMSIS/Include/core_cm0.h **** #define NVIC_USER_IRQ_OFFSET 16 600:Drivers/CMSIS/Include/core_cm0.h **** 601:Drivers/CMSIS/Include/core_cm0.h **** 602:Drivers/CMSIS/Include/core_cm0.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ 603:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret 604:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu 605:Drivers/CMSIS/Include/core_cm0.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu 606:Drivers/CMSIS/Include/core_cm0.h **** 607:Drivers/CMSIS/Include/core_cm0.h **** 608:Drivers/CMSIS/Include/core_cm0.h **** /* Interrupt Priorities are WORD accessible only under Armv6-M */ 609:Drivers/CMSIS/Include/core_cm0.h **** /* The following MACROS handle generation of the register offset and byte masks */ 610:Drivers/CMSIS/Include/core_cm0.h **** #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) 611:Drivers/CMSIS/Include/core_cm0.h **** #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) 612:Drivers/CMSIS/Include/core_cm0.h **** #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) 613:Drivers/CMSIS/Include/core_cm0.h **** 614:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_SetPriorityGrouping(X) (void)(X) 615:Drivers/CMSIS/Include/core_cm0.h **** #define __NVIC_GetPriorityGrouping() (0U) 616:Drivers/CMSIS/Include/core_cm0.h **** 617:Drivers/CMSIS/Include/core_cm0.h **** /** 618:Drivers/CMSIS/Include/core_cm0.h **** \brief Enable Interrupt 619:Drivers/CMSIS/Include/core_cm0.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. 620:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 621:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. ARM GAS /tmp/cceoVgjg.s page 15 622:Drivers/CMSIS/Include/core_cm0.h **** */ 623:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) 624:Drivers/CMSIS/Include/core_cm0.h **** { 625:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 626:Drivers/CMSIS/Include/core_cm0.h **** { 627:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 628:Drivers/CMSIS/Include/core_cm0.h **** } 629:Drivers/CMSIS/Include/core_cm0.h **** } 630:Drivers/CMSIS/Include/core_cm0.h **** 631:Drivers/CMSIS/Include/core_cm0.h **** 632:Drivers/CMSIS/Include/core_cm0.h **** /** 633:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Interrupt Enable status 634:Drivers/CMSIS/Include/core_cm0.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. 635:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 636:Drivers/CMSIS/Include/core_cm0.h **** \return 0 Interrupt is not enabled. 637:Drivers/CMSIS/Include/core_cm0.h **** \return 1 Interrupt is enabled. 638:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 639:Drivers/CMSIS/Include/core_cm0.h **** */ 640:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) 641:Drivers/CMSIS/Include/core_cm0.h **** { 642:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 643:Drivers/CMSIS/Include/core_cm0.h **** { 644:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) 645:Drivers/CMSIS/Include/core_cm0.h **** } 646:Drivers/CMSIS/Include/core_cm0.h **** else 647:Drivers/CMSIS/Include/core_cm0.h **** { 648:Drivers/CMSIS/Include/core_cm0.h **** return(0U); 649:Drivers/CMSIS/Include/core_cm0.h **** } 650:Drivers/CMSIS/Include/core_cm0.h **** } 651:Drivers/CMSIS/Include/core_cm0.h **** 652:Drivers/CMSIS/Include/core_cm0.h **** 653:Drivers/CMSIS/Include/core_cm0.h **** /** 654:Drivers/CMSIS/Include/core_cm0.h **** \brief Disable Interrupt 655:Drivers/CMSIS/Include/core_cm0.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. 656:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 657:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 658:Drivers/CMSIS/Include/core_cm0.h **** */ 659:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) 660:Drivers/CMSIS/Include/core_cm0.h **** { 661:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 662:Drivers/CMSIS/Include/core_cm0.h **** { 663:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 664:Drivers/CMSIS/Include/core_cm0.h **** __DSB(); 665:Drivers/CMSIS/Include/core_cm0.h **** __ISB(); 666:Drivers/CMSIS/Include/core_cm0.h **** } 667:Drivers/CMSIS/Include/core_cm0.h **** } 668:Drivers/CMSIS/Include/core_cm0.h **** 669:Drivers/CMSIS/Include/core_cm0.h **** 670:Drivers/CMSIS/Include/core_cm0.h **** /** 671:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Pending Interrupt 672:Drivers/CMSIS/Include/core_cm0.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe 673:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 674:Drivers/CMSIS/Include/core_cm0.h **** \return 0 Interrupt status is not pending. 675:Drivers/CMSIS/Include/core_cm0.h **** \return 1 Interrupt status is pending. 676:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 677:Drivers/CMSIS/Include/core_cm0.h **** */ 678:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) ARM GAS /tmp/cceoVgjg.s page 16 679:Drivers/CMSIS/Include/core_cm0.h **** { 680:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 681:Drivers/CMSIS/Include/core_cm0.h **** { 682:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL) 683:Drivers/CMSIS/Include/core_cm0.h **** } 684:Drivers/CMSIS/Include/core_cm0.h **** else 685:Drivers/CMSIS/Include/core_cm0.h **** { 686:Drivers/CMSIS/Include/core_cm0.h **** return(0U); 687:Drivers/CMSIS/Include/core_cm0.h **** } 688:Drivers/CMSIS/Include/core_cm0.h **** } 689:Drivers/CMSIS/Include/core_cm0.h **** 690:Drivers/CMSIS/Include/core_cm0.h **** 691:Drivers/CMSIS/Include/core_cm0.h **** /** 692:Drivers/CMSIS/Include/core_cm0.h **** \brief Set Pending Interrupt 693:Drivers/CMSIS/Include/core_cm0.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. 694:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 695:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 696:Drivers/CMSIS/Include/core_cm0.h **** */ 697:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) 698:Drivers/CMSIS/Include/core_cm0.h **** { 699:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 700:Drivers/CMSIS/Include/core_cm0.h **** { 701:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 702:Drivers/CMSIS/Include/core_cm0.h **** } 703:Drivers/CMSIS/Include/core_cm0.h **** } 704:Drivers/CMSIS/Include/core_cm0.h **** 705:Drivers/CMSIS/Include/core_cm0.h **** 706:Drivers/CMSIS/Include/core_cm0.h **** /** 707:Drivers/CMSIS/Include/core_cm0.h **** \brief Clear Pending Interrupt 708:Drivers/CMSIS/Include/core_cm0.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. 709:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Device specific interrupt number. 710:Drivers/CMSIS/Include/core_cm0.h **** \note IRQn must not be negative. 711:Drivers/CMSIS/Include/core_cm0.h **** */ 712:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) 713:Drivers/CMSIS/Include/core_cm0.h **** { 714:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 715:Drivers/CMSIS/Include/core_cm0.h **** { 716:Drivers/CMSIS/Include/core_cm0.h **** NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 717:Drivers/CMSIS/Include/core_cm0.h **** } 718:Drivers/CMSIS/Include/core_cm0.h **** } 719:Drivers/CMSIS/Include/core_cm0.h **** 720:Drivers/CMSIS/Include/core_cm0.h **** 721:Drivers/CMSIS/Include/core_cm0.h **** /** 722:Drivers/CMSIS/Include/core_cm0.h **** \brief Set Interrupt Priority 723:Drivers/CMSIS/Include/core_cm0.h **** \details Sets the priority of a device specific interrupt or a processor exception. 724:Drivers/CMSIS/Include/core_cm0.h **** The interrupt number can be positive to specify a device specific interrupt, 725:Drivers/CMSIS/Include/core_cm0.h **** or negative to specify a processor exception. 726:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Interrupt number. 727:Drivers/CMSIS/Include/core_cm0.h **** \param [in] priority Priority to set. 728:Drivers/CMSIS/Include/core_cm0.h **** \note The priority cannot be set for every processor exception. 729:Drivers/CMSIS/Include/core_cm0.h **** */ 730:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 731:Drivers/CMSIS/Include/core_cm0.h **** { 732:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 42 .loc 2 732 0 43 0002 0028 cmp r0, #0 44 0004 11DB blt .L2 ARM GAS /tmp/cceoVgjg.s page 17 733:Drivers/CMSIS/Include/core_cm0.h **** { 734:Drivers/CMSIS/Include/core_cm0.h **** NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) 45 .loc 2 734 0 46 0006 8308 lsrs r3, r0, #2 47 0008 144D ldr r5, .L4 48 000a C033 adds r3, r3, #192 49 000c 9B00 lsls r3, r3, #2 50 000e 5C59 ldr r4, [r3, r5] 51 0010 0322 movs r2, #3 52 .LVL2: 53 0012 1040 ands r0, r2 54 .LVL3: 55 0014 C000 lsls r0, r0, #3 56 0016 FC32 adds r2, r2, #252 57 0018 1600 movs r6, r2 58 001a 8640 lsls r6, r6, r0 59 001c B443 bics r4, r6 735:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 60 .loc 2 735 0 61 001e 8901 lsls r1, r1, #6 62 .LVL4: 63 0020 0A40 ands r2, r1 64 0022 8240 lsls r2, r2, r0 734:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 65 .loc 2 734 0 66 0024 2243 orrs r2, r4 67 0026 5A51 str r2, [r3, r5] 68 .LVL5: 69 .L1: 70 .LBE33: 71 .LBE32: 138:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 139:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 140:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_SetPriority(IRQn,PreemptPriority); 141:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 72 .loc 1 141 0 73 @ sp needed 74 0028 70BD pop {r4, r5, r6, pc} 75 .LVL6: 76 .L2: 77 .LBB35: 78 .LBB34: 736:Drivers/CMSIS/Include/core_cm0.h **** } 737:Drivers/CMSIS/Include/core_cm0.h **** else 738:Drivers/CMSIS/Include/core_cm0.h **** { 739:Drivers/CMSIS/Include/core_cm0.h **** SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn)) 79 .loc 2 739 0 80 002a C0B2 uxtb r0, r0 81 002c 0F23 movs r3, #15 82 002e 0340 ands r3, r0 83 0030 083B subs r3, r3, #8 84 0032 9B08 lsrs r3, r3, #2 85 0034 0633 adds r3, r3, #6 86 0036 9B00 lsls r3, r3, #2 87 0038 094A ldr r2, .L4+4 88 .LVL7: 89 003a 9446 mov ip, r2 ARM GAS /tmp/cceoVgjg.s page 18 90 003c 6344 add r3, r3, ip 91 003e 5D68 ldr r5, [r3, #4] 92 0040 0324 movs r4, #3 93 0042 2040 ands r0, r4 94 .LVL8: 95 0044 C000 lsls r0, r0, #3 96 0046 FF22 movs r2, #255 97 0048 1400 movs r4, r2 98 004a 8440 lsls r4, r4, r0 99 004c A543 bics r5, r4 740:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 100 .loc 2 740 0 101 004e 8901 lsls r1, r1, #6 102 .LVL9: 103 0050 1140 ands r1, r2 104 0052 8140 lsls r1, r1, r0 739:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 105 .loc 2 739 0 106 0054 2943 orrs r1, r5 107 0056 5960 str r1, [r3, #4] 108 .LVL10: 109 .LBE34: 110 .LBE35: 111 .loc 1 141 0 112 0058 E6E7 b .L1 113 .L5: 114 005a C046 .align 2 115 .L4: 116 005c 00E100E0 .word -536813312 117 0060 00ED00E0 .word -536810240 118 .cfi_endproc 119 .LFE40: 121 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits 122 .align 1 123 .global HAL_NVIC_EnableIRQ 124 .syntax unified 125 .code 16 126 .thumb_func 127 .fpu softvfp 129 HAL_NVIC_EnableIRQ: 130 .LFB41: 142:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 143:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 144:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. 145:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 146:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * function should be called before. 147:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number. 148:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 149:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 150:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 151:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 152:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 153:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 131 .loc 1 153 0 132 .cfi_startproc 133 @ args = 0, pretend = 0, frame = 0 134 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/cceoVgjg.s page 19 135 @ link register save eliminated. 136 .LVL11: 137 .LBB36: 138 .LBB37: 625:Drivers/CMSIS/Include/core_cm0.h **** { 139 .loc 2 625 0 140 0000 0028 cmp r0, #0 141 0002 05DB blt .L6 627:Drivers/CMSIS/Include/core_cm0.h **** } 142 .loc 2 627 0 143 0004 1F23 movs r3, #31 144 0006 1840 ands r0, r3 145 .LVL12: 146 0008 1E3B subs r3, r3, #30 147 000a 8340 lsls r3, r3, r0 148 000c 014A ldr r2, .L8 149 000e 1360 str r3, [r2] 150 .LVL13: 151 .L6: 152 .LBE37: 153 .LBE36: 154:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 155:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 156:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 157:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Enable interrupt */ 158:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); 159:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 154 .loc 1 159 0 155 @ sp needed 156 0010 7047 bx lr 157 .L9: 158 0012 C046 .align 2 159 .L8: 160 0014 00E100E0 .word -536813312 161 .cfi_endproc 162 .LFE41: 164 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits 165 .align 1 166 .global HAL_NVIC_DisableIRQ 167 .syntax unified 168 .code 16 169 .thumb_func 170 .fpu softvfp 172 HAL_NVIC_DisableIRQ: 173 .LFB42: 160:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 161:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 162:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. 163:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number. 164:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 165:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 166:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 167:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 168:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 169:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 174 .loc 1 169 0 175 .cfi_startproc ARM GAS /tmp/cceoVgjg.s page 20 176 @ args = 0, pretend = 0, frame = 0 177 @ frame_needed = 0, uses_anonymous_args = 0 178 @ link register save eliminated. 179 .LVL14: 180 .LBB38: 181 .LBB39: 661:Drivers/CMSIS/Include/core_cm0.h **** { 182 .loc 2 661 0 183 0000 0028 cmp r0, #0 184 0002 0ADB blt .L10 663:Drivers/CMSIS/Include/core_cm0.h **** __DSB(); 185 .loc 2 663 0 186 0004 1F23 movs r3, #31 187 0006 1840 ands r0, r3 188 .LVL15: 189 0008 1E3B subs r3, r3, #30 190 000a 8340 lsls r3, r3, r0 191 000c 0349 ldr r1, .L12 192 000e 8022 movs r2, #128 193 0010 8B50 str r3, [r1, r2] 194 .LBB40: 195 .LBB41: 196 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ ARM GAS /tmp/cceoVgjg.s page 21 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop ARM GAS /tmp/cceoVgjg.s page 22 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** 117:Drivers/CMSIS/Include/cmsis_gcc.h **** 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } 133:Drivers/CMSIS/Include/cmsis_gcc.h **** 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } 144:Drivers/CMSIS/Include/cmsis_gcc.h **** 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. ARM GAS /tmp/cceoVgjg.s page 23 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } 158:Drivers/CMSIS/Include/cmsis_gcc.h **** 159:Drivers/CMSIS/Include/cmsis_gcc.h **** 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 174:Drivers/CMSIS/Include/cmsis_gcc.h **** 175:Drivers/CMSIS/Include/cmsis_gcc.h **** 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } 185:Drivers/CMSIS/Include/cmsis_gcc.h **** 186:Drivers/CMSIS/Include/cmsis_gcc.h **** 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) ARM GAS /tmp/cceoVgjg.s page 24 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 208:Drivers/CMSIS/Include/cmsis_gcc.h **** 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 213:Drivers/CMSIS/Include/cmsis_gcc.h **** 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } 240:Drivers/CMSIS/Include/cmsis_gcc.h **** 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } 254:Drivers/CMSIS/Include/cmsis_gcc.h **** 255:Drivers/CMSIS/Include/cmsis_gcc.h **** 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) ARM GAS /tmp/cceoVgjg.s page 25 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 270:Drivers/CMSIS/Include/cmsis_gcc.h **** 271:Drivers/CMSIS/Include/cmsis_gcc.h **** 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 295:Drivers/CMSIS/Include/cmsis_gcc.h **** 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 309:Drivers/CMSIS/Include/cmsis_gcc.h **** 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 319:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/cceoVgjg.s page 26 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 324:Drivers/CMSIS/Include/cmsis_gcc.h **** 325:Drivers/CMSIS/Include/cmsis_gcc.h **** 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 359:Drivers/CMSIS/Include/cmsis_gcc.h **** 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } 363:Drivers/CMSIS/Include/cmsis_gcc.h **** 364:Drivers/CMSIS/Include/cmsis_gcc.h **** 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 376:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/cceoVgjg.s page 27 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 385:Drivers/CMSIS/Include/cmsis_gcc.h **** 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } 389:Drivers/CMSIS/Include/cmsis_gcc.h **** 390:Drivers/CMSIS/Include/cmsis_gcc.h **** 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 400:Drivers/CMSIS/Include/cmsis_gcc.h **** 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 405:Drivers/CMSIS/Include/cmsis_gcc.h **** 406:Drivers/CMSIS/Include/cmsis_gcc.h **** 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 417:Drivers/CMSIS/Include/cmsis_gcc.h **** 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 429:Drivers/CMSIS/Include/cmsis_gcc.h **** 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) ARM GAS /tmp/cceoVgjg.s page 28 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 444:Drivers/CMSIS/Include/cmsis_gcc.h **** 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 464:Drivers/CMSIS/Include/cmsis_gcc.h **** 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/cceoVgjg.s page 29 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } 495:Drivers/CMSIS/Include/cmsis_gcc.h **** 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } 520:Drivers/CMSIS/Include/cmsis_gcc.h **** 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 545:Drivers/CMSIS/Include/cmsis_gcc.h **** 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); ARM GAS /tmp/cceoVgjg.s page 30 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } 561:Drivers/CMSIS/Include/cmsis_gcc.h **** 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 574:Drivers/CMSIS/Include/cmsis_gcc.h **** 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** 579:Drivers/CMSIS/Include/cmsis_gcc.h **** 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 582:Drivers/CMSIS/Include/cmsis_gcc.h **** 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } 604:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/cceoVgjg.s page 31 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 610:Drivers/CMSIS/Include/cmsis_gcc.h **** 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 627:Drivers/CMSIS/Include/cmsis_gcc.h **** 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } 647:Drivers/CMSIS/Include/cmsis_gcc.h **** 648:Drivers/CMSIS/Include/cmsis_gcc.h **** 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 654:Drivers/CMSIS/Include/cmsis_gcc.h **** 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI ARM GAS /tmp/cceoVgjg.s page 32 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 668:Drivers/CMSIS/Include/cmsis_gcc.h **** 669:Drivers/CMSIS/Include/cmsis_gcc.h **** 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 675:Drivers/CMSIS/Include/cmsis_gcc.h **** 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } 691:Drivers/CMSIS/Include/cmsis_gcc.h **** 692:Drivers/CMSIS/Include/cmsis_gcc.h **** 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. 698:Drivers/CMSIS/Include/cmsis_gcc.h **** 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure ARM GAS /tmp/cceoVgjg.s page 33 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 756:Drivers/CMSIS/Include/cmsis_gcc.h **** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 760:Drivers/CMSIS/Include/cmsis_gcc.h **** 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/cceoVgjg.s page 34 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 777:Drivers/CMSIS/Include/cmsis_gcc.h **** 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } 808:Drivers/CMSIS/Include/cmsis_gcc.h **** 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 818:Drivers/CMSIS/Include/cmsis_gcc.h **** 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 831:Drivers/CMSIS/Include/cmsis_gcc.h **** 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/cceoVgjg.s page 35 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 837:Drivers/CMSIS/Include/cmsis_gcc.h **** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") 843:Drivers/CMSIS/Include/cmsis_gcc.h **** 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 858:Drivers/CMSIS/Include/cmsis_gcc.h **** 859:Drivers/CMSIS/Include/cmsis_gcc.h **** 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } 870:Drivers/CMSIS/Include/cmsis_gcc.h **** 871:Drivers/CMSIS/Include/cmsis_gcc.h **** 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 197 .loc 3 879 0 198 .syntax divided 199 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 200 0012 BFF34F8F dsb 0xF 201 @ 0 "" 2 202 .thumb 203 .syntax unified 204 .LBE41: 205 .LBE40: 206 .LBB42: ARM GAS /tmp/cceoVgjg.s page 36 207 .LBB43: 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } 208 .loc 3 868 0 209 .syntax divided 210 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 211 0016 BFF36F8F isb 0xF 212 @ 0 "" 2 213 .LVL16: 214 .thumb 215 .syntax unified 216 .L10: 217 .LBE43: 218 .LBE42: 219 .LBE39: 220 .LBE38: 170:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 171:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 172:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 173:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Disable interrupt */ 174:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); 175:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 221 .loc 1 175 0 222 @ sp needed 223 001a 7047 bx lr 224 .L13: 225 .align 2 226 .L12: 227 001c 00E100E0 .word -536813312 228 .cfi_endproc 229 .LFE42: 231 .section .text.HAL_NVIC_SystemReset,"ax",%progbits 232 .align 1 233 .global HAL_NVIC_SystemReset 234 .syntax unified 235 .code 16 236 .thumb_func 237 .fpu softvfp 239 HAL_NVIC_SystemReset: 240 .LFB43: 176:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 177:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 178:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. 179:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 180:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 181:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) 182:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 241 .loc 1 182 0 242 .cfi_startproc 243 @ Volatile: function does not return. 244 @ args = 0, pretend = 0, frame = 0 245 @ frame_needed = 0, uses_anonymous_args = 0 246 @ link register save eliminated. 247 .LBB50: 248 .LBB51: 249 .LBB52: 250 .LBB53: 251 .loc 3 879 0 ARM GAS /tmp/cceoVgjg.s page 37 252 .syntax divided 253 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 254 0000 BFF34F8F dsb 0xF 255 @ 0 "" 2 256 .thumb 257 .syntax unified 258 .LBE53: 259 .LBE52: 741:Drivers/CMSIS/Include/core_cm0.h **** } 742:Drivers/CMSIS/Include/core_cm0.h **** } 743:Drivers/CMSIS/Include/core_cm0.h **** 744:Drivers/CMSIS/Include/core_cm0.h **** 745:Drivers/CMSIS/Include/core_cm0.h **** /** 746:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Interrupt Priority 747:Drivers/CMSIS/Include/core_cm0.h **** \details Reads the priority of a device specific interrupt or a processor exception. 748:Drivers/CMSIS/Include/core_cm0.h **** The interrupt number can be positive to specify a device specific interrupt, 749:Drivers/CMSIS/Include/core_cm0.h **** or negative to specify a processor exception. 750:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Interrupt number. 751:Drivers/CMSIS/Include/core_cm0.h **** \return Interrupt Priority. 752:Drivers/CMSIS/Include/core_cm0.h **** Value is aligned automatically to the implemented priority bits of the microc 753:Drivers/CMSIS/Include/core_cm0.h **** */ 754:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) 755:Drivers/CMSIS/Include/core_cm0.h **** { 756:Drivers/CMSIS/Include/core_cm0.h **** 757:Drivers/CMSIS/Include/core_cm0.h **** if ((int32_t)(IRQn) >= 0) 758:Drivers/CMSIS/Include/core_cm0.h **** { 759:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - 760:Drivers/CMSIS/Include/core_cm0.h **** } 761:Drivers/CMSIS/Include/core_cm0.h **** else 762:Drivers/CMSIS/Include/core_cm0.h **** { 763:Drivers/CMSIS/Include/core_cm0.h **** return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - 764:Drivers/CMSIS/Include/core_cm0.h **** } 765:Drivers/CMSIS/Include/core_cm0.h **** } 766:Drivers/CMSIS/Include/core_cm0.h **** 767:Drivers/CMSIS/Include/core_cm0.h **** 768:Drivers/CMSIS/Include/core_cm0.h **** /** 769:Drivers/CMSIS/Include/core_cm0.h **** \brief Encode Priority 770:Drivers/CMSIS/Include/core_cm0.h **** \details Encodes the priority for an interrupt with the given priority group, 771:Drivers/CMSIS/Include/core_cm0.h **** preemptive priority value, and subpriority value. 772:Drivers/CMSIS/Include/core_cm0.h **** In case of a conflict between priority grouping and available 773:Drivers/CMSIS/Include/core_cm0.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. 774:Drivers/CMSIS/Include/core_cm0.h **** \param [in] PriorityGroup Used priority group. 775:Drivers/CMSIS/Include/core_cm0.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). 776:Drivers/CMSIS/Include/core_cm0.h **** \param [in] SubPriority Subpriority value (starting from 0). 777:Drivers/CMSIS/Include/core_cm0.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP 778:Drivers/CMSIS/Include/core_cm0.h **** */ 779:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin 780:Drivers/CMSIS/Include/core_cm0.h **** { 781:Drivers/CMSIS/Include/core_cm0.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 782:Drivers/CMSIS/Include/core_cm0.h **** uint32_t PreemptPriorityBits; 783:Drivers/CMSIS/Include/core_cm0.h **** uint32_t SubPriorityBits; 784:Drivers/CMSIS/Include/core_cm0.h **** 785:Drivers/CMSIS/Include/core_cm0.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 786:Drivers/CMSIS/Include/core_cm0.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 787:Drivers/CMSIS/Include/core_cm0.h **** 788:Drivers/CMSIS/Include/core_cm0.h **** return ( 789:Drivers/CMSIS/Include/core_cm0.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits ARM GAS /tmp/cceoVgjg.s page 38 790:Drivers/CMSIS/Include/core_cm0.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 791:Drivers/CMSIS/Include/core_cm0.h **** ); 792:Drivers/CMSIS/Include/core_cm0.h **** } 793:Drivers/CMSIS/Include/core_cm0.h **** 794:Drivers/CMSIS/Include/core_cm0.h **** 795:Drivers/CMSIS/Include/core_cm0.h **** /** 796:Drivers/CMSIS/Include/core_cm0.h **** \brief Decode Priority 797:Drivers/CMSIS/Include/core_cm0.h **** \details Decodes an interrupt priority value with a given priority group to 798:Drivers/CMSIS/Include/core_cm0.h **** preemptive priority value and subpriority value. 799:Drivers/CMSIS/Include/core_cm0.h **** In case of a conflict between priority grouping and available 800:Drivers/CMSIS/Include/core_cm0.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. 801:Drivers/CMSIS/Include/core_cm0.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC 802:Drivers/CMSIS/Include/core_cm0.h **** \param [in] PriorityGroup Used priority group. 803:Drivers/CMSIS/Include/core_cm0.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). 804:Drivers/CMSIS/Include/core_cm0.h **** \param [out] pSubPriority Subpriority value (starting from 0). 805:Drivers/CMSIS/Include/core_cm0.h **** */ 806:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons 807:Drivers/CMSIS/Include/core_cm0.h **** { 808:Drivers/CMSIS/Include/core_cm0.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used 809:Drivers/CMSIS/Include/core_cm0.h **** uint32_t PreemptPriorityBits; 810:Drivers/CMSIS/Include/core_cm0.h **** uint32_t SubPriorityBits; 811:Drivers/CMSIS/Include/core_cm0.h **** 812:Drivers/CMSIS/Include/core_cm0.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV 813:Drivers/CMSIS/Include/core_cm0.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint 814:Drivers/CMSIS/Include/core_cm0.h **** 815:Drivers/CMSIS/Include/core_cm0.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 816:Drivers/CMSIS/Include/core_cm0.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 817:Drivers/CMSIS/Include/core_cm0.h **** } 818:Drivers/CMSIS/Include/core_cm0.h **** 819:Drivers/CMSIS/Include/core_cm0.h **** 820:Drivers/CMSIS/Include/core_cm0.h **** 821:Drivers/CMSIS/Include/core_cm0.h **** /** 822:Drivers/CMSIS/Include/core_cm0.h **** \brief Set Interrupt Vector 823:Drivers/CMSIS/Include/core_cm0.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. 824:Drivers/CMSIS/Include/core_cm0.h **** The interrupt number can be positive to specify a device specific interrupt, 825:Drivers/CMSIS/Include/core_cm0.h **** or negative to specify a processor exception. 826:Drivers/CMSIS/Include/core_cm0.h **** Address 0 must be mapped to SRAM. 827:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Interrupt number 828:Drivers/CMSIS/Include/core_cm0.h **** \param [in] vector Address of interrupt handler function 829:Drivers/CMSIS/Include/core_cm0.h **** */ 830:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) 831:Drivers/CMSIS/Include/core_cm0.h **** { 832:Drivers/CMSIS/Include/core_cm0.h **** uint32_t *vectors = (uint32_t *)0x0U; 833:Drivers/CMSIS/Include/core_cm0.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; 834:Drivers/CMSIS/Include/core_cm0.h **** } 835:Drivers/CMSIS/Include/core_cm0.h **** 836:Drivers/CMSIS/Include/core_cm0.h **** 837:Drivers/CMSIS/Include/core_cm0.h **** /** 838:Drivers/CMSIS/Include/core_cm0.h **** \brief Get Interrupt Vector 839:Drivers/CMSIS/Include/core_cm0.h **** \details Reads an interrupt vector from interrupt vector table. 840:Drivers/CMSIS/Include/core_cm0.h **** The interrupt number can be positive to specify a device specific interrupt, 841:Drivers/CMSIS/Include/core_cm0.h **** or negative to specify a processor exception. 842:Drivers/CMSIS/Include/core_cm0.h **** \param [in] IRQn Interrupt number. 843:Drivers/CMSIS/Include/core_cm0.h **** \return Address of interrupt handler function 844:Drivers/CMSIS/Include/core_cm0.h **** */ 845:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) 846:Drivers/CMSIS/Include/core_cm0.h **** { ARM GAS /tmp/cceoVgjg.s page 39 847:Drivers/CMSIS/Include/core_cm0.h **** uint32_t *vectors = (uint32_t *)0x0U; 848:Drivers/CMSIS/Include/core_cm0.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; 849:Drivers/CMSIS/Include/core_cm0.h **** } 850:Drivers/CMSIS/Include/core_cm0.h **** 851:Drivers/CMSIS/Include/core_cm0.h **** 852:Drivers/CMSIS/Include/core_cm0.h **** /** 853:Drivers/CMSIS/Include/core_cm0.h **** \brief System Reset 854:Drivers/CMSIS/Include/core_cm0.h **** \details Initiates a system reset request to reset the MCU. 855:Drivers/CMSIS/Include/core_cm0.h **** */ 856:Drivers/CMSIS/Include/core_cm0.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) 857:Drivers/CMSIS/Include/core_cm0.h **** { 858:Drivers/CMSIS/Include/core_cm0.h **** __DSB(); /* Ensure all outstanding memor 859:Drivers/CMSIS/Include/core_cm0.h **** buffered write are completed 860:Drivers/CMSIS/Include/core_cm0.h **** SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 260 .loc 2 860 0 261 0004 034B ldr r3, .L16 262 0006 044A ldr r2, .L16+4 263 0008 DA60 str r2, [r3, #12] 264 .LBB54: 265 .LBB55: 266 .loc 3 879 0 267 .syntax divided 268 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 269 000a BFF34F8F dsb 0xF 270 @ 0 "" 2 271 .thumb 272 .syntax unified 273 .L15: 274 .LBE55: 275 .LBE54: 861:Drivers/CMSIS/Include/core_cm0.h **** SCB_AIRCR_SYSRESETREQ_Msk); 862:Drivers/CMSIS/Include/core_cm0.h **** __DSB(); /* Ensure completion of memory 863:Drivers/CMSIS/Include/core_cm0.h **** 864:Drivers/CMSIS/Include/core_cm0.h **** for(;;) /* wait until reset */ 865:Drivers/CMSIS/Include/core_cm0.h **** { 866:Drivers/CMSIS/Include/core_cm0.h **** __NOP(); 276 .loc 2 866 0 277 .syntax divided 278 @ 866 "Drivers/CMSIS/Include/core_cm0.h" 1 279 000e C046 nop 280 @ 0 "" 2 281 .thumb 282 .syntax unified 283 0010 FDE7 b .L15 284 .L17: 285 0012 C046 .align 2 286 .L16: 287 0014 00ED00E0 .word -536810240 288 0018 0400FA05 .word 100270084 289 .LBE51: 290 .LBE50: 291 .cfi_endproc 292 .LFE43: 294 .section .text.HAL_SYSTICK_Config,"ax",%progbits 295 .align 1 296 .global HAL_SYSTICK_Config 297 .syntax unified ARM GAS /tmp/cceoVgjg.s page 40 298 .code 16 299 .thumb_func 300 .fpu softvfp 302 HAL_SYSTICK_Config: 303 .LFB44: 183:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* System Reset */ 184:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_SystemReset(); 185:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 186:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 187:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 188:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. 189:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. 190:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. 191:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. 192:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * - 1 Function failed. 193:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 194:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 195:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 304 .loc 1 195 0 305 .cfi_startproc 306 @ args = 0, pretend = 0, frame = 0 307 @ frame_needed = 0, uses_anonymous_args = 0 308 @ link register save eliminated. 309 .LVL17: 310 .LBB56: 311 .LBB57: 867:Drivers/CMSIS/Include/core_cm0.h **** } 868:Drivers/CMSIS/Include/core_cm0.h **** } 869:Drivers/CMSIS/Include/core_cm0.h **** 870:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of CMSIS_Core_NVICFunctions */ 871:Drivers/CMSIS/Include/core_cm0.h **** 872:Drivers/CMSIS/Include/core_cm0.h **** 873:Drivers/CMSIS/Include/core_cm0.h **** /* ########################## FPU functions #################################### */ 874:Drivers/CMSIS/Include/core_cm0.h **** /** 875:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_Core_FunctionInterface 876:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions 877:Drivers/CMSIS/Include/core_cm0.h **** \brief Function that provides FPU type. 878:Drivers/CMSIS/Include/core_cm0.h **** @{ 879:Drivers/CMSIS/Include/core_cm0.h **** */ 880:Drivers/CMSIS/Include/core_cm0.h **** 881:Drivers/CMSIS/Include/core_cm0.h **** /** 882:Drivers/CMSIS/Include/core_cm0.h **** \brief get FPU type 883:Drivers/CMSIS/Include/core_cm0.h **** \details returns the FPU type 884:Drivers/CMSIS/Include/core_cm0.h **** \returns 885:Drivers/CMSIS/Include/core_cm0.h **** - \b 0: No FPU 886:Drivers/CMSIS/Include/core_cm0.h **** - \b 1: Single precision FPU 887:Drivers/CMSIS/Include/core_cm0.h **** - \b 2: Double + Single precision FPU 888:Drivers/CMSIS/Include/core_cm0.h **** */ 889:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) 890:Drivers/CMSIS/Include/core_cm0.h **** { 891:Drivers/CMSIS/Include/core_cm0.h **** return 0U; /* No FPU */ 892:Drivers/CMSIS/Include/core_cm0.h **** } 893:Drivers/CMSIS/Include/core_cm0.h **** 894:Drivers/CMSIS/Include/core_cm0.h **** 895:Drivers/CMSIS/Include/core_cm0.h **** /*@} end of CMSIS_Core_FpuFunctions */ 896:Drivers/CMSIS/Include/core_cm0.h **** 897:Drivers/CMSIS/Include/core_cm0.h **** ARM GAS /tmp/cceoVgjg.s page 41 898:Drivers/CMSIS/Include/core_cm0.h **** 899:Drivers/CMSIS/Include/core_cm0.h **** /* ################################## SysTick function ######################################## 900:Drivers/CMSIS/Include/core_cm0.h **** /** 901:Drivers/CMSIS/Include/core_cm0.h **** \ingroup CMSIS_Core_FunctionInterface 902:Drivers/CMSIS/Include/core_cm0.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 903:Drivers/CMSIS/Include/core_cm0.h **** \brief Functions that configure the System. 904:Drivers/CMSIS/Include/core_cm0.h **** @{ 905:Drivers/CMSIS/Include/core_cm0.h **** */ 906:Drivers/CMSIS/Include/core_cm0.h **** 907:Drivers/CMSIS/Include/core_cm0.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) 908:Drivers/CMSIS/Include/core_cm0.h **** 909:Drivers/CMSIS/Include/core_cm0.h **** /** 910:Drivers/CMSIS/Include/core_cm0.h **** \brief System Tick Configuration 911:Drivers/CMSIS/Include/core_cm0.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. 912:Drivers/CMSIS/Include/core_cm0.h **** Counter is in free running mode to generate periodic interrupts. 913:Drivers/CMSIS/Include/core_cm0.h **** \param [in] ticks Number of ticks between two interrupts. 914:Drivers/CMSIS/Include/core_cm0.h **** \return 0 Function succeeded. 915:Drivers/CMSIS/Include/core_cm0.h **** \return 1 Function failed. 916:Drivers/CMSIS/Include/core_cm0.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the 917:Drivers/CMSIS/Include/core_cm0.h **** function SysTick_Config is not included. In this case, the file device. 918:Drivers/CMSIS/Include/core_cm0.h **** must contain a vendor-specific implementation of this function. 919:Drivers/CMSIS/Include/core_cm0.h **** */ 920:Drivers/CMSIS/Include/core_cm0.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 921:Drivers/CMSIS/Include/core_cm0.h **** { 922:Drivers/CMSIS/Include/core_cm0.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 312 .loc 2 922 0 313 0000 0138 subs r0, r0, #1 314 .LVL18: 315 0002 0A4B ldr r3, .L21 316 0004 9842 cmp r0, r3 317 0006 0FD8 bhi .L20 923:Drivers/CMSIS/Include/core_cm0.h **** { 924:Drivers/CMSIS/Include/core_cm0.h **** return (1UL); /* Reload value impossible */ 925:Drivers/CMSIS/Include/core_cm0.h **** } 926:Drivers/CMSIS/Include/core_cm0.h **** 927:Drivers/CMSIS/Include/core_cm0.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 318 .loc 2 927 0 319 0008 094A ldr r2, .L21+4 320 000a 5060 str r0, [r2, #4] 321 .LVL19: 322 .LBB58: 323 .LBB59: 739:Drivers/CMSIS/Include/core_cm0.h **** (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 324 .loc 2 739 0 325 000c 0948 ldr r0, .L21+8 326 .LVL20: 327 000e 036A ldr r3, [r0, #32] 328 0010 1B02 lsls r3, r3, #8 329 0012 1B0A lsrs r3, r3, #8 330 0014 C021 movs r1, #192 331 0016 0906 lsls r1, r1, #24 332 0018 0B43 orrs r3, r1 333 001a 0362 str r3, [r0, #32] 334 .LVL21: 335 .LBE59: 336 .LBE58: 928:Drivers/CMSIS/Include/core_cm0.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int ARM GAS /tmp/cceoVgjg.s page 42 929:Drivers/CMSIS/Include/core_cm0.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val 337 .loc 2 929 0 338 001c 0023 movs r3, #0 339 001e 9360 str r3, [r2, #8] 930:Drivers/CMSIS/Include/core_cm0.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 340 .loc 2 930 0 341 0020 0733 adds r3, r3, #7 342 0022 1360 str r3, [r2] 931:Drivers/CMSIS/Include/core_cm0.h **** SysTick_CTRL_TICKINT_Msk | 932:Drivers/CMSIS/Include/core_cm0.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi 933:Drivers/CMSIS/Include/core_cm0.h **** return (0UL); /* Function successful */ 343 .loc 2 933 0 344 0024 0020 movs r0, #0 345 .LVL22: 346 .L18: 347 .LBE57: 348 .LBE56: 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** return SysTick_Config(TicksNumb); 197:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 349 .loc 1 197 0 350 @ sp needed 351 0026 7047 bx lr 352 .LVL23: 353 .L20: 354 .LBB61: 355 .LBB60: 924:Drivers/CMSIS/Include/core_cm0.h **** } 356 .loc 2 924 0 357 0028 0120 movs r0, #1 358 .LVL24: 359 .LBE60: 360 .LBE61: 196:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** return SysTick_Config(TicksNumb); 361 .loc 1 196 0 362 002a FCE7 b .L18 363 .L22: 364 .align 2 365 .L21: 366 002c FFFFFF00 .word 16777215 367 0030 10E000E0 .word -536813552 368 0034 00ED00E0 .word -536810240 369 .cfi_endproc 370 .LFE44: 372 .section .text.HAL_NVIC_GetPriority,"ax",%progbits 373 .align 1 374 .global HAL_NVIC_GetPriority 375 .syntax unified 376 .code 16 377 .thumb_func 378 .fpu softvfp 380 HAL_NVIC_GetPriority: 381 .LFB45: 198:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 199:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @} 200:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 201:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 202:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions ARM GAS /tmp/cceoVgjg.s page 43 203:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Cortex control functions 204:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * 205:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** @verbatim 206:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 207:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ##### Peripheral Control functions ##### 208:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ============================================================================== 209:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** [..] 210:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX 211:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** (NVIC, SYSTICK) functionalities. 212:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 213:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 214:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** @endverbatim 215:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @{ 216:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 217:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 218:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 219:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 220:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. 221:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number. 222:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 223:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 224:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 225:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 226:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) 227:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 382 .loc 1 227 0 383 .cfi_startproc 384 @ args = 0, pretend = 0, frame = 0 385 @ frame_needed = 0, uses_anonymous_args = 0 386 @ link register save eliminated. 387 .LVL25: 388 .LBB64: 389 .LBB65: 757:Drivers/CMSIS/Include/core_cm0.h **** { 390 .loc 2 757 0 391 0000 0028 cmp r0, #0 392 0002 0CDB blt .L24 759:Drivers/CMSIS/Include/core_cm0.h **** } 393 .loc 2 759 0 394 0004 8308 lsrs r3, r0, #2 395 0006 C033 adds r3, r3, #192 396 0008 9B00 lsls r3, r3, #2 397 000a 0E4A ldr r2, .L26 398 000c 9B58 ldr r3, [r3, r2] 399 000e 0322 movs r2, #3 400 0010 1040 ands r0, r2 401 .LVL26: 402 0012 C000 lsls r0, r0, #3 403 0014 C340 lsrs r3, r3, r0 404 0016 9B09 lsrs r3, r3, #6 405 0018 0320 movs r0, #3 406 001a 1840 ands r0, r3 407 .LVL27: 408 .L23: 409 .LBE65: 410 .LBE64: 228:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ ARM GAS /tmp/cceoVgjg.s page 44 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** return NVIC_GetPriority(IRQn); 230:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 411 .loc 1 230 0 412 @ sp needed 413 001c 7047 bx lr 414 .LVL28: 415 .L24: 416 .LBB67: 417 .LBB66: 763:Drivers/CMSIS/Include/core_cm0.h **** } 418 .loc 2 763 0 419 001e C0B2 uxtb r0, r0 420 0020 0F23 movs r3, #15 421 0022 0340 ands r3, r0 422 0024 083B subs r3, r3, #8 423 0026 9B08 lsrs r3, r3, #2 424 0028 0633 adds r3, r3, #6 425 002a 9B00 lsls r3, r3, #2 426 002c 064A ldr r2, .L26+4 427 002e 9446 mov ip, r2 428 0030 6344 add r3, r3, ip 429 0032 5B68 ldr r3, [r3, #4] 430 0034 0322 movs r2, #3 431 0036 1040 ands r0, r2 432 .LVL29: 433 0038 C000 lsls r0, r0, #3 434 003a C340 lsrs r3, r3, r0 435 003c 9B09 lsrs r3, r3, #6 436 003e 0320 movs r0, #3 437 0040 1840 ands r0, r3 438 .LVL30: 439 .LBE66: 440 .LBE67: 229:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 441 .loc 1 229 0 442 0042 EBE7 b .L23 443 .L27: 444 .align 2 445 .L26: 446 0044 00E100E0 .word -536813312 447 0048 00ED00E0 .word -536810240 448 .cfi_endproc 449 .LFE45: 451 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits 452 .align 1 453 .global HAL_NVIC_SetPendingIRQ 454 .syntax unified 455 .code 16 456 .thumb_func 457 .fpu softvfp 459 HAL_NVIC_SetPendingIRQ: 460 .LFB46: 231:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 232:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 233:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. 234:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number 235:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration ARM GAS /tmp/cceoVgjg.s page 45 236:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 237:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 238:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 239:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 240:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 461 .loc 1 240 0 462 .cfi_startproc 463 @ args = 0, pretend = 0, frame = 0 464 @ frame_needed = 0, uses_anonymous_args = 0 465 @ link register save eliminated. 466 .LVL31: 467 .LBB68: 468 .LBB69: 699:Drivers/CMSIS/Include/core_cm0.h **** { 469 .loc 2 699 0 470 0000 0028 cmp r0, #0 471 0002 07DB blt .L28 701:Drivers/CMSIS/Include/core_cm0.h **** } 472 .loc 2 701 0 473 0004 1F23 movs r3, #31 474 0006 1840 ands r0, r3 475 .LVL32: 476 0008 1E3B subs r3, r3, #30 477 000a 8340 lsls r3, r3, r0 478 000c 0249 ldr r1, .L30 479 000e 8022 movs r2, #128 480 0010 5200 lsls r2, r2, #1 481 0012 8B50 str r3, [r1, r2] 482 .LVL33: 483 .L28: 484 .LBE69: 485 .LBE68: 241:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 242:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 243:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 244:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Set interrupt pending */ 245:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); 246:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 486 .loc 1 246 0 487 @ sp needed 488 0014 7047 bx lr 489 .L31: 490 0016 C046 .align 2 491 .L30: 492 0018 00E100E0 .word -536813312 493 .cfi_endproc 494 .LFE46: 496 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits 497 .align 1 498 .global HAL_NVIC_GetPendingIRQ 499 .syntax unified 500 .code 16 501 .thumb_func 502 .fpu softvfp 504 HAL_NVIC_GetPendingIRQ: 505 .LFB47: 247:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** ARM GAS /tmp/cceoVgjg.s page 46 248:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 249:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC 250:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). 251:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number. 252:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 253:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 254:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. 255:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * - 1 Interrupt status is pending. 256:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 257:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 258:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 506 .loc 1 258 0 507 .cfi_startproc 508 @ args = 0, pretend = 0, frame = 0 509 @ frame_needed = 0, uses_anonymous_args = 0 510 @ link register save eliminated. 511 .LVL34: 512 .LBB70: 513 .LBB71: 680:Drivers/CMSIS/Include/core_cm0.h **** { 514 .loc 2 680 0 515 0000 0028 cmp r0, #0 516 0002 09DB blt .L34 682:Drivers/CMSIS/Include/core_cm0.h **** } 517 .loc 2 682 0 518 0004 054A ldr r2, .L35 519 0006 8023 movs r3, #128 520 0008 5B00 lsls r3, r3, #1 521 000a D358 ldr r3, [r2, r3] 522 000c 1F22 movs r2, #31 523 000e 1040 ands r0, r2 524 .LVL35: 525 0010 C340 lsrs r3, r3, r0 526 0012 0120 movs r0, #1 527 0014 1840 ands r0, r3 528 .LVL36: 529 .L32: 530 .LBE71: 531 .LBE70: 259:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 260:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 261:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 262:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Return 1 if pending else 0 */ 263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); 264:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 532 .loc 1 264 0 533 @ sp needed 534 0016 7047 bx lr 535 .LVL37: 536 .L34: 537 .LBB73: 538 .LBB72: 686:Drivers/CMSIS/Include/core_cm0.h **** } 539 .loc 2 686 0 540 0018 0020 movs r0, #0 541 .LVL38: 542 .LBE72: ARM GAS /tmp/cceoVgjg.s page 47 543 .LBE73: 263:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 544 .loc 1 263 0 545 001a FCE7 b .L32 546 .L36: 547 .align 2 548 .L35: 549 001c 00E100E0 .word -536813312 550 .cfi_endproc 551 .LFE47: 553 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits 554 .align 1 555 .global HAL_NVIC_ClearPendingIRQ 556 .syntax unified 557 .code 16 558 .thumb_func 559 .fpu softvfp 561 HAL_NVIC_ClearPendingIRQ: 562 .LFB48: 265:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 266:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 267:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. 268:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param IRQn External interrupt number. 269:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration 270:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI 271:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 272:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 273:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 274:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 563 .loc 1 274 0 564 .cfi_startproc 565 @ args = 0, pretend = 0, frame = 0 566 @ frame_needed = 0, uses_anonymous_args = 0 567 @ link register save eliminated. 568 .LVL39: 569 .LBB74: 570 .LBB75: 714:Drivers/CMSIS/Include/core_cm0.h **** { 571 .loc 2 714 0 572 0000 0028 cmp r0, #0 573 0002 07DB blt .L37 716:Drivers/CMSIS/Include/core_cm0.h **** } 574 .loc 2 716 0 575 0004 1F23 movs r3, #31 576 0006 1840 ands r0, r3 577 .LVL40: 578 0008 1E3B subs r3, r3, #30 579 000a 8340 lsls r3, r3, r0 580 000c 0249 ldr r1, .L39 581 000e C022 movs r2, #192 582 0010 5200 lsls r2, r2, #1 583 0012 8B50 str r3, [r1, r2] 584 .LVL41: 585 .L37: 586 .LBE75: 587 .LBE74: 275:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ ARM GAS /tmp/cceoVgjg.s page 48 276:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 277:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 278:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Clear pending interrupt */ 279:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); 280:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 588 .loc 1 280 0 589 @ sp needed 590 0014 7047 bx lr 591 .L40: 592 0016 C046 .align 2 593 .L39: 594 0018 00E100E0 .word -536813312 595 .cfi_endproc 596 .LFE48: 598 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits 599 .align 1 600 .global HAL_SYSTICK_CLKSourceConfig 601 .syntax unified 602 .code 16 603 .thumb_func 604 .fpu softvfp 606 HAL_SYSTICK_CLKSourceConfig: 607 .LFB49: 281:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 282:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 283:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief Configures the SysTick clock source. 284:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. 285:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * This parameter can be one of the following values: 286:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock 287:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 288:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 289:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 290:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 291:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 608 .loc 1 291 0 609 .cfi_startproc 610 @ args = 0, pretend = 0, frame = 0 611 @ frame_needed = 0, uses_anonymous_args = 0 612 @ link register save eliminated. 613 .LVL42: 292:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* Check the parameters */ 293:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 294:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 614 .loc 1 294 0 615 0000 0428 cmp r0, #4 616 0002 05D0 beq .L44 295:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 296:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 297:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 298:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** else 299:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 300:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 617 .loc 1 300 0 618 0004 054A ldr r2, .L45 619 0006 1368 ldr r3, [r2] 620 0008 0421 movs r1, #4 621 000a 8B43 bics r3, r1 ARM GAS /tmp/cceoVgjg.s page 49 622 000c 1360 str r3, [r2] 623 .L41: 301:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 302:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 624 .loc 1 302 0 625 @ sp needed 626 000e 7047 bx lr 627 .L44: 296:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 628 .loc 1 296 0 629 0010 024A ldr r2, .L45 630 0012 1368 ldr r3, [r2] 631 0014 0421 movs r1, #4 632 0016 0B43 orrs r3, r1 633 0018 1360 str r3, [r2] 634 001a F8E7 b .L41 635 .L46: 636 .align 2 637 .L45: 638 001c 10E000E0 .word -536813552 639 .cfi_endproc 640 .LFE49: 642 .section .text.HAL_SYSTICK_Callback,"ax",%progbits 643 .align 1 644 .weak HAL_SYSTICK_Callback 645 .syntax unified 646 .code 16 647 .thumb_func 648 .fpu softvfp 650 HAL_SYSTICK_Callback: 651 .LFB51: 303:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 304:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 305:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. 306:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 307:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 308:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) 309:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 310:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 311:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 312:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 313:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /** 314:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @brief SYSTICK callback. 315:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** * @retval None 316:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 317:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) 318:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** { 652 .loc 1 318 0 653 .cfi_startproc 654 @ args = 0, pretend = 0, frame = 0 655 @ frame_needed = 0, uses_anonymous_args = 0 656 @ link register save eliminated. 319:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, 320:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file 321:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** */ 322:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 657 .loc 1 322 0 ARM GAS /tmp/cceoVgjg.s page 50 658 @ sp needed 659 0000 7047 bx lr 660 .cfi_endproc 661 .LFE51: 663 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits 664 .align 1 665 .global HAL_SYSTICK_IRQHandler 666 .syntax unified 667 .code 16 668 .thumb_func 669 .fpu softvfp 671 HAL_SYSTICK_IRQHandler: 672 .LFB50: 309:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** HAL_SYSTICK_Callback(); 673 .loc 1 309 0 674 .cfi_startproc 675 @ args = 0, pretend = 0, frame = 0 676 @ frame_needed = 0, uses_anonymous_args = 0 677 0000 10B5 push {r4, lr} 678 .LCFI1: 679 .cfi_def_cfa_offset 8 680 .cfi_offset 4, -8 681 .cfi_offset 14, -4 310:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** } 682 .loc 1 310 0 683 0002 FFF7FEFF bl HAL_SYSTICK_Callback 684 .LVL43: 311:Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c **** 685 .loc 1 311 0 686 @ sp needed 687 0006 10BD pop {r4, pc} 688 .cfi_endproc 689 .LFE50: 691 .text 692 .Letext0: 693 .file 4 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h" 694 .file 5 "/home/janhenrik/programme/gcc-arm-none-eabi-7-2018-q2-update/arm-none-eabi/include/machin 695 .file 6 "/home/janhenrik/programme/gcc-arm-none-eabi-7-2018-q2-update/arm-none-eabi/include/sys/_s 696 .file 7 "Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" 697 .file 8 "Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h" ARM GAS /tmp/cceoVgjg.s page 51 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f0xx_hal_cortex.c /tmp/cceoVgjg.s:16 .text.HAL_NVIC_SetPriority:0000000000000000 $t /tmp/cceoVgjg.s:23 .text.HAL_NVIC_SetPriority:0000000000000000 HAL_NVIC_SetPriority /tmp/cceoVgjg.s:116 .text.HAL_NVIC_SetPriority:000000000000005c $d /tmp/cceoVgjg.s:122 .text.HAL_NVIC_EnableIRQ:0000000000000000 $t /tmp/cceoVgjg.s:129 .text.HAL_NVIC_EnableIRQ:0000000000000000 HAL_NVIC_EnableIRQ /tmp/cceoVgjg.s:160 .text.HAL_NVIC_EnableIRQ:0000000000000014 $d /tmp/cceoVgjg.s:165 .text.HAL_NVIC_DisableIRQ:0000000000000000 $t /tmp/cceoVgjg.s:172 .text.HAL_NVIC_DisableIRQ:0000000000000000 HAL_NVIC_DisableIRQ /tmp/cceoVgjg.s:227 .text.HAL_NVIC_DisableIRQ:000000000000001c $d /tmp/cceoVgjg.s:232 .text.HAL_NVIC_SystemReset:0000000000000000 $t /tmp/cceoVgjg.s:239 .text.HAL_NVIC_SystemReset:0000000000000000 HAL_NVIC_SystemReset /tmp/cceoVgjg.s:287 .text.HAL_NVIC_SystemReset:0000000000000014 $d /tmp/cceoVgjg.s:295 .text.HAL_SYSTICK_Config:0000000000000000 $t /tmp/cceoVgjg.s:302 .text.HAL_SYSTICK_Config:0000000000000000 HAL_SYSTICK_Config /tmp/cceoVgjg.s:366 .text.HAL_SYSTICK_Config:000000000000002c $d /tmp/cceoVgjg.s:373 .text.HAL_NVIC_GetPriority:0000000000000000 $t /tmp/cceoVgjg.s:380 .text.HAL_NVIC_GetPriority:0000000000000000 HAL_NVIC_GetPriority /tmp/cceoVgjg.s:446 .text.HAL_NVIC_GetPriority:0000000000000044 $d /tmp/cceoVgjg.s:452 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 $t /tmp/cceoVgjg.s:459 .text.HAL_NVIC_SetPendingIRQ:0000000000000000 HAL_NVIC_SetPendingIRQ /tmp/cceoVgjg.s:492 .text.HAL_NVIC_SetPendingIRQ:0000000000000018 $d /tmp/cceoVgjg.s:497 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 $t /tmp/cceoVgjg.s:504 .text.HAL_NVIC_GetPendingIRQ:0000000000000000 HAL_NVIC_GetPendingIRQ /tmp/cceoVgjg.s:549 .text.HAL_NVIC_GetPendingIRQ:000000000000001c $d /tmp/cceoVgjg.s:554 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 $t /tmp/cceoVgjg.s:561 .text.HAL_NVIC_ClearPendingIRQ:0000000000000000 HAL_NVIC_ClearPendingIRQ /tmp/cceoVgjg.s:594 .text.HAL_NVIC_ClearPendingIRQ:0000000000000018 $d /tmp/cceoVgjg.s:599 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 $t /tmp/cceoVgjg.s:606 .text.HAL_SYSTICK_CLKSourceConfig:0000000000000000 HAL_SYSTICK_CLKSourceConfig /tmp/cceoVgjg.s:638 .text.HAL_SYSTICK_CLKSourceConfig:000000000000001c $d /tmp/cceoVgjg.s:643 .text.HAL_SYSTICK_Callback:0000000000000000 $t /tmp/cceoVgjg.s:650 .text.HAL_SYSTICK_Callback:0000000000000000 HAL_SYSTICK_Callback /tmp/cceoVgjg.s:664 .text.HAL_SYSTICK_IRQHandler:0000000000000000 $t /tmp/cceoVgjg.s:671 .text.HAL_SYSTICK_IRQHandler:0000000000000000 HAL_SYSTICK_IRQHandler NO UNDEFINED SYMBOLS