From edde28594fbbf44a25f0fb4229353137bca35a3e Mon Sep 17 00:00:00 2001
From: jaseg <git-bigdata-wsl-arch@jaseg.de>
Date: Fri, 13 Mar 2020 11:48:43 +0100
Subject: prettify linkmem

---
 controller/fw/src/adc.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

(limited to 'controller/fw/src')

diff --git a/controller/fw/src/adc.c b/controller/fw/src/adc.c
index 5f6b995..4801525 100644
--- a/controller/fw/src/adc.c
+++ b/controller/fw/src/adc.c
@@ -12,6 +12,7 @@ static DMA_TypeDef *const adc_dma = DMA2;
 static DMA_Stream_TypeDef *const mem_stream = DMA2_Stream1;
 static DMA_Stream_TypeDef *const adc_stream = DMA2_Stream0;
 static const int dma_adc_channel = 0;
+static const int adc_channel = 10;
 
 /* Configure ADC1 to sample channel 0. Trigger from TIM1 CC0 every 1ms. Transfer readings into alternating buffers
  * throug DMA. Enable DMA interrupts.
@@ -24,9 +25,13 @@ static const int dma_adc_channel = 0;
  * This means we can immediately start running an FFT on ADC DMA transfer complete interrupt.
  */
 void adc_init() {
-    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
+    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN | RCC_AHB1ENR_GPIOCEN;
     RCC->APB2ENR |= RCC_APB2ENR_ADC1EN | RCC_APB2ENR_TIM1EN;
 
+    /* PC0 -> ADC1.ch10 */
+    GPIOC->MODER &= ~GPIO_MODER_MODER0_Msk;
+    GPIOC->MODER |= (3<<GPIO_MODER_MODER0_Pos);
+
     adc_dma->LIFCR |= 0x3f;
     adc_stream->CR = 0; /* disable */
     while (adc_stream->CR & DMA_SxCR_EN)
@@ -45,13 +50,15 @@ void adc_init() {
 
     ADC1->CR1 = (0<<ADC_CR1_RES_Pos) | (0<<ADC_CR1_DISCNUM_Pos) | ADC_CR1_DISCEN | (0<<ADC_CR1_AWDCH_Pos);
     ADC1->CR2 = ADC_CR2_EXTEN | (0<<ADC_CR2_EXTSEL_Pos) | ADC_CR2_DMA | ADC_CR2_ADON | ADC_CR2_DDS;
+    ADC1->SQR3 = (adc_channel<<ADC_SQR3_SQ3_Pos);
+    ADC1->SQR1 = (0<<ADC_SQR1_L_Pos);
 
     TIM1->CR2 = (2<<TIM_CR2_MMS_Pos); /* Enable update event on TRGO to provide a 1ms reference to rest of system */
     TIM1->CR1 = TIM_CR1_CEN;
     TIM1->CCMR1 = (6<<TIM_CCMR1_OC1M_Pos) | (0<<TIM_CCMR1_CC1S_Pos);
     TIM1->CCER = TIM_CCER_CC1E;
-    TIM1->PSC = 84; /* 1us ticks @ f_APB2=84MHz */
-    TIM1->ARR = 1000; /* 1ms period */
+    TIM1->PSC = 84-1; /* 1us ticks @ f_APB2=84MHz */
+    TIM1->ARR = 1000-1; /* 1ms period */
     TIM1->CCR1 = 1;
     TIM1->EGR = TIM_EGR_UG;
 }
-- 
cgit