master-thesis.git - Safety Reset: My master thesis on how to reset smart meters during a cyberwar through a signal encoded in the grid frequency

Age	Commit message (Expand)	Author	Files	Lines
2020-03-10	Crypto v2 draft working	jaseg	7	-133/+205
2020-03-09	WIP cryptographic design	jaseg	8	-5/+291
2020-03-09	Fix a bunch of compiler warnings	jaseg	4	-20/+22
2020-03-09	DSSS sequence matcher works	jaseg	1	-19/+2
2020-03-09	foo	jaseg	3	-26/+35
2020-03-09	demod wip	jaseg	4	-46/+175
2020-03-09	decoding WIP	jaseg	4	-22/+117
2020-03-06	Finish DSSS demodulation stage 1	jaseg	4	-52/+68
2020-03-06	Correlator seems to be working	jaseg	5	-18/+33
2020-03-06	WIP DSSS decoding	jaseg	6	-35/+94
2020-03-05	Working on DSSS demodulator sim	jaseg	9	-34/+468
2020-03-04	Fix frequency measurement simulation	jaseg	7	-174/+289
2020-03-03	wip	jaseg	1	-14/+24
2020-03-03	working on testing	jaseg	3	-50/+172
2020-03-03	cmsis: fix exporting of fft symbols	jaseg	1	-0/+0
2020-03-02	foo	jaseg	3	-0/+0
2020-03-02	foo	jaseg	4	-0/+269
2020-03-02	Finishing up freq meas	jaseg	11	-5/+250
2020-02-28	LDPC decoder fully working	jaseg	3	-48/+108
2020-02-28	embedded ldpc decoder 50% working	jaseg	5	-62/+542
2020-02-28	ldpc decoder: wip	jaseg	1	-0/+152
2020-02-27	Add missing files	jaseg	9	-0/+620
2020-02-27	Build working	jaseg	2	-15/+9
2020-02-27	MUSL experiments	jaseg	1	-14/+21
2020-02-27	Add a bunch of deps	jaseg	10	-563/+62
2020-02-26	demo: SPI Flash interface working	jaseg	4	-53/+88
2020-02-25	Add beginnings of a SPI flash driver	jaseg	4	-37/+245
2020-02-24	controller-fw: initial jtag programming draft	jaseg	5	-13/+122
2020-02-24	Initial reset controller firmware	jaseg	4	-0/+292