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AgeCommit message (Collapse)AuthorFilesLines
2020-03-18Improve frequency measurement error detectionjaseg1-1/+1
2020-03-17Debugging signal capture subsystemjaseg5-4/+51
2020-03-16Fix serialjaseg11-40/+431
2020-03-15Add end-to-end simulationjaseg4-23/+96
2020-03-14Fixup clock configjaseg2-35/+86
2020-03-13having problems with dma m2m modejaseg2-9/+19
2020-03-13prettify linkmemjaseg1-3/+10
2020-03-11Start with integration of everythingjaseg15-82/+1680
2020-03-10Crypto v2 draft workingjaseg2-36/+64
2020-03-09WIP cryptographic designjaseg4-3/+82
2020-03-09Fix a bunch of compiler warningsjaseg2-17/+17
2020-03-09DSSS sequence matcher worksjaseg1-19/+2
2020-03-09foojaseg2-25/+34
2020-03-09demod wipjaseg2-43/+162
2020-03-09decoding WIPjaseg2-18/+79
2020-03-06Finish DSSS demodulation stage 1jaseg2-44/+46
2020-03-06Correlator seems to be workingjaseg1-12/+13
2020-03-06WIP DSSS decodingjaseg1-27/+34
2020-03-05Working on DSSS demodulator simjaseg3-0/+225
2020-03-04Fix frequency measurement simulationjaseg3-15/+70
2020-03-03working on testingjaseg1-12/+12
2020-03-02Finishing up freq measjaseg7-0/+794
2020-02-27Add missing filesjaseg9-0/+620
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