diff options
Diffstat (limited to 'ma')
| -rw-r--r-- | ma/Makefile | 1 | ||||
| -rw-r--r-- | ma/safety_reset.tex | 67 |
2 files changed, 63 insertions, 5 deletions
diff --git a/ma/Makefile b/ma/Makefile index 99bf808..e5e2b85 100644 --- a/ma/Makefile +++ b/ma/Makefile @@ -12,6 +12,7 @@ all: safety_reset.pdf safety_reset.pdf: resources/grid_freq_estimation.pdf safety_reset.pdf: resources/gps_clock_jitter_analysis.pdf +safety_reset.pdf: resources/dsss_experiments-ber.pdf %.pdf: %.tex %.bib pdflatex -shell-escape $< diff --git a/ma/safety_reset.tex b/ma/safety_reset.tex index 392bb3c..8da7960 100644 --- a/ma/safety_reset.tex +++ b/ma/safety_reset.tex @@ -1183,16 +1183,30 @@ indicates SER is related fairly monotonically to the signal-to-noise margins ins \begin{figure} \centering - \includegraphics[width=\textwidth]{../lab-windows/fig_out/dsss_gold_nbits_overview} + \includegraphics{../lab-windows/fig_out/dsss_gold_nbits_overview} \caption{ + Symbol Error Rate (SER) as a function of transmission amplitude. The line indicates the mean of several + measurements for each parameter set. The shaded areas indicate one standard deviation from the mean. Background + noise for each trial is a random segment of measured grid frequency. Background noise amplitude is the same for + all trials. Shown are four traces for four different DSSS sequence lengths. Using a 5-bit gold code, one DSSS + symbol measures 31 chips. 6 bit per symbol are 63 chips, 7 bit are 127 chips and 8 bit 255 chips. This + simulation uses a decimation of 10, which corresponds to an $1 \text{s}$ chip length at our $10 \text{Hz}$ grid + frequency sampling rate. At 5 bit per symbol, one symbol takes $31 \text{s}$ and one bit takes $6.2 \text{s}$ + amortized. At 8 bit one symbol takes $255 \text{s} = 4 \text{min} 15 \text{s}$ and one bit takes $31.9 \text{s}$ + amortized. Here, slower transmission speed buys coding gain. All else being the same this allows for a decrease + in transmission power. } \label{dsss_gold_nbits_overview} \end{figure} \begin{figure} \centering - \includegraphics[width=\textwidth]{../lab-windows/fig_out/dsss_gold_nbits_sensitivity} + \includegraphics{../lab-windows/fig_out/dsss_gold_nbits_sensitivity} \caption{ + Amplitude at a SER of 0.5\ in mHz depending on symbol length. Here we can observe an increase of sensitivity + with increasing symbol length, but we can clearly see diminishing returns above 6 bit (63 chips). Considering + that each bit roughly doubles overall transmission time for a given data length it seems lower bit counts are + preferrable if the necessary transmitter power can be realized. } \label{dsss_gold_nbits_sensitivity} \end{figure} @@ -1200,20 +1214,38 @@ indicates SER is related fairly monotonically to the signal-to-noise margins ins \begin{figure} \begin{subfigure}{\textwidth} \centering - \includegraphics[width=\textwidth]{../lab-windows/fig_out/dsss_thf_amplitude_5678} + \includegraphics{../lab-windows/fig_out/dsss_thf_amplitude_5678} \label{dsss_thf_amplitude_5678} \caption{ + \footnotesize SER vs.\ amplitude graph similar to fig.\ \ref{dsss_gold_nbits_overview} with dependence on + threshold factor color-coded. Each graph shows traces for a single DSSS symbol length. } \end{subfigure} +\end{figure} +\begin{figure} + \ContinuedFloat \begin{subfigure}{\textwidth} \centering - \includegraphics[width=\textwidth]{../lab-windows/fig_out/dsss_thf_sensitivity_5678} + \includegraphics{../lab-windows/fig_out/dsss_thf_sensitivity_5678} \label{dsss_thf_sensitivity_5678} \caption{ + \footnotesize Graphs of amplitude at $SER=0.5$ for each symbol length as well as asymptotic SER for large + amplitudes. Areas shaded red indicate that $SER=0.5$ was not reached for any amplitude in the simulated + range. We can observe that smaller symbol lengths favor lower threshold factors, and that optimal threshold + factors for all symbol lengths are between $4.0$ and $5.0$. } \end{subfigure} \caption{ - } + Dependence of demodulator sensitivity on the threshold factor used for correlation peak detection in our + DSSS demodulator. This is an empirically-determined parameter specific to our demodulation algorithm. At low + threshold factors our classifier yields lots of spurious peaks that have to be thrown out by our maximum + likelihood estimator. These spurious peaks have a random time distribution and thus do not pose much of a + challenge to our MLE but at very low threshold factors the number of spurious peaks slows down decoding and + does still clog our MLE's internal size-limited candidate lists which leads to failed decodings. At very + high threshold factors decoding performance suffers greatly since many valid correlation peaks get + incorrectly ignored. The glitches at medium threshold factors in the 7- and 8-bit graphs are artifacts of + our prototype decoding algorithm that we have not fixed in the prototype implementation since we wanted to + focus on the final C version.} \label{dsss_thf_sensitivity} \end{figure} @@ -1223,16 +1255,31 @@ indicates SER is related fairly monotonically to the signal-to-noise margins ins \includegraphics[width=\textwidth]{../lab-windows/fig_out/chip_duration_sensitivity_5} \label{chip_duration_sensitivity_5} \caption{ + 5 bit Gold code } \end{subfigure} +\end{figure} +\begin{figure} + \ContinuedFloat \begin{subfigure}{\textwidth} \centering \includegraphics[width=\textwidth]{../lab-windows/fig_out/chip_duration_sensitivity_6} \label{chip_duration_sensitivity_6} \caption{ + 6 bit Gold code } \end{subfigure} \caption{ + Dependence of demodulator sensitivity on DSSS chip duration. Due to computational constraints this simulation is + limited to 5 bit and 6 bit DSSS sequences. There is a clearly visible sensitivity maximum at fairly short chip + lengths around $0.2 \text{s}$. Short chip durations shift the entire transmission band up in frequency. In fig.\ + \ref{freq_meas_spectrum} we can see that noise energy is mostly concentrated at lower frequencies, so shifting + our signal up in frequency will reduce the amount of noise the decoder sees behind the correlator by shifting + the band of interest into a lower-noise spectral region. For a practical implementation chip duration is limited + by physical factors such as the maximum modulation slew rate ($\frac{\text{d}P}{\text{d}t}$), the maximum + Rate-Of-Change-Of-Frequency (ROCOF, $\frac{\text{d}f}{\text{d}t}$) the grid can tolerate and possible inertial + effects limiting response of frequency to load changes at certain load levels. + % FIXME are these inertial effects likely? Ask an expert. } \label{chip_duration_sensitivity} \end{figure} @@ -1243,16 +1290,25 @@ indicates SER is related fairly monotonically to the signal-to-noise margins ins \includegraphics[width=\textwidth]{../lab-windows/fig_out/chip_duration_sensitivity_cmp_meas_6} \label{chip_duration_sensitivity_cmp_meas_6} \caption{ + Simulation using baseline frequency data from actual measurements. } \end{subfigure} +\end{figure} +\begin{figure} + \ContinuedFloat \begin{subfigure}{\textwidth} \centering \includegraphics[width=\textwidth]{../lab-windows/fig_out/chip_duration_sensitivity_cmp_synth_6} \label{chip_duration_sensitivity_cmp_synth_6} \caption{ + Simulation using synthetic frequency data. } \end{subfigure} \caption{ + Chip duration/sensitivity simulation results like in fig.\ \ref{chip_duration_sensitivity} compared between a + simulation using measured frequency data like previous graphs and one using artificially generated noise. There + is almost no visible difference indicating that we have found a good model of reality in our noise synthesizer, + but also that real grid frequency behaves like a frequency-shaped gaussian noise process. } \label{chip_duration_sensitivity_cmp} \end{figure} @@ -1355,6 +1411,7 @@ correctly configure than it is to simply use separate hardware and secure the in \includenotebook{Grid frequency estimation}{grid_freq_estimation} \includenotebook{Frequency sensor clock stability analysis}{gps_clock_jitter_analysis} +\includenotebook{DSSS modulation experiments}{dsss_experiments-ber} \chapter{Demonstrator schematics and code} |