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-rw-r--r--gm_platform/fw/.gitignore1
-rw-r--r--gm_platform/fw/adc.c25
-rw-r--r--gm_platform/fw/adc.h2
-rw-r--r--gm_platform/fw/cobs.c95
-rw-r--r--gm_platform/fw/cobs.h2
-rw-r--r--gm_platform/fw/global.h2
-rwxr-xr-xgm_platform/fw/main.binbin6552 -> 6736 bytes
-rw-r--r--gm_platform/fw/main.c3
-rwxr-xr-xgm_platform/fw/main.elfbin180992 -> 181756 bytes
-rw-r--r--gm_platform/fw/main.hex789
-rw-r--r--gm_platform/fw/main.lst6066
-rw-r--r--gm_platform/fw/main.map484
-rw-r--r--gm_platform/fw/serial.c50
-rw-r--r--gm_platform/fw/serial.h5
-rw-r--r--gm_platform/fw/test.py41
-rw-r--r--gm_platform/platform/platform.sch2
16 files changed, 3858 insertions, 3709 deletions
diff --git a/gm_platform/fw/.gitignore b/gm_platform/fw/.gitignore
new file mode 100644
index 0000000..ea25847
--- /dev/null
+++ b/gm_platform/fw/.gitignore
@@ -0,0 +1 @@
+*.expand
diff --git a/gm_platform/fw/adc.c b/gm_platform/fw/adc.c
index 547089b..2a33171 100644
--- a/gm_platform/fw/adc.c
+++ b/gm_platform/fw/adc.c
@@ -16,11 +16,14 @@
*/
#include "adc.h"
+#include "serial.h"
#include <stdbool.h>
#include <stdlib.h>
+#include <assert.h>
-volatile uint16_t adc_buf[ADC_BUFSIZE];
+volatile uint16_t adc_buf[100]; /* 100ms worth of data */
+uint32_t usart_overruns = 0;
static void adc_dma_init(int burstlen);
static void adc_timer_init(int psc, int ivl);
@@ -56,9 +59,6 @@ void adc_configure_scope_mode(int sampling_interval_ns) {
adc_timer_init(12/*250ns/tick*/, cycles);
}
-/* FIXME figure out the proper place to configure this. */
-#define ADC_TIMER_INTERVAL_US 20
-
static void adc_dma_init(int burstlen) {
/* Configure DMA 1 Channel 1 to get rid of all the data */
DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
@@ -70,11 +70,12 @@ static void adc_dma_init(int burstlen) {
| (1<<DMA_CCR_MSIZE_Pos) /* 16 bit */
| (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
| DMA_CCR_MINC
+ | DMA_CCR_HTIE /* Enable half-transfer interrupt. */
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
- /* triggered on transfer completion. We use this to process the ADC data */
+ /* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
+ NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5);
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
}
@@ -99,9 +100,21 @@ static void gdb_dump(void) {
}
void DMA1_Channel1_IRQHandler(void) {
+ uint32_t isr = DMA1->ISR;
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
+
gdb_dump();
+ static_assert(ARRAY_LEN(adc_buf) % 2 == 0, "ADC_BUFSIZE must be even for half-transfer uart tx logic to work");
+
+ int rc;
+ if (isr & DMA_ISR_HTIF2) /* half-transfer */
+ rc = usart_send_packet_nonblocking((uint8_t *)adc_buf, sizeof(adc_buf)/2);
+ else /* end of transfer */
+ rc = usart_send_packet_nonblocking((uint8_t *)adc_buf + ARRAY_LEN(adc_buf)/2, sizeof(adc_buf)/2);
+
+ if (rc)
+ usart_overruns++;
/*
static int debug_buf_pos = 0;
diff --git a/gm_platform/fw/adc.h b/gm_platform/fw/adc.h
index c526858..0818169 100644
--- a/gm_platform/fw/adc.h
+++ b/gm_platform/fw/adc.h
@@ -20,8 +20,6 @@
#include "global.h"
-extern volatile uint16_t adc_buf[ADC_BUFSIZE];
-
void adc_init(void);
void adc_configure_scope_mode(int sampling_interval_ns);
diff --git a/gm_platform/fw/cobs.c b/gm_platform/fw/cobs.c
index 22dcac0..041dd8f 100644
--- a/gm_platform/fw/cobs.c
+++ b/gm_platform/fw/cobs.c
@@ -2,87 +2,11 @@
#include "serial.h"
#include "cobs.h"
-/*@ requires \valid(dst + (0..dstlen-1));
- @ requires \valid_read(src + (0..srclen-1));
- @ requires \separated(dst + (0..dstlen-1), src + (0..srclen-1));
- @
- @ behavior valid:
- @ assumes 0 <= srclen <= 254;
- @ assumes 0 <= dstlen <= 65535;
- @ assumes dstlen >= srclen+2;
- @ assigns dst[0..srclen+1];
- @ ensures \forall integer i; (0 <= i < srclen && \old(src[i]) != 0) ==> dst[i+1] == src[i];
- @ ensures \result == srclen+2;
- @ ensures \forall integer i; 0 <= i <= srclen ==> dst[i] != 0;
- @ ensures dst[srclen+1] == 0;
- @
- @ behavior invalid:
- @ assumes srclen < 0 || srclen > 254
- @ || dstlen < 0 || dstlen > 65535
- @ || dstlen < srclen+2;
- @ assigns \nothing;
- @ ensures \result == -1;
- @
- @ complete behaviors;
- @ disjoint behaviors;
- @*/
-ssize_t cobs_encode(char *dst, size_t dstlen, char *src, size_t srclen) {
- if (dstlen > 65535 || srclen > 254)
- return -1;
- //@ assert 0 <= dstlen <= 65535 && 0 <= srclen <= 254;
-
- if (dstlen < srclen+2)
- return -1;
- //@ assert 0 <= srclen < srclen+2 <= dstlen;
-
- size_t p = 0;
- /*@ loop invariant 0 <= p <= srclen+1;
- @ loop invariant \forall integer i; 0 <= i < p ==> dst[i] != 0;
- @ loop invariant \forall integer i; 0 < i < p ==> (src[i-1] != 0 ==> dst[i] == src[i-1]);
- @ loop assigns p, dst[0..srclen+1];
- @ loop variant srclen-p+1;
- @*/
- while (p <= srclen) {
-
- char val;
- if (p != 0 && src[p-1] != 0) {
- val = src[p-1];
-
- } else {
- size_t q = p;
- /*@ loop invariant 0 <= p <= q <= srclen;
- @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
- @ loop assigns q;
- @ loop variant srclen-q;
- @*/
- while (q < srclen && src[q] != 0)
- q++;
- //@ assert q == srclen || src[q] == 0;
- //@ assert q <= srclen <= 254;
- val = (char)q-p+1;
- //@ assert val != 0;
- }
-
- dst[p] = val;
- p++;
- }
-
- dst[p] = 0;
- //@ assert p == srclen+1;
-
- return srclen+2;
-}
-
-int cobs_encode_usart(char *src, size_t srclen) {
+int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) {
if (srclen > 254)
return -1;
- //@ assert 0 <= srclen <= 254;
size_t p = 0;
- /*@ loop invariant 0 <= p <= srclen+1;
- @ loop assigns p;
- @ loop variant srclen-p+1;
- @*/
while (p <= srclen) {
char val;
@@ -91,25 +15,20 @@ int cobs_encode_usart(char *src, size_t srclen) {
} else {
size_t q = p;
- /*@ loop invariant 0 <= p <= q <= srclen;
- @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
- @ loop assigns q;
- @ loop variant srclen-q;
- @*/
while (q < srclen && src[q] != 0)
q++;
- //@ assert q == srclen || src[q] == 0;
- //@ assert q <= srclen <= 254;
val = (char)q-p+1;
- //@ assert val != 0;
}
- usart_putc(val);
+ int rv = output(val);
+ if (rv)
+ return rv;
p++;
}
- usart_putc(0);
- //@ assert p == srclen+1;
+ int rv = output(0);
+ if (rv)
+ return rv;
return 0;
}
diff --git a/gm_platform/fw/cobs.h b/gm_platform/fw/cobs.h
index 40f7955..8c84ca4 100644
--- a/gm_platform/fw/cobs.h
+++ b/gm_platform/fw/cobs.h
@@ -15,7 +15,7 @@ struct cobs_decode_state {
ssize_t cobs_encode(char *dst, size_t dstlen, char *src, size_t srclen);
ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen);
-int cobs_encode_usart(char *src, size_t srclen);
+int cobs_encode_usart(int (*output)(char), char *src, size_t srclen);
void cobs_decode_incremental_initialize(struct cobs_decode_state *state);
int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src);
diff --git a/gm_platform/fw/global.h b/gm_platform/fw/global.h
index 5fedde7..7d33ca6 100644
--- a/gm_platform/fw/global.h
+++ b/gm_platform/fw/global.h
@@ -42,7 +42,7 @@
#define TS_CAL1 (*(uint16_t *)0x1FFFF7B8)
#define VREFINT_CAL (*(uint16_t *)0x1FFFF7BA)
-#define ADC_BUFSIZE 1024
+#define ARRAY_LEN(x) ((sizeof(x)/sizeof(0[x])) / ((size_t)(!(sizeof(x) % sizeof(0[x])))))
extern volatile unsigned int sys_time;
extern volatile unsigned int sys_time_seconds;
diff --git a/gm_platform/fw/main.bin b/gm_platform/fw/main.bin
index e2b0cdc..8eea2b7 100755
--- a/gm_platform/fw/main.bin
+++ b/gm_platform/fw/main.bin
Binary files differ
diff --git a/gm_platform/fw/main.c b/gm_platform/fw/main.c
index d2bc33c..3020a42 100644
--- a/gm_platform/fw/main.c
+++ b/gm_platform/fw/main.c
@@ -101,9 +101,6 @@ int main(void) {
usart_dma_init();
while (42) {
- char *data = "FOOBAR\n";
- usart_send_packet((uint8_t*)data, 8);
- for (int i=0; i<100000; i++);
//int pol = GPIOB->IDR & (1<<1); /* Sample current polarity */
//leds.error = pol ? 100 : 0;
//for (int i=0; i<10000; i++) ;
diff --git a/gm_platform/fw/main.elf b/gm_platform/fw/main.elf
index f23985f..5b20d44 100755
--- a/gm_platform/fw/main.elf
+++ b/gm_platform/fw/main.elf
Binary files differ
diff --git a/gm_platform/fw/main.hex b/gm_platform/fw/main.hex
index c23d980..39c6bb0 100644
--- a/gm_platform/fw/main.hex
+++ b/gm_platform/fw/main.hex
@@ -1,15 +1,15 @@
:020000040800F2
-:100000000010002095180008B1040008BD04000885
+:10000000001000205519000885040008910400081C
:1000100000000000000000000000000000000000E0
-:10002000000000000000000000000000C104000803
-:100030000000000000000000CD040008D904000802
-:10004000E118000800000000E1180008E1180008AD
-:10005000E1180008E1180008E1180008E11800089C
-:1000600000000000930700085D0A0008E11800087E
-:10007000E1180008E1180008E1180008000000007D
-:10008000E11800080000000000000000E11800086E
-:1000900000000000F5030008E1180008E11800085E
-:1000A00000000000C903000800000000E11800087B
+:10002000000000000000000000000000950400082F
+:100030000000000000000000A1040008AD0400085A
+:10004000A119000800000000A1190008A11900086A
+:10005000A1190008A1190008A1190008A119000898
+:100060000000000063070008A90A0008A1190008A1
+:10007000A1190008A1190008A1190008000000003A
+:10008000A11900080000000000000000A1190008EC
+:1000900000000000C9030008A1190008A119000808
+:1000A000000000009D03000800000000A1190008E6
:1000B0000000000000000000000000000000000040
:1000C00080B582B000AF0200FB1D1A70FB1D1B78CB
:1000D0001A001F231A40044B012191400A001A60A4
@@ -32,383 +32,394 @@
:1001E0000A4B7A68013A5A6001235B4203211800E6
:1001F000FFF77CFF054B00229A60044B07221A6030
:1002000000231800BD4602B080BDC04610E000E0EB
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-:100260000A431A60C0464A4B1A6880239B04134015
-:10027000F9D0474B5A68464B02210A435A6000F0B6
-:1002800011FE454B1B680A21180001F08DF903008F
-:100290001800FFF799FF01235B421800FFF710FFDA
-:1002A00001235B4260211800FFF720FF384B5A6999
-:1002B000374B3A490A435A61354B9A69344B3849AE
-:1002C0000A439A61324BDA69314B02210A43DA61FF
-:1002D0009023DB051A689023DB0532490A431A6034
-:1002E0009023DB059A689023DB052F490A439A6027
-:1002F0009023DB0500221A629023DB05882252003E
-:100300005A622A4A294B12681A60294BC922920064
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-:1003200040210A431A601920FFF7CAFE4021192014
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diff --git a/gm_platform/fw/main.lst b/gm_platform/fw/main.lst
index 5be6e7e..caf6805 100644
--- a/gm_platform/fw/main.lst
+++ b/gm_platform/fw/main.lst
@@ -15,174 +15,178 @@ SYMBOL TABLE:
00000000 l d .debug_frame 00000000 .debug_frame
00000000 l d .debug_str 00000000 .debug_str
00000000 l d .debug_ranges 00000000 .debug_ranges
-00000000 l df *ABS* 00000000 /tmp/ccTaPb5k.o
-080018a4 l .text 00000000 LoopCopyDataInit
-0800189c l .text 00000000 CopyDataInit
-080018b8 l .text 00000000 LoopFillZerobss
-080018b2 l .text 00000000 FillZerobss
-080018c6 l .text 00000000 LoopForever
-080018e0 l .text 00000000 Infinite_Loop
+00000000 l df *ABS* 00000000 /tmp/ccr2qryM.o
+08001964 l .text 00000000 LoopCopyDataInit
+0800195c l .text 00000000 CopyDataInit
+08001978 l .text 00000000 LoopFillZerobss
+08001972 l .text 00000000 FillZerobss
+08001986 l .text 00000000 LoopForever
+080019a0 l .text 00000000 Infinite_Loop
00000000 l df *ABS* 00000000 main.c
080000c0 l F .text 0000002c NVIC_EnableIRQ
080000ec l F .text 000000dc NVIC_SetPriority
080001c8 l F .text 00000048 SysTick_Config
-20000098 l .bss 00000004 leds_update_counter.5785
-2000009c l .bss 00000004 n.5808
+20000098 l .bss 00000004 leds_update_counter.5780
+2000009c l .bss 00000004 n.5803
00000000 l df *ABS* 00000000 adc.c
-08000514 l F .text 0000002c NVIC_EnableIRQ
-08000540 l F .text 000000dc NVIC_SetPriority
-080006c4 l F .text 00000060 adc_dma_init
-08000724 l F .text 00000064 adc_timer_init
-08000788 l F .text 0000000a gdb_dump
+080004e8 l F .text 0000002c NVIC_EnableIRQ
+08000514 l F .text 000000dc NVIC_SetPriority
+08000694 l F .text 00000060 adc_dma_init
+080006f4 l F .text 00000064 adc_timer_init
+08000758 l F .text 0000000a gdb_dump
00000000 l df *ABS* 00000000 serial.c
-080007b0 l F .text 0000002c NVIC_EnableIRQ
-080007dc l F .text 00000030 NVIC_DisableIRQ
-0800080c l F .text 000000dc NVIC_SetPriority
-08000960 l F .text 00000074 usart_schedule_dma
+080007cc l F .text 0000002c NVIC_EnableIRQ
+080007f8 l F .text 00000030 NVIC_DisableIRQ
+08000828 l F .text 000000dc NVIC_SetPriority
+08000984 l F .text 00000074 usart_schedule_dma
+200000a4 l .bss 00000001 x.6221
00000000 l df *ABS* 00000000 cobs.c
00000000 l df *ABS* 00000000 system_stm32f0xx.c
00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c
-08000f90 l F .text 0000001c LL_RCC_HSE_EnableBypass
-08000fac l F .text 00000020 LL_RCC_HSE_DisableBypass
-08000fcc l F .text 0000001c LL_RCC_HSE_Enable
-08000fe8 l F .text 00000028 LL_RCC_HSE_IsReady
-08001010 l F .text 0000001c LL_RCC_HSI_Enable
-0800102c l F .text 00000020 LL_RCC_HSI_IsReady
-0800104c l F .text 00000028 LL_RCC_SetSysClkSource
-08001074 l F .text 00000018 LL_RCC_GetSysClkSource
-0800108c l F .text 00000028 LL_RCC_SetAHBPrescaler
-080010b4 l F .text 0000002c LL_RCC_SetAPB1Prescaler
-080010e0 l F .text 0000001c LL_RCC_PLL_Enable
-080010fc l F .text 00000028 LL_RCC_PLL_IsReady
-08001124 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
-08001170 l F .text 00000034 LL_InitTick
-080011a4 l F .text 00000028 LL_FLASH_SetLatency
-080011cc l F .text 00000018 LL_FLASH_GetLatency
-08001426 l F .text 00000026 UTILS_PLL_IsBusy
-080013ec l F .text 0000003a UTILS_GetPLLOutputFrequency
-0800144c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
-08001390 l F .text 0000005c UTILS_SetFlashLatency
+08001050 l F .text 0000001c LL_RCC_HSE_EnableBypass
+0800106c l F .text 00000020 LL_RCC_HSE_DisableBypass
+0800108c l F .text 0000001c LL_RCC_HSE_Enable
+080010a8 l F .text 00000028 LL_RCC_HSE_IsReady
+080010d0 l F .text 0000001c LL_RCC_HSI_Enable
+080010ec l F .text 00000020 LL_RCC_HSI_IsReady
+0800110c l F .text 00000028 LL_RCC_SetSysClkSource
+08001134 l F .text 00000018 LL_RCC_GetSysClkSource
+0800114c l F .text 00000028 LL_RCC_SetAHBPrescaler
+08001174 l F .text 0000002c LL_RCC_SetAPB1Prescaler
+080011a0 l F .text 0000001c LL_RCC_PLL_Enable
+080011bc l F .text 00000028 LL_RCC_PLL_IsReady
+080011e4 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS
+08001230 l F .text 00000034 LL_InitTick
+08001264 l F .text 00000028 LL_FLASH_SetLatency
+0800128c l F .text 00000018 LL_FLASH_GetLatency
+080014e6 l F .text 00000026 UTILS_PLL_IsBusy
+080014ac l F .text 0000003a UTILS_GetPLLOutputFrequency
+0800150c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem
+08001450 l F .text 0000005c UTILS_SetFlashLatency
00000000 l df *ABS* 00000000 base.c
00000000 l df *ABS* 00000000 cmsis_exports.c
00000000 l df *ABS* 00000000 _udivsi3.o
-080015a8 l .text 00000000 .udivsi3_skip_div0_test
+08001668 l .text 00000000 .udivsi3_skip_div0_test
00000000 l df *ABS* 00000000 _divsi3.o
-080016bc l .text 00000000 .divsi3_skip_div0_test
+0800177c l .text 00000000 .divsi3_skip_div0_test
00000000 l df *ABS* 00000000 _dvmd_tls.o
-080018fc g O .text 00000008 APBPrescTable
+080019b4 g O .text 00000008 APBPrescTable
20000044 g O .data 00000004 tim17
2000007c g O .data 00000004 gpioc
20000088 g O .data 00000004 scb
-08001202 g F .text 00000046 LL_mDelay
-08000a9c g F .text 00000030 usart_send_packet
-080018e0 w F .text 00000002 TIM1_CC_IRQHandler
-08001524 g F .text 0000000a __sinit
-080004bc g F .text 00000004 HardFault_Handler
+080012c2 g F .text 00000046 LL_mDelay
+08000ae8 g F .text 00000034 usart_send_packet
+080019a0 w F .text 00000002 TIM1_CC_IRQHandler
+080015e4 g F .text 0000000a __sinit
+08000490 g F .text 00000004 HardFault_Handler
2000006c g O .data 00000004 rcc
-080004d8 g F .text 0000003c SysTick_Handler
-08001904 g .text 00000000 _sidata
-080004cc g F .text 0000000c PendSV_Handler
+200000a0 g O .bss 00000004 usart_overruns
+080004ac g F .text 0000003c SysTick_Handler
+080019bc g .text 00000000 _sidata
+080004a0 g F .text 0000000c PendSV_Handler
20000020 g O .data 00000004 syscfg
-080004b0 g F .text 0000000c NMI_Handler
-200009d4 g .bss 00000000 __exidx_end
-08001264 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
-080018e0 w F .text 00000002 I2C1_IRQHandler
-08001248 g F .text 0000001c LL_SetSystemCoreClock
-200000a0 g O .bss 00000004 __errno
+08000484 g F .text 0000000c NMI_Handler
+2000051c g .bss 00000000 __exidx_end
+08001324 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI
+080019a0 w F .text 00000002 I2C1_IRQHandler
+08001308 g F .text 0000001c LL_SetSystemCoreClock
+200000a8 g O .bss 00000004 __errno
20000008 g O .data 00000004 tim14
20000048 g O .data 00000004 dbgmcu
2000003c g O .data 00000004 usart1
-08001904 g .text 00000000 _etext
+080019bc g .text 00000000 _etext
20000094 g .bss 00000000 _sbss
-08000c32 g F .text 000000d6 cobs_decode
-200008c8 g O .bss 0000010c usart_tx_buf
+08000cf4 g F .text 000000d6 cobs_decode
+20000110 g O .bss 0000040c usart_tx_buf
20000094 g O .bss 00000004 sys_time_seconds
20000000 g O .data 00000004 SystemCoreClock
2000001c g O .data 00000004 pwr
-080015a8 g F .text 0000010a .hidden __udivsi3
-08001592 g F .text 00000014 __assert_func
+08001668 g F .text 0000010a .hidden __udivsi3
+08001652 g F .text 00000014 __assert_func
20000000 g .data 00000000 _sdata
-080003c8 g F .text 0000002c SPI1_IRQHandler
+0800039c g F .text 0000002c SPI1_IRQHandler
20000060 g O .data 00000004 dma1_channel5
20000058 g O .data 00000004 dma1_channel3
-200009d4 g .bss 00000000 __exidx_start
-080011e4 g F .text 0000001e LL_Init1msTick
+2000051c g .bss 00000000 __exidx_start
+080012a4 g F .text 0000001e LL_Init1msTick
20000054 g O .data 00000004 dma1_channel2
-080018e0 w F .text 00000002 EXTI2_3_IRQHandler
-080018e0 w F .text 00000002 ADC1_IRQHandler
-08000d24 g F .text 000000e2 cobs_decode_incremental
+080019a0 w F .text 00000002 EXTI2_3_IRQHandler
+080019a0 w F .text 00000002 ADC1_IRQHandler
+08000de6 g F .text 000000e2 cobs_decode_incremental
2000004c g O .data 00000004 dma1
-080018e0 w F .text 00000002 TIM17_IRQHandler
-080018e0 w F .text 00000002 RTC_IRQHandler
-200009d4 g .bss 00000000 _ebss
+080019a0 w F .text 00000002 TIM17_IRQHandler
+080019a0 w F .text 00000002 RTC_IRQHandler
+2000051c g .bss 00000000 _ebss
2000002c g O .data 00000004 adc1_common
-08001894 w F .text 00000034 Reset_Handler
+08001954 w F .text 00000034 Reset_Handler
20000070 g O .data 00000004 crc
20000024 g O .data 00000004 exti
08000210 g F .text 0000000a update_leds
20000028 g O .data 00000004 adc1
-080016bc g F .text 00000000 .hidden __aeabi_idiv
-08000acc g F .text 000000c6 cobs_encode
-200000a8 g O .bss 00000020 leds
+0800177c g F .text 00000000 .hidden __aeabi_idiv
+08000b70 g F .text 000000c6 cobs_encode
+200000b0 g O .bss 00000020 leds
20000074 g O .data 00000004 gpioa
-080003f4 g F .text 000000bc TIM16_IRQHandler
-080018e0 w F .text 00000002 TIM3_IRQHandler
-080018e0 w F .text 00000002 EXTI4_15_IRQHandler
-080018e0 w F .text 00000002 RCC_IRQHandler
+080003c8 g F .text 000000bc TIM16_IRQHandler
+080019a0 w F .text 00000002 TIM3_IRQHandler
+080019a0 w F .text 00000002 EXTI4_15_IRQHandler
+080019a0 w F .text 00000002 RCC_IRQHandler
+08000b1c g F .text 00000054 usart_send_packet_nonblocking
20000094 g .bss 00000000 _bss
-08000792 g F .text 0000001e DMA1_Channel1_IRQHandler
-080018e0 g .text 00000002 Default_Handler
-080018ec g O .text 00000010 AHBPrescTable
-08000b92 g F .text 000000a0 cobs_encode_usart
+08000762 g F .text 0000006a DMA1_Channel1_IRQHandler
+080019a0 g .text 00000002 Default_Handler
+080019a4 g O .text 00000010 AHBPrescTable
+08000c36 g F .text 000000be cobs_encode_usart
20000010 g O .data 00000004 wwdg
-080018e0 w F .text 00000002 TIM14_IRQHandler
-080018e0 w F .text 00000002 DMA1_Channel4_5_IRQHandler
+080019a0 w F .text 00000002 TIM14_IRQHandler
+080019a0 w F .text 00000002 DMA1_Channel4_5_IRQHandler
20000030 g O .data 00000004 adc
-08000a2c g F .text 00000030 usart_putc
-080018e0 w F .text 00000002 EXTI0_1_IRQHandler
-08001890 w F .text 00000002 .hidden __aeabi_ldiv0
+08000a50 g F .text 00000030 usart_putc
+080019a0 w F .text 00000002 EXTI0_1_IRQHandler
+08001950 w F .text 00000002 .hidden __aeabi_ldiv0
20000004 g O .data 00000004 tim3
2000000c g O .data 00000004 rtc
-080008e8 g F .text 00000078 usart_dma_init
-0800152e g F .text 0000003a memset
-0800021a g F .text 000001ae main
+08000904 g F .text 00000080 usart_dma_init
+080015ee g F .text 0000003a memset
+0800021a g F .text 00000182 main
20000064 g O .data 00000004 flash
-080015a8 g F .text 00000000 .hidden __aeabi_uidiv
-080004c0 g F .text 0000000c SVC_Handler
+08001668 g F .text 00000000 .hidden __aeabi_uidiv
+08000494 g F .text 0000000c SVC_Handler
20000018 g O .data 00000004 i2c1
20000050 g O .data 00000004 dma1_channel1
-080016bc g F .text 000001cc .hidden __divsi3
+0800177c g F .text 000001cc .hidden __divsi3
20000090 g O .data 00000004 nvic
-08000e1c g F .text 00000088 SystemInit
-200000a4 g O .bss 00000004 _impure_ptr
-080018e0 w F .text 00000002 WWDG_IRQHandler
+08000edc g F .text 00000088 SystemInit
+08000a80 g F .text 00000028 usart_putc_nonblocking
+200000ac g O .bss 00000004 _impure_ptr
+080019a0 w F .text 00000002 WWDG_IRQHandler
20000000 g .data 00000000 _data
20000084 g O .data 00000004 gpiof
-08000a5c g F .text 00000040 DMA1_Channel2_3_IRQHandler
-200000c8 g O .bss 00000800 adc_buf
+08000aa8 g F .text 00000040 DMA1_Channel2_3_IRQHandler
+200000d0 g O .bss 00000040 adc_buf
20000080 g O .data 00000004 gpiod
20001000 g *ABS* 00000000 _estack
-080016b4 g F .text 00000008 .hidden __aeabi_uidivmod
+08001774 g F .text 00000008 .hidden __aeabi_uidivmod
20000068 g O .data 00000004 ob
20000094 g .data 00000000 _edata
20000038 g O .data 00000004 spi1
-080009d4 g F .text 00000058 usart_dma_fifo_push
+080009f8 g F .text 00000058 usart_dma_fifo_push
2000005c g O .data 00000004 dma1_channel4
08000000 g O .isr_vector 00000000 g_pfnVectors
-08000ea4 g F .text 000000ec SystemCoreClockUpdate
-080012f0 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
-08001890 w F .text 00000002 .hidden __aeabi_idiv0
+08000f64 g F .text 000000ec SystemCoreClockUpdate
+080013b0 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE
+08001950 w F .text 00000002 .hidden __aeabi_idiv0
20000014 g O .data 00000004 iwdg
-080018e0 w F .text 00000002 FLASH_IRQHandler
-08000d08 g F .text 0000001c cobs_decode_incremental_initialize
-080018e0 w F .text 00000002 USART1_IRQHandler
-0800061c g F .text 000000a8 adc_configure_scope_mode
-08001568 g F .text 0000002a strlen
-080018e0 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
+080019a0 w F .text 00000002 FLASH_IRQHandler
+08000dca g F .text 0000001c cobs_decode_incremental_initialize
+080019a0 w F .text 00000002 USART1_IRQHandler
+080005f0 g F .text 000000a4 adc_configure_scope_mode
+08001628 g F .text 0000002a strlen
+080019a0 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler
20000078 g O .data 00000004 gpiob
20000034 g O .data 00000004 tim1
2000008c g O .data 00000004 systick
-08001888 g F .text 00000008 .hidden __aeabi_idivmod
+08001948 g F .text 00000008 .hidden __aeabi_idivmod
20000040 g O .data 00000004 tim16
@@ -429,4031 +433,4155 @@ void update_leds() {
int main(void) {
800021a: b580 push {r7, lr}
- 800021c: b082 sub sp, #8
- 800021e: af00 add r7, sp, #0
+ 800021c: af00 add r7, sp, #0
RCC->CR |= RCC_CR_HSEON;
- 8000220: 4b5b ldr r3, [pc, #364] ; (8000390 <main+0x176>)
- 8000222: 681a ldr r2, [r3, #0]
- 8000224: 4b5a ldr r3, [pc, #360] ; (8000390 <main+0x176>)
- 8000226: 2180 movs r1, #128 ; 0x80
- 8000228: 0249 lsls r1, r1, #9
- 800022a: 430a orrs r2, r1
- 800022c: 601a str r2, [r3, #0]
+ 800021e: 4b53 ldr r3, [pc, #332] ; (800036c <main+0x152>)
+ 8000220: 681a ldr r2, [r3, #0]
+ 8000222: 4b52 ldr r3, [pc, #328] ; (800036c <main+0x152>)
+ 8000224: 2180 movs r1, #128 ; 0x80
+ 8000226: 0249 lsls r1, r1, #9
+ 8000228: 430a orrs r2, r1
+ 800022a: 601a str r2, [r3, #0]
while (!(RCC->CR&RCC_CR_HSERDY));
- 800022e: 46c0 nop ; (mov r8, r8)
- 8000230: 4b57 ldr r3, [pc, #348] ; (8000390 <main+0x176>)
- 8000232: 681a ldr r2, [r3, #0]
- 8000234: 2380 movs r3, #128 ; 0x80
- 8000236: 029b lsls r3, r3, #10
- 8000238: 4013 ands r3, r2
- 800023a: d0f9 beq.n 8000230 <main+0x16>
+ 800022c: 46c0 nop ; (mov r8, r8)
+ 800022e: 4b4f ldr r3, [pc, #316] ; (800036c <main+0x152>)
+ 8000230: 681a ldr r2, [r3, #0]
+ 8000232: 2380 movs r3, #128 ; 0x80
+ 8000234: 029b lsls r3, r3, #10
+ 8000236: 4013 ands r3, r2
+ 8000238: d0f9 beq.n 800022e <main+0x14>
RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
- 800023c: 4b54 ldr r3, [pc, #336] ; (8000390 <main+0x176>)
- 800023e: 685a ldr r2, [r3, #4]
- 8000240: 4b53 ldr r3, [pc, #332] ; (8000390 <main+0x176>)
- 8000242: 4954 ldr r1, [pc, #336] ; (8000394 <main+0x17a>)
- 8000244: 400a ands r2, r1
- 8000246: 605a str r2, [r3, #4]
+ 800023a: 4b4c ldr r3, [pc, #304] ; (800036c <main+0x152>)
+ 800023c: 685a ldr r2, [r3, #4]
+ 800023e: 4b4b ldr r3, [pc, #300] ; (800036c <main+0x152>)
+ 8000240: 494b ldr r1, [pc, #300] ; (8000370 <main+0x156>)
+ 8000242: 400a ands r2, r1
+ 8000244: 605a str r2, [r3, #4]
RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */
- 8000248: 4b51 ldr r3, [pc, #324] ; (8000390 <main+0x176>)
- 800024a: 685a ldr r2, [r3, #4]
- 800024c: 4b50 ldr r3, [pc, #320] ; (8000390 <main+0x176>)
- 800024e: 2188 movs r1, #136 ; 0x88
- 8000250: 0349 lsls r1, r1, #13
- 8000252: 430a orrs r2, r1
- 8000254: 605a str r2, [r3, #4]
+ 8000246: 4b49 ldr r3, [pc, #292] ; (800036c <main+0x152>)
+ 8000248: 685a ldr r2, [r3, #4]
+ 800024a: 4b48 ldr r3, [pc, #288] ; (800036c <main+0x152>)
+ 800024c: 2188 movs r1, #136 ; 0x88
+ 800024e: 0349 lsls r1, r1, #13
+ 8000250: 430a orrs r2, r1
+ 8000252: 605a str r2, [r3, #4]
RCC->CR |= RCC_CR_PLLON;
- 8000256: 4b4e ldr r3, [pc, #312] ; (8000390 <main+0x176>)
- 8000258: 681a ldr r2, [r3, #0]
- 800025a: 4b4d ldr r3, [pc, #308] ; (8000390 <main+0x176>)
- 800025c: 2180 movs r1, #128 ; 0x80
- 800025e: 0449 lsls r1, r1, #17
- 8000260: 430a orrs r2, r1
- 8000262: 601a str r2, [r3, #0]
+ 8000254: 4b45 ldr r3, [pc, #276] ; (800036c <main+0x152>)
+ 8000256: 681a ldr r2, [r3, #0]
+ 8000258: 4b44 ldr r3, [pc, #272] ; (800036c <main+0x152>)
+ 800025a: 2180 movs r1, #128 ; 0x80
+ 800025c: 0449 lsls r1, r1, #17
+ 800025e: 430a orrs r2, r1
+ 8000260: 601a str r2, [r3, #0]
while (!(RCC->CR&RCC_CR_PLLRDY));
- 8000264: 46c0 nop ; (mov r8, r8)
- 8000266: 4b4a ldr r3, [pc, #296] ; (8000390 <main+0x176>)
- 8000268: 681a ldr r2, [r3, #0]
- 800026a: 2380 movs r3, #128 ; 0x80
- 800026c: 049b lsls r3, r3, #18
- 800026e: 4013 ands r3, r2
- 8000270: d0f9 beq.n 8000266 <main+0x4c>
+ 8000262: 46c0 nop ; (mov r8, r8)
+ 8000264: 4b41 ldr r3, [pc, #260] ; (800036c <main+0x152>)
+ 8000266: 681a ldr r2, [r3, #0]
+ 8000268: 2380 movs r3, #128 ; 0x80
+ 800026a: 049b lsls r3, r3, #18
+ 800026c: 4013 ands r3, r2
+ 800026e: d0f9 beq.n 8000264 <main+0x4a>
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
- 8000272: 4b47 ldr r3, [pc, #284] ; (8000390 <main+0x176>)
- 8000274: 685a ldr r2, [r3, #4]
- 8000276: 4b46 ldr r3, [pc, #280] ; (8000390 <main+0x176>)
- 8000278: 2102 movs r1, #2
- 800027a: 430a orrs r2, r1
- 800027c: 605a str r2, [r3, #4]
+ 8000270: 4b3e ldr r3, [pc, #248] ; (800036c <main+0x152>)
+ 8000272: 685a ldr r2, [r3, #4]
+ 8000274: 4b3d ldr r3, [pc, #244] ; (800036c <main+0x152>)
+ 8000276: 2102 movs r1, #2
+ 8000278: 430a orrs r2, r1
+ 800027a: 605a str r2, [r3, #4]
SystemCoreClockUpdate();
- 800027e: f000 fe11 bl 8000ea4 <SystemCoreClockUpdate>
+ 800027c: f000 fe72 bl 8000f64 <SystemCoreClockUpdate>
SysTick_Config(SystemCoreClock/10); /* 100ms interval */
- 8000282: 4b45 ldr r3, [pc, #276] ; (8000398 <main+0x17e>)
- 8000284: 681b ldr r3, [r3, #0]
- 8000286: 210a movs r1, #10
- 8000288: 0018 movs r0, r3
- 800028a: f001 f98d bl 80015a8 <__udivsi3>
- 800028e: 0003 movs r3, r0
- 8000290: 0018 movs r0, r3
- 8000292: f7ff ff99 bl 80001c8 <SysTick_Config>
+ 8000280: 4b3c ldr r3, [pc, #240] ; (8000374 <main+0x15a>)
+ 8000282: 681b ldr r3, [r3, #0]
+ 8000284: 210a movs r1, #10
+ 8000286: 0018 movs r0, r3
+ 8000288: f001 f9ee bl 8001668 <__udivsi3>
+ 800028c: 0003 movs r3, r0
+ 800028e: 0018 movs r0, r3
+ 8000290: f7ff ff9a bl 80001c8 <SysTick_Config>
NVIC_EnableIRQ(SysTick_IRQn);
- 8000296: 2301 movs r3, #1
- 8000298: 425b negs r3, r3
- 800029a: 0018 movs r0, r3
- 800029c: f7ff ff10 bl 80000c0 <NVIC_EnableIRQ>
+ 8000294: 2301 movs r3, #1
+ 8000296: 425b negs r3, r3
+ 8000298: 0018 movs r0, r3
+ 800029a: f7ff ff11 bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(SysTick_IRQn, 3<<5);
- 80002a0: 2301 movs r3, #1
- 80002a2: 425b negs r3, r3
- 80002a4: 2160 movs r1, #96 ; 0x60
- 80002a6: 0018 movs r0, r3
- 80002a8: f7ff ff20 bl 80000ec <NVIC_SetPriority>
+ 800029e: 2301 movs r3, #1
+ 80002a0: 425b negs r3, r3
+ 80002a2: 2160 movs r1, #96 ; 0x60
+ 80002a4: 0018 movs r0, r3
+ 80002a6: f7ff ff21 bl 80000ec <NVIC_SetPriority>
/* Turn on lots of neat things */
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN;
- 80002ac: 4b38 ldr r3, [pc, #224] ; (8000390 <main+0x176>)
- 80002ae: 695a ldr r2, [r3, #20]
- 80002b0: 4b37 ldr r3, [pc, #220] ; (8000390 <main+0x176>)
- 80002b2: 493a ldr r1, [pc, #232] ; (800039c <main+0x182>)
- 80002b4: 430a orrs r2, r1
- 80002b6: 615a str r2, [r3, #20]
+ 80002aa: 4b30 ldr r3, [pc, #192] ; (800036c <main+0x152>)
+ 80002ac: 695a ldr r2, [r3, #20]
+ 80002ae: 4b2f ldr r3, [pc, #188] ; (800036c <main+0x152>)
+ 80002b0: 4931 ldr r1, [pc, #196] ; (8000378 <main+0x15e>)
+ 80002b2: 430a orrs r2, r1
+ 80002b4: 615a str r2, [r3, #20]
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_DBGMCUEN |\
- 80002b8: 4b35 ldr r3, [pc, #212] ; (8000390 <main+0x176>)
- 80002ba: 699a ldr r2, [r3, #24]
- 80002bc: 4b34 ldr r3, [pc, #208] ; (8000390 <main+0x176>)
- 80002be: 4938 ldr r1, [pc, #224] ; (80003a0 <main+0x186>)
- 80002c0: 430a orrs r2, r1
- 80002c2: 619a str r2, [r3, #24]
+ 80002b6: 4b2d ldr r3, [pc, #180] ; (800036c <main+0x152>)
+ 80002b8: 699a ldr r2, [r3, #24]
+ 80002ba: 4b2c ldr r3, [pc, #176] ; (800036c <main+0x152>)
+ 80002bc: 492f ldr r1, [pc, #188] ; (800037c <main+0x162>)
+ 80002be: 430a orrs r2, r1
+ 80002c0: 619a str r2, [r3, #24]
RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN;
RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
- 80002c4: 4b32 ldr r3, [pc, #200] ; (8000390 <main+0x176>)
- 80002c6: 69da ldr r2, [r3, #28]
- 80002c8: 4b31 ldr r3, [pc, #196] ; (8000390 <main+0x176>)
- 80002ca: 2102 movs r1, #2
- 80002cc: 430a orrs r2, r1
- 80002ce: 61da str r2, [r3, #28]
+ 80002c2: 4b2a ldr r3, [pc, #168] ; (800036c <main+0x152>)
+ 80002c4: 69da ldr r2, [r3, #28]
+ 80002c6: 4b29 ldr r3, [pc, #164] ; (800036c <main+0x152>)
+ 80002c8: 2102 movs r1, #2
+ 80002ca: 430a orrs r2, r1
+ 80002cc: 61da str r2, [r3, #28]
GPIOA->MODER |=
- 80002d0: 2390 movs r3, #144 ; 0x90
- 80002d2: 05db lsls r3, r3, #23
- 80002d4: 681a ldr r2, [r3, #0]
- 80002d6: 2390 movs r3, #144 ; 0x90
- 80002d8: 05db lsls r3, r3, #23
- 80002da: 4932 ldr r1, [pc, #200] ; (80003a4 <main+0x18a>)
- 80002dc: 430a orrs r2, r1
- 80002de: 601a str r2, [r3, #0]
+ 80002ce: 2390 movs r3, #144 ; 0x90
+ 80002d0: 05db lsls r3, r3, #23
+ 80002d2: 681a ldr r2, [r3, #0]
+ 80002d4: 2390 movs r3, #144 ; 0x90
+ 80002d6: 05db lsls r3, r3, #23
+ 80002d8: 4929 ldr r1, [pc, #164] ; (8000380 <main+0x166>)
+ 80002da: 430a orrs r2, r1
+ 80002dc: 601a str r2, [r3, #0]
| (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */
| (2<<GPIO_MODER_MODER9_Pos) /* PA9 - HOST_RX */
| (2<<GPIO_MODER_MODER10_Pos);/* PA10 - HOST_TX */
/* Set shift register IO GPIO output speed */
GPIOA->OSPEEDR |=
- 80002e0: 2390 movs r3, #144 ; 0x90
- 80002e2: 05db lsls r3, r3, #23
- 80002e4: 689a ldr r2, [r3, #8]
- 80002e6: 2390 movs r3, #144 ; 0x90
- 80002e8: 05db lsls r3, r3, #23
- 80002ea: 492f ldr r1, [pc, #188] ; (80003a8 <main+0x18e>)
- 80002ec: 430a orrs r2, r1
- 80002ee: 609a str r2, [r3, #8]
+ 80002de: 2390 movs r3, #144 ; 0x90
+ 80002e0: 05db lsls r3, r3, #23
+ 80002e2: 689a ldr r2, [r3, #8]
+ 80002e4: 2390 movs r3, #144 ; 0x90
+ 80002e6: 05db lsls r3, r3, #23
+ 80002e8: 4926 ldr r1, [pc, #152] ; (8000384 <main+0x16a>)
+ 80002ea: 430a orrs r2, r1
+ 80002ec: 609a str r2, [r3, #8]
| (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* SD_CS */
| (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCK */
| (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */
| (2<<GPIO_OSPEEDR_OSPEEDR9_Pos); /* HOST_RX */
GPIOA->AFR[0] = (0<<GPIO_AFRL_AFRL5_Pos) | (0<<GPIO_AFRL_AFRL6_Pos) | (0<<GPIO_AFRL_AFRL7_Pos);
- 80002f0: 2390 movs r3, #144 ; 0x90
- 80002f2: 05db lsls r3, r3, #23
- 80002f4: 2200 movs r2, #0
- 80002f6: 621a str r2, [r3, #32]
+ 80002ee: 2390 movs r3, #144 ; 0x90
+ 80002f0: 05db lsls r3, r3, #23
+ 80002f2: 2200 movs r2, #0
+ 80002f4: 621a str r2, [r3, #32]
GPIOA->AFR[1] = (1<<8) | (1<<4);
- 80002f8: 2390 movs r3, #144 ; 0x90
- 80002fa: 05db lsls r3, r3, #23
- 80002fc: 2288 movs r2, #136 ; 0x88
- 80002fe: 0052 lsls r2, r2, #1
- 8000300: 625a str r2, [r3, #36] ; 0x24
+ 80002f6: 2390 movs r3, #144 ; 0x90
+ 80002f8: 05db lsls r3, r3, #23
+ 80002fa: 2288 movs r2, #136 ; 0x88
+ 80002fc: 0052 lsls r2, r2, #1
+ 80002fe: 625a str r2, [r3, #36] ; 0x24
GPIOB->MODER |=
- 8000302: 4a2a ldr r2, [pc, #168] ; (80003ac <main+0x192>)
- 8000304: 4b29 ldr r3, [pc, #164] ; (80003ac <main+0x192>)
- 8000306: 6812 ldr r2, [r2, #0]
- 8000308: 601a str r2, [r3, #0]
+ 8000300: 4a21 ldr r2, [pc, #132] ; (8000388 <main+0x16e>)
+ 8000302: 4b21 ldr r3, [pc, #132] ; (8000388 <main+0x16e>)
+ 8000304: 6812 ldr r2, [r2, #0]
+ 8000306: 601a str r2, [r3, #0]
(0<<GPIO_MODER_MODER1_Pos); /* PB0 - LINE_POL */
SPI1->CR1 =
- 800030a: 4b29 ldr r3, [pc, #164] ; (80003b0 <main+0x196>)
- 800030c: 22c9 movs r2, #201 ; 0xc9
- 800030e: 0092 lsls r2, r2, #2
- 8000310: 601a str r2, [r3, #0]
+ 8000308: 4b20 ldr r3, [pc, #128] ; (800038c <main+0x172>)
+ 800030a: 22c9 movs r2, #201 ; 0xc9
+ 800030c: 0092 lsls r2, r2, #2
+ 800030e: 601a str r2, [r3, #0]
SPI_CR1_SSM
| SPI_CR1_SSI
| (4<<SPI_CR1_BR_Pos) /* /32 ~1.5MHz */
| SPI_CR1_MSTR;
SPI1->CR2 = (7<<SPI_CR2_DS_Pos);
- 8000312: 4b27 ldr r3, [pc, #156] ; (80003b0 <main+0x196>)
- 8000314: 22e0 movs r2, #224 ; 0xe0
- 8000316: 00d2 lsls r2, r2, #3
- 8000318: 605a str r2, [r3, #4]
+ 8000310: 4b1e ldr r3, [pc, #120] ; (800038c <main+0x172>)
+ 8000312: 22e0 movs r2, #224 ; 0xe0
+ 8000314: 00d2 lsls r2, r2, #3
+ 8000316: 605a str r2, [r3, #4]
SPI1->CR1 |= SPI_CR1_SPE;
- 800031a: 4b25 ldr r3, [pc, #148] ; (80003b0 <main+0x196>)
- 800031c: 681a ldr r2, [r3, #0]
- 800031e: 4b24 ldr r3, [pc, #144] ; (80003b0 <main+0x196>)
- 8000320: 2140 movs r1, #64 ; 0x40
- 8000322: 430a orrs r2, r1
- 8000324: 601a str r2, [r3, #0]
+ 8000318: 4b1c ldr r3, [pc, #112] ; (800038c <main+0x172>)
+ 800031a: 681a ldr r2, [r3, #0]
+ 800031c: 4b1b ldr r3, [pc, #108] ; (800038c <main+0x172>)
+ 800031e: 2140 movs r1, #64 ; 0x40
+ 8000320: 430a orrs r2, r1
+ 8000322: 601a str r2, [r3, #0]
NVIC_EnableIRQ(SPI1_IRQn);
- 8000326: 2019 movs r0, #25
- 8000328: f7ff feca bl 80000c0 <NVIC_EnableIRQ>
+ 8000324: 2019 movs r0, #25
+ 8000326: f7ff fecb bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(SPI1_IRQn, 2<<5);
- 800032c: 2140 movs r1, #64 ; 0x40
- 800032e: 2019 movs r0, #25
- 8000330: f7ff fedc bl 80000ec <NVIC_SetPriority>
+ 800032a: 2140 movs r1, #64 ; 0x40
+ 800032c: 2019 movs r0, #25
+ 800032e: f7ff fedd bl 80000ec <NVIC_SetPriority>
TIM16->CR2 = 0;
- 8000334: 4b1f ldr r3, [pc, #124] ; (80003b4 <main+0x19a>)
- 8000336: 2200 movs r2, #0
- 8000338: 605a str r2, [r3, #4]
+ 8000332: 4b17 ldr r3, [pc, #92] ; (8000390 <main+0x176>)
+ 8000334: 2200 movs r2, #0
+ 8000336: 605a str r2, [r3, #4]
TIM16->DIER = TIM_DIER_UIE;
- 800033a: 4b1e ldr r3, [pc, #120] ; (80003b4 <main+0x19a>)
- 800033c: 2201 movs r2, #1
- 800033e: 60da str r2, [r3, #12]
+ 8000338: 4b15 ldr r3, [pc, #84] ; (8000390 <main+0x176>)
+ 800033a: 2201 movs r2, #1
+ 800033c: 60da str r2, [r3, #12]
TIM16->PSC = 48-1; /* 1us */
- 8000340: 4b1c ldr r3, [pc, #112] ; (80003b4 <main+0x19a>)
- 8000342: 222f movs r2, #47 ; 0x2f
- 8000344: 629a str r2, [r3, #40] ; 0x28
+ 800033e: 4b14 ldr r3, [pc, #80] ; (8000390 <main+0x176>)
+ 8000340: 222f movs r2, #47 ; 0x2f
+ 8000342: 629a str r2, [r3, #40] ; 0x28
TIM16->ARR = 1000-1; /* 1ms */
- 8000346: 4b1b ldr r3, [pc, #108] ; (80003b4 <main+0x19a>)
- 8000348: 4a1b ldr r2, [pc, #108] ; (80003b8 <main+0x19e>)
- 800034a: 62da str r2, [r3, #44] ; 0x2c
+ 8000344: 4b12 ldr r3, [pc, #72] ; (8000390 <main+0x176>)
+ 8000346: 4a13 ldr r2, [pc, #76] ; (8000394 <main+0x17a>)
+ 8000348: 62da str r2, [r3, #44] ; 0x2c
TIM16->CR1 = TIM_CR1_CEN;
- 800034c: 4b19 ldr r3, [pc, #100] ; (80003b4 <main+0x19a>)
- 800034e: 2201 movs r2, #1
- 8000350: 601a str r2, [r3, #0]
+ 800034a: 4b11 ldr r3, [pc, #68] ; (8000390 <main+0x176>)
+ 800034c: 2201 movs r2, #1
+ 800034e: 601a str r2, [r3, #0]
NVIC_EnableIRQ(TIM16_IRQn);
- 8000352: 2015 movs r0, #21
- 8000354: f7ff feb4 bl 80000c0 <NVIC_EnableIRQ>
+ 8000350: 2015 movs r0, #21
+ 8000352: f7ff feb5 bl 80000c0 <NVIC_EnableIRQ>
NVIC_SetPriority(TIM16_IRQn, 2<<5);
- 8000358: 2140 movs r1, #64 ; 0x40
- 800035a: 2015 movs r0, #21
- 800035c: f7ff fec6 bl 80000ec <NVIC_SetPriority>
+ 8000356: 2140 movs r1, #64 ; 0x40
+ 8000358: 2015 movs r0, #21
+ 800035a: f7ff fec7 bl 80000ec <NVIC_SetPriority>
adc_configure_scope_mode(1000000);
- 8000360: 4b16 ldr r3, [pc, #88] ; (80003bc <main+0x1a2>)
- 8000362: 0018 movs r0, r3
- 8000364: f000 f95a bl 800061c <adc_configure_scope_mode>
+ 800035e: 4b0e ldr r3, [pc, #56] ; (8000398 <main+0x17e>)
+ 8000360: 0018 movs r0, r3
+ 8000362: f000 f945 bl 80005f0 <adc_configure_scope_mode>
usart_dma_init();
- 8000368: f000 fabe bl 80008e8 <usart_dma_init>
+ 8000366: f000 facd bl 8000904 <usart_dma_init>
while (42) {
- char *data = "FOOBAR\n";
- 800036c: 4b14 ldr r3, [pc, #80] ; (80003c0 <main+0x1a6>)
- 800036e: 603b str r3, [r7, #0]
- usart_send_packet((uint8_t*)data, 8);
- 8000370: 683b ldr r3, [r7, #0]
- 8000372: 2108 movs r1, #8
- 8000374: 0018 movs r0, r3
- 8000376: f000 fb91 bl 8000a9c <usart_send_packet>
- for (int i=0; i<100000; i++);
- 800037a: 2300 movs r3, #0
- 800037c: 607b str r3, [r7, #4]
- 800037e: e002 b.n 8000386 <main+0x16c>
- 8000380: 687b ldr r3, [r7, #4]
- 8000382: 3301 adds r3, #1
- 8000384: 607b str r3, [r7, #4]
- 8000386: 687b ldr r3, [r7, #4]
- 8000388: 4a0e ldr r2, [pc, #56] ; (80003c4 <main+0x1aa>)
- 800038a: 4293 cmp r3, r2
- 800038c: ddf8 ble.n 8000380 <main+0x166>
- while (42) {
- 800038e: e7ed b.n 800036c <main+0x152>
- 8000390: 40021000 .word 0x40021000
- 8000394: ffc3f80c .word 0xffc3f80c
- 8000398: 20000000 .word 0x20000000
- 800039c: 00060011 .word 0x00060011
- 80003a0: 00425a01 .word 0x00425a01
- 80003a4: 0028a970 .word 0x0028a970
- 80003a8: 00088a80 .word 0x00088a80
- 80003ac: 48000400 .word 0x48000400
- 80003b0: 40013000 .word 0x40013000
- 80003b4: 40014400 .word 0x40014400
- 80003b8: 000003e7 .word 0x000003e7
- 80003bc: 000f4240 .word 0x000f4240
- 80003c0: 080018e4 .word 0x080018e4
- 80003c4: 0001869f .word 0x0001869f
-
-080003c8 <SPI1_IRQHandler>:
+ 800036a: e7fe b.n 800036a <main+0x150>
+ 800036c: 40021000 .word 0x40021000
+ 8000370: ffc3f80c .word 0xffc3f80c
+ 8000374: 20000000 .word 0x20000000
+ 8000378: 00060011 .word 0x00060011
+ 800037c: 00425a01 .word 0x00425a01
+ 8000380: 0028a970 .word 0x0028a970
+ 8000384: 00088a80 .word 0x00088a80
+ 8000388: 48000400 .word 0x48000400
+ 800038c: 40013000 .word 0x40013000
+ 8000390: 40014400 .word 0x40014400
+ 8000394: 000003e7 .word 0x000003e7
+ 8000398: 000f4240 .word 0x000f4240
+
+0800039c <SPI1_IRQHandler>:
//for (int i=0; i<10000; i++) ;
//leds.error = 100;
}
}
void SPI1_IRQHandler(void) {
- 80003c8: b580 push {r7, lr}
- 80003ca: af00 add r7, sp, #0
+ 800039c: b580 push {r7, lr}
+ 800039e: af00 add r7, sp, #0
if (SPI1->SR & SPI_SR_TXE) {
- 80003cc: 4b08 ldr r3, [pc, #32] ; (80003f0 <SPI1_IRQHandler+0x28>)
- 80003ce: 689b ldr r3, [r3, #8]
- 80003d0: 2202 movs r2, #2
- 80003d2: 4013 ands r3, r2
- 80003d4: d009 beq.n 80003ea <SPI1_IRQHandler+0x22>
+ 80003a0: 4b08 ldr r3, [pc, #32] ; (80003c4 <SPI1_IRQHandler+0x28>)
+ 80003a2: 689b ldr r3, [r3, #8]
+ 80003a4: 2202 movs r2, #2
+ 80003a6: 4013 ands r3, r2
+ 80003a8: d009 beq.n 80003be <SPI1_IRQHandler+0x22>
/* LED_STB */
GPIOA->BSRR = 1<<3;
- 80003d6: 2390 movs r3, #144 ; 0x90
- 80003d8: 05db lsls r3, r3, #23
- 80003da: 2208 movs r2, #8
- 80003dc: 619a str r2, [r3, #24]
+ 80003aa: 2390 movs r3, #144 ; 0x90
+ 80003ac: 05db lsls r3, r3, #23
+ 80003ae: 2208 movs r2, #8
+ 80003b0: 619a str r2, [r3, #24]
SPI1->CR2 &= ~SPI_CR2_TXEIE;
- 80003de: 4b04 ldr r3, [pc, #16] ; (80003f0 <SPI1_IRQHandler+0x28>)
- 80003e0: 685a ldr r2, [r3, #4]
- 80003e2: 4b03 ldr r3, [pc, #12] ; (80003f0 <SPI1_IRQHandler+0x28>)
- 80003e4: 2180 movs r1, #128 ; 0x80
- 80003e6: 438a bics r2, r1
- 80003e8: 605a str r2, [r3, #4]
+ 80003b2: 4b04 ldr r3, [pc, #16] ; (80003c4 <SPI1_IRQHandler+0x28>)
+ 80003b4: 685a ldr r2, [r3, #4]
+ 80003b6: 4b03 ldr r3, [pc, #12] ; (80003c4 <SPI1_IRQHandler+0x28>)
+ 80003b8: 2180 movs r1, #128 ; 0x80
+ 80003ba: 438a bics r2, r1
+ 80003bc: 605a str r2, [r3, #4]
}
}
- 80003ea: 46c0 nop ; (mov r8, r8)
- 80003ec: 46bd mov sp, r7
- 80003ee: bd80 pop {r7, pc}
- 80003f0: 40013000 .word 0x40013000
+ 80003be: 46c0 nop ; (mov r8, r8)
+ 80003c0: 46bd mov sp, r7
+ 80003c2: bd80 pop {r7, pc}
+ 80003c4: 40013000 .word 0x40013000
-080003f4 <TIM16_IRQHandler>:
+080003c8 <TIM16_IRQHandler>:
void TIM16_IRQHandler(void) {
- 80003f4: b580 push {r7, lr}
- 80003f6: b082 sub sp, #8
- 80003f8: af00 add r7, sp, #0
+ 80003c8: b580 push {r7, lr}
+ 80003ca: b082 sub sp, #8
+ 80003cc: af00 add r7, sp, #0
static int leds_update_counter = 0;
if (TIM16->SR & TIM_SR_UIF) {
- 80003fa: 4b28 ldr r3, [pc, #160] ; (800049c <TIM16_IRQHandler+0xa8>)
- 80003fc: 691b ldr r3, [r3, #16]
- 80003fe: 2201 movs r2, #1
- 8000400: 4013 ands r3, r2
- 8000402: d047 beq.n 8000494 <TIM16_IRQHandler+0xa0>
+ 80003ce: 4b28 ldr r3, [pc, #160] ; (8000470 <TIM16_IRQHandler+0xa8>)
+ 80003d0: 691b ldr r3, [r3, #16]
+ 80003d2: 2201 movs r2, #1
+ 80003d4: 4013 ands r3, r2
+ 80003d6: d047 beq.n 8000468 <TIM16_IRQHandler+0xa0>
TIM16->SR &= ~TIM_SR_UIF;
- 8000404: 4b25 ldr r3, [pc, #148] ; (800049c <TIM16_IRQHandler+0xa8>)
- 8000406: 691a ldr r2, [r3, #16]
- 8000408: 4b24 ldr r3, [pc, #144] ; (800049c <TIM16_IRQHandler+0xa8>)
- 800040a: 2101 movs r1, #1
- 800040c: 438a bics r2, r1
- 800040e: 611a str r2, [r3, #16]
+ 80003d8: 4b25 ldr r3, [pc, #148] ; (8000470 <TIM16_IRQHandler+0xa8>)
+ 80003da: 691a ldr r2, [r3, #16]
+ 80003dc: 4b24 ldr r3, [pc, #144] ; (8000470 <TIM16_IRQHandler+0xa8>)
+ 80003de: 2101 movs r1, #1
+ 80003e0: 438a bics r2, r1
+ 80003e2: 611a str r2, [r3, #16]
uint8_t bits = 0, mask = 1;
- 8000410: 1dfb adds r3, r7, #7
- 8000412: 2200 movs r2, #0
- 8000414: 701a strb r2, [r3, #0]
- 8000416: 1dbb adds r3, r7, #6
- 8000418: 2201 movs r2, #1
- 800041a: 701a strb r2, [r3, #0]
+ 80003e4: 1dfb adds r3, r7, #7
+ 80003e6: 2200 movs r2, #0
+ 80003e8: 701a strb r2, [r3, #0]
+ 80003ea: 1dbb adds r3, r7, #6
+ 80003ec: 2201 movs r2, #1
+ 80003ee: 701a strb r2, [r3, #0]
for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) {
- 800041c: 2300 movs r3, #0
- 800041e: 603b str r3, [r7, #0]
- 8000420: e01d b.n 800045e <TIM16_IRQHandler+0x6a>
+ 80003f0: 2300 movs r3, #0
+ 80003f2: 603b str r3, [r7, #0]
+ 80003f4: e01d b.n 8000432 <TIM16_IRQHandler+0x6a>
if (leds.arr[i]) {
- 8000422: 4b1f ldr r3, [pc, #124] ; (80004a0 <TIM16_IRQHandler+0xac>)
- 8000424: 683a ldr r2, [r7, #0]
- 8000426: 0092 lsls r2, r2, #2
- 8000428: 58d3 ldr r3, [r2, r3]
- 800042a: 2b00 cmp r3, #0
- 800042c: d00f beq.n 800044e <TIM16_IRQHandler+0x5a>
+ 80003f6: 4b1f ldr r3, [pc, #124] ; (8000474 <TIM16_IRQHandler+0xac>)
+ 80003f8: 683a ldr r2, [r7, #0]
+ 80003fa: 0092 lsls r2, r2, #2
+ 80003fc: 58d3 ldr r3, [r2, r3]
+ 80003fe: 2b00 cmp r3, #0
+ 8000400: d00f beq.n 8000422 <TIM16_IRQHandler+0x5a>
leds.arr[i]--;
- 800042e: 4b1c ldr r3, [pc, #112] ; (80004a0 <TIM16_IRQHandler+0xac>)
- 8000430: 683a ldr r2, [r7, #0]
- 8000432: 0092 lsls r2, r2, #2
- 8000434: 58d3 ldr r3, [r2, r3]
- 8000436: 1e59 subs r1, r3, #1
- 8000438: 4b19 ldr r3, [pc, #100] ; (80004a0 <TIM16_IRQHandler+0xac>)
- 800043a: 683a ldr r2, [r7, #0]
- 800043c: 0092 lsls r2, r2, #2
- 800043e: 50d1 str r1, [r2, r3]
+ 8000402: 4b1c ldr r3, [pc, #112] ; (8000474 <TIM16_IRQHandler+0xac>)
+ 8000404: 683a ldr r2, [r7, #0]
+ 8000406: 0092 lsls r2, r2, #2
+ 8000408: 58d3 ldr r3, [r2, r3]
+ 800040a: 1e59 subs r1, r3, #1
+ 800040c: 4b19 ldr r3, [pc, #100] ; (8000474 <TIM16_IRQHandler+0xac>)
+ 800040e: 683a ldr r2, [r7, #0]
+ 8000410: 0092 lsls r2, r2, #2
+ 8000412: 50d1 str r1, [r2, r3]
bits |= mask;
- 8000440: 1dfb adds r3, r7, #7
- 8000442: 1df9 adds r1, r7, #7
- 8000444: 1dba adds r2, r7, #6
- 8000446: 7809 ldrb r1, [r1, #0]
- 8000448: 7812 ldrb r2, [r2, #0]
- 800044a: 430a orrs r2, r1
- 800044c: 701a strb r2, [r3, #0]
+ 8000414: 1dfb adds r3, r7, #7
+ 8000416: 1df9 adds r1, r7, #7
+ 8000418: 1dba adds r2, r7, #6
+ 800041a: 7809 ldrb r1, [r1, #0]
+ 800041c: 7812 ldrb r2, [r2, #0]
+ 800041e: 430a orrs r2, r1
+ 8000420: 701a strb r2, [r3, #0]
}
mask <<= 1;
- 800044e: 1dba adds r2, r7, #6
- 8000450: 1dbb adds r3, r7, #6
- 8000452: 781b ldrb r3, [r3, #0]
- 8000454: 18db adds r3, r3, r3
- 8000456: 7013 strb r3, [r2, #0]
+ 8000422: 1dba adds r2, r7, #6
+ 8000424: 1dbb adds r3, r7, #6
+ 8000426: 781b ldrb r3, [r3, #0]
+ 8000428: 18db adds r3, r3, r3
+ 800042a: 7013 strb r3, [r2, #0]
for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) {
- 8000458: 683b ldr r3, [r7, #0]
- 800045a: 3301 adds r3, #1
- 800045c: 603b str r3, [r7, #0]
- 800045e: 683b ldr r3, [r7, #0]
- 8000460: 2b07 cmp r3, #7
- 8000462: d9de bls.n 8000422 <TIM16_IRQHandler+0x2e>
+ 800042c: 683b ldr r3, [r7, #0]
+ 800042e: 3301 adds r3, #1
+ 8000430: 603b str r3, [r7, #0]
+ 8000432: 683b ldr r3, [r7, #0]
+ 8000434: 2b07 cmp r3, #7
+ 8000436: d9de bls.n 80003f6 <TIM16_IRQHandler+0x2e>
}
if (leds_update_counter++ == 10) {
- 8000464: 4b0f ldr r3, [pc, #60] ; (80004a4 <TIM16_IRQHandler+0xb0>)
- 8000466: 681b ldr r3, [r3, #0]
- 8000468: 1c59 adds r1, r3, #1
- 800046a: 4a0e ldr r2, [pc, #56] ; (80004a4 <TIM16_IRQHandler+0xb0>)
- 800046c: 6011 str r1, [r2, #0]
- 800046e: 2b0a cmp r3, #10
- 8000470: d110 bne.n 8000494 <TIM16_IRQHandler+0xa0>
+ 8000438: 4b0f ldr r3, [pc, #60] ; (8000478 <TIM16_IRQHandler+0xb0>)
+ 800043a: 681b ldr r3, [r3, #0]
+ 800043c: 1c59 adds r1, r3, #1
+ 800043e: 4a0e ldr r2, [pc, #56] ; (8000478 <TIM16_IRQHandler+0xb0>)
+ 8000440: 6011 str r1, [r2, #0]
+ 8000442: 2b0a cmp r3, #10
+ 8000444: d110 bne.n 8000468 <TIM16_IRQHandler+0xa0>
leds_update_counter = 0;
- 8000472: 4b0c ldr r3, [pc, #48] ; (80004a4 <TIM16_IRQHandler+0xb0>)
- 8000474: 2200 movs r2, #0
- 8000476: 601a str r2, [r3, #0]
+ 8000446: 4b0c ldr r3, [pc, #48] ; (8000478 <TIM16_IRQHandler+0xb0>)
+ 8000448: 2200 movs r2, #0
+ 800044a: 601a str r2, [r3, #0]
/* Workaround for SPI hardware bug: Even if configured to 8-bit mode, the SPI will do a 16-bit transfer if the
* data register is accessed through a 16-bit write. Unfortunately, the STMCube register defs define DR as an
* uint16_t, so we have to do some magic here to force an 8-bit write. */
*((volatile uint8_t*)&(SPI1->DR)) = bits;
- 8000478: 4a0b ldr r2, [pc, #44] ; (80004a8 <TIM16_IRQHandler+0xb4>)
- 800047a: 1dfb adds r3, r7, #7
- 800047c: 781b ldrb r3, [r3, #0]
- 800047e: 7013 strb r3, [r2, #0]
+ 800044c: 4a0b ldr r2, [pc, #44] ; (800047c <TIM16_IRQHandler+0xb4>)
+ 800044e: 1dfb adds r3, r7, #7
+ 8000450: 781b ldrb r3, [r3, #0]
+ 8000452: 7013 strb r3, [r2, #0]
SPI1->CR2 |= SPI_CR2_TXEIE;
- 8000480: 4b0a ldr r3, [pc, #40] ; (80004ac <TIM16_IRQHandler+0xb8>)
- 8000482: 685a ldr r2, [r3, #4]
- 8000484: 4b09 ldr r3, [pc, #36] ; (80004ac <TIM16_IRQHandler+0xb8>)
- 8000486: 2180 movs r1, #128 ; 0x80
- 8000488: 430a orrs r2, r1
- 800048a: 605a str r2, [r3, #4]
+ 8000454: 4b0a ldr r3, [pc, #40] ; (8000480 <TIM16_IRQHandler+0xb8>)
+ 8000456: 685a ldr r2, [r3, #4]
+ 8000458: 4b09 ldr r3, [pc, #36] ; (8000480 <TIM16_IRQHandler+0xb8>)
+ 800045a: 2180 movs r1, #128 ; 0x80
+ 800045c: 430a orrs r2, r1
+ 800045e: 605a str r2, [r3, #4]
GPIOA->BRR = 1<<3;
- 800048c: 2390 movs r3, #144 ; 0x90
- 800048e: 05db lsls r3, r3, #23
- 8000490: 2208 movs r2, #8
- 8000492: 629a str r2, [r3, #40] ; 0x28
+ 8000460: 2390 movs r3, #144 ; 0x90
+ 8000462: 05db lsls r3, r3, #23
+ 8000464: 2208 movs r2, #8
+ 8000466: 629a str r2, [r3, #40] ; 0x28
}
}
}
- 8000494: 46c0 nop ; (mov r8, r8)
- 8000496: 46bd mov sp, r7
- 8000498: b002 add sp, #8
- 800049a: bd80 pop {r7, pc}
- 800049c: 40014400 .word 0x40014400
- 80004a0: 200000a8 .word 0x200000a8
- 80004a4: 20000098 .word 0x20000098
- 80004a8: 4001300c .word 0x4001300c
- 80004ac: 40013000 .word 0x40013000
-
-080004b0 <NMI_Handler>:
+ 8000468: 46c0 nop ; (mov r8, r8)
+ 800046a: 46bd mov sp, r7
+ 800046c: b002 add sp, #8
+ 800046e: bd80 pop {r7, pc}
+ 8000470: 40014400 .word 0x40014400
+ 8000474: 200000b0 .word 0x200000b0
+ 8000478: 20000098 .word 0x20000098
+ 800047c: 4001300c .word 0x4001300c
+ 8000480: 40013000 .word 0x40013000
+
+08000484 <NMI_Handler>:
void NMI_Handler(void) {
- 80004b0: b580 push {r7, lr}
- 80004b2: af00 add r7, sp, #0
+ 8000484: b580 push {r7, lr}
+ 8000486: af00 add r7, sp, #0
asm volatile ("bkpt");
- 80004b4: be00 bkpt 0x0000
+ 8000488: be00 bkpt 0x0000
}
- 80004b6: 46c0 nop ; (mov r8, r8)
- 80004b8: 46bd mov sp, r7
- 80004ba: bd80 pop {r7, pc}
+ 800048a: 46c0 nop ; (mov r8, r8)
+ 800048c: 46bd mov sp, r7
+ 800048e: bd80 pop {r7, pc}
-080004bc <HardFault_Handler>:
+08000490 <HardFault_Handler>:
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler() {
asm volatile ("bkpt");
- 80004bc: be00 bkpt 0x0000
+ 8000490: be00 bkpt 0x0000
}
- 80004be: 46c0 nop ; (mov r8, r8)
+ 8000492: 46c0 nop ; (mov r8, r8)
-080004c0 <SVC_Handler>:
+08000494 <SVC_Handler>:
void SVC_Handler(void) {
- 80004c0: b580 push {r7, lr}
- 80004c2: af00 add r7, sp, #0
+ 8000494: b580 push {r7, lr}
+ 8000496: af00 add r7, sp, #0
asm volatile ("bkpt");
- 80004c4: be00 bkpt 0x0000
+ 8000498: be00 bkpt 0x0000
}
- 80004c6: 46c0 nop ; (mov r8, r8)
- 80004c8: 46bd mov sp, r7
- 80004ca: bd80 pop {r7, pc}
+ 800049a: 46c0 nop ; (mov r8, r8)
+ 800049c: 46bd mov sp, r7
+ 800049e: bd80 pop {r7, pc}
-080004cc <PendSV_Handler>:
+080004a0 <PendSV_Handler>:
void PendSV_Handler(void) {
- 80004cc: b580 push {r7, lr}
- 80004ce: af00 add r7, sp, #0
+ 80004a0: b580 push {r7, lr}
+ 80004a2: af00 add r7, sp, #0
asm volatile ("bkpt");
- 80004d0: be00 bkpt 0x0000
+ 80004a4: be00 bkpt 0x0000
}
- 80004d2: 46c0 nop ; (mov r8, r8)
- 80004d4: 46bd mov sp, r7
- 80004d6: bd80 pop {r7, pc}
+ 80004a6: 46c0 nop ; (mov r8, r8)
+ 80004a8: 46bd mov sp, r7
+ 80004aa: bd80 pop {r7, pc}
-080004d8 <SysTick_Handler>:
+080004ac <SysTick_Handler>:
void SysTick_Handler(void) {
- 80004d8: b580 push {r7, lr}
- 80004da: af00 add r7, sp, #0
+ 80004ac: b580 push {r7, lr}
+ 80004ae: af00 add r7, sp, #0
static int n = 0;
if (n++ == 10) {
- 80004dc: 4b0a ldr r3, [pc, #40] ; (8000508 <SysTick_Handler+0x30>)
- 80004de: 681b ldr r3, [r3, #0]
- 80004e0: 1c59 adds r1, r3, #1
- 80004e2: 4a09 ldr r2, [pc, #36] ; (8000508 <SysTick_Handler+0x30>)
- 80004e4: 6011 str r1, [r2, #0]
- 80004e6: 2b0a cmp r3, #10
- 80004e8: d10a bne.n 8000500 <SysTick_Handler+0x28>
+ 80004b0: 4b0a ldr r3, [pc, #40] ; (80004dc <SysTick_Handler+0x30>)
+ 80004b2: 681b ldr r3, [r3, #0]
+ 80004b4: 1c59 adds r1, r3, #1
+ 80004b6: 4a09 ldr r2, [pc, #36] ; (80004dc <SysTick_Handler+0x30>)
+ 80004b8: 6011 str r1, [r2, #0]
+ 80004ba: 2b0a cmp r3, #10
+ 80004bc: d10a bne.n 80004d4 <SysTick_Handler+0x28>
n = 0;
- 80004ea: 4b07 ldr r3, [pc, #28] ; (8000508 <SysTick_Handler+0x30>)
- 80004ec: 2200 movs r2, #0
- 80004ee: 601a str r2, [r3, #0]
+ 80004be: 4b07 ldr r3, [pc, #28] ; (80004dc <SysTick_Handler+0x30>)
+ 80004c0: 2200 movs r2, #0
+ 80004c2: 601a str r2, [r3, #0]
sys_time_seconds++;
- 80004f0: 4b06 ldr r3, [pc, #24] ; (800050c <SysTick_Handler+0x34>)
- 80004f2: 681b ldr r3, [r3, #0]
- 80004f4: 1c5a adds r2, r3, #1
- 80004f6: 4b05 ldr r3, [pc, #20] ; (800050c <SysTick_Handler+0x34>)
- 80004f8: 601a str r2, [r3, #0]
+ 80004c4: 4b06 ldr r3, [pc, #24] ; (80004e0 <SysTick_Handler+0x34>)
+ 80004c6: 681b ldr r3, [r3, #0]
+ 80004c8: 1c5a adds r2, r3, #1
+ 80004ca: 4b05 ldr r3, [pc, #20] ; (80004e0 <SysTick_Handler+0x34>)
+ 80004cc: 601a str r2, [r3, #0]
leds.pps = 100; /* ms */
- 80004fa: 4b05 ldr r3, [pc, #20] ; (8000510 <SysTick_Handler+0x38>)
- 80004fc: 2264 movs r2, #100 ; 0x64
- 80004fe: 619a str r2, [r3, #24]
+ 80004ce: 4b05 ldr r3, [pc, #20] ; (80004e4 <SysTick_Handler+0x38>)
+ 80004d0: 2264 movs r2, #100 ; 0x64
+ 80004d2: 619a str r2, [r3, #24]
}
}
- 8000500: 46c0 nop ; (mov r8, r8)
- 8000502: 46bd mov sp, r7
- 8000504: bd80 pop {r7, pc}
- 8000506: 46c0 nop ; (mov r8, r8)
- 8000508: 2000009c .word 0x2000009c
- 800050c: 20000094 .word 0x20000094
- 8000510: 200000a8 .word 0x200000a8
-
-08000514 <NVIC_EnableIRQ>:
+ 80004d4: 46c0 nop ; (mov r8, r8)
+ 80004d6: 46bd mov sp, r7
+ 80004d8: bd80 pop {r7, pc}
+ 80004da: 46c0 nop ; (mov r8, r8)
+ 80004dc: 2000009c .word 0x2000009c
+ 80004e0: 20000094 .word 0x20000094
+ 80004e4: 200000b0 .word 0x200000b0
+
+080004e8 <NVIC_EnableIRQ>:
{
- 8000514: b580 push {r7, lr}
- 8000516: b082 sub sp, #8
- 8000518: af00 add r7, sp, #0
- 800051a: 0002 movs r2, r0
- 800051c: 1dfb adds r3, r7, #7
- 800051e: 701a strb r2, [r3, #0]
+ 80004e8: b580 push {r7, lr}
+ 80004ea: b082 sub sp, #8
+ 80004ec: af00 add r7, sp, #0
+ 80004ee: 0002 movs r2, r0
+ 80004f0: 1dfb adds r3, r7, #7
+ 80004f2: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- 8000520: 1dfb adds r3, r7, #7
- 8000522: 781b ldrb r3, [r3, #0]
- 8000524: 001a movs r2, r3
- 8000526: 231f movs r3, #31
- 8000528: 401a ands r2, r3
- 800052a: 4b04 ldr r3, [pc, #16] ; (800053c <NVIC_EnableIRQ+0x28>)
- 800052c: 2101 movs r1, #1
- 800052e: 4091 lsls r1, r2
- 8000530: 000a movs r2, r1
- 8000532: 601a str r2, [r3, #0]
+ 80004f4: 1dfb adds r3, r7, #7
+ 80004f6: 781b ldrb r3, [r3, #0]
+ 80004f8: 001a movs r2, r3
+ 80004fa: 231f movs r3, #31
+ 80004fc: 401a ands r2, r3
+ 80004fe: 4b04 ldr r3, [pc, #16] ; (8000510 <NVIC_EnableIRQ+0x28>)
+ 8000500: 2101 movs r1, #1
+ 8000502: 4091 lsls r1, r2
+ 8000504: 000a movs r2, r1
+ 8000506: 601a str r2, [r3, #0]
}
- 8000534: 46c0 nop ; (mov r8, r8)
- 8000536: 46bd mov sp, r7
- 8000538: b002 add sp, #8
- 800053a: bd80 pop {r7, pc}
- 800053c: e000e100 .word 0xe000e100
+ 8000508: 46c0 nop ; (mov r8, r8)
+ 800050a: 46bd mov sp, r7
+ 800050c: b002 add sp, #8
+ 800050e: bd80 pop {r7, pc}
+ 8000510: e000e100 .word 0xe000e100
-08000540 <NVIC_SetPriority>:
+08000514 <NVIC_SetPriority>:
{
- 8000540: b590 push {r4, r7, lr}
- 8000542: b083 sub sp, #12
- 8000544: af00 add r7, sp, #0
- 8000546: 0002 movs r2, r0
- 8000548: 6039 str r1, [r7, #0]
- 800054a: 1dfb adds r3, r7, #7
- 800054c: 701a strb r2, [r3, #0]
+ 8000514: b590 push {r4, r7, lr}
+ 8000516: b083 sub sp, #12
+ 8000518: af00 add r7, sp, #0
+ 800051a: 0002 movs r2, r0
+ 800051c: 6039 str r1, [r7, #0]
+ 800051e: 1dfb adds r3, r7, #7
+ 8000520: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
- 800054e: 1dfb adds r3, r7, #7
- 8000550: 781b ldrb r3, [r3, #0]
- 8000552: 2b7f cmp r3, #127 ; 0x7f
- 8000554: d932 bls.n 80005bc <NVIC_SetPriority+0x7c>
+ 8000522: 1dfb adds r3, r7, #7
+ 8000524: 781b ldrb r3, [r3, #0]
+ 8000526: 2b7f cmp r3, #127 ; 0x7f
+ 8000528: d932 bls.n 8000590 <NVIC_SetPriority+0x7c>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8000556: 4a2f ldr r2, [pc, #188] ; (8000614 <NVIC_SetPriority+0xd4>)
- 8000558: 1dfb adds r3, r7, #7
- 800055a: 781b ldrb r3, [r3, #0]
- 800055c: 0019 movs r1, r3
- 800055e: 230f movs r3, #15
- 8000560: 400b ands r3, r1
- 8000562: 3b08 subs r3, #8
- 8000564: 089b lsrs r3, r3, #2
- 8000566: 3306 adds r3, #6
- 8000568: 009b lsls r3, r3, #2
- 800056a: 18d3 adds r3, r2, r3
- 800056c: 3304 adds r3, #4
- 800056e: 681b ldr r3, [r3, #0]
- 8000570: 1dfa adds r2, r7, #7
- 8000572: 7812 ldrb r2, [r2, #0]
- 8000574: 0011 movs r1, r2
- 8000576: 2203 movs r2, #3
- 8000578: 400a ands r2, r1
- 800057a: 00d2 lsls r2, r2, #3
- 800057c: 21ff movs r1, #255 ; 0xff
- 800057e: 4091 lsls r1, r2
- 8000580: 000a movs r2, r1
- 8000582: 43d2 mvns r2, r2
- 8000584: 401a ands r2, r3
- 8000586: 0011 movs r1, r2
+ 800052a: 4a2f ldr r2, [pc, #188] ; (80005e8 <NVIC_SetPriority+0xd4>)
+ 800052c: 1dfb adds r3, r7, #7
+ 800052e: 781b ldrb r3, [r3, #0]
+ 8000530: 0019 movs r1, r3
+ 8000532: 230f movs r3, #15
+ 8000534: 400b ands r3, r1
+ 8000536: 3b08 subs r3, #8
+ 8000538: 089b lsrs r3, r3, #2
+ 800053a: 3306 adds r3, #6
+ 800053c: 009b lsls r3, r3, #2
+ 800053e: 18d3 adds r3, r2, r3
+ 8000540: 3304 adds r3, #4
+ 8000542: 681b ldr r3, [r3, #0]
+ 8000544: 1dfa adds r2, r7, #7
+ 8000546: 7812 ldrb r2, [r2, #0]
+ 8000548: 0011 movs r1, r2
+ 800054a: 2203 movs r2, #3
+ 800054c: 400a ands r2, r1
+ 800054e: 00d2 lsls r2, r2, #3
+ 8000550: 21ff movs r1, #255 ; 0xff
+ 8000552: 4091 lsls r1, r2
+ 8000554: 000a movs r2, r1
+ 8000556: 43d2 mvns r2, r2
+ 8000558: 401a ands r2, r3
+ 800055a: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 8000588: 683b ldr r3, [r7, #0]
- 800058a: 019b lsls r3, r3, #6
- 800058c: 22ff movs r2, #255 ; 0xff
- 800058e: 401a ands r2, r3
- 8000590: 1dfb adds r3, r7, #7
- 8000592: 781b ldrb r3, [r3, #0]
- 8000594: 0018 movs r0, r3
- 8000596: 2303 movs r3, #3
- 8000598: 4003 ands r3, r0
- 800059a: 00db lsls r3, r3, #3
- 800059c: 409a lsls r2, r3
+ 800055c: 683b ldr r3, [r7, #0]
+ 800055e: 019b lsls r3, r3, #6
+ 8000560: 22ff movs r2, #255 ; 0xff
+ 8000562: 401a ands r2, r3
+ 8000564: 1dfb adds r3, r7, #7
+ 8000566: 781b ldrb r3, [r3, #0]
+ 8000568: 0018 movs r0, r3
+ 800056a: 2303 movs r3, #3
+ 800056c: 4003 ands r3, r0
+ 800056e: 00db lsls r3, r3, #3
+ 8000570: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800059e: 481d ldr r0, [pc, #116] ; (8000614 <NVIC_SetPriority+0xd4>)
- 80005a0: 1dfb adds r3, r7, #7
- 80005a2: 781b ldrb r3, [r3, #0]
- 80005a4: 001c movs r4, r3
- 80005a6: 230f movs r3, #15
- 80005a8: 4023 ands r3, r4
- 80005aa: 3b08 subs r3, #8
- 80005ac: 089b lsrs r3, r3, #2
- 80005ae: 430a orrs r2, r1
- 80005b0: 3306 adds r3, #6
- 80005b2: 009b lsls r3, r3, #2
- 80005b4: 18c3 adds r3, r0, r3
- 80005b6: 3304 adds r3, #4
- 80005b8: 601a str r2, [r3, #0]
+ 8000572: 481d ldr r0, [pc, #116] ; (80005e8 <NVIC_SetPriority+0xd4>)
+ 8000574: 1dfb adds r3, r7, #7
+ 8000576: 781b ldrb r3, [r3, #0]
+ 8000578: 001c movs r4, r3
+ 800057a: 230f movs r3, #15
+ 800057c: 4023 ands r3, r4
+ 800057e: 3b08 subs r3, #8
+ 8000580: 089b lsrs r3, r3, #2
+ 8000582: 430a orrs r2, r1
+ 8000584: 3306 adds r3, #6
+ 8000586: 009b lsls r3, r3, #2
+ 8000588: 18c3 adds r3, r0, r3
+ 800058a: 3304 adds r3, #4
+ 800058c: 601a str r2, [r3, #0]
}
- 80005ba: e027 b.n 800060c <NVIC_SetPriority+0xcc>
+ 800058e: e027 b.n 80005e0 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80005bc: 4a16 ldr r2, [pc, #88] ; (8000618 <NVIC_SetPriority+0xd8>)
- 80005be: 1dfb adds r3, r7, #7
- 80005c0: 781b ldrb r3, [r3, #0]
- 80005c2: b25b sxtb r3, r3
- 80005c4: 089b lsrs r3, r3, #2
- 80005c6: 33c0 adds r3, #192 ; 0xc0
- 80005c8: 009b lsls r3, r3, #2
- 80005ca: 589b ldr r3, [r3, r2]
- 80005cc: 1dfa adds r2, r7, #7
- 80005ce: 7812 ldrb r2, [r2, #0]
- 80005d0: 0011 movs r1, r2
- 80005d2: 2203 movs r2, #3
- 80005d4: 400a ands r2, r1
- 80005d6: 00d2 lsls r2, r2, #3
- 80005d8: 21ff movs r1, #255 ; 0xff
- 80005da: 4091 lsls r1, r2
- 80005dc: 000a movs r2, r1
- 80005de: 43d2 mvns r2, r2
- 80005e0: 401a ands r2, r3
- 80005e2: 0011 movs r1, r2
+ 8000590: 4a16 ldr r2, [pc, #88] ; (80005ec <NVIC_SetPriority+0xd8>)
+ 8000592: 1dfb adds r3, r7, #7
+ 8000594: 781b ldrb r3, [r3, #0]
+ 8000596: b25b sxtb r3, r3
+ 8000598: 089b lsrs r3, r3, #2
+ 800059a: 33c0 adds r3, #192 ; 0xc0
+ 800059c: 009b lsls r3, r3, #2
+ 800059e: 589b ldr r3, [r3, r2]
+ 80005a0: 1dfa adds r2, r7, #7
+ 80005a2: 7812 ldrb r2, [r2, #0]
+ 80005a4: 0011 movs r1, r2
+ 80005a6: 2203 movs r2, #3
+ 80005a8: 400a ands r2, r1
+ 80005aa: 00d2 lsls r2, r2, #3
+ 80005ac: 21ff movs r1, #255 ; 0xff
+ 80005ae: 4091 lsls r1, r2
+ 80005b0: 000a movs r2, r1
+ 80005b2: 43d2 mvns r2, r2
+ 80005b4: 401a ands r2, r3
+ 80005b6: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80005e4: 683b ldr r3, [r7, #0]
- 80005e6: 019b lsls r3, r3, #6
- 80005e8: 22ff movs r2, #255 ; 0xff
- 80005ea: 401a ands r2, r3
- 80005ec: 1dfb adds r3, r7, #7
- 80005ee: 781b ldrb r3, [r3, #0]
- 80005f0: 0018 movs r0, r3
- 80005f2: 2303 movs r3, #3
- 80005f4: 4003 ands r3, r0
- 80005f6: 00db lsls r3, r3, #3
- 80005f8: 409a lsls r2, r3
+ 80005b8: 683b ldr r3, [r7, #0]
+ 80005ba: 019b lsls r3, r3, #6
+ 80005bc: 22ff movs r2, #255 ; 0xff
+ 80005be: 401a ands r2, r3
+ 80005c0: 1dfb adds r3, r7, #7
+ 80005c2: 781b ldrb r3, [r3, #0]
+ 80005c4: 0018 movs r0, r3
+ 80005c6: 2303 movs r3, #3
+ 80005c8: 4003 ands r3, r0
+ 80005ca: 00db lsls r3, r3, #3
+ 80005cc: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80005fa: 4807 ldr r0, [pc, #28] ; (8000618 <NVIC_SetPriority+0xd8>)
- 80005fc: 1dfb adds r3, r7, #7
- 80005fe: 781b ldrb r3, [r3, #0]
- 8000600: b25b sxtb r3, r3
- 8000602: 089b lsrs r3, r3, #2
- 8000604: 430a orrs r2, r1
- 8000606: 33c0 adds r3, #192 ; 0xc0
- 8000608: 009b lsls r3, r3, #2
- 800060a: 501a str r2, [r3, r0]
+ 80005ce: 4807 ldr r0, [pc, #28] ; (80005ec <NVIC_SetPriority+0xd8>)
+ 80005d0: 1dfb adds r3, r7, #7
+ 80005d2: 781b ldrb r3, [r3, #0]
+ 80005d4: b25b sxtb r3, r3
+ 80005d6: 089b lsrs r3, r3, #2
+ 80005d8: 430a orrs r2, r1
+ 80005da: 33c0 adds r3, #192 ; 0xc0
+ 80005dc: 009b lsls r3, r3, #2
+ 80005de: 501a str r2, [r3, r0]
}
- 800060c: 46c0 nop ; (mov r8, r8)
- 800060e: 46bd mov sp, r7
- 8000610: b003 add sp, #12
- 8000612: bd90 pop {r4, r7, pc}
- 8000614: e000ed00 .word 0xe000ed00
- 8000618: e000e100 .word 0xe000e100
-
-0800061c <adc_configure_scope_mode>:
+ 80005e0: 46c0 nop ; (mov r8, r8)
+ 80005e2: 46bd mov sp, r7
+ 80005e4: b003 add sp, #12
+ 80005e6: bd90 pop {r4, r7, pc}
+ 80005e8: e000ed00 .word 0xe000ed00
+ 80005ec: e000e100 .word 0xe000e100
+
+080005f0 <adc_configure_scope_mode>:
static void adc_dma_init(int burstlen);
static void adc_timer_init(int psc, int ivl);
/* Mode that can be used for debugging */
void adc_configure_scope_mode(int sampling_interval_ns) {
- 800061c: b580 push {r7, lr}
- 800061e: b084 sub sp, #16
- 8000620: af00 add r7, sp, #0
- 8000622: 6078 str r0, [r7, #4]
+ 80005f0: b580 push {r7, lr}
+ 80005f2: b084 sub sp, #16
+ 80005f4: af00 add r7, sp, #0
+ 80005f6: 6078 str r0, [r7, #4]
adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0]));
- 8000624: 2380 movs r3, #128 ; 0x80
- 8000626: 00db lsls r3, r3, #3
- 8000628: 0018 movs r0, r3
- 800062a: f000 f84b bl 80006c4 <adc_dma_init>
+ 80005f8: 2020 movs r0, #32
+ 80005fa: f000 f84b bl 8000694 <adc_dma_init>
/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */
- 800062e: 4b21 ldr r3, [pc, #132] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000630: 2280 movs r2, #128 ; 0x80
- 8000632: 0612 lsls r2, r2, #24
- 8000634: 611a str r2, [r3, #16]
+ 80005fe: 4b21 ldr r3, [pc, #132] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000600: 2280 movs r2, #128 ; 0x80
+ 8000602: 0612 lsls r2, r2, #24
+ 8000604: 611a str r2, [r3, #16]
/* Sampling time 239.5 ADC clock cycles -> total conversion time 38.5us*/
ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos);
- 8000636: 4b1f ldr r3, [pc, #124] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000638: 2207 movs r2, #7
- 800063a: 615a str r2, [r3, #20]
+ 8000606: 4b1f ldr r3, [pc, #124] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000608: 2207 movs r2, #7
+ 800060a: 615a str r2, [r3, #20]
/* Setup DMA and triggering */
/* Trigger from TIM1 TRGO */
ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos);
- 800063c: 4b1d ldr r3, [pc, #116] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 800063e: 4a1e ldr r2, [pc, #120] ; (80006b8 <adc_configure_scope_mode+0x9c>)
- 8000640: 60da str r2, [r3, #12]
+ 800060c: 4b1d ldr r3, [pc, #116] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800060e: 4a1e ldr r2, [pc, #120] ; (8000688 <adc_configure_scope_mode+0x98>)
+ 8000610: 60da str r2, [r3, #12]
ADC1->CHSELR = ADC_CHSELR_CHSEL2;
- 8000642: 4b1c ldr r3, [pc, #112] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000644: 2204 movs r2, #4
- 8000646: 629a str r2, [r3, #40] ; 0x28
+ 8000612: 4b1c ldr r3, [pc, #112] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000614: 2204 movs r2, #4
+ 8000616: 629a str r2, [r3, #40] ; 0x28
/* Perform self-calibration */
ADC1->CR |= ADC_CR_ADCAL;
- 8000648: 4b1a ldr r3, [pc, #104] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 800064a: 689a ldr r2, [r3, #8]
- 800064c: 4b19 ldr r3, [pc, #100] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 800064e: 2180 movs r1, #128 ; 0x80
- 8000650: 0609 lsls r1, r1, #24
- 8000652: 430a orrs r2, r1
- 8000654: 609a str r2, [r3, #8]
+ 8000618: 4b1a ldr r3, [pc, #104] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800061a: 689a ldr r2, [r3, #8]
+ 800061c: 4b19 ldr r3, [pc, #100] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800061e: 2180 movs r1, #128 ; 0x80
+ 8000620: 0609 lsls r1, r1, #24
+ 8000622: 430a orrs r2, r1
+ 8000624: 609a str r2, [r3, #8]
while (ADC1->CR & ADC_CR_ADCAL)
- 8000656: 46c0 nop ; (mov r8, r8)
- 8000658: 4b16 ldr r3, [pc, #88] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 800065a: 689b ldr r3, [r3, #8]
- 800065c: 2b00 cmp r3, #0
- 800065e: dbfb blt.n 8000658 <adc_configure_scope_mode+0x3c>
+ 8000626: 46c0 nop ; (mov r8, r8)
+ 8000628: 4b16 ldr r3, [pc, #88] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800062a: 689b ldr r3, [r3, #8]
+ 800062c: 2b00 cmp r3, #0
+ 800062e: dbfb blt.n 8000628 <adc_configure_scope_mode+0x38>
;
/* Enable conversion */
ADC1->CR |= ADC_CR_ADEN;
- 8000660: 4b14 ldr r3, [pc, #80] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000662: 689a ldr r2, [r3, #8]
- 8000664: 4b13 ldr r3, [pc, #76] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000666: 2101 movs r1, #1
- 8000668: 430a orrs r2, r1
- 800066a: 609a str r2, [r3, #8]
+ 8000630: 4b14 ldr r3, [pc, #80] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000632: 689a ldr r2, [r3, #8]
+ 8000634: 4b13 ldr r3, [pc, #76] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000636: 2101 movs r1, #1
+ 8000638: 430a orrs r2, r1
+ 800063a: 609a str r2, [r3, #8]
ADC1->CR |= ADC_CR_ADSTART;
- 800066c: 4b11 ldr r3, [pc, #68] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 800066e: 689a ldr r2, [r3, #8]
- 8000670: 4b10 ldr r3, [pc, #64] ; (80006b4 <adc_configure_scope_mode+0x98>)
- 8000672: 2104 movs r1, #4
- 8000674: 430a orrs r2, r1
- 8000676: 609a str r2, [r3, #8]
+ 800063c: 4b11 ldr r3, [pc, #68] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 800063e: 689a ldr r2, [r3, #8]
+ 8000640: 4b10 ldr r3, [pc, #64] ; (8000684 <adc_configure_scope_mode+0x94>)
+ 8000642: 2104 movs r1, #4
+ 8000644: 430a orrs r2, r1
+ 8000646: 609a str r2, [r3, #8]
/* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us.
Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this
would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */
int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6;
- 8000678: 687b ldr r3, [r7, #4]
- 800067a: 4a10 ldr r2, [pc, #64] ; (80006bc <adc_configure_scope_mode+0xa0>)
- 800067c: 4293 cmp r3, r2
- 800067e: dd06 ble.n 800068e <adc_configure_scope_mode+0x72>
- 8000680: 687b ldr r3, [r7, #4]
- 8000682: 21fa movs r1, #250 ; 0xfa
- 8000684: 0018 movs r0, r3
- 8000686: f001 f819 bl 80016bc <__divsi3>
- 800068a: 0003 movs r3, r0
- 800068c: e000 b.n 8000690 <adc_configure_scope_mode+0x74>
- 800068e: 2306 movs r3, #6
- 8000690: 60fb str r3, [r7, #12]
+ 8000648: 687b ldr r3, [r7, #4]
+ 800064a: 4a10 ldr r2, [pc, #64] ; (800068c <adc_configure_scope_mode+0x9c>)
+ 800064c: 4293 cmp r3, r2
+ 800064e: dd06 ble.n 800065e <adc_configure_scope_mode+0x6e>
+ 8000650: 687b ldr r3, [r7, #4]
+ 8000652: 21fa movs r1, #250 ; 0xfa
+ 8000654: 0018 movs r0, r3
+ 8000656: f001 f891 bl 800177c <__divsi3>
+ 800065a: 0003 movs r3, r0
+ 800065c: e000 b.n 8000660 <adc_configure_scope_mode+0x70>
+ 800065e: 2306 movs r3, #6
+ 8000660: 60fb str r3, [r7, #12]
if (cycles > 0xffff)
- 8000692: 68fa ldr r2, [r7, #12]
- 8000694: 2380 movs r3, #128 ; 0x80
- 8000696: 025b lsls r3, r3, #9
- 8000698: 429a cmp r2, r3
- 800069a: db01 blt.n 80006a0 <adc_configure_scope_mode+0x84>
+ 8000662: 68fa ldr r2, [r7, #12]
+ 8000664: 2380 movs r3, #128 ; 0x80
+ 8000666: 025b lsls r3, r3, #9
+ 8000668: 429a cmp r2, r3
+ 800066a: db01 blt.n 8000670 <adc_configure_scope_mode+0x80>
cycles = 0xffff;
- 800069c: 4b08 ldr r3, [pc, #32] ; (80006c0 <adc_configure_scope_mode+0xa4>)
- 800069e: 60fb str r3, [r7, #12]
+ 800066c: 4b08 ldr r3, [pc, #32] ; (8000690 <adc_configure_scope_mode+0xa0>)
+ 800066e: 60fb str r3, [r7, #12]
adc_timer_init(12/*250ns/tick*/, cycles);
- 80006a0: 68fb ldr r3, [r7, #12]
- 80006a2: 0019 movs r1, r3
- 80006a4: 200c movs r0, #12
- 80006a6: f000 f83d bl 8000724 <adc_timer_init>
+ 8000670: 68fb ldr r3, [r7, #12]
+ 8000672: 0019 movs r1, r3
+ 8000674: 200c movs r0, #12
+ 8000676: f000 f83d bl 80006f4 <adc_timer_init>
}
- 80006aa: 46c0 nop ; (mov r8, r8)
- 80006ac: 46bd mov sp, r7
- 80006ae: b004 add sp, #16
- 80006b0: bd80 pop {r7, pc}
- 80006b2: 46c0 nop ; (mov r8, r8)
- 80006b4: 40012400 .word 0x40012400
- 80006b8: 00000843 .word 0x00000843
- 80006bc: 000005dc .word 0x000005dc
- 80006c0: 0000ffff .word 0x0000ffff
-
-080006c4 <adc_dma_init>:
-
-/* FIXME figure out the proper place to configure this. */
-#define ADC_TIMER_INTERVAL_US 20
+ 800067a: 46c0 nop ; (mov r8, r8)
+ 800067c: 46bd mov sp, r7
+ 800067e: b004 add sp, #16
+ 8000680: bd80 pop {r7, pc}
+ 8000682: 46c0 nop ; (mov r8, r8)
+ 8000684: 40012400 .word 0x40012400
+ 8000688: 00000843 .word 0x00000843
+ 800068c: 000005dc .word 0x000005dc
+ 8000690: 0000ffff .word 0x0000ffff
+
+08000694 <adc_dma_init>:
static void adc_dma_init(int burstlen) {
- 80006c4: b580 push {r7, lr}
- 80006c6: b082 sub sp, #8
- 80006c8: af00 add r7, sp, #0
- 80006ca: 6078 str r0, [r7, #4]
+ 8000694: b580 push {r7, lr}
+ 8000696: b082 sub sp, #8
+ 8000698: af00 add r7, sp, #0
+ 800069a: 6078 str r0, [r7, #4]
/* Configure DMA 1 Channel 1 to get rid of all the data */
DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR;
- 80006cc: 4b11 ldr r3, [pc, #68] ; (8000714 <adc_dma_init+0x50>)
- 80006ce: 4a12 ldr r2, [pc, #72] ; (8000718 <adc_dma_init+0x54>)
- 80006d0: 609a str r2, [r3, #8]
+ 800069c: 4b11 ldr r3, [pc, #68] ; (80006e4 <adc_dma_init+0x50>)
+ 800069e: 4a12 ldr r2, [pc, #72] ; (80006e8 <adc_dma_init+0x54>)
+ 80006a0: 609a str r2, [r3, #8]
DMA1_Channel1->CMAR = (unsigned int)&adc_buf;
- 80006d2: 4b10 ldr r3, [pc, #64] ; (8000714 <adc_dma_init+0x50>)
- 80006d4: 4a11 ldr r2, [pc, #68] ; (800071c <adc_dma_init+0x58>)
- 80006d6: 60da str r2, [r3, #12]
+ 80006a2: 4b10 ldr r3, [pc, #64] ; (80006e4 <adc_dma_init+0x50>)
+ 80006a4: 4a11 ldr r2, [pc, #68] ; (80006ec <adc_dma_init+0x58>)
+ 80006a6: 60da str r2, [r3, #12]
DMA1_Channel1->CNDTR = burstlen;
- 80006d8: 4b0e ldr r3, [pc, #56] ; (8000714 <adc_dma_init+0x50>)
- 80006da: 687a ldr r2, [r7, #4]
- 80006dc: 605a str r2, [r3, #4]
+ 80006a8: 4b0e ldr r3, [pc, #56] ; (80006e4 <adc_dma_init+0x50>)
+ 80006aa: 687a ldr r2, [r7, #4]
+ 80006ac: 605a str r2, [r3, #4]
DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos);
- 80006de: 4b0d ldr r3, [pc, #52] ; (8000714 <adc_dma_init+0x50>)
- 80006e0: 2200 movs r2, #0
- 80006e2: 601a str r2, [r3, #0]
+ 80006ae: 4b0d ldr r3, [pc, #52] ; (80006e4 <adc_dma_init+0x50>)
+ 80006b0: 2200 movs r2, #0
+ 80006b2: 601a str r2, [r3, #0]
DMA1_Channel1->CCR |=
- 80006e4: 4b0b ldr r3, [pc, #44] ; (8000714 <adc_dma_init+0x50>)
- 80006e6: 681a ldr r2, [r3, #0]
- 80006e8: 4b0a ldr r3, [pc, #40] ; (8000714 <adc_dma_init+0x50>)
- 80006ea: 490d ldr r1, [pc, #52] ; (8000720 <adc_dma_init+0x5c>)
- 80006ec: 430a orrs r2, r1
- 80006ee: 601a str r2, [r3, #0]
- | (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */
+ 80006b4: 4b0b ldr r3, [pc, #44] ; (80006e4 <adc_dma_init+0x50>)
+ 80006b6: 681a ldr r2, [r3, #0]
+ 80006b8: 4b0a ldr r3, [pc, #40] ; (80006e4 <adc_dma_init+0x50>)
+ 80006ba: 490d ldr r1, [pc, #52] ; (80006f0 <adc_dma_init+0x5c>)
+ 80006bc: 430a orrs r2, r1
+ 80006be: 601a str r2, [r3, #0]
| DMA_CCR_MINC
+ | DMA_CCR_HTIE /* Enable half-transfer interrupt. */
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
- /* triggered on transfer completion. We use this to process the ADC data */
+ /* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- 80006f0: 2009 movs r0, #9
- 80006f2: f7ff ff0f bl 8000514 <NVIC_EnableIRQ>
- NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5);
- 80006f6: 2140 movs r1, #64 ; 0x40
- 80006f8: 2009 movs r0, #9
- 80006fa: f7ff ff21 bl 8000540 <NVIC_SetPriority>
+ 80006c0: 2009 movs r0, #9
+ 80006c2: f7ff ff11 bl 80004e8 <NVIC_EnableIRQ>
+ NVIC_SetPriority(DMA1_Channel1_IRQn, 3<<5);
+ 80006c6: 2160 movs r1, #96 ; 0x60
+ 80006c8: 2009 movs r0, #9
+ 80006ca: f7ff ff23 bl 8000514 <NVIC_SetPriority>
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
- 80006fe: 4b05 ldr r3, [pc, #20] ; (8000714 <adc_dma_init+0x50>)
- 8000700: 681a ldr r2, [r3, #0]
- 8000702: 4b04 ldr r3, [pc, #16] ; (8000714 <adc_dma_init+0x50>)
- 8000704: 2101 movs r1, #1
- 8000706: 430a orrs r2, r1
- 8000708: 601a str r2, [r3, #0]
+ 80006ce: 4b05 ldr r3, [pc, #20] ; (80006e4 <adc_dma_init+0x50>)
+ 80006d0: 681a ldr r2, [r3, #0]
+ 80006d2: 4b04 ldr r3, [pc, #16] ; (80006e4 <adc_dma_init+0x50>)
+ 80006d4: 2101 movs r1, #1
+ 80006d6: 430a orrs r2, r1
+ 80006d8: 601a str r2, [r3, #0]
}
- 800070a: 46c0 nop ; (mov r8, r8)
- 800070c: 46bd mov sp, r7
- 800070e: b002 add sp, #8
- 8000710: bd80 pop {r7, pc}
- 8000712: 46c0 nop ; (mov r8, r8)
- 8000714: 40020008 .word 0x40020008
- 8000718: 40012440 .word 0x40012440
- 800071c: 200000c8 .word 0x200000c8
- 8000720: 000005a2 .word 0x000005a2
-
-08000724 <adc_timer_init>:
+ 80006da: 46c0 nop ; (mov r8, r8)
+ 80006dc: 46bd mov sp, r7
+ 80006de: b002 add sp, #8
+ 80006e0: bd80 pop {r7, pc}
+ 80006e2: 46c0 nop ; (mov r8, r8)
+ 80006e4: 40020008 .word 0x40020008
+ 80006e8: 40012440 .word 0x40012440
+ 80006ec: 200000d0 .word 0x200000d0
+ 80006f0: 000005a6 .word 0x000005a6
+
+080006f4 <adc_timer_init>:
static void adc_timer_init(int psc, int ivl) {
- 8000724: b580 push {r7, lr}
- 8000726: b082 sub sp, #8
- 8000728: af00 add r7, sp, #0
- 800072a: 6078 str r0, [r7, #4]
- 800072c: 6039 str r1, [r7, #0]
+ 80006f4: b580 push {r7, lr}
+ 80006f6: b082 sub sp, #8
+ 80006f8: af00 add r7, sp, #0
+ 80006fa: 6078 str r0, [r7, #4]
+ 80006fc: 6039 str r1, [r7, #0]
TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */
- 800072e: 4b15 ldr r3, [pc, #84] ; (8000784 <adc_timer_init+0x60>)
- 8000730: 2280 movs r2, #128 ; 0x80
- 8000732: 0212 lsls r2, r2, #8
- 8000734: 645a str r2, [r3, #68] ; 0x44
+ 80006fe: 4b15 ldr r3, [pc, #84] ; (8000754 <adc_timer_init+0x60>)
+ 8000700: 2280 movs r2, #128 ; 0x80
+ 8000702: 0212 lsls r2, r2, #8
+ 8000704: 645a str r2, [r3, #68] ; 0x44
TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
- 8000736: 4b13 ldr r3, [pc, #76] ; (8000784 <adc_timer_init+0x60>)
- 8000738: 22c0 movs r2, #192 ; 0xc0
- 800073a: 01d2 lsls r2, r2, #7
- 800073c: 61da str r2, [r3, #28]
+ 8000706: 4b13 ldr r3, [pc, #76] ; (8000754 <adc_timer_init+0x60>)
+ 8000708: 22c0 movs r2, #192 ; 0xc0
+ 800070a: 01d2 lsls r2, r2, #7
+ 800070c: 61da str r2, [r3, #28]
TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
- 800073e: 4b11 ldr r3, [pc, #68] ; (8000784 <adc_timer_init+0x60>)
- 8000740: 2280 movs r2, #128 ; 0x80
- 8000742: 0152 lsls r2, r2, #5
- 8000744: 621a str r2, [r3, #32]
+ 800070e: 4b11 ldr r3, [pc, #68] ; (8000754 <adc_timer_init+0x60>)
+ 8000710: 2280 movs r2, #128 ; 0x80
+ 8000712: 0152 lsls r2, r2, #5
+ 8000714: 621a str r2, [r3, #32]
TIM1->CCR4 = 1; /* Trigger at start of timer cycle */
- 8000746: 4b0f ldr r3, [pc, #60] ; (8000784 <adc_timer_init+0x60>)
- 8000748: 2201 movs r2, #1
- 800074a: 641a str r2, [r3, #64] ; 0x40
+ 8000716: 4b0f ldr r3, [pc, #60] ; (8000754 <adc_timer_init+0x60>)
+ 8000718: 2201 movs r2, #1
+ 800071a: 641a str r2, [r3, #64] ; 0x40
/* Set prescaler and interval */
TIM1->PSC = psc-1;
- 800074c: 687b ldr r3, [r7, #4]
- 800074e: 1e5a subs r2, r3, #1
- 8000750: 4b0c ldr r3, [pc, #48] ; (8000784 <adc_timer_init+0x60>)
- 8000752: 629a str r2, [r3, #40] ; 0x28
+ 800071c: 687b ldr r3, [r7, #4]
+ 800071e: 1e5a subs r2, r3, #1
+ 8000720: 4b0c ldr r3, [pc, #48] ; (8000754 <adc_timer_init+0x60>)
+ 8000722: 629a str r2, [r3, #40] ; 0x28
TIM1->ARR = ivl-1;
- 8000754: 683b ldr r3, [r7, #0]
- 8000756: 1e5a subs r2, r3, #1
- 8000758: 4b0a ldr r3, [pc, #40] ; (8000784 <adc_timer_init+0x60>)
- 800075a: 62da str r2, [r3, #44] ; 0x2c
+ 8000724: 683b ldr r3, [r7, #0]
+ 8000726: 1e5a subs r2, r3, #1
+ 8000728: 4b0a ldr r3, [pc, #40] ; (8000754 <adc_timer_init+0x60>)
+ 800072a: 62da str r2, [r3, #44] ; 0x2c
/* Preload all values */
TIM1->EGR |= TIM_EGR_UG;
- 800075c: 4b09 ldr r3, [pc, #36] ; (8000784 <adc_timer_init+0x60>)
- 800075e: 695a ldr r2, [r3, #20]
- 8000760: 4b08 ldr r3, [pc, #32] ; (8000784 <adc_timer_init+0x60>)
- 8000762: 2101 movs r1, #1
- 8000764: 430a orrs r2, r1
- 8000766: 615a str r2, [r3, #20]
+ 800072c: 4b09 ldr r3, [pc, #36] ; (8000754 <adc_timer_init+0x60>)
+ 800072e: 695a ldr r2, [r3, #20]
+ 8000730: 4b08 ldr r3, [pc, #32] ; (8000754 <adc_timer_init+0x60>)
+ 8000732: 2101 movs r1, #1
+ 8000734: 430a orrs r2, r1
+ 8000736: 615a str r2, [r3, #20]
TIM1->CR1 = TIM_CR1_ARPE;
- 8000768: 4b06 ldr r3, [pc, #24] ; (8000784 <adc_timer_init+0x60>)
- 800076a: 2280 movs r2, #128 ; 0x80
- 800076c: 601a str r2, [r3, #0]
+ 8000738: 4b06 ldr r3, [pc, #24] ; (8000754 <adc_timer_init+0x60>)
+ 800073a: 2280 movs r2, #128 ; 0x80
+ 800073c: 601a str r2, [r3, #0]
/* And... go! */
TIM1->CR1 |= TIM_CR1_CEN;
- 800076e: 4b05 ldr r3, [pc, #20] ; (8000784 <adc_timer_init+0x60>)
- 8000770: 681a ldr r2, [r3, #0]
- 8000772: 4b04 ldr r3, [pc, #16] ; (8000784 <adc_timer_init+0x60>)
- 8000774: 2101 movs r1, #1
- 8000776: 430a orrs r2, r1
- 8000778: 601a str r2, [r3, #0]
+ 800073e: 4b05 ldr r3, [pc, #20] ; (8000754 <adc_timer_init+0x60>)
+ 8000740: 681a ldr r2, [r3, #0]
+ 8000742: 4b04 ldr r3, [pc, #16] ; (8000754 <adc_timer_init+0x60>)
+ 8000744: 2101 movs r1, #1
+ 8000746: 430a orrs r2, r1
+ 8000748: 601a str r2, [r3, #0]
}
- 800077a: 46c0 nop ; (mov r8, r8)
- 800077c: 46bd mov sp, r7
- 800077e: b002 add sp, #8
- 8000780: bd80 pop {r7, pc}
- 8000782: 46c0 nop ; (mov r8, r8)
- 8000784: 40012c00 .word 0x40012c00
+ 800074a: 46c0 nop ; (mov r8, r8)
+ 800074c: 46bd mov sp, r7
+ 800074e: b002 add sp, #8
+ 8000750: bd80 pop {r7, pc}
+ 8000752: 46c0 nop ; (mov r8, r8)
+ 8000754: 40012c00 .word 0x40012c00
-08000788 <gdb_dump>:
+08000758 <gdb_dump>:
/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */
static void gdb_dump(void) {
- 8000788: b580 push {r7, lr}
- 800078a: af00 add r7, sp, #0
+ 8000758: b580 push {r7, lr}
+ 800075a: af00 add r7, sp, #0
}
- 800078c: 46c0 nop ; (mov r8, r8)
- 800078e: 46bd mov sp, r7
- 8000790: bd80 pop {r7, pc}
+ 800075c: 46c0 nop ; (mov r8, r8)
+ 800075e: 46bd mov sp, r7
+ 8000760: bd80 pop {r7, pc}
-08000792 <DMA1_Channel1_IRQHandler>:
+08000762 <DMA1_Channel1_IRQHandler>:
void DMA1_Channel1_IRQHandler(void) {
- 8000792: b580 push {r7, lr}
- 8000794: af00 add r7, sp, #0
+ 8000762: b580 push {r7, lr}
+ 8000764: b082 sub sp, #8
+ 8000766: af00 add r7, sp, #0
+ uint32_t isr = DMA1->ISR;
+ 8000768: 4b14 ldr r3, [pc, #80] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
+ 800076a: 681b ldr r3, [r3, #0]
+ 800076c: 603b str r3, [r7, #0]
/* Clear the interrupt flag */
DMA1->IFCR |= DMA_IFCR_CGIF1;
- 8000796: 4b05 ldr r3, [pc, #20] ; (80007ac <DMA1_Channel1_IRQHandler+0x1a>)
- 8000798: 685a ldr r2, [r3, #4]
- 800079a: 4b04 ldr r3, [pc, #16] ; (80007ac <DMA1_Channel1_IRQHandler+0x1a>)
- 800079c: 2101 movs r1, #1
- 800079e: 430a orrs r2, r1
- 80007a0: 605a str r2, [r3, #4]
+ 800076e: 4b13 ldr r3, [pc, #76] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
+ 8000770: 685a ldr r2, [r3, #4]
+ 8000772: 4b12 ldr r3, [pc, #72] ; (80007bc <DMA1_Channel1_IRQHandler+0x5a>)
+ 8000774: 2101 movs r1, #1
+ 8000776: 430a orrs r2, r1
+ 8000778: 605a str r2, [r3, #4]
+
gdb_dump();
- 80007a2: f7ff fff1 bl 8000788 <gdb_dump>
+ 800077a: f7ff ffed bl 8000758 <gdb_dump>
+ static_assert(ARRAY_LEN(adc_buf) % 2 == 0, "ADC_BUFSIZE must be even for half-transfer uart tx logic to work");
+
+ int rc;
+ if (isr & DMA_ISR_HTIF2) /* half-transfer */
+ 800077e: 683b ldr r3, [r7, #0]
+ 8000780: 2240 movs r2, #64 ; 0x40
+ 8000782: 4013 ands r3, r2
+ 8000784: d007 beq.n 8000796 <DMA1_Channel1_IRQHandler+0x34>
+ rc = usart_send_packet_nonblocking((uint8_t *)adc_buf, sizeof(adc_buf)/2);
+ 8000786: 4b0e ldr r3, [pc, #56] ; (80007c0 <DMA1_Channel1_IRQHandler+0x5e>)
+ 8000788: 2120 movs r1, #32
+ 800078a: 0018 movs r0, r3
+ 800078c: f000 f9c6 bl 8000b1c <usart_send_packet_nonblocking>
+ 8000790: 0003 movs r3, r0
+ 8000792: 607b str r3, [r7, #4]
+ 8000794: e006 b.n 80007a4 <DMA1_Channel1_IRQHandler+0x42>
+ else /* end of transfer */
+ rc = usart_send_packet_nonblocking((uint8_t *)adc_buf + ARRAY_LEN(adc_buf)/2, sizeof(adc_buf)/2);
+ 8000796: 4b0b ldr r3, [pc, #44] ; (80007c4 <DMA1_Channel1_IRQHandler+0x62>)
+ 8000798: 2120 movs r1, #32
+ 800079a: 0018 movs r0, r3
+ 800079c: f000 f9be bl 8000b1c <usart_send_packet_nonblocking>
+ 80007a0: 0003 movs r3, r0
+ 80007a2: 607b str r3, [r7, #4]
+
+ if (rc)
+ 80007a4: 687b ldr r3, [r7, #4]
+ 80007a6: 2b00 cmp r3, #0
+ 80007a8: d004 beq.n 80007b4 <DMA1_Channel1_IRQHandler+0x52>
+ usart_overruns++;
+ 80007aa: 4b07 ldr r3, [pc, #28] ; (80007c8 <DMA1_Channel1_IRQHandler+0x66>)
+ 80007ac: 681b ldr r3, [r3, #0]
+ 80007ae: 1c5a adds r2, r3, #1
+ 80007b0: 4b05 ldr r3, [pc, #20] ; (80007c8 <DMA1_Channel1_IRQHandler+0x66>)
+ 80007b2: 601a str r2, [r3, #0]
adc_buf[i] = -255;
}
}
}
*/
}
- 80007a6: 46c0 nop ; (mov r8, r8)
- 80007a8: 46bd mov sp, r7
- 80007aa: bd80 pop {r7, pc}
- 80007ac: 40020000 .word 0x40020000
-
-080007b0 <NVIC_EnableIRQ>:
+ 80007b4: 46c0 nop ; (mov r8, r8)
+ 80007b6: 46bd mov sp, r7
+ 80007b8: b002 add sp, #8
+ 80007ba: bd80 pop {r7, pc}
+ 80007bc: 40020000 .word 0x40020000
+ 80007c0: 200000d0 .word 0x200000d0
+ 80007c4: 200000e0 .word 0x200000e0
+ 80007c8: 200000a0 .word 0x200000a0
+
+080007cc <NVIC_EnableIRQ>:
{
- 80007b0: b580 push {r7, lr}
- 80007b2: b082 sub sp, #8
- 80007b4: af00 add r7, sp, #0
- 80007b6: 0002 movs r2, r0
- 80007b8: 1dfb adds r3, r7, #7
- 80007ba: 701a strb r2, [r3, #0]
+ 80007cc: b580 push {r7, lr}
+ 80007ce: b082 sub sp, #8
+ 80007d0: af00 add r7, sp, #0
+ 80007d2: 0002 movs r2, r0
+ 80007d4: 1dfb adds r3, r7, #7
+ 80007d6: 701a strb r2, [r3, #0]
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- 80007bc: 1dfb adds r3, r7, #7
- 80007be: 781b ldrb r3, [r3, #0]
- 80007c0: 001a movs r2, r3
- 80007c2: 231f movs r3, #31
- 80007c4: 401a ands r2, r3
- 80007c6: 4b04 ldr r3, [pc, #16] ; (80007d8 <NVIC_EnableIRQ+0x28>)
- 80007c8: 2101 movs r1, #1
- 80007ca: 4091 lsls r1, r2
- 80007cc: 000a movs r2, r1
- 80007ce: 601a str r2, [r3, #0]
+ 80007d8: 1dfb adds r3, r7, #7
+ 80007da: 781b ldrb r3, [r3, #0]
+ 80007dc: 001a movs r2, r3
+ 80007de: 231f movs r3, #31
+ 80007e0: 401a ands r2, r3
+ 80007e2: 4b04 ldr r3, [pc, #16] ; (80007f4 <NVIC_EnableIRQ+0x28>)
+ 80007e4: 2101 movs r1, #1
+ 80007e6: 4091 lsls r1, r2
+ 80007e8: 000a movs r2, r1
+ 80007ea: 601a str r2, [r3, #0]
}
- 80007d0: 46c0 nop ; (mov r8, r8)
- 80007d2: 46bd mov sp, r7
- 80007d4: b002 add sp, #8
- 80007d6: bd80 pop {r7, pc}
- 80007d8: e000e100 .word 0xe000e100
+ 80007ec: 46c0 nop ; (mov r8, r8)
+ 80007ee: 46bd mov sp, r7
+ 80007f0: b002 add sp, #8
+ 80007f2: bd80 pop {r7, pc}
+ 80007f4: e000e100 .word 0xe000e100
-080007dc <NVIC_DisableIRQ>:
+080007f8 <NVIC_DisableIRQ>:
{
- 80007dc: b580 push {r7, lr}
- 80007de: b082 sub sp, #8
- 80007e0: af00 add r7, sp, #0
- 80007e2: 0002 movs r2, r0
- 80007e4: 1dfb adds r3, r7, #7
- 80007e6: 701a strb r2, [r3, #0]
+ 80007f8: b580 push {r7, lr}
+ 80007fa: b082 sub sp, #8
+ 80007fc: af00 add r7, sp, #0
+ 80007fe: 0002 movs r2, r0
+ 8000800: 1dfb adds r3, r7, #7
+ 8000802: 701a strb r2, [r3, #0]
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
- 80007e8: 1dfb adds r3, r7, #7
- 80007ea: 781b ldrb r3, [r3, #0]
- 80007ec: 001a movs r2, r3
- 80007ee: 231f movs r3, #31
- 80007f0: 4013 ands r3, r2
- 80007f2: 4905 ldr r1, [pc, #20] ; (8000808 <NVIC_DisableIRQ+0x2c>)
- 80007f4: 2201 movs r2, #1
- 80007f6: 409a lsls r2, r3
- 80007f8: 0013 movs r3, r2
- 80007fa: 2280 movs r2, #128 ; 0x80
- 80007fc: 508b str r3, [r1, r2]
+ 8000804: 1dfb adds r3, r7, #7
+ 8000806: 781b ldrb r3, [r3, #0]
+ 8000808: 001a movs r2, r3
+ 800080a: 231f movs r3, #31
+ 800080c: 4013 ands r3, r2
+ 800080e: 4905 ldr r1, [pc, #20] ; (8000824 <NVIC_DisableIRQ+0x2c>)
+ 8000810: 2201 movs r2, #1
+ 8000812: 409a lsls r2, r3
+ 8000814: 0013 movs r3, r2
+ 8000816: 2280 movs r2, #128 ; 0x80
+ 8000818: 508b str r3, [r1, r2]
}
- 80007fe: 46c0 nop ; (mov r8, r8)
- 8000800: 46bd mov sp, r7
- 8000802: b002 add sp, #8
- 8000804: bd80 pop {r7, pc}
- 8000806: 46c0 nop ; (mov r8, r8)
- 8000808: e000e100 .word 0xe000e100
-
-0800080c <NVIC_SetPriority>:
+ 800081a: 46c0 nop ; (mov r8, r8)
+ 800081c: 46bd mov sp, r7
+ 800081e: b002 add sp, #8
+ 8000820: bd80 pop {r7, pc}
+ 8000822: 46c0 nop ; (mov r8, r8)
+ 8000824: e000e100 .word 0xe000e100
+
+08000828 <NVIC_SetPriority>:
{
- 800080c: b590 push {r4, r7, lr}
- 800080e: b083 sub sp, #12
- 8000810: af00 add r7, sp, #0
- 8000812: 0002 movs r2, r0
- 8000814: 6039 str r1, [r7, #0]
- 8000816: 1dfb adds r3, r7, #7
- 8000818: 701a strb r2, [r3, #0]
+ 8000828: b590 push {r4, r7, lr}
+ 800082a: b083 sub sp, #12
+ 800082c: af00 add r7, sp, #0
+ 800082e: 0002 movs r2, r0
+ 8000830: 6039 str r1, [r7, #0]
+ 8000832: 1dfb adds r3, r7, #7
+ 8000834: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) < 0)
- 800081a: 1dfb adds r3, r7, #7
- 800081c: 781b ldrb r3, [r3, #0]
- 800081e: 2b7f cmp r3, #127 ; 0x7f
- 8000820: d932 bls.n 8000888 <NVIC_SetPriority+0x7c>
+ 8000836: 1dfb adds r3, r7, #7
+ 8000838: 781b ldrb r3, [r3, #0]
+ 800083a: 2b7f cmp r3, #127 ; 0x7f
+ 800083c: d932 bls.n 80008a4 <NVIC_SetPriority+0x7c>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8000822: 4a2f ldr r2, [pc, #188] ; (80008e0 <NVIC_SetPriority+0xd4>)
- 8000824: 1dfb adds r3, r7, #7
- 8000826: 781b ldrb r3, [r3, #0]
- 8000828: 0019 movs r1, r3
- 800082a: 230f movs r3, #15
- 800082c: 400b ands r3, r1
- 800082e: 3b08 subs r3, #8
- 8000830: 089b lsrs r3, r3, #2
- 8000832: 3306 adds r3, #6
- 8000834: 009b lsls r3, r3, #2
- 8000836: 18d3 adds r3, r2, r3
- 8000838: 3304 adds r3, #4
- 800083a: 681b ldr r3, [r3, #0]
- 800083c: 1dfa adds r2, r7, #7
- 800083e: 7812 ldrb r2, [r2, #0]
- 8000840: 0011 movs r1, r2
- 8000842: 2203 movs r2, #3
- 8000844: 400a ands r2, r1
- 8000846: 00d2 lsls r2, r2, #3
- 8000848: 21ff movs r1, #255 ; 0xff
- 800084a: 4091 lsls r1, r2
- 800084c: 000a movs r2, r1
- 800084e: 43d2 mvns r2, r2
- 8000850: 401a ands r2, r3
- 8000852: 0011 movs r1, r2
+ 800083e: 4a2f ldr r2, [pc, #188] ; (80008fc <NVIC_SetPriority+0xd4>)
+ 8000840: 1dfb adds r3, r7, #7
+ 8000842: 781b ldrb r3, [r3, #0]
+ 8000844: 0019 movs r1, r3
+ 8000846: 230f movs r3, #15
+ 8000848: 400b ands r3, r1
+ 800084a: 3b08 subs r3, #8
+ 800084c: 089b lsrs r3, r3, #2
+ 800084e: 3306 adds r3, #6
+ 8000850: 009b lsls r3, r3, #2
+ 8000852: 18d3 adds r3, r2, r3
+ 8000854: 3304 adds r3, #4
+ 8000856: 681b ldr r3, [r3, #0]
+ 8000858: 1dfa adds r2, r7, #7
+ 800085a: 7812 ldrb r2, [r2, #0]
+ 800085c: 0011 movs r1, r2
+ 800085e: 2203 movs r2, #3
+ 8000860: 400a ands r2, r1
+ 8000862: 00d2 lsls r2, r2, #3
+ 8000864: 21ff movs r1, #255 ; 0xff
+ 8000866: 4091 lsls r1, r2
+ 8000868: 000a movs r2, r1
+ 800086a: 43d2 mvns r2, r2
+ 800086c: 401a ands r2, r3
+ 800086e: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 8000854: 683b ldr r3, [r7, #0]
- 8000856: 019b lsls r3, r3, #6
- 8000858: 22ff movs r2, #255 ; 0xff
- 800085a: 401a ands r2, r3
- 800085c: 1dfb adds r3, r7, #7
- 800085e: 781b ldrb r3, [r3, #0]
- 8000860: 0018 movs r0, r3
- 8000862: 2303 movs r3, #3
- 8000864: 4003 ands r3, r0
- 8000866: 00db lsls r3, r3, #3
- 8000868: 409a lsls r2, r3
+ 8000870: 683b ldr r3, [r7, #0]
+ 8000872: 019b lsls r3, r3, #6
+ 8000874: 22ff movs r2, #255 ; 0xff
+ 8000876: 401a ands r2, r3
+ 8000878: 1dfb adds r3, r7, #7
+ 800087a: 781b ldrb r3, [r3, #0]
+ 800087c: 0018 movs r0, r3
+ 800087e: 2303 movs r3, #3
+ 8000880: 4003 ands r3, r0
+ 8000882: 00db lsls r3, r3, #3
+ 8000884: 409a lsls r2, r3
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800086a: 481d ldr r0, [pc, #116] ; (80008e0 <NVIC_SetPriority+0xd4>)
- 800086c: 1dfb adds r3, r7, #7
- 800086e: 781b ldrb r3, [r3, #0]
- 8000870: 001c movs r4, r3
- 8000872: 230f movs r3, #15
- 8000874: 4023 ands r3, r4
- 8000876: 3b08 subs r3, #8
- 8000878: 089b lsrs r3, r3, #2
- 800087a: 430a orrs r2, r1
- 800087c: 3306 adds r3, #6
- 800087e: 009b lsls r3, r3, #2
- 8000880: 18c3 adds r3, r0, r3
- 8000882: 3304 adds r3, #4
- 8000884: 601a str r2, [r3, #0]
+ 8000886: 481d ldr r0, [pc, #116] ; (80008fc <NVIC_SetPriority+0xd4>)
+ 8000888: 1dfb adds r3, r7, #7
+ 800088a: 781b ldrb r3, [r3, #0]
+ 800088c: 001c movs r4, r3
+ 800088e: 230f movs r3, #15
+ 8000890: 4023 ands r3, r4
+ 8000892: 3b08 subs r3, #8
+ 8000894: 089b lsrs r3, r3, #2
+ 8000896: 430a orrs r2, r1
+ 8000898: 3306 adds r3, #6
+ 800089a: 009b lsls r3, r3, #2
+ 800089c: 18c3 adds r3, r0, r3
+ 800089e: 3304 adds r3, #4
+ 80008a0: 601a str r2, [r3, #0]
}
- 8000886: e027 b.n 80008d8 <NVIC_SetPriority+0xcc>
+ 80008a2: e027 b.n 80008f4 <NVIC_SetPriority+0xcc>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8000888: 4a16 ldr r2, [pc, #88] ; (80008e4 <NVIC_SetPriority+0xd8>)
- 800088a: 1dfb adds r3, r7, #7
- 800088c: 781b ldrb r3, [r3, #0]
- 800088e: b25b sxtb r3, r3
- 8000890: 089b lsrs r3, r3, #2
- 8000892: 33c0 adds r3, #192 ; 0xc0
- 8000894: 009b lsls r3, r3, #2
- 8000896: 589b ldr r3, [r3, r2]
- 8000898: 1dfa adds r2, r7, #7
- 800089a: 7812 ldrb r2, [r2, #0]
- 800089c: 0011 movs r1, r2
- 800089e: 2203 movs r2, #3
- 80008a0: 400a ands r2, r1
- 80008a2: 00d2 lsls r2, r2, #3
- 80008a4: 21ff movs r1, #255 ; 0xff
- 80008a6: 4091 lsls r1, r2
- 80008a8: 000a movs r2, r1
- 80008aa: 43d2 mvns r2, r2
- 80008ac: 401a ands r2, r3
- 80008ae: 0011 movs r1, r2
+ 80008a4: 4a16 ldr r2, [pc, #88] ; (8000900 <NVIC_SetPriority+0xd8>)
+ 80008a6: 1dfb adds r3, r7, #7
+ 80008a8: 781b ldrb r3, [r3, #0]
+ 80008aa: b25b sxtb r3, r3
+ 80008ac: 089b lsrs r3, r3, #2
+ 80008ae: 33c0 adds r3, #192 ; 0xc0
+ 80008b0: 009b lsls r3, r3, #2
+ 80008b2: 589b ldr r3, [r3, r2]
+ 80008b4: 1dfa adds r2, r7, #7
+ 80008b6: 7812 ldrb r2, [r2, #0]
+ 80008b8: 0011 movs r1, r2
+ 80008ba: 2203 movs r2, #3
+ 80008bc: 400a ands r2, r1
+ 80008be: 00d2 lsls r2, r2, #3
+ 80008c0: 21ff movs r1, #255 ; 0xff
+ 80008c2: 4091 lsls r1, r2
+ 80008c4: 000a movs r2, r1
+ 80008c6: 43d2 mvns r2, r2
+ 80008c8: 401a ands r2, r3
+ 80008ca: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80008b0: 683b ldr r3, [r7, #0]
- 80008b2: 019b lsls r3, r3, #6
- 80008b4: 22ff movs r2, #255 ; 0xff
- 80008b6: 401a ands r2, r3
- 80008b8: 1dfb adds r3, r7, #7
- 80008ba: 781b ldrb r3, [r3, #0]
- 80008bc: 0018 movs r0, r3
- 80008be: 2303 movs r3, #3
- 80008c0: 4003 ands r3, r0
- 80008c2: 00db lsls r3, r3, #3
- 80008c4: 409a lsls r2, r3
+ 80008cc: 683b ldr r3, [r7, #0]
+ 80008ce: 019b lsls r3, r3, #6
+ 80008d0: 22ff movs r2, #255 ; 0xff
+ 80008d2: 401a ands r2, r3
+ 80008d4: 1dfb adds r3, r7, #7
+ 80008d6: 781b ldrb r3, [r3, #0]
+ 80008d8: 0018 movs r0, r3
+ 80008da: 2303 movs r3, #3
+ 80008dc: 4003 ands r3, r0
+ 80008de: 00db lsls r3, r3, #3
+ 80008e0: 409a lsls r2, r3
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80008c6: 4807 ldr r0, [pc, #28] ; (80008e4 <NVIC_SetPriority+0xd8>)
- 80008c8: 1dfb adds r3, r7, #7
- 80008ca: 781b ldrb r3, [r3, #0]
- 80008cc: b25b sxtb r3, r3
- 80008ce: 089b lsrs r3, r3, #2
- 80008d0: 430a orrs r2, r1
- 80008d2: 33c0 adds r3, #192 ; 0xc0
- 80008d4: 009b lsls r3, r3, #2
- 80008d6: 501a str r2, [r3, r0]
+ 80008e2: 4807 ldr r0, [pc, #28] ; (8000900 <NVIC_SetPriority+0xd8>)
+ 80008e4: 1dfb adds r3, r7, #7
+ 80008e6: 781b ldrb r3, [r3, #0]
+ 80008e8: b25b sxtb r3, r3
+ 80008ea: 089b lsrs r3, r3, #2
+ 80008ec: 430a orrs r2, r1
+ 80008ee: 33c0 adds r3, #192 ; 0xc0
+ 80008f0: 009b lsls r3, r3, #2
+ 80008f2: 501a str r2, [r3, r0]
}
- 80008d8: 46c0 nop ; (mov r8, r8)
- 80008da: 46bd mov sp, r7
- 80008dc: b003 add sp, #12
- 80008de: bd90 pop {r4, r7, pc}
- 80008e0: e000ed00 .word 0xe000ed00
- 80008e4: e000e100 .word 0xe000e100
+ 80008f4: 46c0 nop ; (mov r8, r8)
+ 80008f6: 46bd mov sp, r7
+ 80008f8: b003 add sp, #12
+ 80008fa: bd90 pop {r4, r7, pc}
+ 80008fc: e000ed00 .word 0xe000ed00
+ 8000900: e000e100 .word 0xe000e100
-080008e8 <usart_dma_init>:
+08000904 <usart_dma_init>:
-volatile struct dma_tx_buf usart_tx_buf;
-
-static void usart_schedule_dma();
+static void usart_schedule_dma(void);
+int usart_putc_nonblocking(char c);
+int usart_putc(char c);
void usart_dma_init() {
- 80008e8: b580 push {r7, lr}
- 80008ea: af00 add r7, sp, #0
+ 8000904: b580 push {r7, lr}
+ 8000906: af00 add r7, sp, #0
usart_tx_buf.xfr_start = -1,
- 80008ec: 4b17 ldr r3, [pc, #92] ; (800094c <usart_dma_init+0x64>)
- 80008ee: 2201 movs r2, #1
- 80008f0: 4252 negs r2, r2
- 80008f2: 601a str r2, [r3, #0]
+ 8000908: 4b19 ldr r3, [pc, #100] ; (8000970 <usart_dma_init+0x6c>)
+ 800090a: 2201 movs r2, #1
+ 800090c: 4252 negs r2, r2
+ 800090e: 601a str r2, [r3, #0]
usart_tx_buf.xfr_end = 0,
- 80008f4: 4b15 ldr r3, [pc, #84] ; (800094c <usart_dma_init+0x64>)
- 80008f6: 2200 movs r2, #0
- 80008f8: 605a str r2, [r3, #4]
+ 8000910: 4b17 ldr r3, [pc, #92] ; (8000970 <usart_dma_init+0x6c>)
+ 8000912: 2200 movs r2, #0
+ 8000914: 605a str r2, [r3, #4]
usart_tx_buf.wr_pos = 0,
- 80008fa: 4b14 ldr r3, [pc, #80] ; (800094c <usart_dma_init+0x64>)
- 80008fc: 2200 movs r2, #0
- 80008fe: 609a str r2, [r3, #8]
+ 8000916: 4b16 ldr r3, [pc, #88] ; (8000970 <usart_dma_init+0x6c>)
+ 8000918: 2200 movs r2, #0
+ 800091a: 609a str r2, [r3, #8]
/* Configure DMA 1 Channel 2 to handle uart transmission */
DMA1_Channel2->CPAR = (unsigned int)&(USART1->TDR);
- 8000900: 4b13 ldr r3, [pc, #76] ; (8000950 <usart_dma_init+0x68>)
- 8000902: 4a14 ldr r2, [pc, #80] ; (8000954 <usart_dma_init+0x6c>)
- 8000904: 609a str r2, [r3, #8]
+ 800091c: 4b15 ldr r3, [pc, #84] ; (8000974 <usart_dma_init+0x70>)
+ 800091e: 4a16 ldr r2, [pc, #88] ; (8000978 <usart_dma_init+0x74>)
+ 8000920: 609a str r2, [r3, #8]
DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
- 8000906: 4b12 ldr r3, [pc, #72] ; (8000950 <usart_dma_init+0x68>)
- 8000908: 2292 movs r2, #146 ; 0x92
- 800090a: 601a str r2, [r3, #0]
+ 8000922: 4b14 ldr r3, [pc, #80] ; (8000974 <usart_dma_init+0x70>)
+ 8000924: 2292 movs r2, #146 ; 0x92
+ 8000926: 601a str r2, [r3, #0]
| (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
/* triggered on transfer completion. We use this to process the ADC data */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 800090c: 200a movs r0, #10
- 800090e: f7ff ff4f bl 80007b0 <NVIC_EnableIRQ>
+ 8000928: 200a movs r0, #10
+ 800092a: f7ff ff4f bl 80007cc <NVIC_EnableIRQ>
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
- 8000912: 2120 movs r1, #32
- 8000914: 200a movs r0, #10
- 8000916: f7ff ff79 bl 800080c <NVIC_SetPriority>
+ 800092e: 2120 movs r1, #32
+ 8000930: 200a movs r0, #10
+ 8000932: f7ff ff79 bl 8000828 <NVIC_SetPriority>
USART1->CR1 = /* 8-bit -> M1, M0 clear */
- 800091a: 4b0f ldr r3, [pc, #60] ; (8000958 <usart_dma_init+0x70>)
- 800091c: 4a0f ldr r2, [pc, #60] ; (800095c <usart_dma_init+0x74>)
- 800091e: 601a str r2, [r3, #0]
- | USART_CR1_RXNEIE /* Enable receive interrupt */
- /* other interrupts clear */
- | USART_CR1_TE
+ 8000936: 4b11 ldr r3, [pc, #68] ; (800097c <usart_dma_init+0x78>)
+ 8000938: 4a11 ldr r2, [pc, #68] ; (8000980 <usart_dma_init+0x7c>)
+ 800093a: 601a str r2, [r3, #0]
| USART_CR1_RE;
- /* Set divider for 1MBd @48MHz system clock. */
- USART1->BRR = 48;
- 8000920: 4b0d ldr r3, [pc, #52] ; (8000958 <usart_dma_init+0x70>)
- 8000922: 2230 movs r2, #48 ; 0x30
- 8000924: 60da str r2, [r3, #12]
+ /* Set divider for 115.2kBd @48MHz system clock. */
+ //USART1->BRR = 417;
+
+ //USART1->BRR = 48; /* 1MBd */
+ USART1->BRR = 96; /* 500kBd */
+ 800093c: 4b0f ldr r3, [pc, #60] ; (800097c <usart_dma_init+0x78>)
+ 800093e: 2260 movs r2, #96 ; 0x60
+ 8000940: 60da str r2, [r3, #12]
+ USART1->BRR = 192; /* 250kBd */
+ 8000942: 4b0e ldr r3, [pc, #56] ; (800097c <usart_dma_init+0x78>)
+ 8000944: 22c0 movs r2, #192 ; 0xc0
+ 8000946: 60da str r2, [r3, #12]
+ //USART1->BRR = 208; /* 230400 */
USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
- 8000926: 4b0c ldr r3, [pc, #48] ; (8000958 <usart_dma_init+0x70>)
- 8000928: 22c0 movs r2, #192 ; 0xc0
- 800092a: 0292 lsls r2, r2, #10
- 800092c: 605a str r2, [r3, #4]
+ 8000948: 4b0c ldr r3, [pc, #48] ; (800097c <usart_dma_init+0x78>)
+ 800094a: 22c0 movs r2, #192 ; 0xc0
+ 800094c: 0292 lsls r2, r2, #10
+ 800094e: 605a str r2, [r3, #4]
USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */
- 800092e: 4b0a ldr r3, [pc, #40] ; (8000958 <usart_dma_init+0x70>)
- 8000930: 689a ldr r2, [r3, #8]
- 8000932: 4b09 ldr r3, [pc, #36] ; (8000958 <usart_dma_init+0x70>)
- 8000934: 2180 movs r1, #128 ; 0x80
- 8000936: 430a orrs r2, r1
- 8000938: 609a str r2, [r3, #8]
+ 8000950: 4b0a ldr r3, [pc, #40] ; (800097c <usart_dma_init+0x78>)
+ 8000952: 689a ldr r2, [r3, #8]
+ 8000954: 4b09 ldr r3, [pc, #36] ; (800097c <usart_dma_init+0x78>)
+ 8000956: 2180 movs r1, #128 ; 0x80
+ 8000958: 430a orrs r2, r1
+ 800095a: 609a str r2, [r3, #8]
/* Enable receive interrupt */
//NVIC_EnableIRQ(USART1_IRQn);
//NVIC_SetPriority(USART1_IRQn, 1);
/* And... go! */
USART1->CR1 |= USART_CR1_UE;
- 800093a: 4b07 ldr r3, [pc, #28] ; (8000958 <usart_dma_init+0x70>)
- 800093c: 681a ldr r2, [r3, #0]
- 800093e: 4b06 ldr r3, [pc, #24] ; (8000958 <usart_dma_init+0x70>)
- 8000940: 2101 movs r1, #1
- 8000942: 430a orrs r2, r1
- 8000944: 601a str r2, [r3, #0]
+ 800095c: 4b07 ldr r3, [pc, #28] ; (800097c <usart_dma_init+0x78>)
+ 800095e: 681a ldr r2, [r3, #0]
+ 8000960: 4b06 ldr r3, [pc, #24] ; (800097c <usart_dma_init+0x78>)
+ 8000962: 2101 movs r1, #1
+ 8000964: 430a orrs r2, r1
+ 8000966: 601a str r2, [r3, #0]
}
- 8000946: 46c0 nop ; (mov r8, r8)
- 8000948: 46bd mov sp, r7
- 800094a: bd80 pop {r7, pc}
- 800094c: 200008c8 .word 0x200008c8
- 8000950: 4002001c .word 0x4002001c
- 8000954: 40013828 .word 0x40013828
- 8000958: 40013800 .word 0x40013800
- 800095c: 0000202c .word 0x0000202c
-
-08000960 <usart_schedule_dma>:
+ 8000968: 46c0 nop ; (mov r8, r8)
+ 800096a: 46bd mov sp, r7
+ 800096c: bd80 pop {r7, pc}
+ 800096e: 46c0 nop ; (mov r8, r8)
+ 8000970: 20000110 .word 0x20000110
+ 8000974: 4002001c .word 0x4002001c
+ 8000978: 40013828 .word 0x40013828
+ 800097c: 40013800 .word 0x40013800
+ 8000980: 0000202c .word 0x0000202c
+
+08000984 <usart_schedule_dma>:
void usart_schedule_dma() {
- 8000960: b580 push {r7, lr}
- 8000962: b084 sub sp, #16
- 8000964: af00 add r7, sp, #0
+ 8000984: b580 push {r7, lr}
+ 8000986: b084 sub sp, #16
+ 8000988: af00 add r7, sp, #0
/* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ
* disables. */
volatile struct dma_tx_buf *buf = &usart_tx_buf;
- 8000966: 4b19 ldr r3, [pc, #100] ; (80009cc <usart_schedule_dma+0x6c>)
- 8000968: 60bb str r3, [r7, #8]
+ 800098a: 4b19 ldr r3, [pc, #100] ; (80009f0 <usart_schedule_dma+0x6c>)
+ 800098c: 60bb str r3, [r7, #8]
size_t xfr_len, xfr_start = buf->xfr_end;
- 800096a: 68bb ldr r3, [r7, #8]
- 800096c: 685b ldr r3, [r3, #4]
- 800096e: 607b str r3, [r7, #4]
+ 800098e: 68bb ldr r3, [r7, #8]
+ 8000990: 685b ldr r3, [r3, #4]
+ 8000992: 607b str r3, [r7, #4]
if (buf->wr_pos > xfr_start) /* no wraparound */
- 8000970: 68bb ldr r3, [r7, #8]
- 8000972: 689b ldr r3, [r3, #8]
- 8000974: 687a ldr r2, [r7, #4]
- 8000976: 429a cmp r2, r3
- 8000978: d205 bcs.n 8000986 <usart_schedule_dma+0x26>
+ 8000994: 68bb ldr r3, [r7, #8]
+ 8000996: 689b ldr r3, [r3, #8]
+ 8000998: 687a ldr r2, [r7, #4]
+ 800099a: 429a cmp r2, r3
+ 800099c: d205 bcs.n 80009aa <usart_schedule_dma+0x26>
xfr_len = buf->wr_pos - xfr_start;
- 800097a: 68bb ldr r3, [r7, #8]
- 800097c: 689a ldr r2, [r3, #8]
- 800097e: 687b ldr r3, [r7, #4]
- 8000980: 1ad3 subs r3, r2, r3
- 8000982: 60fb str r3, [r7, #12]
- 8000984: e004 b.n 8000990 <usart_schedule_dma+0x30>
+ 800099e: 68bb ldr r3, [r7, #8]
+ 80009a0: 689a ldr r2, [r3, #8]
+ 80009a2: 687b ldr r3, [r7, #4]
+ 80009a4: 1ad3 subs r3, r2, r3
+ 80009a6: 60fb str r3, [r7, #12]
+ 80009a8: e004 b.n 80009b4 <usart_schedule_dma+0x30>
else /* wraparound */
xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */
- 8000986: 687b ldr r3, [r7, #4]
- 8000988: 2280 movs r2, #128 ; 0x80
- 800098a: 0052 lsls r2, r2, #1
- 800098c: 1ad3 subs r3, r2, r3
- 800098e: 60fb str r3, [r7, #12]
+ 80009aa: 687b ldr r3, [r7, #4]
+ 80009ac: 2280 movs r2, #128 ; 0x80
+ 80009ae: 00d2 lsls r2, r2, #3
+ 80009b0: 1ad3 subs r3, r2, r3
+ 80009b2: 60fb str r3, [r7, #12]
buf->xfr_start = xfr_start;
- 8000990: 68bb ldr r3, [r7, #8]
- 8000992: 687a ldr r2, [r7, #4]
- 8000994: 601a str r2, [r3, #0]
+ 80009b4: 68bb ldr r3, [r7, #8]
+ 80009b6: 687a ldr r2, [r7, #4]
+ 80009b8: 601a str r2, [r3, #0]
buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */
- 8000996: 687a ldr r2, [r7, #4]
- 8000998: 68fb ldr r3, [r7, #12]
- 800099a: 18d3 adds r3, r2, r3
- 800099c: 22ff movs r2, #255 ; 0xff
- 800099e: 401a ands r2, r3
- 80009a0: 68bb ldr r3, [r7, #8]
- 80009a2: 605a str r2, [r3, #4]
+ 80009ba: 687a ldr r2, [r7, #4]
+ 80009bc: 68fb ldr r3, [r7, #12]
+ 80009be: 18d3 adds r3, r2, r3
+ 80009c0: 059b lsls r3, r3, #22
+ 80009c2: 0d9a lsrs r2, r3, #22
+ 80009c4: 68bb ldr r3, [r7, #8]
+ 80009c6: 605a str r2, [r3, #4]
/* initiate transmission of new buffer */
DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start);
- 80009a4: 68bb ldr r3, [r7, #8]
- 80009a6: 330c adds r3, #12
- 80009a8: 001a movs r2, r3
- 80009aa: 687b ldr r3, [r7, #4]
- 80009ac: 18d2 adds r2, r2, r3
- 80009ae: 4b08 ldr r3, [pc, #32] ; (80009d0 <usart_schedule_dma+0x70>)
- 80009b0: 60da str r2, [r3, #12]
+ 80009c8: 68bb ldr r3, [r7, #8]
+ 80009ca: 330c adds r3, #12
+ 80009cc: 001a movs r2, r3
+ 80009ce: 687b ldr r3, [r7, #4]
+ 80009d0: 18d2 adds r2, r2, r3
+ 80009d2: 4b08 ldr r3, [pc, #32] ; (80009f4 <usart_schedule_dma+0x70>)
+ 80009d4: 60da str r2, [r3, #12]
DMA1_Channel2->CNDTR = xfr_len;
- 80009b2: 4b07 ldr r3, [pc, #28] ; (80009d0 <usart_schedule_dma+0x70>)
- 80009b4: 68fa ldr r2, [r7, #12]
- 80009b6: 605a str r2, [r3, #4]
+ 80009d6: 4b07 ldr r3, [pc, #28] ; (80009f4 <usart_schedule_dma+0x70>)
+ 80009d8: 68fa ldr r2, [r7, #12]
+ 80009da: 605a str r2, [r3, #4]
DMA1_Channel2->CCR |= DMA_CCR_EN;
- 80009b8: 4b05 ldr r3, [pc, #20] ; (80009d0 <usart_schedule_dma+0x70>)
- 80009ba: 681a ldr r2, [r3, #0]
- 80009bc: 4b04 ldr r3, [pc, #16] ; (80009d0 <usart_schedule_dma+0x70>)
- 80009be: 2101 movs r1, #1
- 80009c0: 430a orrs r2, r1
- 80009c2: 601a str r2, [r3, #0]
+ 80009dc: 4b05 ldr r3, [pc, #20] ; (80009f4 <usart_schedule_dma+0x70>)
+ 80009de: 681a ldr r2, [r3, #0]
+ 80009e0: 4b04 ldr r3, [pc, #16] ; (80009f4 <usart_schedule_dma+0x70>)
+ 80009e2: 2101 movs r1, #1
+ 80009e4: 430a orrs r2, r1
+ 80009e6: 601a str r2, [r3, #0]
}
- 80009c4: 46c0 nop ; (mov r8, r8)
- 80009c6: 46bd mov sp, r7
- 80009c8: b004 add sp, #16
- 80009ca: bd80 pop {r7, pc}
- 80009cc: 200008c8 .word 0x200008c8
- 80009d0: 4002001c .word 0x4002001c
+ 80009e8: 46c0 nop ; (mov r8, r8)
+ 80009ea: 46bd mov sp, r7
+ 80009ec: b004 add sp, #16
+ 80009ee: bd80 pop {r7, pc}
+ 80009f0: 20000110 .word 0x20000110
+ 80009f4: 4002001c .word 0x4002001c
-080009d4 <usart_dma_fifo_push>:
+080009f8 <usart_dma_fifo_push>:
int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) {
- 80009d4: b580 push {r7, lr}
- 80009d6: b082 sub sp, #8
- 80009d8: af00 add r7, sp, #0
- 80009da: 6078 str r0, [r7, #4]
- 80009dc: 000a movs r2, r1
- 80009de: 1cfb adds r3, r7, #3
- 80009e0: 701a strb r2, [r3, #0]
+ 80009f8: b580 push {r7, lr}
+ 80009fa: b082 sub sp, #8
+ 80009fc: af00 add r7, sp, #0
+ 80009fe: 6078 str r0, [r7, #4]
+ 8000a00: 000a movs r2, r1
+ 8000a02: 1cfb adds r3, r7, #3
+ 8000a04: 701a strb r2, [r3, #0]
/* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */
NVIC_DisableIRQ(DMA1_Channel2_3_IRQn);
- 80009e2: 200a movs r0, #10
- 80009e4: f7ff fefa bl 80007dc <NVIC_DisableIRQ>
+ 8000a06: 200a movs r0, #10
+ 8000a08: f7ff fef6 bl 80007f8 <NVIC_DisableIRQ>
if (buf->wr_pos == buf->xfr_start) {
- 80009e8: 687b ldr r3, [r7, #4]
- 80009ea: 689a ldr r2, [r3, #8]
- 80009ec: 687b ldr r3, [r7, #4]
- 80009ee: 681b ldr r3, [r3, #0]
- 80009f0: 429a cmp r2, r3
- 80009f2: d105 bne.n 8000a00 <usart_dma_fifo_push+0x2c>
+ 8000a0c: 687b ldr r3, [r7, #4]
+ 8000a0e: 689a ldr r2, [r3, #8]
+ 8000a10: 687b ldr r3, [r7, #4]
+ 8000a12: 681b ldr r3, [r3, #0]
+ 8000a14: 429a cmp r2, r3
+ 8000a16: d105 bne.n 8000a24 <usart_dma_fifo_push+0x2c>
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 80009f4: 200a movs r0, #10
- 80009f6: f7ff fedb bl 80007b0 <NVIC_EnableIRQ>
+ 8000a18: 200a movs r0, #10
+ 8000a1a: f7ff fed7 bl 80007cc <NVIC_EnableIRQ>
return -EBUSY;
- 80009fa: 2310 movs r3, #16
- 80009fc: 425b negs r3, r3
- 80009fe: e011 b.n 8000a24 <usart_dma_fifo_push+0x50>
+ 8000a1e: 2310 movs r3, #16
+ 8000a20: 425b negs r3, r3
+ 8000a22: e011 b.n 8000a48 <usart_dma_fifo_push+0x50>
}
buf->data[buf->wr_pos] = c;
- 8000a00: 687b ldr r3, [r7, #4]
- 8000a02: 689b ldr r3, [r3, #8]
- 8000a04: 687a ldr r2, [r7, #4]
- 8000a06: 18d3 adds r3, r2, r3
- 8000a08: 1cfa adds r2, r7, #3
- 8000a0a: 7812 ldrb r2, [r2, #0]
- 8000a0c: 731a strb r2, [r3, #12]
+ 8000a24: 687b ldr r3, [r7, #4]
+ 8000a26: 689b ldr r3, [r3, #8]
+ 8000a28: 687a ldr r2, [r7, #4]
+ 8000a2a: 18d3 adds r3, r2, r3
+ 8000a2c: 1cfa adds r2, r7, #3
+ 8000a2e: 7812 ldrb r2, [r2, #0]
+ 8000a30: 731a strb r2, [r3, #12]
buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data);
- 8000a0e: 687b ldr r3, [r7, #4]
- 8000a10: 689b ldr r3, [r3, #8]
- 8000a12: 3301 adds r3, #1
- 8000a14: 22ff movs r2, #255 ; 0xff
- 8000a16: 401a ands r2, r3
- 8000a18: 687b ldr r3, [r7, #4]
- 8000a1a: 609a str r2, [r3, #8]
+ 8000a32: 687b ldr r3, [r7, #4]
+ 8000a34: 689b ldr r3, [r3, #8]
+ 8000a36: 3301 adds r3, #1
+ 8000a38: 059b lsls r3, r3, #22
+ 8000a3a: 0d9a lsrs r2, r3, #22
+ 8000a3c: 687b ldr r3, [r7, #4]
+ 8000a3e: 609a str r2, [r3, #8]
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8000a1c: 200a movs r0, #10
- 8000a1e: f7ff fec7 bl 80007b0 <NVIC_EnableIRQ>
+ 8000a40: 200a movs r0, #10
+ 8000a42: f7ff fec3 bl 80007cc <NVIC_EnableIRQ>
return 0;
- 8000a22: 2300 movs r3, #0
+ 8000a46: 2300 movs r3, #0
}
- 8000a24: 0018 movs r0, r3
- 8000a26: 46bd mov sp, r7
- 8000a28: b002 add sp, #8
- 8000a2a: bd80 pop {r7, pc}
-
-08000a2c <usart_putc>:
-
-void usart_putc(char c) {
- 8000a2c: b580 push {r7, lr}
- 8000a2e: b082 sub sp, #8
- 8000a30: af00 add r7, sp, #0
- 8000a32: 0002 movs r2, r0
- 8000a34: 1dfb adds r3, r7, #7
- 8000a36: 701a strb r2, [r3, #0]
+ 8000a48: 0018 movs r0, r3
+ 8000a4a: 46bd mov sp, r7
+ 8000a4c: b002 add sp, #8
+ 8000a4e: bd80 pop {r7, pc}
+
+08000a50 <usart_putc>:
+
+int usart_putc(char c) {
+ 8000a50: b580 push {r7, lr}
+ 8000a52: b082 sub sp, #8
+ 8000a54: af00 add r7, sp, #0
+ 8000a56: 0002 movs r2, r0
+ 8000a58: 1dfb adds r3, r7, #7
+ 8000a5a: 701a strb r2, [r3, #0]
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
- 8000a38: 46c0 nop ; (mov r8, r8)
- 8000a3a: 1dfb adds r3, r7, #7
- 8000a3c: 781a ldrb r2, [r3, #0]
- 8000a3e: 4b06 ldr r3, [pc, #24] ; (8000a58 <usart_putc+0x2c>)
- 8000a40: 0011 movs r1, r2
- 8000a42: 0018 movs r0, r3
- 8000a44: f7ff ffc6 bl 80009d4 <usart_dma_fifo_push>
- 8000a48: 0003 movs r3, r0
- 8000a4a: 3310 adds r3, #16
- 8000a4c: d0f5 beq.n 8000a3a <usart_putc+0xe>
+ 8000a5c: 46c0 nop ; (mov r8, r8)
+ 8000a5e: 1dfb adds r3, r7, #7
+ 8000a60: 781a ldrb r2, [r3, #0]
+ 8000a62: 4b06 ldr r3, [pc, #24] ; (8000a7c <usart_putc+0x2c>)
+ 8000a64: 0011 movs r1, r2
+ 8000a66: 0018 movs r0, r3
+ 8000a68: f7ff ffc6 bl 80009f8 <usart_dma_fifo_push>
+ 8000a6c: 0003 movs r3, r0
+ 8000a6e: 3310 adds r3, #16
+ 8000a70: d0f5 beq.n 8000a5e <usart_putc+0xe>
/* idle */
}
+ return 0;
+ 8000a72: 2300 movs r3, #0
}
- 8000a4e: 46c0 nop ; (mov r8, r8)
- 8000a50: 46c0 nop ; (mov r8, r8)
- 8000a52: 46bd mov sp, r7
- 8000a54: b002 add sp, #8
- 8000a56: bd80 pop {r7, pc}
- 8000a58: 200008c8 .word 0x200008c8
+ 8000a74: 0018 movs r0, r3
+ 8000a76: 46bd mov sp, r7
+ 8000a78: b002 add sp, #8
+ 8000a7a: bd80 pop {r7, pc}
+ 8000a7c: 20000110 .word 0x20000110
+
+08000a80 <usart_putc_nonblocking>:
+
+int usart_putc_nonblocking(char c) {
+ 8000a80: b580 push {r7, lr}
+ 8000a82: b082 sub sp, #8
+ 8000a84: af00 add r7, sp, #0
+ 8000a86: 0002 movs r2, r0
+ 8000a88: 1dfb adds r3, r7, #7
+ 8000a8a: 701a strb r2, [r3, #0]
+ return usart_dma_fifo_push(&usart_tx_buf, c);
+ 8000a8c: 1dfb adds r3, r7, #7
+ 8000a8e: 781a ldrb r2, [r3, #0]
+ 8000a90: 4b04 ldr r3, [pc, #16] ; (8000aa4 <usart_putc_nonblocking+0x24>)
+ 8000a92: 0011 movs r1, r2
+ 8000a94: 0018 movs r0, r3
+ 8000a96: f7ff ffaf bl 80009f8 <usart_dma_fifo_push>
+ 8000a9a: 0003 movs r3, r0
+}
+ 8000a9c: 0018 movs r0, r3
+ 8000a9e: 46bd mov sp, r7
+ 8000aa0: b002 add sp, #8
+ 8000aa2: bd80 pop {r7, pc}
+ 8000aa4: 20000110 .word 0x20000110
+
+08000aa8 <DMA1_Channel2_3_IRQHandler>:
-08000a5c <DMA1_Channel2_3_IRQHandler>:
void DMA1_Channel2_3_IRQHandler(void) {
- 8000a5c: b580 push {r7, lr}
- 8000a5e: af00 add r7, sp, #0
+ 8000aa8: b580 push {r7, lr}
+ 8000aaa: af00 add r7, sp, #0
/* Transfer complete */
DMA1->IFCR |= DMA_IFCR_CTCIF2;
- 8000a60: 4b0b ldr r3, [pc, #44] ; (8000a90 <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000a62: 685a ldr r2, [r3, #4]
- 8000a64: 4b0a ldr r3, [pc, #40] ; (8000a90 <DMA1_Channel2_3_IRQHandler+0x34>)
- 8000a66: 2120 movs r1, #32
- 8000a68: 430a orrs r2, r1
- 8000a6a: 605a str r2, [r3, #4]
+ 8000aac: 4b0b ldr r3, [pc, #44] ; (8000adc <DMA1_Channel2_3_IRQHandler+0x34>)
+ 8000aae: 685a ldr r2, [r3, #4]
+ 8000ab0: 4b0a ldr r3, [pc, #40] ; (8000adc <DMA1_Channel2_3_IRQHandler+0x34>)
+ 8000ab2: 2120 movs r1, #32
+ 8000ab4: 430a orrs r2, r1
+ 8000ab6: 605a str r2, [r3, #4]
DMA1_Channel2->CCR &= ~DMA_CCR_EN;
- 8000a6c: 4b09 ldr r3, [pc, #36] ; (8000a94 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000a6e: 681a ldr r2, [r3, #0]
- 8000a70: 4b08 ldr r3, [pc, #32] ; (8000a94 <DMA1_Channel2_3_IRQHandler+0x38>)
- 8000a72: 2101 movs r1, #1
- 8000a74: 438a bics r2, r1
- 8000a76: 601a str r2, [r3, #0]
+ 8000ab8: 4b09 ldr r3, [pc, #36] ; (8000ae0 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000aba: 681a ldr r2, [r3, #0]
+ 8000abc: 4b08 ldr r3, [pc, #32] ; (8000ae0 <DMA1_Channel2_3_IRQHandler+0x38>)
+ 8000abe: 2101 movs r1, #1
+ 8000ac0: 438a bics r2, r1
+ 8000ac2: 601a str r2, [r3, #0]
if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */
- 8000a78: 4b07 ldr r3, [pc, #28] ; (8000a98 <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000a7a: 689a ldr r2, [r3, #8]
- 8000a7c: 4b06 ldr r3, [pc, #24] ; (8000a98 <DMA1_Channel2_3_IRQHandler+0x3c>)
- 8000a7e: 685b ldr r3, [r3, #4]
- 8000a80: 429a cmp r2, r3
- 8000a82: d001 beq.n 8000a88 <DMA1_Channel2_3_IRQHandler+0x2c>
+ 8000ac4: 4b07 ldr r3, [pc, #28] ; (8000ae4 <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000ac6: 689a ldr r2, [r3, #8]
+ 8000ac8: 4b06 ldr r3, [pc, #24] ; (8000ae4 <DMA1_Channel2_3_IRQHandler+0x3c>)
+ 8000aca: 685b ldr r3, [r3, #4]
+ 8000acc: 429a cmp r2, r3
+ 8000ace: d001 beq.n 8000ad4 <DMA1_Channel2_3_IRQHandler+0x2c>
usart_schedule_dma();
- 8000a84: f7ff ff6c bl 8000960 <usart_schedule_dma>
+ 8000ad0: f7ff ff58 bl 8000984 <usart_schedule_dma>
}
- 8000a88: 46c0 nop ; (mov r8, r8)
- 8000a8a: 46bd mov sp, r7
- 8000a8c: bd80 pop {r7, pc}
- 8000a8e: 46c0 nop ; (mov r8, r8)
- 8000a90: 40020000 .word 0x40020000
- 8000a94: 4002001c .word 0x4002001c
- 8000a98: 200008c8 .word 0x200008c8
+ 8000ad4: 46c0 nop ; (mov r8, r8)
+ 8000ad6: 46bd mov sp, r7
+ 8000ad8: bd80 pop {r7, pc}
+ 8000ada: 46c0 nop ; (mov r8, r8)
+ 8000adc: 40020000 .word 0x40020000
+ 8000ae0: 4002001c .word 0x4002001c
+ 8000ae4: 20000110 .word 0x20000110
-08000a9c <usart_send_packet>:
+08000ae8 <usart_send_packet>:
void usart_send_packet(const uint8_t *data, size_t len) {
- 8000a9c: b580 push {r7, lr}
- 8000a9e: b082 sub sp, #8
- 8000aa0: af00 add r7, sp, #0
- 8000aa2: 6078 str r0, [r7, #4]
- 8000aa4: 6039 str r1, [r7, #0]
+ 8000ae8: b580 push {r7, lr}
+ 8000aea: b082 sub sp, #8
+ 8000aec: af00 add r7, sp, #0
+ 8000aee: 6078 str r0, [r7, #4]
+ 8000af0: 6039 str r1, [r7, #0]
/* ignore return value as putf is blocking and always succeeds */
- (void)cobs_encode_usart((char *)data, len);
- 8000aa6: 683a ldr r2, [r7, #0]
- 8000aa8: 687b ldr r3, [r7, #4]
- 8000aaa: 0011 movs r1, r2
- 8000aac: 0018 movs r0, r3
- 8000aae: f000 f870 bl 8000b92 <cobs_encode_usart>
+ (void)cobs_encode_usart(usart_putc, (char *)data, len);
+ 8000af2: 683a ldr r2, [r7, #0]
+ 8000af4: 6879 ldr r1, [r7, #4]
+ 8000af6: 4b07 ldr r3, [pc, #28] ; (8000b14 <usart_send_packet+0x2c>)
+ 8000af8: 0018 movs r0, r3
+ 8000afa: f000 f89c bl 8000c36 <cobs_encode_usart>
/* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
- 8000ab2: 4b05 ldr r3, [pc, #20] ; (8000ac8 <usart_send_packet+0x2c>)
- 8000ab4: 681b ldr r3, [r3, #0]
- 8000ab6: 2201 movs r2, #1
- 8000ab8: 4013 ands r3, r2
- 8000aba: d101 bne.n 8000ac0 <usart_send_packet+0x24>
+ 8000afe: 4b06 ldr r3, [pc, #24] ; (8000b18 <usart_send_packet+0x30>)
+ 8000b00: 681b ldr r3, [r3, #0]
+ 8000b02: 2201 movs r2, #1
+ 8000b04: 4013 ands r3, r2
+ 8000b06: d101 bne.n 8000b0c <usart_send_packet+0x24>
usart_schedule_dma();
- 8000abc: f7ff ff50 bl 8000960 <usart_schedule_dma>
+ 8000b08: f7ff ff3c bl 8000984 <usart_schedule_dma>
}
- 8000ac0: 46c0 nop ; (mov r8, r8)
- 8000ac2: 46bd mov sp, r7
- 8000ac4: b002 add sp, #8
- 8000ac6: bd80 pop {r7, pc}
- 8000ac8: 4002001c .word 0x4002001c
+ 8000b0c: 46c0 nop ; (mov r8, r8)
+ 8000b0e: 46bd mov sp, r7
+ 8000b10: b002 add sp, #8
+ 8000b12: bd80 pop {r7, pc}
+ 8000b14: 08000a51 .word 0x08000a51
+ 8000b18: 4002001c .word 0x4002001c
+
+08000b1c <usart_send_packet_nonblocking>:
+
+int usart_send_packet_nonblocking(const uint8_t *data, size_t len) {
+ 8000b1c: b580 push {r7, lr}
+ 8000b1e: b084 sub sp, #16
+ 8000b20: af00 add r7, sp, #0
+ 8000b22: 6078 str r0, [r7, #4]
+ 8000b24: 6039 str r1, [r7, #0]
+ //if (rc)
+ // return rc;
+ /* END */
+ static uint8_t x = 0;
+
+ for (size_t i=0; i<351; i++)
+ 8000b26: 2300 movs r3, #0
+ 8000b28: 60fb str r3, [r7, #12]
+ 8000b2a: e00b b.n 8000b44 <usart_send_packet_nonblocking+0x28>
+ usart_putc_nonblocking(x++);
+ 8000b2c: 4b0e ldr r3, [pc, #56] ; (8000b68 <usart_send_packet_nonblocking+0x4c>)
+ 8000b2e: 781b ldrb r3, [r3, #0]
+ 8000b30: 1c5a adds r2, r3, #1
+ 8000b32: b2d1 uxtb r1, r2
+ 8000b34: 4a0c ldr r2, [pc, #48] ; (8000b68 <usart_send_packet_nonblocking+0x4c>)
+ 8000b36: 7011 strb r1, [r2, #0]
+ 8000b38: 0018 movs r0, r3
+ 8000b3a: f7ff ffa1 bl 8000a80 <usart_putc_nonblocking>
+ for (size_t i=0; i<351; i++)
+ 8000b3e: 68fb ldr r3, [r7, #12]
+ 8000b40: 3301 adds r3, #1
+ 8000b42: 60fb str r3, [r7, #12]
+ 8000b44: 68fa ldr r2, [r7, #12]
+ 8000b46: 23af movs r3, #175 ; 0xaf
+ 8000b48: 005b lsls r3, r3, #1
+ 8000b4a: 429a cmp r2, r3
+ 8000b4c: d9ee bls.n 8000b2c <usart_send_packet_nonblocking+0x10>
-08000acc <cobs_encode>:
+ /* If the DMA stream is idle right now, schedule a transfer */
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ 8000b4e: 4b07 ldr r3, [pc, #28] ; (8000b6c <usart_send_packet_nonblocking+0x50>)
+ 8000b50: 681b ldr r3, [r3, #0]
+ 8000b52: 2201 movs r2, #1
+ 8000b54: 4013 ands r3, r2
+ 8000b56: d101 bne.n 8000b5c <usart_send_packet_nonblocking+0x40>
+ usart_schedule_dma();
+ 8000b58: f7ff ff14 bl 8000984 <usart_schedule_dma>
+ return 0;
+ 8000b5c: 2300 movs r3, #0
+}
+ 8000b5e: 0018 movs r0, r3
+ 8000b60: 46bd mov sp, r7
+ 8000b62: b004 add sp, #16
+ 8000b64: bd80 pop {r7, pc}
+ 8000b66: 46c0 nop ; (mov r8, r8)
+ 8000b68: 200000a4 .word 0x200000a4
+ 8000b6c: 4002001c .word 0x4002001c
+
+08000b70 <cobs_encode>:
@ ensures \result == -1;
@
@ complete behaviors;
@ disjoint behaviors;
@*/
ssize_t cobs_encode(char *dst, size_t dstlen, char *src, size_t srclen) {
- 8000acc: b580 push {r7, lr}
- 8000ace: b088 sub sp, #32
- 8000ad0: af00 add r7, sp, #0
- 8000ad2: 60f8 str r0, [r7, #12]
- 8000ad4: 60b9 str r1, [r7, #8]
- 8000ad6: 607a str r2, [r7, #4]
- 8000ad8: 603b str r3, [r7, #0]
+ 8000b70: b580 push {r7, lr}
+ 8000b72: b088 sub sp, #32
+ 8000b74: af00 add r7, sp, #0
+ 8000b76: 60f8 str r0, [r7, #12]
+ 8000b78: 60b9 str r1, [r7, #8]
+ 8000b7a: 607a str r2, [r7, #4]
+ 8000b7c: 603b str r3, [r7, #0]
if (dstlen > 65535 || srclen > 254)
- 8000ada: 68ba ldr r2, [r7, #8]
- 8000adc: 2380 movs r3, #128 ; 0x80
- 8000ade: 025b lsls r3, r3, #9
- 8000ae0: 429a cmp r2, r3
- 8000ae2: d202 bcs.n 8000aea <cobs_encode+0x1e>
- 8000ae4: 683b ldr r3, [r7, #0]
- 8000ae6: 2bfe cmp r3, #254 ; 0xfe
- 8000ae8: d902 bls.n 8000af0 <cobs_encode+0x24>
+ 8000b7e: 68ba ldr r2, [r7, #8]
+ 8000b80: 2380 movs r3, #128 ; 0x80
+ 8000b82: 025b lsls r3, r3, #9
+ 8000b84: 429a cmp r2, r3
+ 8000b86: d202 bcs.n 8000b8e <cobs_encode+0x1e>
+ 8000b88: 683b ldr r3, [r7, #0]
+ 8000b8a: 2bfe cmp r3, #254 ; 0xfe
+ 8000b8c: d902 bls.n 8000b94 <cobs_encode+0x24>
return -1;
- 8000aea: 2301 movs r3, #1
- 8000aec: 425b negs r3, r3
- 8000aee: e04c b.n 8000b8a <cobs_encode+0xbe>
+ 8000b8e: 2301 movs r3, #1
+ 8000b90: 425b negs r3, r3
+ 8000b92: e04c b.n 8000c2e <cobs_encode+0xbe>
//@ assert 0 <= dstlen <= 65535 && 0 <= srclen <= 254;
if (dstlen < srclen+2)
- 8000af0: 683b ldr r3, [r7, #0]
- 8000af2: 3302 adds r3, #2
- 8000af4: 68ba ldr r2, [r7, #8]
- 8000af6: 429a cmp r2, r3
- 8000af8: d202 bcs.n 8000b00 <cobs_encode+0x34>
+ 8000b94: 683b ldr r3, [r7, #0]
+ 8000b96: 3302 adds r3, #2
+ 8000b98: 68ba ldr r2, [r7, #8]
+ 8000b9a: 429a cmp r2, r3
+ 8000b9c: d202 bcs.n 8000ba4 <cobs_encode+0x34>
return -1;
- 8000afa: 2301 movs r3, #1
- 8000afc: 425b negs r3, r3
- 8000afe: e044 b.n 8000b8a <cobs_encode+0xbe>
+ 8000b9e: 2301 movs r3, #1
+ 8000ba0: 425b negs r3, r3
+ 8000ba2: e044 b.n 8000c2e <cobs_encode+0xbe>
//@ assert 0 <= srclen < srclen+2 <= dstlen;
size_t p = 0;
- 8000b00: 2300 movs r3, #0
- 8000b02: 61fb str r3, [r7, #28]
+ 8000ba4: 2300 movs r3, #0
+ 8000ba6: 61fb str r3, [r7, #28]
@ loop invariant \forall integer i; 0 <= i < p ==> dst[i] != 0;
@ loop invariant \forall integer i; 0 < i < p ==> (src[i-1] != 0 ==> dst[i] == src[i-1]);
@ loop assigns p, dst[0..srclen+1];
@ loop variant srclen-p+1;
@*/
while (p <= srclen) {
- 8000b04: e036 b.n 8000b74 <cobs_encode+0xa8>
+ 8000ba8: e036 b.n 8000c18 <cobs_encode+0xa8>
char val;
if (p != 0 && src[p-1] != 0) {
- 8000b06: 69fb ldr r3, [r7, #28]
- 8000b08: 2b00 cmp r3, #0
- 8000b0a: d00f beq.n 8000b2c <cobs_encode+0x60>
- 8000b0c: 69fb ldr r3, [r7, #28]
- 8000b0e: 3b01 subs r3, #1
- 8000b10: 687a ldr r2, [r7, #4]
- 8000b12: 18d3 adds r3, r2, r3
- 8000b14: 781b ldrb r3, [r3, #0]
- 8000b16: 2b00 cmp r3, #0
- 8000b18: d008 beq.n 8000b2c <cobs_encode+0x60>
+ 8000baa: 69fb ldr r3, [r7, #28]
+ 8000bac: 2b00 cmp r3, #0
+ 8000bae: d00f beq.n 8000bd0 <cobs_encode+0x60>
+ 8000bb0: 69fb ldr r3, [r7, #28]
+ 8000bb2: 3b01 subs r3, #1
+ 8000bb4: 687a ldr r2, [r7, #4]
+ 8000bb6: 18d3 adds r3, r2, r3
+ 8000bb8: 781b ldrb r3, [r3, #0]
+ 8000bba: 2b00 cmp r3, #0
+ 8000bbc: d008 beq.n 8000bd0 <cobs_encode+0x60>
val = src[p-1];
- 8000b1a: 69fb ldr r3, [r7, #28]
- 8000b1c: 3b01 subs r3, #1
- 8000b1e: 687a ldr r2, [r7, #4]
- 8000b20: 18d2 adds r2, r2, r3
- 8000b22: 231b movs r3, #27
- 8000b24: 18fb adds r3, r7, r3
- 8000b26: 7812 ldrb r2, [r2, #0]
- 8000b28: 701a strb r2, [r3, #0]
- 8000b2a: e019 b.n 8000b60 <cobs_encode+0x94>
+ 8000bbe: 69fb ldr r3, [r7, #28]
+ 8000bc0: 3b01 subs r3, #1
+ 8000bc2: 687a ldr r2, [r7, #4]
+ 8000bc4: 18d2 adds r2, r2, r3
+ 8000bc6: 231b movs r3, #27
+ 8000bc8: 18fb adds r3, r7, r3
+ 8000bca: 7812 ldrb r2, [r2, #0]
+ 8000bcc: 701a strb r2, [r3, #0]
+ 8000bce: e019 b.n 8000c04 <cobs_encode+0x94>
} else {
size_t q = p;
- 8000b2c: 69fb ldr r3, [r7, #28]
- 8000b2e: 617b str r3, [r7, #20]
+ 8000bd0: 69fb ldr r3, [r7, #28]
+ 8000bd2: 617b str r3, [r7, #20]
/*@ loop invariant 0 <= p <= q <= srclen;
@ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
@ loop assigns q;
@ loop variant srclen-q;
@*/
while (q < srclen && src[q] != 0)
- 8000b30: e002 b.n 8000b38 <cobs_encode+0x6c>
+ 8000bd4: e002 b.n 8000bdc <cobs_encode+0x6c>
q++;
- 8000b32: 697b ldr r3, [r7, #20]
- 8000b34: 3301 adds r3, #1
- 8000b36: 617b str r3, [r7, #20]
+ 8000bd6: 697b ldr r3, [r7, #20]
+ 8000bd8: 3301 adds r3, #1
+ 8000bda: 617b str r3, [r7, #20]
while (q < srclen && src[q] != 0)
- 8000b38: 697a ldr r2, [r7, #20]
- 8000b3a: 683b ldr r3, [r7, #0]
- 8000b3c: 429a cmp r2, r3
- 8000b3e: d205 bcs.n 8000b4c <cobs_encode+0x80>
- 8000b40: 687a ldr r2, [r7, #4]
- 8000b42: 697b ldr r3, [r7, #20]
- 8000b44: 18d3 adds r3, r2, r3
- 8000b46: 781b ldrb r3, [r3, #0]
- 8000b48: 2b00 cmp r3, #0
- 8000b4a: d1f2 bne.n 8000b32 <cobs_encode+0x66>
+ 8000bdc: 697a ldr r2, [r7, #20]
+ 8000bde: 683b ldr r3, [r7, #0]
+ 8000be0: 429a cmp r2, r3
+ 8000be2: d205 bcs.n 8000bf0 <cobs_encode+0x80>
+ 8000be4: 687a ldr r2, [r7, #4]
+ 8000be6: 697b ldr r3, [r7, #20]
+ 8000be8: 18d3 adds r3, r2, r3
+ 8000bea: 781b ldrb r3, [r3, #0]
+ 8000bec: 2b00 cmp r3, #0
+ 8000bee: d1f2 bne.n 8000bd6 <cobs_encode+0x66>
//@ assert q == srclen || src[q] == 0;
//@ assert q <= srclen <= 254;
val = (char)q-p+1;
- 8000b4c: 697b ldr r3, [r7, #20]
- 8000b4e: b2da uxtb r2, r3
- 8000b50: 69fb ldr r3, [r7, #28]
- 8000b52: b2db uxtb r3, r3
- 8000b54: 1ad3 subs r3, r2, r3
- 8000b56: b2da uxtb r2, r3
- 8000b58: 231b movs r3, #27
- 8000b5a: 18fb adds r3, r7, r3
- 8000b5c: 3201 adds r2, #1
- 8000b5e: 701a strb r2, [r3, #0]
+ 8000bf0: 697b ldr r3, [r7, #20]
+ 8000bf2: b2da uxtb r2, r3
+ 8000bf4: 69fb ldr r3, [r7, #28]
+ 8000bf6: b2db uxtb r3, r3
+ 8000bf8: 1ad3 subs r3, r2, r3
+ 8000bfa: b2da uxtb r2, r3
+ 8000bfc: 231b movs r3, #27
+ 8000bfe: 18fb adds r3, r7, r3
+ 8000c00: 3201 adds r2, #1
+ 8000c02: 701a strb r2, [r3, #0]
//@ assert val != 0;
}
dst[p] = val;
- 8000b60: 68fa ldr r2, [r7, #12]
- 8000b62: 69fb ldr r3, [r7, #28]
- 8000b64: 18d3 adds r3, r2, r3
- 8000b66: 221b movs r2, #27
- 8000b68: 18ba adds r2, r7, r2
- 8000b6a: 7812 ldrb r2, [r2, #0]
- 8000b6c: 701a strb r2, [r3, #0]
+ 8000c04: 68fa ldr r2, [r7, #12]
+ 8000c06: 69fb ldr r3, [r7, #28]
+ 8000c08: 18d3 adds r3, r2, r3
+ 8000c0a: 221b movs r2, #27
+ 8000c0c: 18ba adds r2, r7, r2
+ 8000c0e: 7812 ldrb r2, [r2, #0]
+ 8000c10: 701a strb r2, [r3, #0]
p++;
- 8000b6e: 69fb ldr r3, [r7, #28]
- 8000b70: 3301 adds r3, #1
- 8000b72: 61fb str r3, [r7, #28]
+ 8000c12: 69fb ldr r3, [r7, #28]
+ 8000c14: 3301 adds r3, #1
+ 8000c16: 61fb str r3, [r7, #28]
while (p <= srclen) {
- 8000b74: 69fa ldr r2, [r7, #28]
- 8000b76: 683b ldr r3, [r7, #0]
- 8000b78: 429a cmp r2, r3
- 8000b7a: d9c4 bls.n 8000b06 <cobs_encode+0x3a>
+ 8000c18: 69fa ldr r2, [r7, #28]
+ 8000c1a: 683b ldr r3, [r7, #0]
+ 8000c1c: 429a cmp r2, r3
+ 8000c1e: d9c4 bls.n 8000baa <cobs_encode+0x3a>
}
dst[p] = 0;
- 8000b7c: 68fa ldr r2, [r7, #12]
- 8000b7e: 69fb ldr r3, [r7, #28]
- 8000b80: 18d3 adds r3, r2, r3
- 8000b82: 2200 movs r2, #0
- 8000b84: 701a strb r2, [r3, #0]
+ 8000c20: 68fa ldr r2, [r7, #12]
+ 8000c22: 69fb ldr r3, [r7, #28]
+ 8000c24: 18d3 adds r3, r2, r3
+ 8000c26: 2200 movs r2, #0
+ 8000c28: 701a strb r2, [r3, #0]
//@ assert p == srclen+1;
return srclen+2;
- 8000b86: 683b ldr r3, [r7, #0]
- 8000b88: 3302 adds r3, #2
+ 8000c2a: 683b ldr r3, [r7, #0]
+ 8000c2c: 3302 adds r3, #2
}
- 8000b8a: 0018 movs r0, r3
- 8000b8c: 46bd mov sp, r7
- 8000b8e: b008 add sp, #32
- 8000b90: bd80 pop {r7, pc}
-
-08000b92 <cobs_encode_usart>:
-
-int cobs_encode_usart(char *src, size_t srclen) {
- 8000b92: b580 push {r7, lr}
- 8000b94: b086 sub sp, #24
- 8000b96: af00 add r7, sp, #0
- 8000b98: 6078 str r0, [r7, #4]
- 8000b9a: 6039 str r1, [r7, #0]
+ 8000c2e: 0018 movs r0, r3
+ 8000c30: 46bd mov sp, r7
+ 8000c32: b008 add sp, #32
+ 8000c34: bd80 pop {r7, pc}
+
+08000c36 <cobs_encode_usart>:
+
+int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) {
+ 8000c36: b580 push {r7, lr}
+ 8000c38: b08a sub sp, #40 ; 0x28
+ 8000c3a: af00 add r7, sp, #0
+ 8000c3c: 60f8 str r0, [r7, #12]
+ 8000c3e: 60b9 str r1, [r7, #8]
+ 8000c40: 607a str r2, [r7, #4]
if (srclen > 254)
- 8000b9c: 683b ldr r3, [r7, #0]
- 8000b9e: 2bfe cmp r3, #254 ; 0xfe
- 8000ba0: d902 bls.n 8000ba8 <cobs_encode_usart+0x16>
+ 8000c42: 687b ldr r3, [r7, #4]
+ 8000c44: 2bfe cmp r3, #254 ; 0xfe
+ 8000c46: d902 bls.n 8000c4e <cobs_encode_usart+0x18>
return -1;
- 8000ba2: 2301 movs r3, #1
- 8000ba4: 425b negs r3, r3
- 8000ba6: e040 b.n 8000c2a <cobs_encode_usart+0x98>
+ 8000c48: 2301 movs r3, #1
+ 8000c4a: 425b negs r3, r3
+ 8000c4c: e04e b.n 8000cec <cobs_encode_usart+0xb6>
//@ assert 0 <= srclen <= 254;
size_t p = 0;
- 8000ba8: 2300 movs r3, #0
- 8000baa: 617b str r3, [r7, #20]
+ 8000c4e: 2300 movs r3, #0
+ 8000c50: 627b str r3, [r7, #36] ; 0x24
/*@ loop invariant 0 <= p <= srclen+1;
@ loop assigns p;
@ loop variant srclen-p+1;
@*/
while (p <= srclen) {
- 8000bac: e035 b.n 8000c1a <cobs_encode_usart+0x88>
+ 8000c52: e03c b.n 8000cce <cobs_encode_usart+0x98>
char val;
if (p != 0 && src[p-1] != 0) {
- 8000bae: 697b ldr r3, [r7, #20]
- 8000bb0: 2b00 cmp r3, #0
- 8000bb2: d00f beq.n 8000bd4 <cobs_encode_usart+0x42>
- 8000bb4: 697b ldr r3, [r7, #20]
- 8000bb6: 3b01 subs r3, #1
- 8000bb8: 687a ldr r2, [r7, #4]
- 8000bba: 18d3 adds r3, r2, r3
- 8000bbc: 781b ldrb r3, [r3, #0]
- 8000bbe: 2b00 cmp r3, #0
- 8000bc0: d008 beq.n 8000bd4 <cobs_encode_usart+0x42>
+ 8000c54: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000c56: 2b00 cmp r3, #0
+ 8000c58: d00f beq.n 8000c7a <cobs_encode_usart+0x44>
+ 8000c5a: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000c5c: 3b01 subs r3, #1
+ 8000c5e: 68ba ldr r2, [r7, #8]
+ 8000c60: 18d3 adds r3, r2, r3
+ 8000c62: 781b ldrb r3, [r3, #0]
+ 8000c64: 2b00 cmp r3, #0
+ 8000c66: d008 beq.n 8000c7a <cobs_encode_usart+0x44>
val = src[p-1];
- 8000bc2: 697b ldr r3, [r7, #20]
- 8000bc4: 3b01 subs r3, #1
- 8000bc6: 687a ldr r2, [r7, #4]
- 8000bc8: 18d2 adds r2, r2, r3
- 8000bca: 2313 movs r3, #19
- 8000bcc: 18fb adds r3, r7, r3
- 8000bce: 7812 ldrb r2, [r2, #0]
- 8000bd0: 701a strb r2, [r3, #0]
- 8000bd2: e019 b.n 8000c08 <cobs_encode_usart+0x76>
+ 8000c68: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000c6a: 3b01 subs r3, #1
+ 8000c6c: 68ba ldr r2, [r7, #8]
+ 8000c6e: 18d2 adds r2, r2, r3
+ 8000c70: 2323 movs r3, #35 ; 0x23
+ 8000c72: 18fb adds r3, r7, r3
+ 8000c74: 7812 ldrb r2, [r2, #0]
+ 8000c76: 701a strb r2, [r3, #0]
+ 8000c78: e019 b.n 8000cae <cobs_encode_usart+0x78>
} else {
size_t q = p;
- 8000bd4: 697b ldr r3, [r7, #20]
- 8000bd6: 60fb str r3, [r7, #12]
+ 8000c7a: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000c7c: 61fb str r3, [r7, #28]
/*@ loop invariant 0 <= p <= q <= srclen;
@ loop invariant \forall integer i; p <= i < q ==> src[i] != 0;
@ loop assigns q;
@ loop variant srclen-q;
@*/
while (q < srclen && src[q] != 0)
- 8000bd8: e002 b.n 8000be0 <cobs_encode_usart+0x4e>
+ 8000c7e: e002 b.n 8000c86 <cobs_encode_usart+0x50>
q++;
- 8000bda: 68fb ldr r3, [r7, #12]
- 8000bdc: 3301 adds r3, #1
- 8000bde: 60fb str r3, [r7, #12]
+ 8000c80: 69fb ldr r3, [r7, #28]
+ 8000c82: 3301 adds r3, #1
+ 8000c84: 61fb str r3, [r7, #28]
while (q < srclen && src[q] != 0)
- 8000be0: 68fa ldr r2, [r7, #12]
- 8000be2: 683b ldr r3, [r7, #0]
- 8000be4: 429a cmp r2, r3
- 8000be6: d205 bcs.n 8000bf4 <cobs_encode_usart+0x62>
- 8000be8: 687a ldr r2, [r7, #4]
- 8000bea: 68fb ldr r3, [r7, #12]
- 8000bec: 18d3 adds r3, r2, r3
- 8000bee: 781b ldrb r3, [r3, #0]
- 8000bf0: 2b00 cmp r3, #0
- 8000bf2: d1f2 bne.n 8000bda <cobs_encode_usart+0x48>
+ 8000c86: 69fa ldr r2, [r7, #28]
+ 8000c88: 687b ldr r3, [r7, #4]
+ 8000c8a: 429a cmp r2, r3
+ 8000c8c: d205 bcs.n 8000c9a <cobs_encode_usart+0x64>
+ 8000c8e: 68ba ldr r2, [r7, #8]
+ 8000c90: 69fb ldr r3, [r7, #28]
+ 8000c92: 18d3 adds r3, r2, r3
+ 8000c94: 781b ldrb r3, [r3, #0]
+ 8000c96: 2b00 cmp r3, #0
+ 8000c98: d1f2 bne.n 8000c80 <cobs_encode_usart+0x4a>
//@ assert q == srclen || src[q] == 0;
//@ assert q <= srclen <= 254;
val = (char)q-p+1;
- 8000bf4: 68fb ldr r3, [r7, #12]
- 8000bf6: b2da uxtb r2, r3
- 8000bf8: 697b ldr r3, [r7, #20]
- 8000bfa: b2db uxtb r3, r3
- 8000bfc: 1ad3 subs r3, r2, r3
- 8000bfe: b2da uxtb r2, r3
- 8000c00: 2313 movs r3, #19
- 8000c02: 18fb adds r3, r7, r3
- 8000c04: 3201 adds r2, #1
- 8000c06: 701a strb r2, [r3, #0]
+ 8000c9a: 69fb ldr r3, [r7, #28]
+ 8000c9c: b2da uxtb r2, r3
+ 8000c9e: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000ca0: b2db uxtb r3, r3
+ 8000ca2: 1ad3 subs r3, r2, r3
+ 8000ca4: b2da uxtb r2, r3
+ 8000ca6: 2323 movs r3, #35 ; 0x23
+ 8000ca8: 18fb adds r3, r7, r3
+ 8000caa: 3201 adds r2, #1
+ 8000cac: 701a strb r2, [r3, #0]
//@ assert val != 0;
}
- usart_putc(val);
- 8000c08: 2313 movs r3, #19
- 8000c0a: 18fb adds r3, r7, r3
- 8000c0c: 781b ldrb r3, [r3, #0]
- 8000c0e: 0018 movs r0, r3
- 8000c10: f7ff ff0c bl 8000a2c <usart_putc>
+ int rv = output(val);
+ 8000cae: 2323 movs r3, #35 ; 0x23
+ 8000cb0: 18fb adds r3, r7, r3
+ 8000cb2: 781a ldrb r2, [r3, #0]
+ 8000cb4: 68fb ldr r3, [r7, #12]
+ 8000cb6: 0010 movs r0, r2
+ 8000cb8: 4798 blx r3
+ 8000cba: 0003 movs r3, r0
+ 8000cbc: 617b str r3, [r7, #20]
+ if (rv)
+ 8000cbe: 697b ldr r3, [r7, #20]
+ 8000cc0: 2b00 cmp r3, #0
+ 8000cc2: d001 beq.n 8000cc8 <cobs_encode_usart+0x92>
+ return rv;
+ 8000cc4: 697b ldr r3, [r7, #20]
+ 8000cc6: e011 b.n 8000cec <cobs_encode_usart+0xb6>
p++;
- 8000c14: 697b ldr r3, [r7, #20]
- 8000c16: 3301 adds r3, #1
- 8000c18: 617b str r3, [r7, #20]
+ 8000cc8: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8000cca: 3301 adds r3, #1
+ 8000ccc: 627b str r3, [r7, #36] ; 0x24
while (p <= srclen) {
- 8000c1a: 697a ldr r2, [r7, #20]
- 8000c1c: 683b ldr r3, [r7, #0]
- 8000c1e: 429a cmp r2, r3
- 8000c20: d9c5 bls.n 8000bae <cobs_encode_usart+0x1c>
+ 8000cce: 6a7a ldr r2, [r7, #36] ; 0x24
+ 8000cd0: 687b ldr r3, [r7, #4]
+ 8000cd2: 429a cmp r2, r3
+ 8000cd4: d9be bls.n 8000c54 <cobs_encode_usart+0x1e>
}
- usart_putc(0);
- 8000c22: 2000 movs r0, #0
- 8000c24: f7ff ff02 bl 8000a2c <usart_putc>
+ int rv = output(0);
+ 8000cd6: 68fb ldr r3, [r7, #12]
+ 8000cd8: 2000 movs r0, #0
+ 8000cda: 4798 blx r3
+ 8000cdc: 0003 movs r3, r0
+ 8000cde: 61bb str r3, [r7, #24]
+ if (rv)
+ 8000ce0: 69bb ldr r3, [r7, #24]
+ 8000ce2: 2b00 cmp r3, #0
+ 8000ce4: d001 beq.n 8000cea <cobs_encode_usart+0xb4>
+ return rv;
+ 8000ce6: 69bb ldr r3, [r7, #24]
+ 8000ce8: e000 b.n 8000cec <cobs_encode_usart+0xb6>
//@ assert p == srclen+1;
return 0;
- 8000c28: 2300 movs r3, #0
+ 8000cea: 2300 movs r3, #0
}
- 8000c2a: 0018 movs r0, r3
- 8000c2c: 46bd mov sp, r7
- 8000c2e: b006 add sp, #24
- 8000c30: bd80 pop {r7, pc}
+ 8000cec: 0018 movs r0, r3
+ 8000cee: 46bd mov sp, r7
+ 8000cf0: b00a add sp, #40 ; 0x28
+ 8000cf2: bd80 pop {r7, pc}
-08000c32 <cobs_decode>:
+08000cf4 <cobs_decode>:
@ ensures \result == -1;
@
@ complete behaviors;
@ disjoint behaviors;
@*/
ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) {
- 8000c32: b580 push {r7, lr}
- 8000c34: b088 sub sp, #32
- 8000c36: af00 add r7, sp, #0
- 8000c38: 60f8 str r0, [r7, #12]
- 8000c3a: 60b9 str r1, [r7, #8]
- 8000c3c: 607a str r2, [r7, #4]
- 8000c3e: 603b str r3, [r7, #0]
+ 8000cf4: b580 push {r7, lr}
+ 8000cf6: b088 sub sp, #32
+ 8000cf8: af00 add r7, sp, #0
+ 8000cfa: 60f8 str r0, [r7, #12]
+ 8000cfc: 60b9 str r1, [r7, #8]
+ 8000cfe: 607a str r2, [r7, #4]
+ 8000d00: 603b str r3, [r7, #0]
if (dstlen > 65535 || srclen > 65535)
- 8000c40: 68ba ldr r2, [r7, #8]
- 8000c42: 2380 movs r3, #128 ; 0x80
- 8000c44: 025b lsls r3, r3, #9
- 8000c46: 429a cmp r2, r3
- 8000c48: d204 bcs.n 8000c54 <cobs_decode+0x22>
- 8000c4a: 683a ldr r2, [r7, #0]
- 8000c4c: 2380 movs r3, #128 ; 0x80
- 8000c4e: 025b lsls r3, r3, #9
- 8000c50: 429a cmp r2, r3
- 8000c52: d302 bcc.n 8000c5a <cobs_decode+0x28>
+ 8000d02: 68ba ldr r2, [r7, #8]
+ 8000d04: 2380 movs r3, #128 ; 0x80
+ 8000d06: 025b lsls r3, r3, #9
+ 8000d08: 429a cmp r2, r3
+ 8000d0a: d204 bcs.n 8000d16 <cobs_decode+0x22>
+ 8000d0c: 683a ldr r2, [r7, #0]
+ 8000d0e: 2380 movs r3, #128 ; 0x80
+ 8000d10: 025b lsls r3, r3, #9
+ 8000d12: 429a cmp r2, r3
+ 8000d14: d302 bcc.n 8000d1c <cobs_decode+0x28>
return -1;
- 8000c54: 2301 movs r3, #1
- 8000c56: 425b negs r3, r3
- 8000c58: e052 b.n 8000d00 <cobs_decode+0xce>
+ 8000d16: 2301 movs r3, #1
+ 8000d18: 425b negs r3, r3
+ 8000d1a: e052 b.n 8000dc2 <cobs_decode+0xce>
if (srclen < 1)
- 8000c5a: 683b ldr r3, [r7, #0]
- 8000c5c: 2b00 cmp r3, #0
- 8000c5e: d102 bne.n 8000c66 <cobs_decode+0x34>
+ 8000d1c: 683b ldr r3, [r7, #0]
+ 8000d1e: 2b00 cmp r3, #0
+ 8000d20: d102 bne.n 8000d28 <cobs_decode+0x34>
return -1;
- 8000c60: 2301 movs r3, #1
- 8000c62: 425b negs r3, r3
- 8000c64: e04c b.n 8000d00 <cobs_decode+0xce>
+ 8000d22: 2301 movs r3, #1
+ 8000d24: 425b negs r3, r3
+ 8000d26: e04c b.n 8000dc2 <cobs_decode+0xce>
if (dstlen < srclen)
- 8000c66: 68ba ldr r2, [r7, #8]
- 8000c68: 683b ldr r3, [r7, #0]
- 8000c6a: 429a cmp r2, r3
- 8000c6c: d202 bcs.n 8000c74 <cobs_decode+0x42>
+ 8000d28: 68ba ldr r2, [r7, #8]
+ 8000d2a: 683b ldr r3, [r7, #0]
+ 8000d2c: 429a cmp r2, r3
+ 8000d2e: d202 bcs.n 8000d36 <cobs_decode+0x42>
return -1;
- 8000c6e: 2301 movs r3, #1
- 8000c70: 425b negs r3, r3
- 8000c72: e045 b.n 8000d00 <cobs_decode+0xce>
+ 8000d30: 2301 movs r3, #1
+ 8000d32: 425b negs r3, r3
+ 8000d34: e045 b.n 8000dc2 <cobs_decode+0xce>
size_t p = 1;
- 8000c74: 2301 movs r3, #1
- 8000c76: 61fb str r3, [r7, #28]
+ 8000d36: 2301 movs r3, #1
+ 8000d38: 61fb str r3, [r7, #28]
size_t c = (unsigned char)src[0];
- 8000c78: 687b ldr r3, [r7, #4]
- 8000c7a: 781b ldrb r3, [r3, #0]
- 8000c7c: 61bb str r3, [r7, #24]
+ 8000d3a: 687b ldr r3, [r7, #4]
+ 8000d3c: 781b ldrb r3, [r3, #0]
+ 8000d3e: 61bb str r3, [r7, #24]
//@ assert 0 <= c < 256;
//@ assert 0 <= c;
//@ assert c < 256;
if (c == 0)
- 8000c7e: 69bb ldr r3, [r7, #24]
- 8000c80: 2b00 cmp r3, #0
- 8000c82: d124 bne.n 8000cce <cobs_decode+0x9c>
+ 8000d40: 69bb ldr r3, [r7, #24]
+ 8000d42: 2b00 cmp r3, #0
+ 8000d44: d124 bne.n 8000d90 <cobs_decode+0x9c>
return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8000c84: 2302 movs r3, #2
- 8000c86: 425b negs r3, r3
- 8000c88: e03a b.n 8000d00 <cobs_decode+0xce>
+ 8000d46: 2302 movs r3, #2
+ 8000d48: 425b negs r3, r3
+ 8000d4a: e03a b.n 8000dc2 <cobs_decode+0xce>
@ loop assigns dst[0..dstlen-1], p, c;
@ loop variant srclen-p;
@*/
while (p < srclen && src[p]) {
char val;
c--;
- 8000c8a: 69bb ldr r3, [r7, #24]
- 8000c8c: 3b01 subs r3, #1
- 8000c8e: 61bb str r3, [r7, #24]
+ 8000d4c: 69bb ldr r3, [r7, #24]
+ 8000d4e: 3b01 subs r3, #1
+ 8000d50: 61bb str r3, [r7, #24]
//@ assert src[p] != 0;
if (c == 0) {
- 8000c90: 69bb ldr r3, [r7, #24]
- 8000c92: 2b00 cmp r3, #0
- 8000c94: d109 bne.n 8000caa <cobs_decode+0x78>
+ 8000d52: 69bb ldr r3, [r7, #24]
+ 8000d54: 2b00 cmp r3, #0
+ 8000d56: d109 bne.n 8000d6c <cobs_decode+0x78>
c = (unsigned char)src[p];
- 8000c96: 687a ldr r2, [r7, #4]
- 8000c98: 69fb ldr r3, [r7, #28]
- 8000c9a: 18d3 adds r3, r2, r3
- 8000c9c: 781b ldrb r3, [r3, #0]
- 8000c9e: 61bb str r3, [r7, #24]
+ 8000d58: 687a ldr r2, [r7, #4]
+ 8000d5a: 69fb ldr r3, [r7, #28]
+ 8000d5c: 18d3 adds r3, r2, r3
+ 8000d5e: 781b ldrb r3, [r3, #0]
+ 8000d60: 61bb str r3, [r7, #24]
val = 0;
- 8000ca0: 2317 movs r3, #23
- 8000ca2: 18fb adds r3, r7, r3
- 8000ca4: 2200 movs r2, #0
- 8000ca6: 701a strb r2, [r3, #0]
- 8000ca8: e006 b.n 8000cb8 <cobs_decode+0x86>
+ 8000d62: 2317 movs r3, #23
+ 8000d64: 18fb adds r3, r7, r3
+ 8000d66: 2200 movs r2, #0
+ 8000d68: 701a strb r2, [r3, #0]
+ 8000d6a: e006 b.n 8000d7a <cobs_decode+0x86>
} else {
val = src[p];
- 8000caa: 687a ldr r2, [r7, #4]
- 8000cac: 69fb ldr r3, [r7, #28]
- 8000cae: 18d2 adds r2, r2, r3
- 8000cb0: 2317 movs r3, #23
- 8000cb2: 18fb adds r3, r7, r3
- 8000cb4: 7812 ldrb r2, [r2, #0]
- 8000cb6: 701a strb r2, [r3, #0]
+ 8000d6c: 687a ldr r2, [r7, #4]
+ 8000d6e: 69fb ldr r3, [r7, #28]
+ 8000d70: 18d2 adds r2, r2, r3
+ 8000d72: 2317 movs r3, #23
+ 8000d74: 18fb adds r3, r7, r3
+ 8000d76: 7812 ldrb r2, [r2, #0]
+ 8000d78: 701a strb r2, [r3, #0]
}
//@ assert 0 <= p-1 <= dstlen-1;
dst[p-1] = val;
- 8000cb8: 69fb ldr r3, [r7, #28]
- 8000cba: 3b01 subs r3, #1
- 8000cbc: 68fa ldr r2, [r7, #12]
- 8000cbe: 18d3 adds r3, r2, r3
- 8000cc0: 2217 movs r2, #23
- 8000cc2: 18ba adds r2, r7, r2
- 8000cc4: 7812 ldrb r2, [r2, #0]
- 8000cc6: 701a strb r2, [r3, #0]
+ 8000d7a: 69fb ldr r3, [r7, #28]
+ 8000d7c: 3b01 subs r3, #1
+ 8000d7e: 68fa ldr r2, [r7, #12]
+ 8000d80: 18d3 adds r3, r2, r3
+ 8000d82: 2217 movs r2, #23
+ 8000d84: 18ba adds r2, r7, r2
+ 8000d86: 7812 ldrb r2, [r2, #0]
+ 8000d88: 701a strb r2, [r3, #0]
p++;
- 8000cc8: 69fb ldr r3, [r7, #28]
- 8000cca: 3301 adds r3, #1
- 8000ccc: 61fb str r3, [r7, #28]
+ 8000d8a: 69fb ldr r3, [r7, #28]
+ 8000d8c: 3301 adds r3, #1
+ 8000d8e: 61fb str r3, [r7, #28]
while (p < srclen && src[p]) {
- 8000cce: 69fa ldr r2, [r7, #28]
- 8000cd0: 683b ldr r3, [r7, #0]
- 8000cd2: 429a cmp r2, r3
- 8000cd4: d205 bcs.n 8000ce2 <cobs_decode+0xb0>
- 8000cd6: 687a ldr r2, [r7, #4]
- 8000cd8: 69fb ldr r3, [r7, #28]
- 8000cda: 18d3 adds r3, r2, r3
- 8000cdc: 781b ldrb r3, [r3, #0]
- 8000cde: 2b00 cmp r3, #0
- 8000ce0: d1d3 bne.n 8000c8a <cobs_decode+0x58>
+ 8000d90: 69fa ldr r2, [r7, #28]
+ 8000d92: 683b ldr r3, [r7, #0]
+ 8000d94: 429a cmp r2, r3
+ 8000d96: d205 bcs.n 8000da4 <cobs_decode+0xb0>
+ 8000d98: 687a ldr r2, [r7, #4]
+ 8000d9a: 69fb ldr r3, [r7, #28]
+ 8000d9c: 18d3 adds r3, r2, r3
+ 8000d9e: 781b ldrb r3, [r3, #0]
+ 8000da0: 2b00 cmp r3, #0
+ 8000da2: d1d3 bne.n 8000d4c <cobs_decode+0x58>
}
if (p == srclen)
- 8000ce2: 69fa ldr r2, [r7, #28]
- 8000ce4: 683b ldr r3, [r7, #0]
- 8000ce6: 429a cmp r2, r3
- 8000ce8: d102 bne.n 8000cf0 <cobs_decode+0xbe>
+ 8000da4: 69fa ldr r2, [r7, #28]
+ 8000da6: 683b ldr r3, [r7, #0]
+ 8000da8: 429a cmp r2, r3
+ 8000daa: d102 bne.n 8000db2 <cobs_decode+0xbe>
return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */
- 8000cea: 2302 movs r3, #2
- 8000cec: 425b negs r3, r3
- 8000cee: e007 b.n 8000d00 <cobs_decode+0xce>
+ 8000dac: 2302 movs r3, #2
+ 8000dae: 425b negs r3, r3
+ 8000db0: e007 b.n 8000dc2 <cobs_decode+0xce>
if (c != 1)
- 8000cf0: 69bb ldr r3, [r7, #24]
- 8000cf2: 2b01 cmp r3, #1
- 8000cf4: d002 beq.n 8000cfc <cobs_decode+0xca>
+ 8000db2: 69bb ldr r3, [r7, #24]
+ 8000db4: 2b01 cmp r3, #1
+ 8000db6: d002 beq.n 8000dbe <cobs_decode+0xca>
return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 8000cf6: 2303 movs r3, #3
- 8000cf8: 425b negs r3, r3
- 8000cfa: e001 b.n 8000d00 <cobs_decode+0xce>
+ 8000db8: 2303 movs r3, #3
+ 8000dba: 425b negs r3, r3
+ 8000dbc: e001 b.n 8000dc2 <cobs_decode+0xce>
//@ assert 0 < p <= srclen <= 65535;
//@ assert src[p] == 0;
//@ assert \forall integer i; 1 <= i < p ==> src[i] != 0;
return p-1;
- 8000cfc: 69fb ldr r3, [r7, #28]
- 8000cfe: 3b01 subs r3, #1
+ 8000dbe: 69fb ldr r3, [r7, #28]
+ 8000dc0: 3b01 subs r3, #1
}
- 8000d00: 0018 movs r0, r3
- 8000d02: 46bd mov sp, r7
- 8000d04: b008 add sp, #32
- 8000d06: bd80 pop {r7, pc}
+ 8000dc2: 0018 movs r0, r3
+ 8000dc4: 46bd mov sp, r7
+ 8000dc6: b008 add sp, #32
+ 8000dc8: bd80 pop {r7, pc}
-08000d08 <cobs_decode_incremental_initialize>:
+08000dca <cobs_decode_incremental_initialize>:
void cobs_decode_incremental_initialize(struct cobs_decode_state *state) {
- 8000d08: b580 push {r7, lr}
- 8000d0a: b082 sub sp, #8
- 8000d0c: af00 add r7, sp, #0
- 8000d0e: 6078 str r0, [r7, #4]
+ 8000dca: b580 push {r7, lr}
+ 8000dcc: b082 sub sp, #8
+ 8000dce: af00 add r7, sp, #0
+ 8000dd0: 6078 str r0, [r7, #4]
state->p = 0;
- 8000d10: 687b ldr r3, [r7, #4]
- 8000d12: 2200 movs r2, #0
- 8000d14: 601a str r2, [r3, #0]
+ 8000dd2: 687b ldr r3, [r7, #4]
+ 8000dd4: 2200 movs r2, #0
+ 8000dd6: 601a str r2, [r3, #0]
state->c = 0;
- 8000d16: 687b ldr r3, [r7, #4]
- 8000d18: 2200 movs r2, #0
- 8000d1a: 605a str r2, [r3, #4]
+ 8000dd8: 687b ldr r3, [r7, #4]
+ 8000dda: 2200 movs r2, #0
+ 8000ddc: 605a str r2, [r3, #4]
}
- 8000d1c: 46c0 nop ; (mov r8, r8)
- 8000d1e: 46bd mov sp, r7
- 8000d20: b002 add sp, #8
- 8000d22: bd80 pop {r7, pc}
+ 8000dde: 46c0 nop ; (mov r8, r8)
+ 8000de0: 46bd mov sp, r7
+ 8000de2: b002 add sp, #8
+ 8000de4: bd80 pop {r7, pc}
-08000d24 <cobs_decode_incremental>:
+08000de6 <cobs_decode_incremental>:
int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) {
- 8000d24: b580 push {r7, lr}
- 8000d26: b088 sub sp, #32
- 8000d28: af00 add r7, sp, #0
- 8000d2a: 60f8 str r0, [r7, #12]
- 8000d2c: 60b9 str r1, [r7, #8]
- 8000d2e: 607a str r2, [r7, #4]
- 8000d30: 001a movs r2, r3
- 8000d32: 1cfb adds r3, r7, #3
- 8000d34: 701a strb r2, [r3, #0]
+ 8000de6: b580 push {r7, lr}
+ 8000de8: b088 sub sp, #32
+ 8000dea: af00 add r7, sp, #0
+ 8000dec: 60f8 str r0, [r7, #12]
+ 8000dee: 60b9 str r1, [r7, #8]
+ 8000df0: 607a str r2, [r7, #4]
+ 8000df2: 001a movs r2, r3
+ 8000df4: 1cfb adds r3, r7, #3
+ 8000df6: 701a strb r2, [r3, #0]
if (state->p == 0) {
- 8000d36: 68fb ldr r3, [r7, #12]
- 8000d38: 681b ldr r3, [r3, #0]
- 8000d3a: 2b00 cmp r3, #0
- 8000d3c: d10e bne.n 8000d5c <cobs_decode_incremental+0x38>
+ 8000df8: 68fb ldr r3, [r7, #12]
+ 8000dfa: 681b ldr r3, [r3, #0]
+ 8000dfc: 2b00 cmp r3, #0
+ 8000dfe: d10e bne.n 8000e1e <cobs_decode_incremental+0x38>
if (src == 0)
- 8000d3e: 1cfb adds r3, r7, #3
- 8000d40: 781b ldrb r3, [r3, #0]
- 8000d42: 2b00 cmp r3, #0
- 8000d44: d054 beq.n 8000df0 <cobs_decode_incremental+0xcc>
+ 8000e00: 1cfb adds r3, r7, #3
+ 8000e02: 781b ldrb r3, [r3, #0]
+ 8000e04: 2b00 cmp r3, #0
+ 8000e06: d054 beq.n 8000eb2 <cobs_decode_incremental+0xcc>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
state->c = (unsigned char)src;
- 8000d46: 1cfb adds r3, r7, #3
- 8000d48: 781a ldrb r2, [r3, #0]
- 8000d4a: 68fb ldr r3, [r7, #12]
- 8000d4c: 605a str r2, [r3, #4]
+ 8000e08: 1cfb adds r3, r7, #3
+ 8000e0a: 781a ldrb r2, [r3, #0]
+ 8000e0c: 68fb ldr r3, [r7, #12]
+ 8000e0e: 605a str r2, [r3, #4]
state->p++;
- 8000d4e: 68fb ldr r3, [r7, #12]
- 8000d50: 681b ldr r3, [r3, #0]
- 8000d52: 1c5a adds r2, r3, #1
- 8000d54: 68fb ldr r3, [r7, #12]
- 8000d56: 601a str r2, [r3, #0]
+ 8000e10: 68fb ldr r3, [r7, #12]
+ 8000e12: 681b ldr r3, [r3, #0]
+ 8000e14: 1c5a adds r2, r3, #1
+ 8000e16: 68fb ldr r3, [r7, #12]
+ 8000e18: 601a str r2, [r3, #0]
return 0;
- 8000d58: 2300 movs r3, #0
- 8000d5a: e050 b.n 8000dfe <cobs_decode_incremental+0xda>
+ 8000e1a: 2300 movs r3, #0
+ 8000e1c: e050 b.n 8000ec0 <cobs_decode_incremental+0xda>
}
if (!src) {
- 8000d5c: 1cfb adds r3, r7, #3
- 8000d5e: 781b ldrb r3, [r3, #0]
- 8000d60: 2b00 cmp r3, #0
- 8000d62: d10d bne.n 8000d80 <cobs_decode_incremental+0x5c>
+ 8000e1e: 1cfb adds r3, r7, #3
+ 8000e20: 781b ldrb r3, [r3, #0]
+ 8000e22: 2b00 cmp r3, #0
+ 8000e24: d10d bne.n 8000e42 <cobs_decode_incremental+0x5c>
if (state->c != 1)
- 8000d64: 68fb ldr r3, [r7, #12]
- 8000d66: 685b ldr r3, [r3, #4]
- 8000d68: 2b01 cmp r3, #1
- 8000d6a: d139 bne.n 8000de0 <cobs_decode_incremental+0xbc>
+ 8000e26: 68fb ldr r3, [r7, #12]
+ 8000e28: 685b ldr r3, [r3, #4]
+ 8000e2a: 2b01 cmp r3, #1
+ 8000e2c: d139 bne.n 8000ea2 <cobs_decode_incremental+0xbc>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
int rv = state->p-1;
- 8000d6c: 68fb ldr r3, [r7, #12]
- 8000d6e: 681b ldr r3, [r3, #0]
- 8000d70: 3b01 subs r3, #1
- 8000d72: 617b str r3, [r7, #20]
+ 8000e2e: 68fb ldr r3, [r7, #12]
+ 8000e30: 681b ldr r3, [r3, #0]
+ 8000e32: 3b01 subs r3, #1
+ 8000e34: 617b str r3, [r7, #20]
cobs_decode_incremental_initialize(state);
- 8000d74: 68fb ldr r3, [r7, #12]
- 8000d76: 0018 movs r0, r3
- 8000d78: f7ff ffc6 bl 8000d08 <cobs_decode_incremental_initialize>
+ 8000e36: 68fb ldr r3, [r7, #12]
+ 8000e38: 0018 movs r0, r3
+ 8000e3a: f7ff ffc6 bl 8000dca <cobs_decode_incremental_initialize>
return rv;
- 8000d7c: 697b ldr r3, [r7, #20]
- 8000d7e: e03e b.n 8000dfe <cobs_decode_incremental+0xda>
+ 8000e3e: 697b ldr r3, [r7, #20]
+ 8000e40: e03e b.n 8000ec0 <cobs_decode_incremental+0xda>
}
char val;
state->c--;
- 8000d80: 68fb ldr r3, [r7, #12]
- 8000d82: 685b ldr r3, [r3, #4]
- 8000d84: 1e5a subs r2, r3, #1
- 8000d86: 68fb ldr r3, [r7, #12]
- 8000d88: 605a str r2, [r3, #4]
+ 8000e42: 68fb ldr r3, [r7, #12]
+ 8000e44: 685b ldr r3, [r3, #4]
+ 8000e46: 1e5a subs r2, r3, #1
+ 8000e48: 68fb ldr r3, [r7, #12]
+ 8000e4a: 605a str r2, [r3, #4]
if (state->c == 0) {
- 8000d8a: 68fb ldr r3, [r7, #12]
- 8000d8c: 685b ldr r3, [r3, #4]
- 8000d8e: 2b00 cmp r3, #0
- 8000d90: d108 bne.n 8000da4 <cobs_decode_incremental+0x80>
+ 8000e4c: 68fb ldr r3, [r7, #12]
+ 8000e4e: 685b ldr r3, [r3, #4]
+ 8000e50: 2b00 cmp r3, #0
+ 8000e52: d108 bne.n 8000e66 <cobs_decode_incremental+0x80>
state->c = (unsigned char)src;
- 8000d92: 1cfb adds r3, r7, #3
- 8000d94: 781a ldrb r2, [r3, #0]
- 8000d96: 68fb ldr r3, [r7, #12]
- 8000d98: 605a str r2, [r3, #4]
+ 8000e54: 1cfb adds r3, r7, #3
+ 8000e56: 781a ldrb r2, [r3, #0]
+ 8000e58: 68fb ldr r3, [r7, #12]
+ 8000e5a: 605a str r2, [r3, #4]
val = 0;
- 8000d9a: 231f movs r3, #31
- 8000d9c: 18fb adds r3, r7, r3
- 8000d9e: 2200 movs r2, #0
- 8000da0: 701a strb r2, [r3, #0]
- 8000da2: e004 b.n 8000dae <cobs_decode_incremental+0x8a>
+ 8000e5c: 231f movs r3, #31
+ 8000e5e: 18fb adds r3, r7, r3
+ 8000e60: 2200 movs r2, #0
+ 8000e62: 701a strb r2, [r3, #0]
+ 8000e64: e004 b.n 8000e70 <cobs_decode_incremental+0x8a>
} else {
val = src;
- 8000da4: 231f movs r3, #31
- 8000da6: 18fb adds r3, r7, r3
- 8000da8: 1cfa adds r2, r7, #3
- 8000daa: 7812 ldrb r2, [r2, #0]
- 8000dac: 701a strb r2, [r3, #0]
+ 8000e66: 231f movs r3, #31
+ 8000e68: 18fb adds r3, r7, r3
+ 8000e6a: 1cfa adds r2, r7, #3
+ 8000e6c: 7812 ldrb r2, [r2, #0]
+ 8000e6e: 701a strb r2, [r3, #0]
}
size_t pos = state->p-1;
- 8000dae: 68fb ldr r3, [r7, #12]
- 8000db0: 681b ldr r3, [r3, #0]
- 8000db2: 3b01 subs r3, #1
- 8000db4: 61bb str r3, [r7, #24]
+ 8000e70: 68fb ldr r3, [r7, #12]
+ 8000e72: 681b ldr r3, [r3, #0]
+ 8000e74: 3b01 subs r3, #1
+ 8000e76: 61bb str r3, [r7, #24]
if (pos >= dstlen)
- 8000db6: 69ba ldr r2, [r7, #24]
- 8000db8: 687b ldr r3, [r7, #4]
- 8000dba: 429a cmp r2, r3
- 8000dbc: d302 bcc.n 8000dc4 <cobs_decode_incremental+0xa0>
+ 8000e78: 69ba ldr r2, [r7, #24]
+ 8000e7a: 687b ldr r3, [r7, #4]
+ 8000e7c: 429a cmp r2, r3
+ 8000e7e: d302 bcc.n 8000e86 <cobs_decode_incremental+0xa0>
return -2; /* output buffer too small */
- 8000dbe: 2302 movs r3, #2
- 8000dc0: 425b negs r3, r3
- 8000dc2: e01c b.n 8000dfe <cobs_decode_incremental+0xda>
+ 8000e80: 2302 movs r3, #2
+ 8000e82: 425b negs r3, r3
+ 8000e84: e01c b.n 8000ec0 <cobs_decode_incremental+0xda>
dst[pos] = val;
- 8000dc4: 68ba ldr r2, [r7, #8]
- 8000dc6: 69bb ldr r3, [r7, #24]
- 8000dc8: 18d3 adds r3, r2, r3
- 8000dca: 221f movs r2, #31
- 8000dcc: 18ba adds r2, r7, r2
- 8000dce: 7812 ldrb r2, [r2, #0]
- 8000dd0: 701a strb r2, [r3, #0]
+ 8000e86: 68ba ldr r2, [r7, #8]
+ 8000e88: 69bb ldr r3, [r7, #24]
+ 8000e8a: 18d3 adds r3, r2, r3
+ 8000e8c: 221f movs r2, #31
+ 8000e8e: 18ba adds r2, r7, r2
+ 8000e90: 7812 ldrb r2, [r2, #0]
+ 8000e92: 701a strb r2, [r3, #0]
state->p++;
- 8000dd2: 68fb ldr r3, [r7, #12]
- 8000dd4: 681b ldr r3, [r3, #0]
- 8000dd6: 1c5a adds r2, r3, #1
- 8000dd8: 68fb ldr r3, [r7, #12]
- 8000dda: 601a str r2, [r3, #0]
+ 8000e94: 68fb ldr r3, [r7, #12]
+ 8000e96: 681b ldr r3, [r3, #0]
+ 8000e98: 1c5a adds r2, r3, #1
+ 8000e9a: 68fb ldr r3, [r7, #12]
+ 8000e9c: 601a str r2, [r3, #0]
return 0;
- 8000ddc: 2300 movs r3, #0
- 8000dde: e00e b.n 8000dfe <cobs_decode_incremental+0xda>
+ 8000e9e: 2300 movs r3, #0
+ 8000ea0: e00e b.n 8000ec0 <cobs_decode_incremental+0xda>
goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */
- 8000de0: 46c0 nop ; (mov r8, r8)
+ 8000ea2: 46c0 nop ; (mov r8, r8)
errout:
cobs_decode_incremental_initialize(state);
- 8000de2: 68fb ldr r3, [r7, #12]
- 8000de4: 0018 movs r0, r3
- 8000de6: f7ff ff8f bl 8000d08 <cobs_decode_incremental_initialize>
+ 8000ea4: 68fb ldr r3, [r7, #12]
+ 8000ea6: 0018 movs r0, r3
+ 8000ea8: f7ff ff8f bl 8000dca <cobs_decode_incremental_initialize>
return -1;
- 8000dea: 2301 movs r3, #1
- 8000dec: 425b negs r3, r3
- 8000dee: e006 b.n 8000dfe <cobs_decode_incremental+0xda>
+ 8000eac: 2301 movs r3, #1
+ 8000eae: 425b negs r3, r3
+ 8000eb0: e006 b.n 8000ec0 <cobs_decode_incremental+0xda>
goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */
- 8000df0: 46c0 nop ; (mov r8, r8)
+ 8000eb2: 46c0 nop ; (mov r8, r8)
empty_errout:
cobs_decode_incremental_initialize(state);
- 8000df2: 68fb ldr r3, [r7, #12]
- 8000df4: 0018 movs r0, r3
- 8000df6: f7ff ff87 bl 8000d08 <cobs_decode_incremental_initialize>
+ 8000eb4: 68fb ldr r3, [r7, #12]
+ 8000eb6: 0018 movs r0, r3
+ 8000eb8: f7ff ff87 bl 8000dca <cobs_decode_incremental_initialize>
return -3;
- 8000dfa: 2303 movs r3, #3
- 8000dfc: 425b negs r3, r3
+ 8000ebc: 2303 movs r3, #3
+ 8000ebe: 425b negs r3, r3
}
- 8000dfe: 0018 movs r0, r3
- 8000e00: 46bd mov sp, r7
- 8000e02: b008 add sp, #32
- 8000e04: bd80 pop {r7, pc}
- 8000e06: 1904 .short 0x1904
- 8000e08: 00000800 .word 0x00000800
- 8000e0c: 00942000 .word 0x00942000
- 8000e10: 00942000 .word 0x00942000
- 8000e14: 09d42000 .word 0x09d42000
- 8000e18: 00002000 .word 0x00002000
-
-08000e1c <SystemInit>:
+ 8000ec0: 0018 movs r0, r3
+ 8000ec2: 46bd mov sp, r7
+ 8000ec4: b008 add sp, #32
+ 8000ec6: bd80 pop {r7, pc}
+ 8000ec8: 080019bc .word 0x080019bc
+ 8000ecc: 20000000 .word 0x20000000
+ 8000ed0: 20000094 .word 0x20000094
+ 8000ed4: 20000094 .word 0x20000094
+ 8000ed8: 2000051c .word 0x2000051c
+
+08000edc <SystemInit>:
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
- 8000e1c: b580 push {r7, lr}
- 8000e1e: af00 add r7, sp, #0
+ 8000edc: b580 push {r7, lr}
+ 8000ede: af00 add r7, sp, #0
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
- 8000e20: 4b1a ldr r3, [pc, #104] ; (8000e8c <SystemInit+0x70>)
- 8000e22: 681a ldr r2, [r3, #0]
- 8000e24: 4b19 ldr r3, [pc, #100] ; (8000e8c <SystemInit+0x70>)
- 8000e26: 2101 movs r1, #1
- 8000e28: 430a orrs r2, r1
- 8000e2a: 601a str r2, [r3, #0]
+ 8000ee0: 4b1a ldr r3, [pc, #104] ; (8000f4c <SystemInit+0x70>)
+ 8000ee2: 681a ldr r2, [r3, #0]
+ 8000ee4: 4b19 ldr r3, [pc, #100] ; (8000f4c <SystemInit+0x70>)
+ 8000ee6: 2101 movs r1, #1
+ 8000ee8: 430a orrs r2, r1
+ 8000eea: 601a str r2, [r3, #0]
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
- 8000e2c: 4b17 ldr r3, [pc, #92] ; (8000e8c <SystemInit+0x70>)
- 8000e2e: 685a ldr r2, [r3, #4]
- 8000e30: 4b16 ldr r3, [pc, #88] ; (8000e8c <SystemInit+0x70>)
- 8000e32: 4917 ldr r1, [pc, #92] ; (8000e90 <SystemInit+0x74>)
- 8000e34: 400a ands r2, r1
- 8000e36: 605a str r2, [r3, #4]
+ 8000eec: 4b17 ldr r3, [pc, #92] ; (8000f4c <SystemInit+0x70>)
+ 8000eee: 685a ldr r2, [r3, #4]
+ 8000ef0: 4b16 ldr r3, [pc, #88] ; (8000f4c <SystemInit+0x70>)
+ 8000ef2: 4917 ldr r1, [pc, #92] ; (8000f50 <SystemInit+0x74>)
+ 8000ef4: 400a ands r2, r1
+ 8000ef6: 605a str r2, [r3, #4]
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
- 8000e38: 4b14 ldr r3, [pc, #80] ; (8000e8c <SystemInit+0x70>)
- 8000e3a: 681a ldr r2, [r3, #0]
- 8000e3c: 4b13 ldr r3, [pc, #76] ; (8000e8c <SystemInit+0x70>)
- 8000e3e: 4915 ldr r1, [pc, #84] ; (8000e94 <SystemInit+0x78>)
- 8000e40: 400a ands r2, r1
- 8000e42: 601a str r2, [r3, #0]
+ 8000ef8: 4b14 ldr r3, [pc, #80] ; (8000f4c <SystemInit+0x70>)
+ 8000efa: 681a ldr r2, [r3, #0]
+ 8000efc: 4b13 ldr r3, [pc, #76] ; (8000f4c <SystemInit+0x70>)
+ 8000efe: 4915 ldr r1, [pc, #84] ; (8000f54 <SystemInit+0x78>)
+ 8000f00: 400a ands r2, r1
+ 8000f02: 601a str r2, [r3, #0]
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
- 8000e44: 4b11 ldr r3, [pc, #68] ; (8000e8c <SystemInit+0x70>)
- 8000e46: 681a ldr r2, [r3, #0]
- 8000e48: 4b10 ldr r3, [pc, #64] ; (8000e8c <SystemInit+0x70>)
- 8000e4a: 4913 ldr r1, [pc, #76] ; (8000e98 <SystemInit+0x7c>)
- 8000e4c: 400a ands r2, r1
- 8000e4e: 601a str r2, [r3, #0]
+ 8000f04: 4b11 ldr r3, [pc, #68] ; (8000f4c <SystemInit+0x70>)
+ 8000f06: 681a ldr r2, [r3, #0]
+ 8000f08: 4b10 ldr r3, [pc, #64] ; (8000f4c <SystemInit+0x70>)
+ 8000f0a: 4913 ldr r1, [pc, #76] ; (8000f58 <SystemInit+0x7c>)
+ 8000f0c: 400a ands r2, r1
+ 8000f0e: 601a str r2, [r3, #0]
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
- 8000e50: 4b0e ldr r3, [pc, #56] ; (8000e8c <SystemInit+0x70>)
- 8000e52: 685a ldr r2, [r3, #4]
- 8000e54: 4b0d ldr r3, [pc, #52] ; (8000e8c <SystemInit+0x70>)
- 8000e56: 4911 ldr r1, [pc, #68] ; (8000e9c <SystemInit+0x80>)
- 8000e58: 400a ands r2, r1
- 8000e5a: 605a str r2, [r3, #4]
+ 8000f10: 4b0e ldr r3, [pc, #56] ; (8000f4c <SystemInit+0x70>)
+ 8000f12: 685a ldr r2, [r3, #4]
+ 8000f14: 4b0d ldr r3, [pc, #52] ; (8000f4c <SystemInit+0x70>)
+ 8000f16: 4911 ldr r1, [pc, #68] ; (8000f5c <SystemInit+0x80>)
+ 8000f18: 400a ands r2, r1
+ 8000f1a: 605a str r2, [r3, #4]
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
- 8000e5c: 4b0b ldr r3, [pc, #44] ; (8000e8c <SystemInit+0x70>)
- 8000e5e: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000e60: 4b0a ldr r3, [pc, #40] ; (8000e8c <SystemInit+0x70>)
- 8000e62: 210f movs r1, #15
- 8000e64: 438a bics r2, r1
- 8000e66: 62da str r2, [r3, #44] ; 0x2c
+ 8000f1c: 4b0b ldr r3, [pc, #44] ; (8000f4c <SystemInit+0x70>)
+ 8000f1e: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000f20: 4b0a ldr r3, [pc, #40] ; (8000f4c <SystemInit+0x70>)
+ 8000f22: 210f movs r1, #15
+ 8000f24: 438a bics r2, r1
+ 8000f26: 62da str r2, [r3, #44] ; 0x2c
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
- 8000e68: 4b08 ldr r3, [pc, #32] ; (8000e8c <SystemInit+0x70>)
- 8000e6a: 6b1a ldr r2, [r3, #48] ; 0x30
- 8000e6c: 4b07 ldr r3, [pc, #28] ; (8000e8c <SystemInit+0x70>)
- 8000e6e: 490c ldr r1, [pc, #48] ; (8000ea0 <SystemInit+0x84>)
- 8000e70: 400a ands r2, r1
- 8000e72: 631a str r2, [r3, #48] ; 0x30
+ 8000f28: 4b08 ldr r3, [pc, #32] ; (8000f4c <SystemInit+0x70>)
+ 8000f2a: 6b1a ldr r2, [r3, #48] ; 0x30
+ 8000f2c: 4b07 ldr r3, [pc, #28] ; (8000f4c <SystemInit+0x70>)
+ 8000f2e: 490c ldr r1, [pc, #48] ; (8000f60 <SystemInit+0x84>)
+ 8000f30: 400a ands r2, r1
+ 8000f32: 631a str r2, [r3, #48] ; 0x30
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
- 8000e74: 4b05 ldr r3, [pc, #20] ; (8000e8c <SystemInit+0x70>)
- 8000e76: 6b5a ldr r2, [r3, #52] ; 0x34
- 8000e78: 4b04 ldr r3, [pc, #16] ; (8000e8c <SystemInit+0x70>)
- 8000e7a: 2101 movs r1, #1
- 8000e7c: 438a bics r2, r1
- 8000e7e: 635a str r2, [r3, #52] ; 0x34
+ 8000f34: 4b05 ldr r3, [pc, #20] ; (8000f4c <SystemInit+0x70>)
+ 8000f36: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000f38: 4b04 ldr r3, [pc, #16] ; (8000f4c <SystemInit+0x70>)
+ 8000f3a: 2101 movs r1, #1
+ 8000f3c: 438a bics r2, r1
+ 8000f3e: 635a str r2, [r3, #52] ; 0x34
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
- 8000e80: 4b02 ldr r3, [pc, #8] ; (8000e8c <SystemInit+0x70>)
- 8000e82: 2200 movs r2, #0
- 8000e84: 609a str r2, [r3, #8]
+ 8000f40: 4b02 ldr r3, [pc, #8] ; (8000f4c <SystemInit+0x70>)
+ 8000f42: 2200 movs r2, #0
+ 8000f44: 609a str r2, [r3, #8]
}
- 8000e86: 46c0 nop ; (mov r8, r8)
- 8000e88: 46bd mov sp, r7
- 8000e8a: bd80 pop {r7, pc}
- 8000e8c: 40021000 .word 0x40021000
- 8000e90: 08ffb80c .word 0x08ffb80c
- 8000e94: fef6ffff .word 0xfef6ffff
- 8000e98: fffbffff .word 0xfffbffff
- 8000e9c: ffc0ffff .word 0xffc0ffff
- 8000ea0: fffffeec .word 0xfffffeec
-
-08000ea4 <SystemCoreClockUpdate>:
+ 8000f46: 46c0 nop ; (mov r8, r8)
+ 8000f48: 46bd mov sp, r7
+ 8000f4a: bd80 pop {r7, pc}
+ 8000f4c: 40021000 .word 0x40021000
+ 8000f50: 08ffb80c .word 0x08ffb80c
+ 8000f54: fef6ffff .word 0xfef6ffff
+ 8000f58: fffbffff .word 0xfffbffff
+ 8000f5c: ffc0ffff .word 0xffc0ffff
+ 8000f60: fffffeec .word 0xfffffeec
+
+08000f64 <SystemCoreClockUpdate>:
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
- 8000ea4: b580 push {r7, lr}
- 8000ea6: b084 sub sp, #16
- 8000ea8: af00 add r7, sp, #0
+ 8000f64: b580 push {r7, lr}
+ 8000f66: b084 sub sp, #16
+ 8000f68: af00 add r7, sp, #0
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
- 8000eaa: 2300 movs r3, #0
- 8000eac: 60fb str r3, [r7, #12]
- 8000eae: 2300 movs r3, #0
- 8000eb0: 60bb str r3, [r7, #8]
- 8000eb2: 2300 movs r3, #0
- 8000eb4: 607b str r3, [r7, #4]
- 8000eb6: 2300 movs r3, #0
- 8000eb8: 603b str r3, [r7, #0]
+ 8000f6a: 2300 movs r3, #0
+ 8000f6c: 60fb str r3, [r7, #12]
+ 8000f6e: 2300 movs r3, #0
+ 8000f70: 60bb str r3, [r7, #8]
+ 8000f72: 2300 movs r3, #0
+ 8000f74: 607b str r3, [r7, #4]
+ 8000f76: 2300 movs r3, #0
+ 8000f78: 603b str r3, [r7, #0]
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
- 8000eba: 4b31 ldr r3, [pc, #196] ; (8000f80 <SystemCoreClockUpdate+0xdc>)
- 8000ebc: 685b ldr r3, [r3, #4]
- 8000ebe: 220c movs r2, #12
- 8000ec0: 4013 ands r3, r2
- 8000ec2: 60fb str r3, [r7, #12]
+ 8000f7a: 4b31 ldr r3, [pc, #196] ; (8001040 <SystemCoreClockUpdate+0xdc>)
+ 8000f7c: 685b ldr r3, [r3, #4]
+ 8000f7e: 220c movs r2, #12
+ 8000f80: 4013 ands r3, r2
+ 8000f82: 60fb str r3, [r7, #12]
switch (tmp)
- 8000ec4: 68fb ldr r3, [r7, #12]
- 8000ec6: 2b08 cmp r3, #8
- 8000ec8: d011 beq.n 8000eee <SystemCoreClockUpdate+0x4a>
- 8000eca: 68fb ldr r3, [r7, #12]
- 8000ecc: 2b08 cmp r3, #8
- 8000ece: d841 bhi.n 8000f54 <SystemCoreClockUpdate+0xb0>
- 8000ed0: 68fb ldr r3, [r7, #12]
- 8000ed2: 2b00 cmp r3, #0
- 8000ed4: d003 beq.n 8000ede <SystemCoreClockUpdate+0x3a>
- 8000ed6: 68fb ldr r3, [r7, #12]
- 8000ed8: 2b04 cmp r3, #4
- 8000eda: d004 beq.n 8000ee6 <SystemCoreClockUpdate+0x42>
- 8000edc: e03a b.n 8000f54 <SystemCoreClockUpdate+0xb0>
+ 8000f84: 68fb ldr r3, [r7, #12]
+ 8000f86: 2b08 cmp r3, #8
+ 8000f88: d011 beq.n 8000fae <SystemCoreClockUpdate+0x4a>
+ 8000f8a: 68fb ldr r3, [r7, #12]
+ 8000f8c: 2b08 cmp r3, #8
+ 8000f8e: d841 bhi.n 8001014 <SystemCoreClockUpdate+0xb0>
+ 8000f90: 68fb ldr r3, [r7, #12]
+ 8000f92: 2b00 cmp r3, #0
+ 8000f94: d003 beq.n 8000f9e <SystemCoreClockUpdate+0x3a>
+ 8000f96: 68fb ldr r3, [r7, #12]
+ 8000f98: 2b04 cmp r3, #4
+ 8000f9a: d004 beq.n 8000fa6 <SystemCoreClockUpdate+0x42>
+ 8000f9c: e03a b.n 8001014 <SystemCoreClockUpdate+0xb0>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 8000ede: 4b29 ldr r3, [pc, #164] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000ee0: 4a29 ldr r2, [pc, #164] ; (8000f88 <SystemCoreClockUpdate+0xe4>)
- 8000ee2: 601a str r2, [r3, #0]
+ 8000f9e: 4b29 ldr r3, [pc, #164] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8000fa0: 4a29 ldr r2, [pc, #164] ; (8001048 <SystemCoreClockUpdate+0xe4>)
+ 8000fa2: 601a str r2, [r3, #0]
break;
- 8000ee4: e03a b.n 8000f5c <SystemCoreClockUpdate+0xb8>
+ 8000fa4: e03a b.n 800101c <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
- 8000ee6: 4b27 ldr r3, [pc, #156] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000ee8: 4a27 ldr r2, [pc, #156] ; (8000f88 <SystemCoreClockUpdate+0xe4>)
- 8000eea: 601a str r2, [r3, #0]
+ 8000fa6: 4b27 ldr r3, [pc, #156] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8000fa8: 4a27 ldr r2, [pc, #156] ; (8001048 <SystemCoreClockUpdate+0xe4>)
+ 8000faa: 601a str r2, [r3, #0]
break;
- 8000eec: e036 b.n 8000f5c <SystemCoreClockUpdate+0xb8>
+ 8000fac: e036 b.n 800101c <SystemCoreClockUpdate+0xb8>
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- 8000eee: 4b24 ldr r3, [pc, #144] ; (8000f80 <SystemCoreClockUpdate+0xdc>)
- 8000ef0: 685a ldr r2, [r3, #4]
- 8000ef2: 23f0 movs r3, #240 ; 0xf0
- 8000ef4: 039b lsls r3, r3, #14
- 8000ef6: 4013 ands r3, r2
- 8000ef8: 60bb str r3, [r7, #8]
+ 8000fae: 4b24 ldr r3, [pc, #144] ; (8001040 <SystemCoreClockUpdate+0xdc>)
+ 8000fb0: 685a ldr r2, [r3, #4]
+ 8000fb2: 23f0 movs r3, #240 ; 0xf0
+ 8000fb4: 039b lsls r3, r3, #14
+ 8000fb6: 4013 ands r3, r2
+ 8000fb8: 60bb str r3, [r7, #8]
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- 8000efa: 4b21 ldr r3, [pc, #132] ; (8000f80 <SystemCoreClockUpdate+0xdc>)
- 8000efc: 685a ldr r2, [r3, #4]
- 8000efe: 2380 movs r3, #128 ; 0x80
- 8000f00: 025b lsls r3, r3, #9
- 8000f02: 4013 ands r3, r2
- 8000f04: 607b str r3, [r7, #4]
+ 8000fba: 4b21 ldr r3, [pc, #132] ; (8001040 <SystemCoreClockUpdate+0xdc>)
+ 8000fbc: 685a ldr r2, [r3, #4]
+ 8000fbe: 2380 movs r3, #128 ; 0x80
+ 8000fc0: 025b lsls r3, r3, #9
+ 8000fc2: 4013 ands r3, r2
+ 8000fc4: 607b str r3, [r7, #4]
pllmull = ( pllmull >> 18) + 2;
- 8000f06: 68bb ldr r3, [r7, #8]
- 8000f08: 0c9b lsrs r3, r3, #18
- 8000f0a: 3302 adds r3, #2
- 8000f0c: 60bb str r3, [r7, #8]
+ 8000fc6: 68bb ldr r3, [r7, #8]
+ 8000fc8: 0c9b lsrs r3, r3, #18
+ 8000fca: 3302 adds r3, #2
+ 8000fcc: 60bb str r3, [r7, #8]
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- 8000f0e: 4b1c ldr r3, [pc, #112] ; (8000f80 <SystemCoreClockUpdate+0xdc>)
- 8000f10: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000f12: 220f movs r2, #15
- 8000f14: 4013 ands r3, r2
- 8000f16: 3301 adds r3, #1
- 8000f18: 603b str r3, [r7, #0]
+ 8000fce: 4b1c ldr r3, [pc, #112] ; (8001040 <SystemCoreClockUpdate+0xdc>)
+ 8000fd0: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000fd2: 220f movs r2, #15
+ 8000fd4: 4013 ands r3, r2
+ 8000fd6: 3301 adds r3, #1
+ 8000fd8: 603b str r3, [r7, #0]
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- 8000f1a: 687a ldr r2, [r7, #4]
- 8000f1c: 2380 movs r3, #128 ; 0x80
- 8000f1e: 025b lsls r3, r3, #9
- 8000f20: 429a cmp r2, r3
- 8000f22: d10a bne.n 8000f3a <SystemCoreClockUpdate+0x96>
+ 8000fda: 687a ldr r2, [r7, #4]
+ 8000fdc: 2380 movs r3, #128 ; 0x80
+ 8000fde: 025b lsls r3, r3, #9
+ 8000fe0: 429a cmp r2, r3
+ 8000fe2: d10a bne.n 8000ffa <SystemCoreClockUpdate+0x96>
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- 8000f24: 6839 ldr r1, [r7, #0]
- 8000f26: 4818 ldr r0, [pc, #96] ; (8000f88 <SystemCoreClockUpdate+0xe4>)
- 8000f28: f000 fb3e bl 80015a8 <__udivsi3>
- 8000f2c: 0003 movs r3, r0
- 8000f2e: 001a movs r2, r3
- 8000f30: 68bb ldr r3, [r7, #8]
- 8000f32: 435a muls r2, r3
- 8000f34: 4b13 ldr r3, [pc, #76] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000f36: 601a str r2, [r3, #0]
+ 8000fe4: 6839 ldr r1, [r7, #0]
+ 8000fe6: 4818 ldr r0, [pc, #96] ; (8001048 <SystemCoreClockUpdate+0xe4>)
+ 8000fe8: f000 fb3e bl 8001668 <__udivsi3>
+ 8000fec: 0003 movs r3, r0
+ 8000fee: 001a movs r2, r3
+ 8000ff0: 68bb ldr r3, [r7, #8]
+ 8000ff2: 435a muls r2, r3
+ 8000ff4: 4b13 ldr r3, [pc, #76] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8000ff6: 601a str r2, [r3, #0]
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
- 8000f38: e010 b.n 8000f5c <SystemCoreClockUpdate+0xb8>
+ 8000ff8: e010 b.n 800101c <SystemCoreClockUpdate+0xb8>
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- 8000f3a: 68b9 ldr r1, [r7, #8]
- 8000f3c: 000a movs r2, r1
- 8000f3e: 0152 lsls r2, r2, #5
- 8000f40: 1a52 subs r2, r2, r1
- 8000f42: 0193 lsls r3, r2, #6
- 8000f44: 1a9b subs r3, r3, r2
- 8000f46: 00db lsls r3, r3, #3
- 8000f48: 185b adds r3, r3, r1
- 8000f4a: 021b lsls r3, r3, #8
- 8000f4c: 001a movs r2, r3
- 8000f4e: 4b0d ldr r3, [pc, #52] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000f50: 601a str r2, [r3, #0]
+ 8000ffa: 68b9 ldr r1, [r7, #8]
+ 8000ffc: 000a movs r2, r1
+ 8000ffe: 0152 lsls r2, r2, #5
+ 8001000: 1a52 subs r2, r2, r1
+ 8001002: 0193 lsls r3, r2, #6
+ 8001004: 1a9b subs r3, r3, r2
+ 8001006: 00db lsls r3, r3, #3
+ 8001008: 185b adds r3, r3, r1
+ 800100a: 021b lsls r3, r3, #8
+ 800100c: 001a movs r2, r3
+ 800100e: 4b0d ldr r3, [pc, #52] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8001010: 601a str r2, [r3, #0]
break;
- 8000f52: e003 b.n 8000f5c <SystemCoreClockUpdate+0xb8>
+ 8001012: e003 b.n 800101c <SystemCoreClockUpdate+0xb8>
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
- 8000f54: 4b0b ldr r3, [pc, #44] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000f56: 4a0c ldr r2, [pc, #48] ; (8000f88 <SystemCoreClockUpdate+0xe4>)
- 8000f58: 601a str r2, [r3, #0]
+ 8001014: 4b0b ldr r3, [pc, #44] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8001016: 4a0c ldr r2, [pc, #48] ; (8001048 <SystemCoreClockUpdate+0xe4>)
+ 8001018: 601a str r2, [r3, #0]
break;
- 8000f5a: 46c0 nop ; (mov r8, r8)
+ 800101a: 46c0 nop ; (mov r8, r8)
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- 8000f5c: 4b08 ldr r3, [pc, #32] ; (8000f80 <SystemCoreClockUpdate+0xdc>)
- 8000f5e: 685b ldr r3, [r3, #4]
- 8000f60: 091b lsrs r3, r3, #4
- 8000f62: 220f movs r2, #15
- 8000f64: 4013 ands r3, r2
- 8000f66: 4a09 ldr r2, [pc, #36] ; (8000f8c <SystemCoreClockUpdate+0xe8>)
- 8000f68: 5cd3 ldrb r3, [r2, r3]
- 8000f6a: 60fb str r3, [r7, #12]
+ 800101c: 4b08 ldr r3, [pc, #32] ; (8001040 <SystemCoreClockUpdate+0xdc>)
+ 800101e: 685b ldr r3, [r3, #4]
+ 8001020: 091b lsrs r3, r3, #4
+ 8001022: 220f movs r2, #15
+ 8001024: 4013 ands r3, r2
+ 8001026: 4a09 ldr r2, [pc, #36] ; (800104c <SystemCoreClockUpdate+0xe8>)
+ 8001028: 5cd3 ldrb r3, [r2, r3]
+ 800102a: 60fb str r3, [r7, #12]
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
- 8000f6c: 4b05 ldr r3, [pc, #20] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000f6e: 681a ldr r2, [r3, #0]
- 8000f70: 68fb ldr r3, [r7, #12]
- 8000f72: 40da lsrs r2, r3
- 8000f74: 4b03 ldr r3, [pc, #12] ; (8000f84 <SystemCoreClockUpdate+0xe0>)
- 8000f76: 601a str r2, [r3, #0]
+ 800102c: 4b05 ldr r3, [pc, #20] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 800102e: 681a ldr r2, [r3, #0]
+ 8001030: 68fb ldr r3, [r7, #12]
+ 8001032: 40da lsrs r2, r3
+ 8001034: 4b03 ldr r3, [pc, #12] ; (8001044 <SystemCoreClockUpdate+0xe0>)
+ 8001036: 601a str r2, [r3, #0]
}
- 8000f78: 46c0 nop ; (mov r8, r8)
- 8000f7a: 46bd mov sp, r7
- 8000f7c: b004 add sp, #16
- 8000f7e: bd80 pop {r7, pc}
- 8000f80: 40021000 .word 0x40021000
- 8000f84: 20000000 .word 0x20000000
- 8000f88: 007a1200 .word 0x007a1200
- 8000f8c: 080018ec .word 0x080018ec
-
-08000f90 <LL_RCC_HSE_EnableBypass>:
+ 8001038: 46c0 nop ; (mov r8, r8)
+ 800103a: 46bd mov sp, r7
+ 800103c: b004 add sp, #16
+ 800103e: bd80 pop {r7, pc}
+ 8001040: 40021000 .word 0x40021000
+ 8001044: 20000000 .word 0x20000000
+ 8001048: 007a1200 .word 0x007a1200
+ 800104c: 080019a4 .word 0x080019a4
+
+08001050 <LL_RCC_HSE_EnableBypass>:
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
- 8000f90: b580 push {r7, lr}
- 8000f92: af00 add r7, sp, #0
+ 8001050: b580 push {r7, lr}
+ 8001052: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
- 8000f94: 4b04 ldr r3, [pc, #16] ; (8000fa8 <LL_RCC_HSE_EnableBypass+0x18>)
- 8000f96: 681a ldr r2, [r3, #0]
- 8000f98: 4b03 ldr r3, [pc, #12] ; (8000fa8 <LL_RCC_HSE_EnableBypass+0x18>)
- 8000f9a: 2180 movs r1, #128 ; 0x80
- 8000f9c: 02c9 lsls r1, r1, #11
- 8000f9e: 430a orrs r2, r1
- 8000fa0: 601a str r2, [r3, #0]
+ 8001054: 4b04 ldr r3, [pc, #16] ; (8001068 <LL_RCC_HSE_EnableBypass+0x18>)
+ 8001056: 681a ldr r2, [r3, #0]
+ 8001058: 4b03 ldr r3, [pc, #12] ; (8001068 <LL_RCC_HSE_EnableBypass+0x18>)
+ 800105a: 2180 movs r1, #128 ; 0x80
+ 800105c: 02c9 lsls r1, r1, #11
+ 800105e: 430a orrs r2, r1
+ 8001060: 601a str r2, [r3, #0]
}
- 8000fa2: 46c0 nop ; (mov r8, r8)
- 8000fa4: 46bd mov sp, r7
- 8000fa6: bd80 pop {r7, pc}
- 8000fa8: 40021000 .word 0x40021000
+ 8001062: 46c0 nop ; (mov r8, r8)
+ 8001064: 46bd mov sp, r7
+ 8001066: bd80 pop {r7, pc}
+ 8001068: 40021000 .word 0x40021000
-08000fac <LL_RCC_HSE_DisableBypass>:
+0800106c <LL_RCC_HSE_DisableBypass>:
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
- 8000fac: b580 push {r7, lr}
- 8000fae: af00 add r7, sp, #0
+ 800106c: b580 push {r7, lr}
+ 800106e: af00 add r7, sp, #0
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
- 8000fb0: 4b04 ldr r3, [pc, #16] ; (8000fc4 <LL_RCC_HSE_DisableBypass+0x18>)
- 8000fb2: 681a ldr r2, [r3, #0]
- 8000fb4: 4b03 ldr r3, [pc, #12] ; (8000fc4 <LL_RCC_HSE_DisableBypass+0x18>)
- 8000fb6: 4904 ldr r1, [pc, #16] ; (8000fc8 <LL_RCC_HSE_DisableBypass+0x1c>)
- 8000fb8: 400a ands r2, r1
- 8000fba: 601a str r2, [r3, #0]
+ 8001070: 4b04 ldr r3, [pc, #16] ; (8001084 <LL_RCC_HSE_DisableBypass+0x18>)
+ 8001072: 681a ldr r2, [r3, #0]
+ 8001074: 4b03 ldr r3, [pc, #12] ; (8001084 <LL_RCC_HSE_DisableBypass+0x18>)
+ 8001076: 4904 ldr r1, [pc, #16] ; (8001088 <LL_RCC_HSE_DisableBypass+0x1c>)
+ 8001078: 400a ands r2, r1
+ 800107a: 601a str r2, [r3, #0]
}
- 8000fbc: 46c0 nop ; (mov r8, r8)
- 8000fbe: 46bd mov sp, r7
- 8000fc0: bd80 pop {r7, pc}
- 8000fc2: 46c0 nop ; (mov r8, r8)
- 8000fc4: 40021000 .word 0x40021000
- 8000fc8: fffbffff .word 0xfffbffff
-
-08000fcc <LL_RCC_HSE_Enable>:
+ 800107c: 46c0 nop ; (mov r8, r8)
+ 800107e: 46bd mov sp, r7
+ 8001080: bd80 pop {r7, pc}
+ 8001082: 46c0 nop ; (mov r8, r8)
+ 8001084: 40021000 .word 0x40021000
+ 8001088: fffbffff .word 0xfffbffff
+
+0800108c <LL_RCC_HSE_Enable>:
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
- 8000fcc: b580 push {r7, lr}
- 8000fce: af00 add r7, sp, #0
+ 800108c: b580 push {r7, lr}
+ 800108e: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSEON);
- 8000fd0: 4b04 ldr r3, [pc, #16] ; (8000fe4 <LL_RCC_HSE_Enable+0x18>)
- 8000fd2: 681a ldr r2, [r3, #0]
- 8000fd4: 4b03 ldr r3, [pc, #12] ; (8000fe4 <LL_RCC_HSE_Enable+0x18>)
- 8000fd6: 2180 movs r1, #128 ; 0x80
- 8000fd8: 0249 lsls r1, r1, #9
- 8000fda: 430a orrs r2, r1
- 8000fdc: 601a str r2, [r3, #0]
+ 8001090: 4b04 ldr r3, [pc, #16] ; (80010a4 <LL_RCC_HSE_Enable+0x18>)
+ 8001092: 681a ldr r2, [r3, #0]
+ 8001094: 4b03 ldr r3, [pc, #12] ; (80010a4 <LL_RCC_HSE_Enable+0x18>)
+ 8001096: 2180 movs r1, #128 ; 0x80
+ 8001098: 0249 lsls r1, r1, #9
+ 800109a: 430a orrs r2, r1
+ 800109c: 601a str r2, [r3, #0]
}
- 8000fde: 46c0 nop ; (mov r8, r8)
- 8000fe0: 46bd mov sp, r7
- 8000fe2: bd80 pop {r7, pc}
- 8000fe4: 40021000 .word 0x40021000
+ 800109e: 46c0 nop ; (mov r8, r8)
+ 80010a0: 46bd mov sp, r7
+ 80010a2: bd80 pop {r7, pc}
+ 80010a4: 40021000 .word 0x40021000
-08000fe8 <LL_RCC_HSE_IsReady>:
+080010a8 <LL_RCC_HSE_IsReady>:
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
- 8000fe8: b580 push {r7, lr}
- 8000fea: af00 add r7, sp, #0
+ 80010a8: b580 push {r7, lr}
+ 80010aa: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
- 8000fec: 4b06 ldr r3, [pc, #24] ; (8001008 <LL_RCC_HSE_IsReady+0x20>)
- 8000fee: 681a ldr r2, [r3, #0]
- 8000ff0: 2380 movs r3, #128 ; 0x80
- 8000ff2: 029b lsls r3, r3, #10
- 8000ff4: 4013 ands r3, r2
- 8000ff6: 4a05 ldr r2, [pc, #20] ; (800100c <LL_RCC_HSE_IsReady+0x24>)
- 8000ff8: 4694 mov ip, r2
- 8000ffa: 4463 add r3, ip
- 8000ffc: 425a negs r2, r3
- 8000ffe: 4153 adcs r3, r2
- 8001000: b2db uxtb r3, r3
+ 80010ac: 4b06 ldr r3, [pc, #24] ; (80010c8 <LL_RCC_HSE_IsReady+0x20>)
+ 80010ae: 681a ldr r2, [r3, #0]
+ 80010b0: 2380 movs r3, #128 ; 0x80
+ 80010b2: 029b lsls r3, r3, #10
+ 80010b4: 4013 ands r3, r2
+ 80010b6: 4a05 ldr r2, [pc, #20] ; (80010cc <LL_RCC_HSE_IsReady+0x24>)
+ 80010b8: 4694 mov ip, r2
+ 80010ba: 4463 add r3, ip
+ 80010bc: 425a negs r2, r3
+ 80010be: 4153 adcs r3, r2
+ 80010c0: b2db uxtb r3, r3
}
- 8001002: 0018 movs r0, r3
- 8001004: 46bd mov sp, r7
- 8001006: bd80 pop {r7, pc}
- 8001008: 40021000 .word 0x40021000
- 800100c: fffe0000 .word 0xfffe0000
+ 80010c2: 0018 movs r0, r3
+ 80010c4: 46bd mov sp, r7
+ 80010c6: bd80 pop {r7, pc}
+ 80010c8: 40021000 .word 0x40021000
+ 80010cc: fffe0000 .word 0xfffe0000
-08001010 <LL_RCC_HSI_Enable>:
+080010d0 <LL_RCC_HSI_Enable>:
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
- 8001010: b580 push {r7, lr}
- 8001012: af00 add r7, sp, #0
+ 80010d0: b580 push {r7, lr}
+ 80010d2: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_HSION);
- 8001014: 4b04 ldr r3, [pc, #16] ; (8001028 <LL_RCC_HSI_Enable+0x18>)
- 8001016: 681a ldr r2, [r3, #0]
- 8001018: 4b03 ldr r3, [pc, #12] ; (8001028 <LL_RCC_HSI_Enable+0x18>)
- 800101a: 2101 movs r1, #1
- 800101c: 430a orrs r2, r1
- 800101e: 601a str r2, [r3, #0]
+ 80010d4: 4b04 ldr r3, [pc, #16] ; (80010e8 <LL_RCC_HSI_Enable+0x18>)
+ 80010d6: 681a ldr r2, [r3, #0]
+ 80010d8: 4b03 ldr r3, [pc, #12] ; (80010e8 <LL_RCC_HSI_Enable+0x18>)
+ 80010da: 2101 movs r1, #1
+ 80010dc: 430a orrs r2, r1
+ 80010de: 601a str r2, [r3, #0]
}
- 8001020: 46c0 nop ; (mov r8, r8)
- 8001022: 46bd mov sp, r7
- 8001024: bd80 pop {r7, pc}
- 8001026: 46c0 nop ; (mov r8, r8)
- 8001028: 40021000 .word 0x40021000
+ 80010e0: 46c0 nop ; (mov r8, r8)
+ 80010e2: 46bd mov sp, r7
+ 80010e4: bd80 pop {r7, pc}
+ 80010e6: 46c0 nop ; (mov r8, r8)
+ 80010e8: 40021000 .word 0x40021000
-0800102c <LL_RCC_HSI_IsReady>:
+080010ec <LL_RCC_HSI_IsReady>:
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
- 800102c: b580 push {r7, lr}
- 800102e: af00 add r7, sp, #0
+ 80010ec: b580 push {r7, lr}
+ 80010ee: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
- 8001030: 4b05 ldr r3, [pc, #20] ; (8001048 <LL_RCC_HSI_IsReady+0x1c>)
- 8001032: 681b ldr r3, [r3, #0]
- 8001034: 2202 movs r2, #2
- 8001036: 4013 ands r3, r2
- 8001038: 3b02 subs r3, #2
- 800103a: 425a negs r2, r3
- 800103c: 4153 adcs r3, r2
- 800103e: b2db uxtb r3, r3
+ 80010f0: 4b05 ldr r3, [pc, #20] ; (8001108 <LL_RCC_HSI_IsReady+0x1c>)
+ 80010f2: 681b ldr r3, [r3, #0]
+ 80010f4: 2202 movs r2, #2
+ 80010f6: 4013 ands r3, r2
+ 80010f8: 3b02 subs r3, #2
+ 80010fa: 425a negs r2, r3
+ 80010fc: 4153 adcs r3, r2
+ 80010fe: b2db uxtb r3, r3
}
- 8001040: 0018 movs r0, r3
- 8001042: 46bd mov sp, r7
- 8001044: bd80 pop {r7, pc}
- 8001046: 46c0 nop ; (mov r8, r8)
- 8001048: 40021000 .word 0x40021000
+ 8001100: 0018 movs r0, r3
+ 8001102: 46bd mov sp, r7
+ 8001104: bd80 pop {r7, pc}
+ 8001106: 46c0 nop ; (mov r8, r8)
+ 8001108: 40021000 .word 0x40021000
-0800104c <LL_RCC_SetSysClkSource>:
+0800110c <LL_RCC_SetSysClkSource>:
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
- 800104c: b580 push {r7, lr}
- 800104e: b082 sub sp, #8
- 8001050: af00 add r7, sp, #0
- 8001052: 6078 str r0, [r7, #4]
+ 800110c: b580 push {r7, lr}
+ 800110e: b082 sub sp, #8
+ 8001110: af00 add r7, sp, #0
+ 8001112: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
- 8001054: 4b06 ldr r3, [pc, #24] ; (8001070 <LL_RCC_SetSysClkSource+0x24>)
- 8001056: 685b ldr r3, [r3, #4]
- 8001058: 2203 movs r2, #3
- 800105a: 4393 bics r3, r2
- 800105c: 0019 movs r1, r3
- 800105e: 4b04 ldr r3, [pc, #16] ; (8001070 <LL_RCC_SetSysClkSource+0x24>)
- 8001060: 687a ldr r2, [r7, #4]
- 8001062: 430a orrs r2, r1
- 8001064: 605a str r2, [r3, #4]
+ 8001114: 4b06 ldr r3, [pc, #24] ; (8001130 <LL_RCC_SetSysClkSource+0x24>)
+ 8001116: 685b ldr r3, [r3, #4]
+ 8001118: 2203 movs r2, #3
+ 800111a: 4393 bics r3, r2
+ 800111c: 0019 movs r1, r3
+ 800111e: 4b04 ldr r3, [pc, #16] ; (8001130 <LL_RCC_SetSysClkSource+0x24>)
+ 8001120: 687a ldr r2, [r7, #4]
+ 8001122: 430a orrs r2, r1
+ 8001124: 605a str r2, [r3, #4]
}
- 8001066: 46c0 nop ; (mov r8, r8)
- 8001068: 46bd mov sp, r7
- 800106a: b002 add sp, #8
- 800106c: bd80 pop {r7, pc}
- 800106e: 46c0 nop ; (mov r8, r8)
- 8001070: 40021000 .word 0x40021000
-
-08001074 <LL_RCC_GetSysClkSource>:
+ 8001126: 46c0 nop ; (mov r8, r8)
+ 8001128: 46bd mov sp, r7
+ 800112a: b002 add sp, #8
+ 800112c: bd80 pop {r7, pc}
+ 800112e: 46c0 nop ; (mov r8, r8)
+ 8001130: 40021000 .word 0x40021000
+
+08001134 <LL_RCC_GetSysClkSource>:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*)
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
- 8001074: b580 push {r7, lr}
- 8001076: af00 add r7, sp, #0
+ 8001134: b580 push {r7, lr}
+ 8001136: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
- 8001078: 4b03 ldr r3, [pc, #12] ; (8001088 <LL_RCC_GetSysClkSource+0x14>)
- 800107a: 685b ldr r3, [r3, #4]
- 800107c: 220c movs r2, #12
- 800107e: 4013 ands r3, r2
+ 8001138: 4b03 ldr r3, [pc, #12] ; (8001148 <LL_RCC_GetSysClkSource+0x14>)
+ 800113a: 685b ldr r3, [r3, #4]
+ 800113c: 220c movs r2, #12
+ 800113e: 4013 ands r3, r2
}
- 8001080: 0018 movs r0, r3
- 8001082: 46bd mov sp, r7
- 8001084: bd80 pop {r7, pc}
- 8001086: 46c0 nop ; (mov r8, r8)
- 8001088: 40021000 .word 0x40021000
+ 8001140: 0018 movs r0, r3
+ 8001142: 46bd mov sp, r7
+ 8001144: bd80 pop {r7, pc}
+ 8001146: 46c0 nop ; (mov r8, r8)
+ 8001148: 40021000 .word 0x40021000
-0800108c <LL_RCC_SetAHBPrescaler>:
+0800114c <LL_RCC_SetAHBPrescaler>:
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
- 800108c: b580 push {r7, lr}
- 800108e: b082 sub sp, #8
- 8001090: af00 add r7, sp, #0
- 8001092: 6078 str r0, [r7, #4]
+ 800114c: b580 push {r7, lr}
+ 800114e: b082 sub sp, #8
+ 8001150: af00 add r7, sp, #0
+ 8001152: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
- 8001094: 4b06 ldr r3, [pc, #24] ; (80010b0 <LL_RCC_SetAHBPrescaler+0x24>)
- 8001096: 685b ldr r3, [r3, #4]
- 8001098: 22f0 movs r2, #240 ; 0xf0
- 800109a: 4393 bics r3, r2
- 800109c: 0019 movs r1, r3
- 800109e: 4b04 ldr r3, [pc, #16] ; (80010b0 <LL_RCC_SetAHBPrescaler+0x24>)
- 80010a0: 687a ldr r2, [r7, #4]
- 80010a2: 430a orrs r2, r1
- 80010a4: 605a str r2, [r3, #4]
+ 8001154: 4b06 ldr r3, [pc, #24] ; (8001170 <LL_RCC_SetAHBPrescaler+0x24>)
+ 8001156: 685b ldr r3, [r3, #4]
+ 8001158: 22f0 movs r2, #240 ; 0xf0
+ 800115a: 4393 bics r3, r2
+ 800115c: 0019 movs r1, r3
+ 800115e: 4b04 ldr r3, [pc, #16] ; (8001170 <LL_RCC_SetAHBPrescaler+0x24>)
+ 8001160: 687a ldr r2, [r7, #4]
+ 8001162: 430a orrs r2, r1
+ 8001164: 605a str r2, [r3, #4]
}
- 80010a6: 46c0 nop ; (mov r8, r8)
- 80010a8: 46bd mov sp, r7
- 80010aa: b002 add sp, #8
- 80010ac: bd80 pop {r7, pc}
- 80010ae: 46c0 nop ; (mov r8, r8)
- 80010b0: 40021000 .word 0x40021000
-
-080010b4 <LL_RCC_SetAPB1Prescaler>:
+ 8001166: 46c0 nop ; (mov r8, r8)
+ 8001168: 46bd mov sp, r7
+ 800116a: b002 add sp, #8
+ 800116c: bd80 pop {r7, pc}
+ 800116e: 46c0 nop ; (mov r8, r8)
+ 8001170: 40021000 .word 0x40021000
+
+08001174 <LL_RCC_SetAPB1Prescaler>:
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
- 80010b4: b580 push {r7, lr}
- 80010b6: b082 sub sp, #8
- 80010b8: af00 add r7, sp, #0
- 80010ba: 6078 str r0, [r7, #4]
+ 8001174: b580 push {r7, lr}
+ 8001176: b082 sub sp, #8
+ 8001178: af00 add r7, sp, #0
+ 800117a: 6078 str r0, [r7, #4]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler);
- 80010bc: 4b06 ldr r3, [pc, #24] ; (80010d8 <LL_RCC_SetAPB1Prescaler+0x24>)
- 80010be: 685b ldr r3, [r3, #4]
- 80010c0: 4a06 ldr r2, [pc, #24] ; (80010dc <LL_RCC_SetAPB1Prescaler+0x28>)
- 80010c2: 4013 ands r3, r2
- 80010c4: 0019 movs r1, r3
- 80010c6: 4b04 ldr r3, [pc, #16] ; (80010d8 <LL_RCC_SetAPB1Prescaler+0x24>)
- 80010c8: 687a ldr r2, [r7, #4]
- 80010ca: 430a orrs r2, r1
- 80010cc: 605a str r2, [r3, #4]
+ 800117c: 4b06 ldr r3, [pc, #24] ; (8001198 <LL_RCC_SetAPB1Prescaler+0x24>)
+ 800117e: 685b ldr r3, [r3, #4]
+ 8001180: 4a06 ldr r2, [pc, #24] ; (800119c <LL_RCC_SetAPB1Prescaler+0x28>)
+ 8001182: 4013 ands r3, r2
+ 8001184: 0019 movs r1, r3
+ 8001186: 4b04 ldr r3, [pc, #16] ; (8001198 <LL_RCC_SetAPB1Prescaler+0x24>)
+ 8001188: 687a ldr r2, [r7, #4]
+ 800118a: 430a orrs r2, r1
+ 800118c: 605a str r2, [r3, #4]
}
- 80010ce: 46c0 nop ; (mov r8, r8)
- 80010d0: 46bd mov sp, r7
- 80010d2: b002 add sp, #8
- 80010d4: bd80 pop {r7, pc}
- 80010d6: 46c0 nop ; (mov r8, r8)
- 80010d8: 40021000 .word 0x40021000
- 80010dc: fffff8ff .word 0xfffff8ff
-
-080010e0 <LL_RCC_PLL_Enable>:
+ 800118e: 46c0 nop ; (mov r8, r8)
+ 8001190: 46bd mov sp, r7
+ 8001192: b002 add sp, #8
+ 8001194: bd80 pop {r7, pc}
+ 8001196: 46c0 nop ; (mov r8, r8)
+ 8001198: 40021000 .word 0x40021000
+ 800119c: fffff8ff .word 0xfffff8ff
+
+080011a0 <LL_RCC_PLL_Enable>:
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
- 80010e0: b580 push {r7, lr}
- 80010e2: af00 add r7, sp, #0
+ 80011a0: b580 push {r7, lr}
+ 80011a2: af00 add r7, sp, #0
SET_BIT(RCC->CR, RCC_CR_PLLON);
- 80010e4: 4b04 ldr r3, [pc, #16] ; (80010f8 <LL_RCC_PLL_Enable+0x18>)
- 80010e6: 681a ldr r2, [r3, #0]
- 80010e8: 4b03 ldr r3, [pc, #12] ; (80010f8 <LL_RCC_PLL_Enable+0x18>)
- 80010ea: 2180 movs r1, #128 ; 0x80
- 80010ec: 0449 lsls r1, r1, #17
- 80010ee: 430a orrs r2, r1
- 80010f0: 601a str r2, [r3, #0]
+ 80011a4: 4b04 ldr r3, [pc, #16] ; (80011b8 <LL_RCC_PLL_Enable+0x18>)
+ 80011a6: 681a ldr r2, [r3, #0]
+ 80011a8: 4b03 ldr r3, [pc, #12] ; (80011b8 <LL_RCC_PLL_Enable+0x18>)
+ 80011aa: 2180 movs r1, #128 ; 0x80
+ 80011ac: 0449 lsls r1, r1, #17
+ 80011ae: 430a orrs r2, r1
+ 80011b0: 601a str r2, [r3, #0]
}
- 80010f2: 46c0 nop ; (mov r8, r8)
- 80010f4: 46bd mov sp, r7
- 80010f6: bd80 pop {r7, pc}
- 80010f8: 40021000 .word 0x40021000
+ 80011b2: 46c0 nop ; (mov r8, r8)
+ 80011b4: 46bd mov sp, r7
+ 80011b6: bd80 pop {r7, pc}
+ 80011b8: 40021000 .word 0x40021000
-080010fc <LL_RCC_PLL_IsReady>:
+080011bc <LL_RCC_PLL_IsReady>:
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
- 80010fc: b580 push {r7, lr}
- 80010fe: af00 add r7, sp, #0
+ 80011bc: b580 push {r7, lr}
+ 80011be: af00 add r7, sp, #0
return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
- 8001100: 4b07 ldr r3, [pc, #28] ; (8001120 <LL_RCC_PLL_IsReady+0x24>)
- 8001102: 681a ldr r2, [r3, #0]
- 8001104: 2380 movs r3, #128 ; 0x80
- 8001106: 049b lsls r3, r3, #18
- 8001108: 4013 ands r3, r2
- 800110a: 22fe movs r2, #254 ; 0xfe
- 800110c: 0612 lsls r2, r2, #24
- 800110e: 4694 mov ip, r2
- 8001110: 4463 add r3, ip
- 8001112: 425a negs r2, r3
- 8001114: 4153 adcs r3, r2
- 8001116: b2db uxtb r3, r3
+ 80011c0: 4b07 ldr r3, [pc, #28] ; (80011e0 <LL_RCC_PLL_IsReady+0x24>)
+ 80011c2: 681a ldr r2, [r3, #0]
+ 80011c4: 2380 movs r3, #128 ; 0x80
+ 80011c6: 049b lsls r3, r3, #18
+ 80011c8: 4013 ands r3, r2
+ 80011ca: 22fe movs r2, #254 ; 0xfe
+ 80011cc: 0612 lsls r2, r2, #24
+ 80011ce: 4694 mov ip, r2
+ 80011d0: 4463 add r3, ip
+ 80011d2: 425a negs r2, r3
+ 80011d4: 4153 adcs r3, r2
+ 80011d6: b2db uxtb r3, r3
}
- 8001118: 0018 movs r0, r3
- 800111a: 46bd mov sp, r7
- 800111c: bd80 pop {r7, pc}
- 800111e: 46c0 nop ; (mov r8, r8)
- 8001120: 40021000 .word 0x40021000
+ 80011d8: 0018 movs r0, r3
+ 80011da: 46bd mov sp, r7
+ 80011dc: bd80 pop {r7, pc}
+ 80011de: 46c0 nop ; (mov r8, r8)
+ 80011e0: 40021000 .word 0x40021000
-08001124 <LL_RCC_PLL_ConfigDomain_SYS>:
+080011e4 <LL_RCC_PLL_ConfigDomain_SYS>:
* @arg @ref LL_RCC_PLL_MUL_15
* @arg @ref LL_RCC_PLL_MUL_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
{
- 8001124: b580 push {r7, lr}
- 8001126: b082 sub sp, #8
- 8001128: af00 add r7, sp, #0
- 800112a: 6078 str r0, [r7, #4]
- 800112c: 6039 str r1, [r7, #0]
+ 80011e4: b580 push {r7, lr}
+ 80011e6: b082 sub sp, #8
+ 80011e8: af00 add r7, sp, #0
+ 80011ea: 6078 str r0, [r7, #4]
+ 80011ec: 6039 str r1, [r7, #0]
MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
- 800112e: 4b0e ldr r3, [pc, #56] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 8001130: 685b ldr r3, [r3, #4]
- 8001132: 4a0e ldr r2, [pc, #56] ; (800116c <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
- 8001134: 4013 ands r3, r2
- 8001136: 0019 movs r1, r3
- 8001138: 687a ldr r2, [r7, #4]
- 800113a: 2380 movs r3, #128 ; 0x80
- 800113c: 025b lsls r3, r3, #9
- 800113e: 401a ands r2, r3
- 8001140: 683b ldr r3, [r7, #0]
- 8001142: 431a orrs r2, r3
- 8001144: 4b08 ldr r3, [pc, #32] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 8001146: 430a orrs r2, r1
- 8001148: 605a str r2, [r3, #4]
+ 80011ee: 4b0e ldr r3, [pc, #56] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 80011f0: 685b ldr r3, [r3, #4]
+ 80011f2: 4a0e ldr r2, [pc, #56] ; (800122c <LL_RCC_PLL_ConfigDomain_SYS+0x48>)
+ 80011f4: 4013 ands r3, r2
+ 80011f6: 0019 movs r1, r3
+ 80011f8: 687a ldr r2, [r7, #4]
+ 80011fa: 2380 movs r3, #128 ; 0x80
+ 80011fc: 025b lsls r3, r3, #9
+ 80011fe: 401a ands r2, r3
+ 8001200: 683b ldr r3, [r7, #0]
+ 8001202: 431a orrs r2, r3
+ 8001204: 4b08 ldr r3, [pc, #32] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 8001206: 430a orrs r2, r1
+ 8001208: 605a str r2, [r3, #4]
MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
- 800114a: 4b07 ldr r3, [pc, #28] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 800114c: 6adb ldr r3, [r3, #44] ; 0x2c
- 800114e: 220f movs r2, #15
- 8001150: 4393 bics r3, r2
- 8001152: 0019 movs r1, r3
- 8001154: 687b ldr r3, [r7, #4]
- 8001156: 220f movs r2, #15
- 8001158: 401a ands r2, r3
- 800115a: 4b03 ldr r3, [pc, #12] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
- 800115c: 430a orrs r2, r1
- 800115e: 62da str r2, [r3, #44] ; 0x2c
+ 800120a: 4b07 ldr r3, [pc, #28] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 800120c: 6adb ldr r3, [r3, #44] ; 0x2c
+ 800120e: 220f movs r2, #15
+ 8001210: 4393 bics r3, r2
+ 8001212: 0019 movs r1, r3
+ 8001214: 687b ldr r3, [r7, #4]
+ 8001216: 220f movs r2, #15
+ 8001218: 401a ands r2, r3
+ 800121a: 4b03 ldr r3, [pc, #12] ; (8001228 <LL_RCC_PLL_ConfigDomain_SYS+0x44>)
+ 800121c: 430a orrs r2, r1
+ 800121e: 62da str r2, [r3, #44] ; 0x2c
}
- 8001160: 46c0 nop ; (mov r8, r8)
- 8001162: 46bd mov sp, r7
- 8001164: b002 add sp, #8
- 8001166: bd80 pop {r7, pc}
- 8001168: 40021000 .word 0x40021000
- 800116c: ffc2ffff .word 0xffc2ffff
-
-08001170 <LL_InitTick>:
+ 8001220: 46c0 nop ; (mov r8, r8)
+ 8001222: 46bd mov sp, r7
+ 8001224: b002 add sp, #8
+ 8001226: bd80 pop {r7, pc}
+ 8001228: 40021000 .word 0x40021000
+ 800122c: ffc2ffff .word 0xffc2ffff
+
+08001230 <LL_InitTick>:
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
- 8001170: b580 push {r7, lr}
- 8001172: b082 sub sp, #8
- 8001174: af00 add r7, sp, #0
- 8001176: 6078 str r0, [r7, #4]
- 8001178: 6039 str r1, [r7, #0]
+ 8001230: b580 push {r7, lr}
+ 8001232: b082 sub sp, #8
+ 8001234: af00 add r7, sp, #0
+ 8001236: 6078 str r0, [r7, #4]
+ 8001238: 6039 str r1, [r7, #0]
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- 800117a: 6839 ldr r1, [r7, #0]
- 800117c: 6878 ldr r0, [r7, #4]
- 800117e: f000 fa13 bl 80015a8 <__udivsi3>
- 8001182: 0003 movs r3, r0
- 8001184: 001a movs r2, r3
- 8001186: 4b06 ldr r3, [pc, #24] ; (80011a0 <LL_InitTick+0x30>)
- 8001188: 3a01 subs r2, #1
- 800118a: 605a str r2, [r3, #4]
+ 800123a: 6839 ldr r1, [r7, #0]
+ 800123c: 6878 ldr r0, [r7, #4]
+ 800123e: f000 fa13 bl 8001668 <__udivsi3>
+ 8001242: 0003 movs r3, r0
+ 8001244: 001a movs r2, r3
+ 8001246: 4b06 ldr r3, [pc, #24] ; (8001260 <LL_InitTick+0x30>)
+ 8001248: 3a01 subs r2, #1
+ 800124a: 605a str r2, [r3, #4]
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 800118c: 4b04 ldr r3, [pc, #16] ; (80011a0 <LL_InitTick+0x30>)
- 800118e: 2200 movs r2, #0
- 8001190: 609a str r2, [r3, #8]
+ 800124c: 4b04 ldr r3, [pc, #16] ; (8001260 <LL_InitTick+0x30>)
+ 800124e: 2200 movs r2, #0
+ 8001250: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001192: 4b03 ldr r3, [pc, #12] ; (80011a0 <LL_InitTick+0x30>)
- 8001194: 2205 movs r2, #5
- 8001196: 601a str r2, [r3, #0]
+ 8001252: 4b03 ldr r3, [pc, #12] ; (8001260 <LL_InitTick+0x30>)
+ 8001254: 2205 movs r2, #5
+ 8001256: 601a str r2, [r3, #0]
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
- 8001198: 46c0 nop ; (mov r8, r8)
- 800119a: 46bd mov sp, r7
- 800119c: b002 add sp, #8
- 800119e: bd80 pop {r7, pc}
- 80011a0: e000e010 .word 0xe000e010
+ 8001258: 46c0 nop ; (mov r8, r8)
+ 800125a: 46bd mov sp, r7
+ 800125c: b002 add sp, #8
+ 800125e: bd80 pop {r7, pc}
+ 8001260: e000e010 .word 0xe000e010
-080011a4 <LL_FLASH_SetLatency>:
+08001264 <LL_FLASH_SetLatency>:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
- 80011a4: b580 push {r7, lr}
- 80011a6: b082 sub sp, #8
- 80011a8: af00 add r7, sp, #0
- 80011aa: 6078 str r0, [r7, #4]
+ 8001264: b580 push {r7, lr}
+ 8001266: b082 sub sp, #8
+ 8001268: af00 add r7, sp, #0
+ 800126a: 6078 str r0, [r7, #4]
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
- 80011ac: 4b06 ldr r3, [pc, #24] ; (80011c8 <LL_FLASH_SetLatency+0x24>)
- 80011ae: 681b ldr r3, [r3, #0]
- 80011b0: 2201 movs r2, #1
- 80011b2: 4393 bics r3, r2
- 80011b4: 0019 movs r1, r3
- 80011b6: 4b04 ldr r3, [pc, #16] ; (80011c8 <LL_FLASH_SetLatency+0x24>)
- 80011b8: 687a ldr r2, [r7, #4]
- 80011ba: 430a orrs r2, r1
- 80011bc: 601a str r2, [r3, #0]
+ 800126c: 4b06 ldr r3, [pc, #24] ; (8001288 <LL_FLASH_SetLatency+0x24>)
+ 800126e: 681b ldr r3, [r3, #0]
+ 8001270: 2201 movs r2, #1
+ 8001272: 4393 bics r3, r2
+ 8001274: 0019 movs r1, r3
+ 8001276: 4b04 ldr r3, [pc, #16] ; (8001288 <LL_FLASH_SetLatency+0x24>)
+ 8001278: 687a ldr r2, [r7, #4]
+ 800127a: 430a orrs r2, r1
+ 800127c: 601a str r2, [r3, #0]
}
- 80011be: 46c0 nop ; (mov r8, r8)
- 80011c0: 46bd mov sp, r7
- 80011c2: b002 add sp, #8
- 80011c4: bd80 pop {r7, pc}
- 80011c6: 46c0 nop ; (mov r8, r8)
- 80011c8: 40022000 .word 0x40022000
-
-080011cc <LL_FLASH_GetLatency>:
+ 800127e: 46c0 nop ; (mov r8, r8)
+ 8001280: 46bd mov sp, r7
+ 8001282: b002 add sp, #8
+ 8001284: bd80 pop {r7, pc}
+ 8001286: 46c0 nop ; (mov r8, r8)
+ 8001288: 40022000 .word 0x40022000
+
+0800128c <LL_FLASH_GetLatency>:
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
- 80011cc: b580 push {r7, lr}
- 80011ce: af00 add r7, sp, #0
+ 800128c: b580 push {r7, lr}
+ 800128e: af00 add r7, sp, #0
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
- 80011d0: 4b03 ldr r3, [pc, #12] ; (80011e0 <LL_FLASH_GetLatency+0x14>)
- 80011d2: 681b ldr r3, [r3, #0]
- 80011d4: 2201 movs r2, #1
- 80011d6: 4013 ands r3, r2
+ 8001290: 4b03 ldr r3, [pc, #12] ; (80012a0 <LL_FLASH_GetLatency+0x14>)
+ 8001292: 681b ldr r3, [r3, #0]
+ 8001294: 2201 movs r2, #1
+ 8001296: 4013 ands r3, r2
}
- 80011d8: 0018 movs r0, r3
- 80011da: 46bd mov sp, r7
- 80011dc: bd80 pop {r7, pc}
- 80011de: 46c0 nop ; (mov r8, r8)
- 80011e0: 40022000 .word 0x40022000
+ 8001298: 0018 movs r0, r3
+ 800129a: 46bd mov sp, r7
+ 800129c: bd80 pop {r7, pc}
+ 800129e: 46c0 nop ; (mov r8, r8)
+ 80012a0: 40022000 .word 0x40022000
-080011e4 <LL_Init1msTick>:
+080012a4 <LL_Init1msTick>:
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
- 80011e4: b580 push {r7, lr}
- 80011e6: b082 sub sp, #8
- 80011e8: af00 add r7, sp, #0
- 80011ea: 6078 str r0, [r7, #4]
+ 80012a4: b580 push {r7, lr}
+ 80012a6: b082 sub sp, #8
+ 80012a8: af00 add r7, sp, #0
+ 80012aa: 6078 str r0, [r7, #4]
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
- 80011ec: 23fa movs r3, #250 ; 0xfa
- 80011ee: 009a lsls r2, r3, #2
- 80011f0: 687b ldr r3, [r7, #4]
- 80011f2: 0011 movs r1, r2
- 80011f4: 0018 movs r0, r3
- 80011f6: f7ff ffbb bl 8001170 <LL_InitTick>
+ 80012ac: 23fa movs r3, #250 ; 0xfa
+ 80012ae: 009a lsls r2, r3, #2
+ 80012b0: 687b ldr r3, [r7, #4]
+ 80012b2: 0011 movs r1, r2
+ 80012b4: 0018 movs r0, r3
+ 80012b6: f7ff ffbb bl 8001230 <LL_InitTick>
}
- 80011fa: 46c0 nop ; (mov r8, r8)
- 80011fc: 46bd mov sp, r7
- 80011fe: b002 add sp, #8
- 8001200: bd80 pop {r7, pc}
+ 80012ba: 46c0 nop ; (mov r8, r8)
+ 80012bc: 46bd mov sp, r7
+ 80012be: b002 add sp, #8
+ 80012c0: bd80 pop {r7, pc}
-08001202 <LL_mDelay>:
+080012c2 <LL_mDelay>:
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
- 8001202: b580 push {r7, lr}
- 8001204: b084 sub sp, #16
- 8001206: af00 add r7, sp, #0
- 8001208: 6078 str r0, [r7, #4]
+ 80012c2: b580 push {r7, lr}
+ 80012c4: b084 sub sp, #16
+ 80012c6: af00 add r7, sp, #0
+ 80012c8: 6078 str r0, [r7, #4]
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- 800120a: 4b0e ldr r3, [pc, #56] ; (8001244 <LL_mDelay+0x42>)
- 800120c: 681b ldr r3, [r3, #0]
- 800120e: 60fb str r3, [r7, #12]
+ 80012ca: 4b0e ldr r3, [pc, #56] ; (8001304 <LL_mDelay+0x42>)
+ 80012cc: 681b ldr r3, [r3, #0]
+ 80012ce: 60fb str r3, [r7, #12]
/* Add this code to indicate that local variable is not used */
((void)tmp);
- 8001210: 68fb ldr r3, [r7, #12]
+ 80012d0: 68fb ldr r3, [r7, #12]
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
- 8001212: 687b ldr r3, [r7, #4]
- 8001214: 3301 adds r3, #1
- 8001216: d00c beq.n 8001232 <LL_mDelay+0x30>
+ 80012d2: 687b ldr r3, [r7, #4]
+ 80012d4: 3301 adds r3, #1
+ 80012d6: d00c beq.n 80012f2 <LL_mDelay+0x30>
{
Delay++;
- 8001218: 687b ldr r3, [r7, #4]
- 800121a: 3301 adds r3, #1
- 800121c: 607b str r3, [r7, #4]
+ 80012d8: 687b ldr r3, [r7, #4]
+ 80012da: 3301 adds r3, #1
+ 80012dc: 607b str r3, [r7, #4]
}
while (Delay)
- 800121e: e008 b.n 8001232 <LL_mDelay+0x30>
+ 80012de: e008 b.n 80012f2 <LL_mDelay+0x30>
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- 8001220: 4b08 ldr r3, [pc, #32] ; (8001244 <LL_mDelay+0x42>)
- 8001222: 681a ldr r2, [r3, #0]
- 8001224: 2380 movs r3, #128 ; 0x80
- 8001226: 025b lsls r3, r3, #9
- 8001228: 4013 ands r3, r2
- 800122a: d002 beq.n 8001232 <LL_mDelay+0x30>
+ 80012e0: 4b08 ldr r3, [pc, #32] ; (8001304 <LL_mDelay+0x42>)
+ 80012e2: 681a ldr r2, [r3, #0]
+ 80012e4: 2380 movs r3, #128 ; 0x80
+ 80012e6: 025b lsls r3, r3, #9
+ 80012e8: 4013 ands r3, r2
+ 80012ea: d002 beq.n 80012f2 <LL_mDelay+0x30>
{
Delay--;
- 800122c: 687b ldr r3, [r7, #4]
- 800122e: 3b01 subs r3, #1
- 8001230: 607b str r3, [r7, #4]
+ 80012ec: 687b ldr r3, [r7, #4]
+ 80012ee: 3b01 subs r3, #1
+ 80012f0: 607b str r3, [r7, #4]
while (Delay)
- 8001232: 687b ldr r3, [r7, #4]
- 8001234: 2b00 cmp r3, #0
- 8001236: d1f3 bne.n 8001220 <LL_mDelay+0x1e>
+ 80012f2: 687b ldr r3, [r7, #4]
+ 80012f4: 2b00 cmp r3, #0
+ 80012f6: d1f3 bne.n 80012e0 <LL_mDelay+0x1e>
}
}
}
- 8001238: 46c0 nop ; (mov r8, r8)
- 800123a: 46c0 nop ; (mov r8, r8)
- 800123c: 46bd mov sp, r7
- 800123e: b004 add sp, #16
- 8001240: bd80 pop {r7, pc}
- 8001242: 46c0 nop ; (mov r8, r8)
- 8001244: e000e010 .word 0xe000e010
-
-08001248 <LL_SetSystemCoreClock>:
+ 80012f8: 46c0 nop ; (mov r8, r8)
+ 80012fa: 46c0 nop ; (mov r8, r8)
+ 80012fc: 46bd mov sp, r7
+ 80012fe: b004 add sp, #16
+ 8001300: bd80 pop {r7, pc}
+ 8001302: 46c0 nop ; (mov r8, r8)
+ 8001304: e000e010 .word 0xe000e010
+
+08001308 <LL_SetSystemCoreClock>:
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
- 8001248: b580 push {r7, lr}
- 800124a: b082 sub sp, #8
- 800124c: af00 add r7, sp, #0
- 800124e: 6078 str r0, [r7, #4]
+ 8001308: b580 push {r7, lr}
+ 800130a: b082 sub sp, #8
+ 800130c: af00 add r7, sp, #0
+ 800130e: 6078 str r0, [r7, #4]
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
- 8001250: 4b03 ldr r3, [pc, #12] ; (8001260 <LL_SetSystemCoreClock+0x18>)
- 8001252: 687a ldr r2, [r7, #4]
- 8001254: 601a str r2, [r3, #0]
+ 8001310: 4b03 ldr r3, [pc, #12] ; (8001320 <LL_SetSystemCoreClock+0x18>)
+ 8001312: 687a ldr r2, [r7, #4]
+ 8001314: 601a str r2, [r3, #0]
}
- 8001256: 46c0 nop ; (mov r8, r8)
- 8001258: 46bd mov sp, r7
- 800125a: b002 add sp, #8
- 800125c: bd80 pop {r7, pc}
- 800125e: 46c0 nop ; (mov r8, r8)
- 8001260: 20000000 .word 0x20000000
-
-08001264 <LL_PLL_ConfigSystemClock_HSI>:
+ 8001316: 46c0 nop ; (mov r8, r8)
+ 8001318: 46bd mov sp, r7
+ 800131a: b002 add sp, #8
+ 800131c: bd80 pop {r7, pc}
+ 800131e: 46c0 nop ; (mov r8, r8)
+ 8001320: 20000000 .word 0x20000000
+
+08001324 <LL_PLL_ConfigSystemClock_HSI>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 8001264: b590 push {r4, r7, lr}
- 8001266: b085 sub sp, #20
- 8001268: af00 add r7, sp, #0
- 800126a: 6078 str r0, [r7, #4]
- 800126c: 6039 str r1, [r7, #0]
+ 8001324: b590 push {r4, r7, lr}
+ 8001326: b085 sub sp, #20
+ 8001328: af00 add r7, sp, #0
+ 800132a: 6078 str r0, [r7, #4]
+ 800132c: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 800126e: 230f movs r3, #15
- 8001270: 18fb adds r3, r7, r3
- 8001272: 2201 movs r2, #1
- 8001274: 701a strb r2, [r3, #0]
+ 800132e: 230f movs r3, #15
+ 8001330: 18fb adds r3, r7, r3
+ 8001332: 2201 movs r2, #1
+ 8001334: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 8001276: 2300 movs r3, #0
- 8001278: 60bb str r3, [r7, #8]
+ 8001336: 2300 movs r3, #0
+ 8001338: 60bb str r3, [r7, #8]
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 800127a: f000 f8d4 bl 8001426 <UTILS_PLL_IsBusy>
- 800127e: 0003 movs r3, r0
- 8001280: 2b01 cmp r3, #1
- 8001282: d128 bne.n 80012d6 <LL_PLL_ConfigSystemClock_HSI+0x72>
+ 800133a: f000 f8d4 bl 80014e6 <UTILS_PLL_IsBusy>
+ 800133e: 0003 movs r3, r0
+ 8001340: 2b01 cmp r3, #1
+ 8001342: d128 bne.n 8001396 <LL_PLL_ConfigSystemClock_HSI+0x72>
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
- 8001284: 687b ldr r3, [r7, #4]
- 8001286: 2201 movs r2, #1
- 8001288: 605a str r2, [r3, #4]
+ 8001344: 687b ldr r3, [r7, #4]
+ 8001346: 2201 movs r2, #1
+ 8001348: 605a str r2, [r3, #4]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
- 800128a: 687b ldr r3, [r7, #4]
- 800128c: 4a17 ldr r2, [pc, #92] ; (80012ec <LL_PLL_ConfigSystemClock_HSI+0x88>)
- 800128e: 0019 movs r1, r3
- 8001290: 0010 movs r0, r2
- 8001292: f000 f8ab bl 80013ec <UTILS_GetPLLOutputFrequency>
- 8001296: 0003 movs r3, r0
- 8001298: 60bb str r3, [r7, #8]
+ 800134a: 687b ldr r3, [r7, #4]
+ 800134c: 4a17 ldr r2, [pc, #92] ; (80013ac <LL_PLL_ConfigSystemClock_HSI+0x88>)
+ 800134e: 0019 movs r1, r3
+ 8001350: 0010 movs r0, r2
+ 8001352: f000 f8ab bl 80014ac <UTILS_GetPLLOutputFrequency>
+ 8001356: 0003 movs r3, r0
+ 8001358: 60bb str r3, [r7, #8]
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
- 800129a: f7ff fec7 bl 800102c <LL_RCC_HSI_IsReady>
- 800129e: 0003 movs r3, r0
- 80012a0: 2b01 cmp r3, #1
- 80012a2: d007 beq.n 80012b4 <LL_PLL_ConfigSystemClock_HSI+0x50>
+ 800135a: f7ff fec7 bl 80010ec <LL_RCC_HSI_IsReady>
+ 800135e: 0003 movs r3, r0
+ 8001360: 2b01 cmp r3, #1
+ 8001362: d007 beq.n 8001374 <LL_PLL_ConfigSystemClock_HSI+0x50>
{
LL_RCC_HSI_Enable();
- 80012a4: f7ff feb4 bl 8001010 <LL_RCC_HSI_Enable>
+ 8001364: f7ff feb4 bl 80010d0 <LL_RCC_HSI_Enable>
while (LL_RCC_HSI_IsReady() != 1U)
- 80012a8: 46c0 nop ; (mov r8, r8)
- 80012aa: f7ff febf bl 800102c <LL_RCC_HSI_IsReady>
- 80012ae: 0003 movs r3, r0
- 80012b0: 2b01 cmp r3, #1
- 80012b2: d1fa bne.n 80012aa <LL_PLL_ConfigSystemClock_HSI+0x46>
+ 8001368: 46c0 nop ; (mov r8, r8)
+ 800136a: f7ff febf bl 80010ec <LL_RCC_HSI_IsReady>
+ 800136e: 0003 movs r3, r0
+ 8001370: 2b01 cmp r3, #1
+ 8001372: d1fa bne.n 800136a <LL_PLL_ConfigSystemClock_HSI+0x46>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
- 80012b4: 687b ldr r3, [r7, #4]
- 80012b6: 681b ldr r3, [r3, #0]
- 80012b8: 0019 movs r1, r3
- 80012ba: 2000 movs r0, #0
- 80012bc: f7ff ff32 bl 8001124 <LL_RCC_PLL_ConfigDomain_SYS>
+ 8001374: 687b ldr r3, [r7, #4]
+ 8001376: 681b ldr r3, [r3, #0]
+ 8001378: 0019 movs r1, r3
+ 800137a: 2000 movs r0, #0
+ 800137c: f7ff ff32 bl 80011e4 <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 80012c0: 230f movs r3, #15
- 80012c2: 18fc adds r4, r7, r3
- 80012c4: 683a ldr r2, [r7, #0]
- 80012c6: 68bb ldr r3, [r7, #8]
- 80012c8: 0011 movs r1, r2
- 80012ca: 0018 movs r0, r3
- 80012cc: f000 f8be bl 800144c <UTILS_EnablePLLAndSwitchSystem>
- 80012d0: 0003 movs r3, r0
- 80012d2: 7023 strb r3, [r4, #0]
- 80012d4: e003 b.n 80012de <LL_PLL_ConfigSystemClock_HSI+0x7a>
+ 8001380: 230f movs r3, #15
+ 8001382: 18fc adds r4, r7, r3
+ 8001384: 683a ldr r2, [r7, #0]
+ 8001386: 68bb ldr r3, [r7, #8]
+ 8001388: 0011 movs r1, r2
+ 800138a: 0018 movs r0, r3
+ 800138c: f000 f8be bl 800150c <UTILS_EnablePLLAndSwitchSystem>
+ 8001390: 0003 movs r3, r0
+ 8001392: 7023 strb r3, [r4, #0]
+ 8001394: e003 b.n 800139e <LL_PLL_ConfigSystemClock_HSI+0x7a>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 80012d6: 230f movs r3, #15
- 80012d8: 18fb adds r3, r7, r3
- 80012da: 2200 movs r2, #0
- 80012dc: 701a strb r2, [r3, #0]
+ 8001396: 230f movs r3, #15
+ 8001398: 18fb adds r3, r7, r3
+ 800139a: 2200 movs r2, #0
+ 800139c: 701a strb r2, [r3, #0]
}
return status;
- 80012de: 230f movs r3, #15
- 80012e0: 18fb adds r3, r7, r3
- 80012e2: 781b ldrb r3, [r3, #0]
+ 800139e: 230f movs r3, #15
+ 80013a0: 18fb adds r3, r7, r3
+ 80013a2: 781b ldrb r3, [r3, #0]
}
- 80012e4: 0018 movs r0, r3
- 80012e6: 46bd mov sp, r7
- 80012e8: b005 add sp, #20
- 80012ea: bd90 pop {r4, r7, pc}
- 80012ec: 007a1200 .word 0x007a1200
+ 80013a4: 0018 movs r0, r3
+ 80013a6: 46bd mov sp, r7
+ 80013a8: b005 add sp, #20
+ 80013aa: bd90 pop {r4, r7, pc}
+ 80013ac: 007a1200 .word 0x007a1200
-080012f0 <LL_PLL_ConfigSystemClock_HSE>:
+080013b0 <LL_PLL_ConfigSystemClock_HSE>:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 80012f0: b590 push {r4, r7, lr}
- 80012f2: b087 sub sp, #28
- 80012f4: af00 add r7, sp, #0
- 80012f6: 60f8 str r0, [r7, #12]
- 80012f8: 60b9 str r1, [r7, #8]
- 80012fa: 607a str r2, [r7, #4]
- 80012fc: 603b str r3, [r7, #0]
+ 80013b0: b590 push {r4, r7, lr}
+ 80013b2: b087 sub sp, #28
+ 80013b4: af00 add r7, sp, #0
+ 80013b6: 60f8 str r0, [r7, #12]
+ 80013b8: 60b9 str r1, [r7, #8]
+ 80013ba: 607a str r2, [r7, #4]
+ 80013bc: 603b str r3, [r7, #0]
ErrorStatus status = SUCCESS;
- 80012fe: 2317 movs r3, #23
- 8001300: 18fb adds r3, r7, r3
- 8001302: 2201 movs r2, #1
- 8001304: 701a strb r2, [r3, #0]
+ 80013be: 2317 movs r3, #23
+ 80013c0: 18fb adds r3, r7, r3
+ 80013c2: 2201 movs r2, #1
+ 80013c4: 701a strb r2, [r3, #0]
uint32_t pllfreq = 0U;
- 8001306: 2300 movs r3, #0
- 8001308: 613b str r3, [r7, #16]
+ 80013c6: 2300 movs r3, #0
+ 80013c8: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
- 800130a: f000 f88c bl 8001426 <UTILS_PLL_IsBusy>
- 800130e: 0003 movs r3, r0
- 8001310: 2b01 cmp r3, #1
- 8001312: d132 bne.n 800137a <LL_PLL_ConfigSystemClock_HSE+0x8a>
+ 80013ca: f000 f88c bl 80014e6 <UTILS_PLL_IsBusy>
+ 80013ce: 0003 movs r3, r0
+ 80013d0: 2b01 cmp r3, #1
+ 80013d2: d132 bne.n 800143a <LL_PLL_ConfigSystemClock_HSE+0x8a>
#else
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
- 8001314: 687a ldr r2, [r7, #4]
- 8001316: 68fb ldr r3, [r7, #12]
- 8001318: 0011 movs r1, r2
- 800131a: 0018 movs r0, r3
- 800131c: f000 f866 bl 80013ec <UTILS_GetPLLOutputFrequency>
- 8001320: 0003 movs r3, r0
- 8001322: 613b str r3, [r7, #16]
+ 80013d4: 687a ldr r2, [r7, #4]
+ 80013d6: 68fb ldr r3, [r7, #12]
+ 80013d8: 0011 movs r1, r2
+ 80013da: 0018 movs r0, r3
+ 80013dc: f000 f866 bl 80014ac <UTILS_GetPLLOutputFrequency>
+ 80013e0: 0003 movs r3, r0
+ 80013e2: 613b str r3, [r7, #16]
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
- 8001324: f7ff fe60 bl 8000fe8 <LL_RCC_HSE_IsReady>
- 8001328: 0003 movs r3, r0
- 800132a: 2b01 cmp r3, #1
- 800132c: d00f beq.n 800134e <LL_PLL_ConfigSystemClock_HSE+0x5e>
+ 80013e4: f7ff fe60 bl 80010a8 <LL_RCC_HSE_IsReady>
+ 80013e8: 0003 movs r3, r0
+ 80013ea: 2b01 cmp r3, #1
+ 80013ec: d00f beq.n 800140e <LL_PLL_ConfigSystemClock_HSE+0x5e>
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- 800132e: 68bb ldr r3, [r7, #8]
- 8001330: 2b01 cmp r3, #1
- 8001332: d102 bne.n 800133a <LL_PLL_ConfigSystemClock_HSE+0x4a>
+ 80013ee: 68bb ldr r3, [r7, #8]
+ 80013f0: 2b01 cmp r3, #1
+ 80013f2: d102 bne.n 80013fa <LL_PLL_ConfigSystemClock_HSE+0x4a>
{
LL_RCC_HSE_EnableBypass();
- 8001334: f7ff fe2c bl 8000f90 <LL_RCC_HSE_EnableBypass>
- 8001338: e001 b.n 800133e <LL_PLL_ConfigSystemClock_HSE+0x4e>
+ 80013f4: f7ff fe2c bl 8001050 <LL_RCC_HSE_EnableBypass>
+ 80013f8: e001 b.n 80013fe <LL_PLL_ConfigSystemClock_HSE+0x4e>
}
else
{
LL_RCC_HSE_DisableBypass();
- 800133a: f7ff fe37 bl 8000fac <LL_RCC_HSE_DisableBypass>
+ 80013fa: f7ff fe37 bl 800106c <LL_RCC_HSE_DisableBypass>
}
/* Enable HSE */
LL_RCC_HSE_Enable();
- 800133e: f7ff fe45 bl 8000fcc <LL_RCC_HSE_Enable>
+ 80013fe: f7ff fe45 bl 800108c <LL_RCC_HSE_Enable>
while (LL_RCC_HSE_IsReady() != 1U)
- 8001342: 46c0 nop ; (mov r8, r8)
- 8001344: f7ff fe50 bl 8000fe8 <LL_RCC_HSE_IsReady>
- 8001348: 0003 movs r3, r0
- 800134a: 2b01 cmp r3, #1
- 800134c: d1fa bne.n 8001344 <LL_PLL_ConfigSystemClock_HSE+0x54>
+ 8001402: 46c0 nop ; (mov r8, r8)
+ 8001404: f7ff fe50 bl 80010a8 <LL_RCC_HSE_IsReady>
+ 8001408: 0003 movs r3, r0
+ 800140a: 2b01 cmp r3, #1
+ 800140c: d1fa bne.n 8001404 <LL_PLL_ConfigSystemClock_HSE+0x54>
/* Configure PLL */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
- 800134e: 687b ldr r3, [r7, #4]
- 8001350: 685b ldr r3, [r3, #4]
- 8001352: 2280 movs r2, #128 ; 0x80
- 8001354: 0252 lsls r2, r2, #9
- 8001356: 431a orrs r2, r3
- 8001358: 687b ldr r3, [r7, #4]
- 800135a: 681b ldr r3, [r3, #0]
- 800135c: 0019 movs r1, r3
- 800135e: 0010 movs r0, r2
- 8001360: f7ff fee0 bl 8001124 <LL_RCC_PLL_ConfigDomain_SYS>
+ 800140e: 687b ldr r3, [r7, #4]
+ 8001410: 685b ldr r3, [r3, #4]
+ 8001412: 2280 movs r2, #128 ; 0x80
+ 8001414: 0252 lsls r2, r2, #9
+ 8001416: 431a orrs r2, r3
+ 8001418: 687b ldr r3, [r7, #4]
+ 800141a: 681b ldr r3, [r3, #0]
+ 800141c: 0019 movs r1, r3
+ 800141e: 0010 movs r0, r2
+ 8001420: f7ff fee0 bl 80011e4 <LL_RCC_PLL_ConfigDomain_SYS>
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- 8001364: 2317 movs r3, #23
- 8001366: 18fc adds r4, r7, r3
- 8001368: 683a ldr r2, [r7, #0]
- 800136a: 693b ldr r3, [r7, #16]
- 800136c: 0011 movs r1, r2
- 800136e: 0018 movs r0, r3
- 8001370: f000 f86c bl 800144c <UTILS_EnablePLLAndSwitchSystem>
- 8001374: 0003 movs r3, r0
- 8001376: 7023 strb r3, [r4, #0]
- 8001378: e003 b.n 8001382 <LL_PLL_ConfigSystemClock_HSE+0x92>
+ 8001424: 2317 movs r3, #23
+ 8001426: 18fc adds r4, r7, r3
+ 8001428: 683a ldr r2, [r7, #0]
+ 800142a: 693b ldr r3, [r7, #16]
+ 800142c: 0011 movs r1, r2
+ 800142e: 0018 movs r0, r3
+ 8001430: f000 f86c bl 800150c <UTILS_EnablePLLAndSwitchSystem>
+ 8001434: 0003 movs r3, r0
+ 8001436: 7023 strb r3, [r4, #0]
+ 8001438: e003 b.n 8001442 <LL_PLL_ConfigSystemClock_HSE+0x92>
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
- 800137a: 2317 movs r3, #23
- 800137c: 18fb adds r3, r7, r3
- 800137e: 2200 movs r2, #0
- 8001380: 701a strb r2, [r3, #0]
+ 800143a: 2317 movs r3, #23
+ 800143c: 18fb adds r3, r7, r3
+ 800143e: 2200 movs r2, #0
+ 8001440: 701a strb r2, [r3, #0]
}
return status;
- 8001382: 2317 movs r3, #23
- 8001384: 18fb adds r3, r7, r3
- 8001386: 781b ldrb r3, [r3, #0]
+ 8001442: 2317 movs r3, #23
+ 8001444: 18fb adds r3, r7, r3
+ 8001446: 781b ldrb r3, [r3, #0]
}
- 8001388: 0018 movs r0, r3
- 800138a: 46bd mov sp, r7
- 800138c: b007 add sp, #28
- 800138e: bd90 pop {r4, r7, pc}
+ 8001448: 0018 movs r0, r3
+ 800144a: 46bd mov sp, r7
+ 800144c: b007 add sp, #28
+ 800144e: bd90 pop {r4, r7, pc}
-08001390 <UTILS_SetFlashLatency>:
+08001450 <UTILS_SetFlashLatency>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
- 8001390: b580 push {r7, lr}
- 8001392: b084 sub sp, #16
- 8001394: af00 add r7, sp, #0
- 8001396: 6078 str r0, [r7, #4]
+ 8001450: b580 push {r7, lr}
+ 8001452: b084 sub sp, #16
+ 8001454: af00 add r7, sp, #0
+ 8001456: 6078 str r0, [r7, #4]
ErrorStatus status = SUCCESS;
- 8001398: 210f movs r1, #15
- 800139a: 187b adds r3, r7, r1
- 800139c: 2201 movs r2, #1
- 800139e: 701a strb r2, [r3, #0]
+ 8001458: 210f movs r1, #15
+ 800145a: 187b adds r3, r7, r1
+ 800145c: 2201 movs r2, #1
+ 800145e: 701a strb r2, [r3, #0]
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
- 80013a0: 2300 movs r3, #0
- 80013a2: 60bb str r3, [r7, #8]
+ 8001460: 2300 movs r3, #0
+ 8001462: 60bb str r3, [r7, #8]
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
- 80013a4: 687b ldr r3, [r7, #4]
- 80013a6: 2b00 cmp r3, #0
- 80013a8: d103 bne.n 80013b2 <UTILS_SetFlashLatency+0x22>
+ 8001464: 687b ldr r3, [r7, #4]
+ 8001466: 2b00 cmp r3, #0
+ 8001468: d103 bne.n 8001472 <UTILS_SetFlashLatency+0x22>
{
status = ERROR;
- 80013aa: 187b adds r3, r7, r1
- 80013ac: 2200 movs r2, #0
- 80013ae: 701a strb r2, [r3, #0]
- 80013b0: e013 b.n 80013da <UTILS_SetFlashLatency+0x4a>
+ 800146a: 187b adds r3, r7, r1
+ 800146c: 2200 movs r2, #0
+ 800146e: 701a strb r2, [r3, #0]
+ 8001470: e013 b.n 800149a <UTILS_SetFlashLatency+0x4a>
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
- 80013b2: 687b ldr r3, [r7, #4]
- 80013b4: 4a0c ldr r2, [pc, #48] ; (80013e8 <UTILS_SetFlashLatency+0x58>)
- 80013b6: 4293 cmp r3, r2
- 80013b8: d901 bls.n 80013be <UTILS_SetFlashLatency+0x2e>
+ 8001472: 687b ldr r3, [r7, #4]
+ 8001474: 4a0c ldr r2, [pc, #48] ; (80014a8 <UTILS_SetFlashLatency+0x58>)
+ 8001476: 4293 cmp r3, r2
+ 8001478: d901 bls.n 800147e <UTILS_SetFlashLatency+0x2e>
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
- 80013ba: 2301 movs r3, #1
- 80013bc: 60bb str r3, [r7, #8]
+ 800147a: 2301 movs r3, #1
+ 800147c: 60bb str r3, [r7, #8]
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
LL_FLASH_SetLatency(latency);
- 80013be: 68bb ldr r3, [r7, #8]
- 80013c0: 0018 movs r0, r3
- 80013c2: f7ff feef bl 80011a4 <LL_FLASH_SetLatency>
+ 800147e: 68bb ldr r3, [r7, #8]
+ 8001480: 0018 movs r0, r3
+ 8001482: f7ff feef bl 8001264 <LL_FLASH_SetLatency>
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
- 80013c6: f7ff ff01 bl 80011cc <LL_FLASH_GetLatency>
- 80013ca: 0002 movs r2, r0
- 80013cc: 68bb ldr r3, [r7, #8]
- 80013ce: 4293 cmp r3, r2
- 80013d0: d003 beq.n 80013da <UTILS_SetFlashLatency+0x4a>
+ 8001486: f7ff ff01 bl 800128c <LL_FLASH_GetLatency>
+ 800148a: 0002 movs r2, r0
+ 800148c: 68bb ldr r3, [r7, #8]
+ 800148e: 4293 cmp r3, r2
+ 8001490: d003 beq.n 800149a <UTILS_SetFlashLatency+0x4a>
{
status = ERROR;
- 80013d2: 230f movs r3, #15
- 80013d4: 18fb adds r3, r7, r3
- 80013d6: 2200 movs r2, #0
- 80013d8: 701a strb r2, [r3, #0]
+ 8001492: 230f movs r3, #15
+ 8001494: 18fb adds r3, r7, r3
+ 8001496: 2200 movs r2, #0
+ 8001498: 701a strb r2, [r3, #0]
}
}
return status;
- 80013da: 230f movs r3, #15
- 80013dc: 18fb adds r3, r7, r3
- 80013de: 781b ldrb r3, [r3, #0]
+ 800149a: 230f movs r3, #15
+ 800149c: 18fb adds r3, r7, r3
+ 800149e: 781b ldrb r3, [r3, #0]
}
- 80013e0: 0018 movs r0, r3
- 80013e2: 46bd mov sp, r7
- 80013e4: b004 add sp, #16
- 80013e6: bd80 pop {r7, pc}
- 80013e8: 016e3600 .word 0x016e3600
+ 80014a0: 0018 movs r0, r3
+ 80014a2: 46bd mov sp, r7
+ 80014a4: b004 add sp, #16
+ 80014a6: bd80 pop {r7, pc}
+ 80014a8: 016e3600 .word 0x016e3600
-080013ec <UTILS_GetPLLOutputFrequency>:
+080014ac <UTILS_GetPLLOutputFrequency>:
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
- 80013ec: b580 push {r7, lr}
- 80013ee: b084 sub sp, #16
- 80013f0: af00 add r7, sp, #0
- 80013f2: 6078 str r0, [r7, #4]
- 80013f4: 6039 str r1, [r7, #0]
+ 80014ac: b580 push {r7, lr}
+ 80014ae: b084 sub sp, #16
+ 80014b0: af00 add r7, sp, #0
+ 80014b2: 6078 str r0, [r7, #4]
+ 80014b4: 6039 str r1, [r7, #0]
uint32_t pllfreq = 0U;
- 80013f6: 2300 movs r3, #0
- 80013f8: 60fb str r3, [r7, #12]
+ 80014b6: 2300 movs r3, #0
+ 80014b8: 60fb str r3, [r7, #12]
/* The application software must set correctly the PLL multiplication factor to
be in the range 16-48MHz */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
- 80013fa: 683b ldr r3, [r7, #0]
- 80013fc: 685b ldr r3, [r3, #4]
- 80013fe: 3301 adds r3, #1
- 8001400: 0019 movs r1, r3
- 8001402: 6878 ldr r0, [r7, #4]
- 8001404: f000 f8d0 bl 80015a8 <__udivsi3>
- 8001408: 0003 movs r3, r0
- 800140a: 0019 movs r1, r3
- 800140c: 683b ldr r3, [r7, #0]
- 800140e: 681b ldr r3, [r3, #0]
- 8001410: 0c9b lsrs r3, r3, #18
- 8001412: 220f movs r2, #15
- 8001414: 4013 ands r3, r2
- 8001416: 3302 adds r3, #2
- 8001418: 434b muls r3, r1
- 800141a: 60fb str r3, [r7, #12]
+ 80014ba: 683b ldr r3, [r7, #0]
+ 80014bc: 685b ldr r3, [r3, #4]
+ 80014be: 3301 adds r3, #1
+ 80014c0: 0019 movs r1, r3
+ 80014c2: 6878 ldr r0, [r7, #4]
+ 80014c4: f000 f8d0 bl 8001668 <__udivsi3>
+ 80014c8: 0003 movs r3, r0
+ 80014ca: 0019 movs r1, r3
+ 80014cc: 683b ldr r3, [r7, #0]
+ 80014ce: 681b ldr r3, [r3, #0]
+ 80014d0: 0c9b lsrs r3, r3, #18
+ 80014d2: 220f movs r2, #15
+ 80014d4: 4013 ands r3, r2
+ 80014d6: 3302 adds r3, #2
+ 80014d8: 434b muls r3, r1
+ 80014da: 60fb str r3, [r7, #12]
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
- 800141c: 68fb ldr r3, [r7, #12]
+ 80014dc: 68fb ldr r3, [r7, #12]
}
- 800141e: 0018 movs r0, r3
- 8001420: 46bd mov sp, r7
- 8001422: b004 add sp, #16
- 8001424: bd80 pop {r7, pc}
+ 80014de: 0018 movs r0, r3
+ 80014e0: 46bd mov sp, r7
+ 80014e2: b004 add sp, #16
+ 80014e4: bd80 pop {r7, pc}
-08001426 <UTILS_PLL_IsBusy>:
+080014e6 <UTILS_PLL_IsBusy>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
- 8001426: b580 push {r7, lr}
- 8001428: b082 sub sp, #8
- 800142a: af00 add r7, sp, #0
+ 80014e6: b580 push {r7, lr}
+ 80014e8: b082 sub sp, #8
+ 80014ea: af00 add r7, sp, #0
ErrorStatus status = SUCCESS;
- 800142c: 1dfb adds r3, r7, #7
- 800142e: 2201 movs r2, #1
- 8001430: 701a strb r2, [r3, #0]
+ 80014ec: 1dfb adds r3, r7, #7
+ 80014ee: 2201 movs r2, #1
+ 80014f0: 701a strb r2, [r3, #0]
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
- 8001432: f7ff fe63 bl 80010fc <LL_RCC_PLL_IsReady>
- 8001436: 1e03 subs r3, r0, #0
- 8001438: d002 beq.n 8001440 <UTILS_PLL_IsBusy+0x1a>
+ 80014f2: f7ff fe63 bl 80011bc <LL_RCC_PLL_IsReady>
+ 80014f6: 1e03 subs r3, r0, #0
+ 80014f8: d002 beq.n 8001500 <UTILS_PLL_IsBusy+0x1a>
{
/* PLL configuration cannot be modified */
status = ERROR;
- 800143a: 1dfb adds r3, r7, #7
- 800143c: 2200 movs r2, #0
- 800143e: 701a strb r2, [r3, #0]
+ 80014fa: 1dfb adds r3, r7, #7
+ 80014fc: 2200 movs r2, #0
+ 80014fe: 701a strb r2, [r3, #0]
}
return status;
- 8001440: 1dfb adds r3, r7, #7
- 8001442: 781b ldrb r3, [r3, #0]
+ 8001500: 1dfb adds r3, r7, #7
+ 8001502: 781b ldrb r3, [r3, #0]
}
- 8001444: 0018 movs r0, r3
- 8001446: 46bd mov sp, r7
- 8001448: b002 add sp, #8
- 800144a: bd80 pop {r7, pc}
+ 8001504: 0018 movs r0, r3
+ 8001506: 46bd mov sp, r7
+ 8001508: b002 add sp, #8
+ 800150a: bd80 pop {r7, pc}
-0800144c <UTILS_EnablePLLAndSwitchSystem>:
+0800150c <UTILS_EnablePLLAndSwitchSystem>:
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
- 800144c: b590 push {r4, r7, lr}
- 800144e: b085 sub sp, #20
- 8001450: af00 add r7, sp, #0
- 8001452: 6078 str r0, [r7, #4]
- 8001454: 6039 str r1, [r7, #0]
+ 800150c: b590 push {r4, r7, lr}
+ 800150e: b085 sub sp, #20
+ 8001510: af00 add r7, sp, #0
+ 8001512: 6078 str r0, [r7, #4]
+ 8001514: 6039 str r1, [r7, #0]
ErrorStatus status = SUCCESS;
- 8001456: 200f movs r0, #15
- 8001458: 183b adds r3, r7, r0
- 800145a: 2201 movs r2, #1
- 800145c: 701a strb r2, [r3, #0]
+ 8001516: 200f movs r0, #15
+ 8001518: 183b adds r3, r7, r0
+ 800151a: 2201 movs r2, #1
+ 800151c: 701a strb r2, [r3, #0]
uint32_t sysclk_frequency_current = 0U;
- 800145e: 2300 movs r3, #0
- 8001460: 60bb str r3, [r7, #8]
+ 800151e: 2300 movs r3, #0
+ 8001520: 60bb str r3, [r7, #8]
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]);
- 8001462: 4b2e ldr r3, [pc, #184] ; (800151c <UTILS_EnablePLLAndSwitchSystem+0xd0>)
- 8001464: 681a ldr r2, [r3, #0]
- 8001466: 683b ldr r3, [r7, #0]
- 8001468: 681b ldr r3, [r3, #0]
- 800146a: 091b lsrs r3, r3, #4
- 800146c: 210f movs r1, #15
- 800146e: 400b ands r3, r1
- 8001470: 492b ldr r1, [pc, #172] ; (8001520 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 8001472: 5ccb ldrb r3, [r1, r3]
- 8001474: 409a lsls r2, r3
- 8001476: 0013 movs r3, r2
- 8001478: 60bb str r3, [r7, #8]
+ 8001522: 4b2e ldr r3, [pc, #184] ; (80015dc <UTILS_EnablePLLAndSwitchSystem+0xd0>)
+ 8001524: 681a ldr r2, [r3, #0]
+ 8001526: 683b ldr r3, [r7, #0]
+ 8001528: 681b ldr r3, [r3, #0]
+ 800152a: 091b lsrs r3, r3, #4
+ 800152c: 210f movs r1, #15
+ 800152e: 400b ands r3, r1
+ 8001530: 492b ldr r1, [pc, #172] ; (80015e0 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 8001532: 5ccb ldrb r3, [r1, r3]
+ 8001534: 409a lsls r2, r3
+ 8001536: 0013 movs r3, r2
+ 8001538: 60bb str r3, [r7, #8]
/* Increasing the number of wait states because of higher CPU frequency */
if (sysclk_frequency_current < SYSCLK_Frequency)
- 800147a: 68ba ldr r2, [r7, #8]
- 800147c: 687b ldr r3, [r7, #4]
- 800147e: 429a cmp r2, r3
- 8001480: d206 bcs.n 8001490 <UTILS_EnablePLLAndSwitchSystem+0x44>
+ 800153a: 68ba ldr r2, [r7, #8]
+ 800153c: 687b ldr r3, [r7, #4]
+ 800153e: 429a cmp r2, r3
+ 8001540: d206 bcs.n 8001550 <UTILS_EnablePLLAndSwitchSystem+0x44>
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 8001482: 183c adds r4, r7, r0
- 8001484: 687b ldr r3, [r7, #4]
- 8001486: 0018 movs r0, r3
- 8001488: f7ff ff82 bl 8001390 <UTILS_SetFlashLatency>
- 800148c: 0003 movs r3, r0
- 800148e: 7023 strb r3, [r4, #0]
+ 8001542: 183c adds r4, r7, r0
+ 8001544: 687b ldr r3, [r7, #4]
+ 8001546: 0018 movs r0, r3
+ 8001548: f7ff ff82 bl 8001450 <UTILS_SetFlashLatency>
+ 800154c: 0003 movs r3, r0
+ 800154e: 7023 strb r3, [r4, #0]
}
/* Update system clock configuration */
if (status == SUCCESS)
- 8001490: 230f movs r3, #15
- 8001492: 18fb adds r3, r7, r3
- 8001494: 781b ldrb r3, [r3, #0]
- 8001496: 2b01 cmp r3, #1
- 8001498: d11a bne.n 80014d0 <UTILS_EnablePLLAndSwitchSystem+0x84>
+ 8001550: 230f movs r3, #15
+ 8001552: 18fb adds r3, r7, r3
+ 8001554: 781b ldrb r3, [r3, #0]
+ 8001556: 2b01 cmp r3, #1
+ 8001558: d11a bne.n 8001590 <UTILS_EnablePLLAndSwitchSystem+0x84>
{
/* Enable PLL */
LL_RCC_PLL_Enable();
- 800149a: f7ff fe21 bl 80010e0 <LL_RCC_PLL_Enable>
+ 800155a: f7ff fe21 bl 80011a0 <LL_RCC_PLL_Enable>
while (LL_RCC_PLL_IsReady() != 1U)
- 800149e: 46c0 nop ; (mov r8, r8)
- 80014a0: f7ff fe2c bl 80010fc <LL_RCC_PLL_IsReady>
- 80014a4: 0003 movs r3, r0
- 80014a6: 2b01 cmp r3, #1
- 80014a8: d1fa bne.n 80014a0 <UTILS_EnablePLLAndSwitchSystem+0x54>
+ 800155e: 46c0 nop ; (mov r8, r8)
+ 8001560: f7ff fe2c bl 80011bc <LL_RCC_PLL_IsReady>
+ 8001564: 0003 movs r3, r0
+ 8001566: 2b01 cmp r3, #1
+ 8001568: d1fa bne.n 8001560 <UTILS_EnablePLLAndSwitchSystem+0x54>
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- 80014aa: 683b ldr r3, [r7, #0]
- 80014ac: 681b ldr r3, [r3, #0]
- 80014ae: 0018 movs r0, r3
- 80014b0: f7ff fdec bl 800108c <LL_RCC_SetAHBPrescaler>
+ 800156a: 683b ldr r3, [r7, #0]
+ 800156c: 681b ldr r3, [r3, #0]
+ 800156e: 0018 movs r0, r3
+ 8001570: f7ff fdec bl 800114c <LL_RCC_SetAHBPrescaler>
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- 80014b4: 2002 movs r0, #2
- 80014b6: f7ff fdc9 bl 800104c <LL_RCC_SetSysClkSource>
+ 8001574: 2002 movs r0, #2
+ 8001576: f7ff fdc9 bl 800110c <LL_RCC_SetSysClkSource>
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- 80014ba: 46c0 nop ; (mov r8, r8)
- 80014bc: f7ff fdda bl 8001074 <LL_RCC_GetSysClkSource>
- 80014c0: 0003 movs r3, r0
- 80014c2: 2b08 cmp r3, #8
- 80014c4: d1fa bne.n 80014bc <UTILS_EnablePLLAndSwitchSystem+0x70>
+ 800157a: 46c0 nop ; (mov r8, r8)
+ 800157c: f7ff fdda bl 8001134 <LL_RCC_GetSysClkSource>
+ 8001580: 0003 movs r3, r0
+ 8001582: 2b08 cmp r3, #8
+ 8001584: d1fa bne.n 800157c <UTILS_EnablePLLAndSwitchSystem+0x70>
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- 80014c6: 683b ldr r3, [r7, #0]
- 80014c8: 685b ldr r3, [r3, #4]
- 80014ca: 0018 movs r0, r3
- 80014cc: f7ff fdf2 bl 80010b4 <LL_RCC_SetAPB1Prescaler>
+ 8001586: 683b ldr r3, [r7, #0]
+ 8001588: 685b ldr r3, [r3, #4]
+ 800158a: 0018 movs r0, r3
+ 800158c: f7ff fdf2 bl 8001174 <LL_RCC_SetAPB1Prescaler>
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (sysclk_frequency_current > SYSCLK_Frequency)
- 80014d0: 68ba ldr r2, [r7, #8]
- 80014d2: 687b ldr r3, [r7, #4]
- 80014d4: 429a cmp r2, r3
- 80014d6: d907 bls.n 80014e8 <UTILS_EnablePLLAndSwitchSystem+0x9c>
+ 8001590: 68ba ldr r2, [r7, #8]
+ 8001592: 687b ldr r3, [r7, #4]
+ 8001594: 429a cmp r2, r3
+ 8001596: d907 bls.n 80015a8 <UTILS_EnablePLLAndSwitchSystem+0x9c>
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- 80014d8: 230f movs r3, #15
- 80014da: 18fc adds r4, r7, r3
- 80014dc: 687b ldr r3, [r7, #4]
- 80014de: 0018 movs r0, r3
- 80014e0: f7ff ff56 bl 8001390 <UTILS_SetFlashLatency>
- 80014e4: 0003 movs r3, r0
- 80014e6: 7023 strb r3, [r4, #0]
+ 8001598: 230f movs r3, #15
+ 800159a: 18fc adds r4, r7, r3
+ 800159c: 687b ldr r3, [r7, #4]
+ 800159e: 0018 movs r0, r3
+ 80015a0: f7ff ff56 bl 8001450 <UTILS_SetFlashLatency>
+ 80015a4: 0003 movs r3, r0
+ 80015a6: 7023 strb r3, [r4, #0]
}
/* Update SystemCoreClock variable */
if (status == SUCCESS)
- 80014e8: 230f movs r3, #15
- 80014ea: 18fb adds r3, r7, r3
- 80014ec: 781b ldrb r3, [r3, #0]
- 80014ee: 2b01 cmp r3, #1
- 80014f0: d10c bne.n 800150c <UTILS_EnablePLLAndSwitchSystem+0xc0>
+ 80015a8: 230f movs r3, #15
+ 80015aa: 18fb adds r3, r7, r3
+ 80015ac: 781b ldrb r3, [r3, #0]
+ 80015ae: 2b01 cmp r3, #1
+ 80015b0: d10c bne.n 80015cc <UTILS_EnablePLLAndSwitchSystem+0xc0>
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- 80014f2: 683b ldr r3, [r7, #0]
- 80014f4: 681b ldr r3, [r3, #0]
- 80014f6: 091b lsrs r3, r3, #4
- 80014f8: 220f movs r2, #15
- 80014fa: 4013 ands r3, r2
- 80014fc: 4a08 ldr r2, [pc, #32] ; (8001520 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
- 80014fe: 5cd3 ldrb r3, [r2, r3]
- 8001500: 001a movs r2, r3
- 8001502: 687b ldr r3, [r7, #4]
- 8001504: 40d3 lsrs r3, r2
- 8001506: 0018 movs r0, r3
- 8001508: f7ff fe9e bl 8001248 <LL_SetSystemCoreClock>
+ 80015b2: 683b ldr r3, [r7, #0]
+ 80015b4: 681b ldr r3, [r3, #0]
+ 80015b6: 091b lsrs r3, r3, #4
+ 80015b8: 220f movs r2, #15
+ 80015ba: 4013 ands r3, r2
+ 80015bc: 4a08 ldr r2, [pc, #32] ; (80015e0 <UTILS_EnablePLLAndSwitchSystem+0xd4>)
+ 80015be: 5cd3 ldrb r3, [r2, r3]
+ 80015c0: 001a movs r2, r3
+ 80015c2: 687b ldr r3, [r7, #4]
+ 80015c4: 40d3 lsrs r3, r2
+ 80015c6: 0018 movs r0, r3
+ 80015c8: f7ff fe9e bl 8001308 <LL_SetSystemCoreClock>
}
return status;
- 800150c: 230f movs r3, #15
- 800150e: 18fb adds r3, r7, r3
- 8001510: 781b ldrb r3, [r3, #0]
+ 80015cc: 230f movs r3, #15
+ 80015ce: 18fb adds r3, r7, r3
+ 80015d0: 781b ldrb r3, [r3, #0]
}
- 8001512: 0018 movs r0, r3
- 8001514: 46bd mov sp, r7
- 8001516: b005 add sp, #20
- 8001518: bd90 pop {r4, r7, pc}
- 800151a: 46c0 nop ; (mov r8, r8)
- 800151c: 20000000 .word 0x20000000
- 8001520: 080018ec .word 0x080018ec
-
-08001524 <__sinit>:
+ 80015d2: 0018 movs r0, r3
+ 80015d4: 46bd mov sp, r7
+ 80015d6: b005 add sp, #20
+ 80015d8: bd90 pop {r4, r7, pc}
+ 80015da: 46c0 nop ; (mov r8, r8)
+ 80015dc: 20000000 .word 0x20000000
+ 80015e0: 080019a4 .word 0x080019a4
+
+080015e4 <__sinit>:
#include <stdbool.h>
int __errno = 0;
void *_impure_ptr = NULL;
void __sinit(void) {
- 8001524: b580 push {r7, lr}
- 8001526: af00 add r7, sp, #0
+ 80015e4: b580 push {r7, lr}
+ 80015e6: af00 add r7, sp, #0
}
- 8001528: 46c0 nop ; (mov r8, r8)
- 800152a: 46bd mov sp, r7
- 800152c: bd80 pop {r7, pc}
+ 80015e8: 46c0 nop ; (mov r8, r8)
+ 80015ea: 46bd mov sp, r7
+ 80015ec: bd80 pop {r7, pc}
-0800152e <memset>:
+080015ee <memset>:
void *memset(void *s, int c, size_t n) {
- 800152e: b580 push {r7, lr}
- 8001530: b086 sub sp, #24
- 8001532: af00 add r7, sp, #0
- 8001534: 60f8 str r0, [r7, #12]
- 8001536: 60b9 str r1, [r7, #8]
- 8001538: 607a str r2, [r7, #4]
+ 80015ee: b580 push {r7, lr}
+ 80015f0: b086 sub sp, #24
+ 80015f2: af00 add r7, sp, #0
+ 80015f4: 60f8 str r0, [r7, #12]
+ 80015f6: 60b9 str r1, [r7, #8]
+ 80015f8: 607a str r2, [r7, #4]
char *end = (char *)s + n;
- 800153a: 68fa ldr r2, [r7, #12]
- 800153c: 687b ldr r3, [r7, #4]
- 800153e: 18d3 adds r3, r2, r3
- 8001540: 613b str r3, [r7, #16]
+ 80015fa: 68fa ldr r2, [r7, #12]
+ 80015fc: 687b ldr r3, [r7, #4]
+ 80015fe: 18d3 adds r3, r2, r3
+ 8001600: 613b str r3, [r7, #16]
for (char *p = (char *)s; p < end; p++)
- 8001542: 68fb ldr r3, [r7, #12]
- 8001544: 617b str r3, [r7, #20]
- 8001546: e006 b.n 8001556 <memset+0x28>
+ 8001602: 68fb ldr r3, [r7, #12]
+ 8001604: 617b str r3, [r7, #20]
+ 8001606: e006 b.n 8001616 <memset+0x28>
*p = (char)c;
- 8001548: 68bb ldr r3, [r7, #8]
- 800154a: b2da uxtb r2, r3
- 800154c: 697b ldr r3, [r7, #20]
- 800154e: 701a strb r2, [r3, #0]
+ 8001608: 68bb ldr r3, [r7, #8]
+ 800160a: b2da uxtb r2, r3
+ 800160c: 697b ldr r3, [r7, #20]
+ 800160e: 701a strb r2, [r3, #0]
for (char *p = (char *)s; p < end; p++)
- 8001550: 697b ldr r3, [r7, #20]
- 8001552: 3301 adds r3, #1
- 8001554: 617b str r3, [r7, #20]
- 8001556: 697a ldr r2, [r7, #20]
- 8001558: 693b ldr r3, [r7, #16]
- 800155a: 429a cmp r2, r3
- 800155c: d3f4 bcc.n 8001548 <memset+0x1a>
+ 8001610: 697b ldr r3, [r7, #20]
+ 8001612: 3301 adds r3, #1
+ 8001614: 617b str r3, [r7, #20]
+ 8001616: 697a ldr r2, [r7, #20]
+ 8001618: 693b ldr r3, [r7, #16]
+ 800161a: 429a cmp r2, r3
+ 800161c: d3f4 bcc.n 8001608 <memset+0x1a>
return s;
- 800155e: 68fb ldr r3, [r7, #12]
+ 800161e: 68fb ldr r3, [r7, #12]
}
- 8001560: 0018 movs r0, r3
- 8001562: 46bd mov sp, r7
- 8001564: b006 add sp, #24
- 8001566: bd80 pop {r7, pc}
+ 8001620: 0018 movs r0, r3
+ 8001622: 46bd mov sp, r7
+ 8001624: b006 add sp, #24
+ 8001626: bd80 pop {r7, pc}
-08001568 <strlen>:
+08001628 <strlen>:
size_t strlen(const char *s) {
- 8001568: b580 push {r7, lr}
- 800156a: b084 sub sp, #16
- 800156c: af00 add r7, sp, #0
- 800156e: 6078 str r0, [r7, #4]
+ 8001628: b580 push {r7, lr}
+ 800162a: b084 sub sp, #16
+ 800162c: af00 add r7, sp, #0
+ 800162e: 6078 str r0, [r7, #4]
const char *start = s;
- 8001570: 687b ldr r3, [r7, #4]
- 8001572: 60fb str r3, [r7, #12]
+ 8001630: 687b ldr r3, [r7, #4]
+ 8001632: 60fb str r3, [r7, #12]
while (*s++);
- 8001574: 46c0 nop ; (mov r8, r8)
- 8001576: 687b ldr r3, [r7, #4]
- 8001578: 1c5a adds r2, r3, #1
- 800157a: 607a str r2, [r7, #4]
- 800157c: 781b ldrb r3, [r3, #0]
- 800157e: 2b00 cmp r3, #0
- 8001580: d1f9 bne.n 8001576 <strlen+0xe>
+ 8001634: 46c0 nop ; (mov r8, r8)
+ 8001636: 687b ldr r3, [r7, #4]
+ 8001638: 1c5a adds r2, r3, #1
+ 800163a: 607a str r2, [r7, #4]
+ 800163c: 781b ldrb r3, [r3, #0]
+ 800163e: 2b00 cmp r3, #0
+ 8001640: d1f9 bne.n 8001636 <strlen+0xe>
return s - start - 1;
- 8001582: 687a ldr r2, [r7, #4]
- 8001584: 68fb ldr r3, [r7, #12]
- 8001586: 1ad3 subs r3, r2, r3
- 8001588: 3b01 subs r3, #1
+ 8001642: 687a ldr r2, [r7, #4]
+ 8001644: 68fb ldr r3, [r7, #12]
+ 8001646: 1ad3 subs r3, r2, r3
+ 8001648: 3b01 subs r3, #1
}
- 800158a: 0018 movs r0, r3
- 800158c: 46bd mov sp, r7
- 800158e: b004 add sp, #16
- 8001590: bd80 pop {r7, pc}
+ 800164a: 0018 movs r0, r3
+ 800164c: 46bd mov sp, r7
+ 800164e: b004 add sp, #16
+ 8001650: bd80 pop {r7, pc}
-08001592 <__assert_func>:
+08001652 <__assert_func>:
void __assert_func(bool value) {
- 8001592: b580 push {r7, lr}
- 8001594: b082 sub sp, #8
- 8001596: af00 add r7, sp, #0
- 8001598: 0002 movs r2, r0
- 800159a: 1dfb adds r3, r7, #7
- 800159c: 701a strb r2, [r3, #0]
+ 8001652: b580 push {r7, lr}
+ 8001654: b082 sub sp, #8
+ 8001656: af00 add r7, sp, #0
+ 8001658: 0002 movs r2, r0
+ 800165a: 1dfb adds r3, r7, #7
+ 800165c: 701a strb r2, [r3, #0]
}
- 800159e: 46c0 nop ; (mov r8, r8)
- 80015a0: 46bd mov sp, r7
- 80015a2: b002 add sp, #8
- 80015a4: bd80 pop {r7, pc}
+ 800165e: 46c0 nop ; (mov r8, r8)
+ 8001660: 46bd mov sp, r7
+ 8001662: b002 add sp, #8
+ 8001664: bd80 pop {r7, pc}
...
-080015a8 <__udivsi3>:
- 80015a8: 2200 movs r2, #0
- 80015aa: 0843 lsrs r3, r0, #1
- 80015ac: 428b cmp r3, r1
- 80015ae: d374 bcc.n 800169a <__udivsi3+0xf2>
- 80015b0: 0903 lsrs r3, r0, #4
- 80015b2: 428b cmp r3, r1
- 80015b4: d35f bcc.n 8001676 <__udivsi3+0xce>
- 80015b6: 0a03 lsrs r3, r0, #8
- 80015b8: 428b cmp r3, r1
- 80015ba: d344 bcc.n 8001646 <__udivsi3+0x9e>
- 80015bc: 0b03 lsrs r3, r0, #12
- 80015be: 428b cmp r3, r1
- 80015c0: d328 bcc.n 8001614 <__udivsi3+0x6c>
- 80015c2: 0c03 lsrs r3, r0, #16
- 80015c4: 428b cmp r3, r1
- 80015c6: d30d bcc.n 80015e4 <__udivsi3+0x3c>
- 80015c8: 22ff movs r2, #255 ; 0xff
- 80015ca: 0209 lsls r1, r1, #8
- 80015cc: ba12 rev r2, r2
- 80015ce: 0c03 lsrs r3, r0, #16
- 80015d0: 428b cmp r3, r1
- 80015d2: d302 bcc.n 80015da <__udivsi3+0x32>
- 80015d4: 1212 asrs r2, r2, #8
- 80015d6: 0209 lsls r1, r1, #8
- 80015d8: d065 beq.n 80016a6 <__udivsi3+0xfe>
- 80015da: 0b03 lsrs r3, r0, #12
- 80015dc: 428b cmp r3, r1
- 80015de: d319 bcc.n 8001614 <__udivsi3+0x6c>
- 80015e0: e000 b.n 80015e4 <__udivsi3+0x3c>
- 80015e2: 0a09 lsrs r1, r1, #8
- 80015e4: 0bc3 lsrs r3, r0, #15
- 80015e6: 428b cmp r3, r1
- 80015e8: d301 bcc.n 80015ee <__udivsi3+0x46>
- 80015ea: 03cb lsls r3, r1, #15
- 80015ec: 1ac0 subs r0, r0, r3
- 80015ee: 4152 adcs r2, r2
- 80015f0: 0b83 lsrs r3, r0, #14
- 80015f2: 428b cmp r3, r1
- 80015f4: d301 bcc.n 80015fa <__udivsi3+0x52>
- 80015f6: 038b lsls r3, r1, #14
- 80015f8: 1ac0 subs r0, r0, r3
- 80015fa: 4152 adcs r2, r2
- 80015fc: 0b43 lsrs r3, r0, #13
- 80015fe: 428b cmp r3, r1
- 8001600: d301 bcc.n 8001606 <__udivsi3+0x5e>
- 8001602: 034b lsls r3, r1, #13
- 8001604: 1ac0 subs r0, r0, r3
- 8001606: 4152 adcs r2, r2
- 8001608: 0b03 lsrs r3, r0, #12
- 800160a: 428b cmp r3, r1
- 800160c: d301 bcc.n 8001612 <__udivsi3+0x6a>
- 800160e: 030b lsls r3, r1, #12
- 8001610: 1ac0 subs r0, r0, r3
- 8001612: 4152 adcs r2, r2
- 8001614: 0ac3 lsrs r3, r0, #11
- 8001616: 428b cmp r3, r1
- 8001618: d301 bcc.n 800161e <__udivsi3+0x76>
- 800161a: 02cb lsls r3, r1, #11
- 800161c: 1ac0 subs r0, r0, r3
- 800161e: 4152 adcs r2, r2
- 8001620: 0a83 lsrs r3, r0, #10
- 8001622: 428b cmp r3, r1
- 8001624: d301 bcc.n 800162a <__udivsi3+0x82>
- 8001626: 028b lsls r3, r1, #10
- 8001628: 1ac0 subs r0, r0, r3
- 800162a: 4152 adcs r2, r2
- 800162c: 0a43 lsrs r3, r0, #9
- 800162e: 428b cmp r3, r1
- 8001630: d301 bcc.n 8001636 <__udivsi3+0x8e>
- 8001632: 024b lsls r3, r1, #9
- 8001634: 1ac0 subs r0, r0, r3
- 8001636: 4152 adcs r2, r2
- 8001638: 0a03 lsrs r3, r0, #8
- 800163a: 428b cmp r3, r1
- 800163c: d301 bcc.n 8001642 <__udivsi3+0x9a>
- 800163e: 020b lsls r3, r1, #8
- 8001640: 1ac0 subs r0, r0, r3
- 8001642: 4152 adcs r2, r2
- 8001644: d2cd bcs.n 80015e2 <__udivsi3+0x3a>
- 8001646: 09c3 lsrs r3, r0, #7
- 8001648: 428b cmp r3, r1
- 800164a: d301 bcc.n 8001650 <__udivsi3+0xa8>
- 800164c: 01cb lsls r3, r1, #7
- 800164e: 1ac0 subs r0, r0, r3
- 8001650: 4152 adcs r2, r2
- 8001652: 0983 lsrs r3, r0, #6
- 8001654: 428b cmp r3, r1
- 8001656: d301 bcc.n 800165c <__udivsi3+0xb4>
- 8001658: 018b lsls r3, r1, #6
- 800165a: 1ac0 subs r0, r0, r3
- 800165c: 4152 adcs r2, r2
- 800165e: 0943 lsrs r3, r0, #5
- 8001660: 428b cmp r3, r1
- 8001662: d301 bcc.n 8001668 <__udivsi3+0xc0>
- 8001664: 014b lsls r3, r1, #5
- 8001666: 1ac0 subs r0, r0, r3
- 8001668: 4152 adcs r2, r2
- 800166a: 0903 lsrs r3, r0, #4
+08001668 <__udivsi3>:
+ 8001668: 2200 movs r2, #0
+ 800166a: 0843 lsrs r3, r0, #1
800166c: 428b cmp r3, r1
- 800166e: d301 bcc.n 8001674 <__udivsi3+0xcc>
- 8001670: 010b lsls r3, r1, #4
- 8001672: 1ac0 subs r0, r0, r3
- 8001674: 4152 adcs r2, r2
- 8001676: 08c3 lsrs r3, r0, #3
+ 800166e: d374 bcc.n 800175a <__udivsi3+0xf2>
+ 8001670: 0903 lsrs r3, r0, #4
+ 8001672: 428b cmp r3, r1
+ 8001674: d35f bcc.n 8001736 <__udivsi3+0xce>
+ 8001676: 0a03 lsrs r3, r0, #8
8001678: 428b cmp r3, r1
- 800167a: d301 bcc.n 8001680 <__udivsi3+0xd8>
- 800167c: 00cb lsls r3, r1, #3
- 800167e: 1ac0 subs r0, r0, r3
- 8001680: 4152 adcs r2, r2
- 8001682: 0883 lsrs r3, r0, #2
+ 800167a: d344 bcc.n 8001706 <__udivsi3+0x9e>
+ 800167c: 0b03 lsrs r3, r0, #12
+ 800167e: 428b cmp r3, r1
+ 8001680: d328 bcc.n 80016d4 <__udivsi3+0x6c>
+ 8001682: 0c03 lsrs r3, r0, #16
8001684: 428b cmp r3, r1
- 8001686: d301 bcc.n 800168c <__udivsi3+0xe4>
- 8001688: 008b lsls r3, r1, #2
- 800168a: 1ac0 subs r0, r0, r3
- 800168c: 4152 adcs r2, r2
- 800168e: 0843 lsrs r3, r0, #1
+ 8001686: d30d bcc.n 80016a4 <__udivsi3+0x3c>
+ 8001688: 22ff movs r2, #255 ; 0xff
+ 800168a: 0209 lsls r1, r1, #8
+ 800168c: ba12 rev r2, r2
+ 800168e: 0c03 lsrs r3, r0, #16
8001690: 428b cmp r3, r1
- 8001692: d301 bcc.n 8001698 <__udivsi3+0xf0>
- 8001694: 004b lsls r3, r1, #1
- 8001696: 1ac0 subs r0, r0, r3
- 8001698: 4152 adcs r2, r2
- 800169a: 1a41 subs r1, r0, r1
- 800169c: d200 bcs.n 80016a0 <__udivsi3+0xf8>
- 800169e: 4601 mov r1, r0
- 80016a0: 4152 adcs r2, r2
- 80016a2: 4610 mov r0, r2
- 80016a4: 4770 bx lr
- 80016a6: e7ff b.n 80016a8 <__udivsi3+0x100>
- 80016a8: b501 push {r0, lr}
- 80016aa: 2000 movs r0, #0
- 80016ac: f000 f8f0 bl 8001890 <__aeabi_idiv0>
- 80016b0: bd02 pop {r1, pc}
- 80016b2: 46c0 nop ; (mov r8, r8)
-
-080016b4 <__aeabi_uidivmod>:
- 80016b4: 2900 cmp r1, #0
- 80016b6: d0f7 beq.n 80016a8 <__udivsi3+0x100>
- 80016b8: e776 b.n 80015a8 <__udivsi3>
- 80016ba: 4770 bx lr
-
-080016bc <__divsi3>:
- 80016bc: 4603 mov r3, r0
- 80016be: 430b orrs r3, r1
- 80016c0: d47f bmi.n 80017c2 <__divsi3+0x106>
- 80016c2: 2200 movs r2, #0
- 80016c4: 0843 lsrs r3, r0, #1
- 80016c6: 428b cmp r3, r1
- 80016c8: d374 bcc.n 80017b4 <__divsi3+0xf8>
- 80016ca: 0903 lsrs r3, r0, #4
- 80016cc: 428b cmp r3, r1
- 80016ce: d35f bcc.n 8001790 <__divsi3+0xd4>
- 80016d0: 0a03 lsrs r3, r0, #8
- 80016d2: 428b cmp r3, r1
- 80016d4: d344 bcc.n 8001760 <__divsi3+0xa4>
- 80016d6: 0b03 lsrs r3, r0, #12
- 80016d8: 428b cmp r3, r1
- 80016da: d328 bcc.n 800172e <__divsi3+0x72>
- 80016dc: 0c03 lsrs r3, r0, #16
- 80016de: 428b cmp r3, r1
- 80016e0: d30d bcc.n 80016fe <__divsi3+0x42>
- 80016e2: 22ff movs r2, #255 ; 0xff
- 80016e4: 0209 lsls r1, r1, #8
- 80016e6: ba12 rev r2, r2
- 80016e8: 0c03 lsrs r3, r0, #16
- 80016ea: 428b cmp r3, r1
- 80016ec: d302 bcc.n 80016f4 <__divsi3+0x38>
- 80016ee: 1212 asrs r2, r2, #8
- 80016f0: 0209 lsls r1, r1, #8
- 80016f2: d065 beq.n 80017c0 <__divsi3+0x104>
- 80016f4: 0b03 lsrs r3, r0, #12
- 80016f6: 428b cmp r3, r1
- 80016f8: d319 bcc.n 800172e <__divsi3+0x72>
- 80016fa: e000 b.n 80016fe <__divsi3+0x42>
- 80016fc: 0a09 lsrs r1, r1, #8
- 80016fe: 0bc3 lsrs r3, r0, #15
- 8001700: 428b cmp r3, r1
- 8001702: d301 bcc.n 8001708 <__divsi3+0x4c>
- 8001704: 03cb lsls r3, r1, #15
- 8001706: 1ac0 subs r0, r0, r3
- 8001708: 4152 adcs r2, r2
- 800170a: 0b83 lsrs r3, r0, #14
- 800170c: 428b cmp r3, r1
- 800170e: d301 bcc.n 8001714 <__divsi3+0x58>
- 8001710: 038b lsls r3, r1, #14
- 8001712: 1ac0 subs r0, r0, r3
- 8001714: 4152 adcs r2, r2
- 8001716: 0b43 lsrs r3, r0, #13
- 8001718: 428b cmp r3, r1
- 800171a: d301 bcc.n 8001720 <__divsi3+0x64>
- 800171c: 034b lsls r3, r1, #13
- 800171e: 1ac0 subs r0, r0, r3
- 8001720: 4152 adcs r2, r2
- 8001722: 0b03 lsrs r3, r0, #12
- 8001724: 428b cmp r3, r1
- 8001726: d301 bcc.n 800172c <__divsi3+0x70>
- 8001728: 030b lsls r3, r1, #12
- 800172a: 1ac0 subs r0, r0, r3
- 800172c: 4152 adcs r2, r2
- 800172e: 0ac3 lsrs r3, r0, #11
- 8001730: 428b cmp r3, r1
- 8001732: d301 bcc.n 8001738 <__divsi3+0x7c>
- 8001734: 02cb lsls r3, r1, #11
- 8001736: 1ac0 subs r0, r0, r3
- 8001738: 4152 adcs r2, r2
- 800173a: 0a83 lsrs r3, r0, #10
- 800173c: 428b cmp r3, r1
- 800173e: d301 bcc.n 8001744 <__divsi3+0x88>
- 8001740: 028b lsls r3, r1, #10
- 8001742: 1ac0 subs r0, r0, r3
- 8001744: 4152 adcs r2, r2
- 8001746: 0a43 lsrs r3, r0, #9
- 8001748: 428b cmp r3, r1
- 800174a: d301 bcc.n 8001750 <__divsi3+0x94>
- 800174c: 024b lsls r3, r1, #9
- 800174e: 1ac0 subs r0, r0, r3
- 8001750: 4152 adcs r2, r2
- 8001752: 0a03 lsrs r3, r0, #8
- 8001754: 428b cmp r3, r1
- 8001756: d301 bcc.n 800175c <__divsi3+0xa0>
- 8001758: 020b lsls r3, r1, #8
- 800175a: 1ac0 subs r0, r0, r3
- 800175c: 4152 adcs r2, r2
- 800175e: d2cd bcs.n 80016fc <__divsi3+0x40>
- 8001760: 09c3 lsrs r3, r0, #7
- 8001762: 428b cmp r3, r1
- 8001764: d301 bcc.n 800176a <__divsi3+0xae>
- 8001766: 01cb lsls r3, r1, #7
- 8001768: 1ac0 subs r0, r0, r3
- 800176a: 4152 adcs r2, r2
- 800176c: 0983 lsrs r3, r0, #6
- 800176e: 428b cmp r3, r1
- 8001770: d301 bcc.n 8001776 <__divsi3+0xba>
- 8001772: 018b lsls r3, r1, #6
- 8001774: 1ac0 subs r0, r0, r3
- 8001776: 4152 adcs r2, r2
- 8001778: 0943 lsrs r3, r0, #5
- 800177a: 428b cmp r3, r1
- 800177c: d301 bcc.n 8001782 <__divsi3+0xc6>
- 800177e: 014b lsls r3, r1, #5
- 8001780: 1ac0 subs r0, r0, r3
- 8001782: 4152 adcs r2, r2
- 8001784: 0903 lsrs r3, r0, #4
+ 8001692: d302 bcc.n 800169a <__udivsi3+0x32>
+ 8001694: 1212 asrs r2, r2, #8
+ 8001696: 0209 lsls r1, r1, #8
+ 8001698: d065 beq.n 8001766 <__udivsi3+0xfe>
+ 800169a: 0b03 lsrs r3, r0, #12
+ 800169c: 428b cmp r3, r1
+ 800169e: d319 bcc.n 80016d4 <__udivsi3+0x6c>
+ 80016a0: e000 b.n 80016a4 <__udivsi3+0x3c>
+ 80016a2: 0a09 lsrs r1, r1, #8
+ 80016a4: 0bc3 lsrs r3, r0, #15
+ 80016a6: 428b cmp r3, r1
+ 80016a8: d301 bcc.n 80016ae <__udivsi3+0x46>
+ 80016aa: 03cb lsls r3, r1, #15
+ 80016ac: 1ac0 subs r0, r0, r3
+ 80016ae: 4152 adcs r2, r2
+ 80016b0: 0b83 lsrs r3, r0, #14
+ 80016b2: 428b cmp r3, r1
+ 80016b4: d301 bcc.n 80016ba <__udivsi3+0x52>
+ 80016b6: 038b lsls r3, r1, #14
+ 80016b8: 1ac0 subs r0, r0, r3
+ 80016ba: 4152 adcs r2, r2
+ 80016bc: 0b43 lsrs r3, r0, #13
+ 80016be: 428b cmp r3, r1
+ 80016c0: d301 bcc.n 80016c6 <__udivsi3+0x5e>
+ 80016c2: 034b lsls r3, r1, #13
+ 80016c4: 1ac0 subs r0, r0, r3
+ 80016c6: 4152 adcs r2, r2
+ 80016c8: 0b03 lsrs r3, r0, #12
+ 80016ca: 428b cmp r3, r1
+ 80016cc: d301 bcc.n 80016d2 <__udivsi3+0x6a>
+ 80016ce: 030b lsls r3, r1, #12
+ 80016d0: 1ac0 subs r0, r0, r3
+ 80016d2: 4152 adcs r2, r2
+ 80016d4: 0ac3 lsrs r3, r0, #11
+ 80016d6: 428b cmp r3, r1
+ 80016d8: d301 bcc.n 80016de <__udivsi3+0x76>
+ 80016da: 02cb lsls r3, r1, #11
+ 80016dc: 1ac0 subs r0, r0, r3
+ 80016de: 4152 adcs r2, r2
+ 80016e0: 0a83 lsrs r3, r0, #10
+ 80016e2: 428b cmp r3, r1
+ 80016e4: d301 bcc.n 80016ea <__udivsi3+0x82>
+ 80016e6: 028b lsls r3, r1, #10
+ 80016e8: 1ac0 subs r0, r0, r3
+ 80016ea: 4152 adcs r2, r2
+ 80016ec: 0a43 lsrs r3, r0, #9
+ 80016ee: 428b cmp r3, r1
+ 80016f0: d301 bcc.n 80016f6 <__udivsi3+0x8e>
+ 80016f2: 024b lsls r3, r1, #9
+ 80016f4: 1ac0 subs r0, r0, r3
+ 80016f6: 4152 adcs r2, r2
+ 80016f8: 0a03 lsrs r3, r0, #8
+ 80016fa: 428b cmp r3, r1
+ 80016fc: d301 bcc.n 8001702 <__udivsi3+0x9a>
+ 80016fe: 020b lsls r3, r1, #8
+ 8001700: 1ac0 subs r0, r0, r3
+ 8001702: 4152 adcs r2, r2
+ 8001704: d2cd bcs.n 80016a2 <__udivsi3+0x3a>
+ 8001706: 09c3 lsrs r3, r0, #7
+ 8001708: 428b cmp r3, r1
+ 800170a: d301 bcc.n 8001710 <__udivsi3+0xa8>
+ 800170c: 01cb lsls r3, r1, #7
+ 800170e: 1ac0 subs r0, r0, r3
+ 8001710: 4152 adcs r2, r2
+ 8001712: 0983 lsrs r3, r0, #6
+ 8001714: 428b cmp r3, r1
+ 8001716: d301 bcc.n 800171c <__udivsi3+0xb4>
+ 8001718: 018b lsls r3, r1, #6
+ 800171a: 1ac0 subs r0, r0, r3
+ 800171c: 4152 adcs r2, r2
+ 800171e: 0943 lsrs r3, r0, #5
+ 8001720: 428b cmp r3, r1
+ 8001722: d301 bcc.n 8001728 <__udivsi3+0xc0>
+ 8001724: 014b lsls r3, r1, #5
+ 8001726: 1ac0 subs r0, r0, r3
+ 8001728: 4152 adcs r2, r2
+ 800172a: 0903 lsrs r3, r0, #4
+ 800172c: 428b cmp r3, r1
+ 800172e: d301 bcc.n 8001734 <__udivsi3+0xcc>
+ 8001730: 010b lsls r3, r1, #4
+ 8001732: 1ac0 subs r0, r0, r3
+ 8001734: 4152 adcs r2, r2
+ 8001736: 08c3 lsrs r3, r0, #3
+ 8001738: 428b cmp r3, r1
+ 800173a: d301 bcc.n 8001740 <__udivsi3+0xd8>
+ 800173c: 00cb lsls r3, r1, #3
+ 800173e: 1ac0 subs r0, r0, r3
+ 8001740: 4152 adcs r2, r2
+ 8001742: 0883 lsrs r3, r0, #2
+ 8001744: 428b cmp r3, r1
+ 8001746: d301 bcc.n 800174c <__udivsi3+0xe4>
+ 8001748: 008b lsls r3, r1, #2
+ 800174a: 1ac0 subs r0, r0, r3
+ 800174c: 4152 adcs r2, r2
+ 800174e: 0843 lsrs r3, r0, #1
+ 8001750: 428b cmp r3, r1
+ 8001752: d301 bcc.n 8001758 <__udivsi3+0xf0>
+ 8001754: 004b lsls r3, r1, #1
+ 8001756: 1ac0 subs r0, r0, r3
+ 8001758: 4152 adcs r2, r2
+ 800175a: 1a41 subs r1, r0, r1
+ 800175c: d200 bcs.n 8001760 <__udivsi3+0xf8>
+ 800175e: 4601 mov r1, r0
+ 8001760: 4152 adcs r2, r2
+ 8001762: 4610 mov r0, r2
+ 8001764: 4770 bx lr
+ 8001766: e7ff b.n 8001768 <__udivsi3+0x100>
+ 8001768: b501 push {r0, lr}
+ 800176a: 2000 movs r0, #0
+ 800176c: f000 f8f0 bl 8001950 <__aeabi_idiv0>
+ 8001770: bd02 pop {r1, pc}
+ 8001772: 46c0 nop ; (mov r8, r8)
+
+08001774 <__aeabi_uidivmod>:
+ 8001774: 2900 cmp r1, #0
+ 8001776: d0f7 beq.n 8001768 <__udivsi3+0x100>
+ 8001778: e776 b.n 8001668 <__udivsi3>
+ 800177a: 4770 bx lr
+
+0800177c <__divsi3>:
+ 800177c: 4603 mov r3, r0
+ 800177e: 430b orrs r3, r1
+ 8001780: d47f bmi.n 8001882 <__divsi3+0x106>
+ 8001782: 2200 movs r2, #0
+ 8001784: 0843 lsrs r3, r0, #1
8001786: 428b cmp r3, r1
- 8001788: d301 bcc.n 800178e <__divsi3+0xd2>
- 800178a: 010b lsls r3, r1, #4
- 800178c: 1ac0 subs r0, r0, r3
- 800178e: 4152 adcs r2, r2
- 8001790: 08c3 lsrs r3, r0, #3
+ 8001788: d374 bcc.n 8001874 <__divsi3+0xf8>
+ 800178a: 0903 lsrs r3, r0, #4
+ 800178c: 428b cmp r3, r1
+ 800178e: d35f bcc.n 8001850 <__divsi3+0xd4>
+ 8001790: 0a03 lsrs r3, r0, #8
8001792: 428b cmp r3, r1
- 8001794: d301 bcc.n 800179a <__divsi3+0xde>
- 8001796: 00cb lsls r3, r1, #3
- 8001798: 1ac0 subs r0, r0, r3
- 800179a: 4152 adcs r2, r2
- 800179c: 0883 lsrs r3, r0, #2
+ 8001794: d344 bcc.n 8001820 <__divsi3+0xa4>
+ 8001796: 0b03 lsrs r3, r0, #12
+ 8001798: 428b cmp r3, r1
+ 800179a: d328 bcc.n 80017ee <__divsi3+0x72>
+ 800179c: 0c03 lsrs r3, r0, #16
800179e: 428b cmp r3, r1
- 80017a0: d301 bcc.n 80017a6 <__divsi3+0xea>
- 80017a2: 008b lsls r3, r1, #2
- 80017a4: 1ac0 subs r0, r0, r3
- 80017a6: 4152 adcs r2, r2
- 80017a8: 0843 lsrs r3, r0, #1
+ 80017a0: d30d bcc.n 80017be <__divsi3+0x42>
+ 80017a2: 22ff movs r2, #255 ; 0xff
+ 80017a4: 0209 lsls r1, r1, #8
+ 80017a6: ba12 rev r2, r2
+ 80017a8: 0c03 lsrs r3, r0, #16
80017aa: 428b cmp r3, r1
- 80017ac: d301 bcc.n 80017b2 <__divsi3+0xf6>
- 80017ae: 004b lsls r3, r1, #1
- 80017b0: 1ac0 subs r0, r0, r3
- 80017b2: 4152 adcs r2, r2
- 80017b4: 1a41 subs r1, r0, r1
- 80017b6: d200 bcs.n 80017ba <__divsi3+0xfe>
- 80017b8: 4601 mov r1, r0
- 80017ba: 4152 adcs r2, r2
- 80017bc: 4610 mov r0, r2
- 80017be: 4770 bx lr
- 80017c0: e05d b.n 800187e <__divsi3+0x1c2>
- 80017c2: 0fca lsrs r2, r1, #31
- 80017c4: d000 beq.n 80017c8 <__divsi3+0x10c>
- 80017c6: 4249 negs r1, r1
- 80017c8: 1003 asrs r3, r0, #32
- 80017ca: d300 bcc.n 80017ce <__divsi3+0x112>
- 80017cc: 4240 negs r0, r0
- 80017ce: 4053 eors r3, r2
- 80017d0: 2200 movs r2, #0
- 80017d2: 469c mov ip, r3
- 80017d4: 0903 lsrs r3, r0, #4
- 80017d6: 428b cmp r3, r1
- 80017d8: d32d bcc.n 8001836 <__divsi3+0x17a>
- 80017da: 0a03 lsrs r3, r0, #8
- 80017dc: 428b cmp r3, r1
- 80017de: d312 bcc.n 8001806 <__divsi3+0x14a>
- 80017e0: 22fc movs r2, #252 ; 0xfc
- 80017e2: 0189 lsls r1, r1, #6
- 80017e4: ba12 rev r2, r2
- 80017e6: 0a03 lsrs r3, r0, #8
- 80017e8: 428b cmp r3, r1
- 80017ea: d30c bcc.n 8001806 <__divsi3+0x14a>
- 80017ec: 0189 lsls r1, r1, #6
- 80017ee: 1192 asrs r2, r2, #6
+ 80017ac: d302 bcc.n 80017b4 <__divsi3+0x38>
+ 80017ae: 1212 asrs r2, r2, #8
+ 80017b0: 0209 lsls r1, r1, #8
+ 80017b2: d065 beq.n 8001880 <__divsi3+0x104>
+ 80017b4: 0b03 lsrs r3, r0, #12
+ 80017b6: 428b cmp r3, r1
+ 80017b8: d319 bcc.n 80017ee <__divsi3+0x72>
+ 80017ba: e000 b.n 80017be <__divsi3+0x42>
+ 80017bc: 0a09 lsrs r1, r1, #8
+ 80017be: 0bc3 lsrs r3, r0, #15
+ 80017c0: 428b cmp r3, r1
+ 80017c2: d301 bcc.n 80017c8 <__divsi3+0x4c>
+ 80017c4: 03cb lsls r3, r1, #15
+ 80017c6: 1ac0 subs r0, r0, r3
+ 80017c8: 4152 adcs r2, r2
+ 80017ca: 0b83 lsrs r3, r0, #14
+ 80017cc: 428b cmp r3, r1
+ 80017ce: d301 bcc.n 80017d4 <__divsi3+0x58>
+ 80017d0: 038b lsls r3, r1, #14
+ 80017d2: 1ac0 subs r0, r0, r3
+ 80017d4: 4152 adcs r2, r2
+ 80017d6: 0b43 lsrs r3, r0, #13
+ 80017d8: 428b cmp r3, r1
+ 80017da: d301 bcc.n 80017e0 <__divsi3+0x64>
+ 80017dc: 034b lsls r3, r1, #13
+ 80017de: 1ac0 subs r0, r0, r3
+ 80017e0: 4152 adcs r2, r2
+ 80017e2: 0b03 lsrs r3, r0, #12
+ 80017e4: 428b cmp r3, r1
+ 80017e6: d301 bcc.n 80017ec <__divsi3+0x70>
+ 80017e8: 030b lsls r3, r1, #12
+ 80017ea: 1ac0 subs r0, r0, r3
+ 80017ec: 4152 adcs r2, r2
+ 80017ee: 0ac3 lsrs r3, r0, #11
80017f0: 428b cmp r3, r1
- 80017f2: d308 bcc.n 8001806 <__divsi3+0x14a>
- 80017f4: 0189 lsls r1, r1, #6
- 80017f6: 1192 asrs r2, r2, #6
- 80017f8: 428b cmp r3, r1
- 80017fa: d304 bcc.n 8001806 <__divsi3+0x14a>
- 80017fc: 0189 lsls r1, r1, #6
- 80017fe: d03a beq.n 8001876 <__divsi3+0x1ba>
- 8001800: 1192 asrs r2, r2, #6
- 8001802: e000 b.n 8001806 <__divsi3+0x14a>
- 8001804: 0989 lsrs r1, r1, #6
- 8001806: 09c3 lsrs r3, r0, #7
+ 80017f2: d301 bcc.n 80017f8 <__divsi3+0x7c>
+ 80017f4: 02cb lsls r3, r1, #11
+ 80017f6: 1ac0 subs r0, r0, r3
+ 80017f8: 4152 adcs r2, r2
+ 80017fa: 0a83 lsrs r3, r0, #10
+ 80017fc: 428b cmp r3, r1
+ 80017fe: d301 bcc.n 8001804 <__divsi3+0x88>
+ 8001800: 028b lsls r3, r1, #10
+ 8001802: 1ac0 subs r0, r0, r3
+ 8001804: 4152 adcs r2, r2
+ 8001806: 0a43 lsrs r3, r0, #9
8001808: 428b cmp r3, r1
- 800180a: d301 bcc.n 8001810 <__divsi3+0x154>
- 800180c: 01cb lsls r3, r1, #7
+ 800180a: d301 bcc.n 8001810 <__divsi3+0x94>
+ 800180c: 024b lsls r3, r1, #9
800180e: 1ac0 subs r0, r0, r3
8001810: 4152 adcs r2, r2
- 8001812: 0983 lsrs r3, r0, #6
+ 8001812: 0a03 lsrs r3, r0, #8
8001814: 428b cmp r3, r1
- 8001816: d301 bcc.n 800181c <__divsi3+0x160>
- 8001818: 018b lsls r3, r1, #6
+ 8001816: d301 bcc.n 800181c <__divsi3+0xa0>
+ 8001818: 020b lsls r3, r1, #8
800181a: 1ac0 subs r0, r0, r3
800181c: 4152 adcs r2, r2
- 800181e: 0943 lsrs r3, r0, #5
- 8001820: 428b cmp r3, r1
- 8001822: d301 bcc.n 8001828 <__divsi3+0x16c>
- 8001824: 014b lsls r3, r1, #5
- 8001826: 1ac0 subs r0, r0, r3
- 8001828: 4152 adcs r2, r2
- 800182a: 0903 lsrs r3, r0, #4
- 800182c: 428b cmp r3, r1
- 800182e: d301 bcc.n 8001834 <__divsi3+0x178>
- 8001830: 010b lsls r3, r1, #4
- 8001832: 1ac0 subs r0, r0, r3
- 8001834: 4152 adcs r2, r2
- 8001836: 08c3 lsrs r3, r0, #3
- 8001838: 428b cmp r3, r1
- 800183a: d301 bcc.n 8001840 <__divsi3+0x184>
- 800183c: 00cb lsls r3, r1, #3
- 800183e: 1ac0 subs r0, r0, r3
- 8001840: 4152 adcs r2, r2
- 8001842: 0883 lsrs r3, r0, #2
- 8001844: 428b cmp r3, r1
- 8001846: d301 bcc.n 800184c <__divsi3+0x190>
- 8001848: 008b lsls r3, r1, #2
- 800184a: 1ac0 subs r0, r0, r3
- 800184c: 4152 adcs r2, r2
- 800184e: d2d9 bcs.n 8001804 <__divsi3+0x148>
- 8001850: 0843 lsrs r3, r0, #1
+ 800181e: d2cd bcs.n 80017bc <__divsi3+0x40>
+ 8001820: 09c3 lsrs r3, r0, #7
+ 8001822: 428b cmp r3, r1
+ 8001824: d301 bcc.n 800182a <__divsi3+0xae>
+ 8001826: 01cb lsls r3, r1, #7
+ 8001828: 1ac0 subs r0, r0, r3
+ 800182a: 4152 adcs r2, r2
+ 800182c: 0983 lsrs r3, r0, #6
+ 800182e: 428b cmp r3, r1
+ 8001830: d301 bcc.n 8001836 <__divsi3+0xba>
+ 8001832: 018b lsls r3, r1, #6
+ 8001834: 1ac0 subs r0, r0, r3
+ 8001836: 4152 adcs r2, r2
+ 8001838: 0943 lsrs r3, r0, #5
+ 800183a: 428b cmp r3, r1
+ 800183c: d301 bcc.n 8001842 <__divsi3+0xc6>
+ 800183e: 014b lsls r3, r1, #5
+ 8001840: 1ac0 subs r0, r0, r3
+ 8001842: 4152 adcs r2, r2
+ 8001844: 0903 lsrs r3, r0, #4
+ 8001846: 428b cmp r3, r1
+ 8001848: d301 bcc.n 800184e <__divsi3+0xd2>
+ 800184a: 010b lsls r3, r1, #4
+ 800184c: 1ac0 subs r0, r0, r3
+ 800184e: 4152 adcs r2, r2
+ 8001850: 08c3 lsrs r3, r0, #3
8001852: 428b cmp r3, r1
- 8001854: d301 bcc.n 800185a <__divsi3+0x19e>
- 8001856: 004b lsls r3, r1, #1
+ 8001854: d301 bcc.n 800185a <__divsi3+0xde>
+ 8001856: 00cb lsls r3, r1, #3
8001858: 1ac0 subs r0, r0, r3
800185a: 4152 adcs r2, r2
- 800185c: 1a41 subs r1, r0, r1
- 800185e: d200 bcs.n 8001862 <__divsi3+0x1a6>
- 8001860: 4601 mov r1, r0
- 8001862: 4663 mov r3, ip
- 8001864: 4152 adcs r2, r2
- 8001866: 105b asrs r3, r3, #1
- 8001868: 4610 mov r0, r2
- 800186a: d301 bcc.n 8001870 <__divsi3+0x1b4>
- 800186c: 4240 negs r0, r0
- 800186e: 2b00 cmp r3, #0
- 8001870: d500 bpl.n 8001874 <__divsi3+0x1b8>
- 8001872: 4249 negs r1, r1
- 8001874: 4770 bx lr
- 8001876: 4663 mov r3, ip
- 8001878: 105b asrs r3, r3, #1
- 800187a: d300 bcc.n 800187e <__divsi3+0x1c2>
- 800187c: 4240 negs r0, r0
- 800187e: b501 push {r0, lr}
- 8001880: 2000 movs r0, #0
- 8001882: f000 f805 bl 8001890 <__aeabi_idiv0>
- 8001886: bd02 pop {r1, pc}
-
-08001888 <__aeabi_idivmod>:
- 8001888: 2900 cmp r1, #0
- 800188a: d0f8 beq.n 800187e <__divsi3+0x1c2>
- 800188c: e716 b.n 80016bc <__divsi3>
- 800188e: 4770 bx lr
-
-08001890 <__aeabi_idiv0>:
- 8001890: 4770 bx lr
- 8001892: 46c0 nop ; (mov r8, r8)
-
-08001894 <Reset_Handler>:
+ 800185c: 0883 lsrs r3, r0, #2
+ 800185e: 428b cmp r3, r1
+ 8001860: d301 bcc.n 8001866 <__divsi3+0xea>
+ 8001862: 008b lsls r3, r1, #2
+ 8001864: 1ac0 subs r0, r0, r3
+ 8001866: 4152 adcs r2, r2
+ 8001868: 0843 lsrs r3, r0, #1
+ 800186a: 428b cmp r3, r1
+ 800186c: d301 bcc.n 8001872 <__divsi3+0xf6>
+ 800186e: 004b lsls r3, r1, #1
+ 8001870: 1ac0 subs r0, r0, r3
+ 8001872: 4152 adcs r2, r2
+ 8001874: 1a41 subs r1, r0, r1
+ 8001876: d200 bcs.n 800187a <__divsi3+0xfe>
+ 8001878: 4601 mov r1, r0
+ 800187a: 4152 adcs r2, r2
+ 800187c: 4610 mov r0, r2
+ 800187e: 4770 bx lr
+ 8001880: e05d b.n 800193e <__divsi3+0x1c2>
+ 8001882: 0fca lsrs r2, r1, #31
+ 8001884: d000 beq.n 8001888 <__divsi3+0x10c>
+ 8001886: 4249 negs r1, r1
+ 8001888: 1003 asrs r3, r0, #32
+ 800188a: d300 bcc.n 800188e <__divsi3+0x112>
+ 800188c: 4240 negs r0, r0
+ 800188e: 4053 eors r3, r2
+ 8001890: 2200 movs r2, #0
+ 8001892: 469c mov ip, r3
+ 8001894: 0903 lsrs r3, r0, #4
+ 8001896: 428b cmp r3, r1
+ 8001898: d32d bcc.n 80018f6 <__divsi3+0x17a>
+ 800189a: 0a03 lsrs r3, r0, #8
+ 800189c: 428b cmp r3, r1
+ 800189e: d312 bcc.n 80018c6 <__divsi3+0x14a>
+ 80018a0: 22fc movs r2, #252 ; 0xfc
+ 80018a2: 0189 lsls r1, r1, #6
+ 80018a4: ba12 rev r2, r2
+ 80018a6: 0a03 lsrs r3, r0, #8
+ 80018a8: 428b cmp r3, r1
+ 80018aa: d30c bcc.n 80018c6 <__divsi3+0x14a>
+ 80018ac: 0189 lsls r1, r1, #6
+ 80018ae: 1192 asrs r2, r2, #6
+ 80018b0: 428b cmp r3, r1
+ 80018b2: d308 bcc.n 80018c6 <__divsi3+0x14a>
+ 80018b4: 0189 lsls r1, r1, #6
+ 80018b6: 1192 asrs r2, r2, #6
+ 80018b8: 428b cmp r3, r1
+ 80018ba: d304 bcc.n 80018c6 <__divsi3+0x14a>
+ 80018bc: 0189 lsls r1, r1, #6
+ 80018be: d03a beq.n 8001936 <__divsi3+0x1ba>
+ 80018c0: 1192 asrs r2, r2, #6
+ 80018c2: e000 b.n 80018c6 <__divsi3+0x14a>
+ 80018c4: 0989 lsrs r1, r1, #6
+ 80018c6: 09c3 lsrs r3, r0, #7
+ 80018c8: 428b cmp r3, r1
+ 80018ca: d301 bcc.n 80018d0 <__divsi3+0x154>
+ 80018cc: 01cb lsls r3, r1, #7
+ 80018ce: 1ac0 subs r0, r0, r3
+ 80018d0: 4152 adcs r2, r2
+ 80018d2: 0983 lsrs r3, r0, #6
+ 80018d4: 428b cmp r3, r1
+ 80018d6: d301 bcc.n 80018dc <__divsi3+0x160>
+ 80018d8: 018b lsls r3, r1, #6
+ 80018da: 1ac0 subs r0, r0, r3
+ 80018dc: 4152 adcs r2, r2
+ 80018de: 0943 lsrs r3, r0, #5
+ 80018e0: 428b cmp r3, r1
+ 80018e2: d301 bcc.n 80018e8 <__divsi3+0x16c>
+ 80018e4: 014b lsls r3, r1, #5
+ 80018e6: 1ac0 subs r0, r0, r3
+ 80018e8: 4152 adcs r2, r2
+ 80018ea: 0903 lsrs r3, r0, #4
+ 80018ec: 428b cmp r3, r1
+ 80018ee: d301 bcc.n 80018f4 <__divsi3+0x178>
+ 80018f0: 010b lsls r3, r1, #4
+ 80018f2: 1ac0 subs r0, r0, r3
+ 80018f4: 4152 adcs r2, r2
+ 80018f6: 08c3 lsrs r3, r0, #3
+ 80018f8: 428b cmp r3, r1
+ 80018fa: d301 bcc.n 8001900 <__divsi3+0x184>
+ 80018fc: 00cb lsls r3, r1, #3
+ 80018fe: 1ac0 subs r0, r0, r3
+ 8001900: 4152 adcs r2, r2
+ 8001902: 0883 lsrs r3, r0, #2
+ 8001904: 428b cmp r3, r1
+ 8001906: d301 bcc.n 800190c <__divsi3+0x190>
+ 8001908: 008b lsls r3, r1, #2
+ 800190a: 1ac0 subs r0, r0, r3
+ 800190c: 4152 adcs r2, r2
+ 800190e: d2d9 bcs.n 80018c4 <__divsi3+0x148>
+ 8001910: 0843 lsrs r3, r0, #1
+ 8001912: 428b cmp r3, r1
+ 8001914: d301 bcc.n 800191a <__divsi3+0x19e>
+ 8001916: 004b lsls r3, r1, #1
+ 8001918: 1ac0 subs r0, r0, r3
+ 800191a: 4152 adcs r2, r2
+ 800191c: 1a41 subs r1, r0, r1
+ 800191e: d200 bcs.n 8001922 <__divsi3+0x1a6>
+ 8001920: 4601 mov r1, r0
+ 8001922: 4663 mov r3, ip
+ 8001924: 4152 adcs r2, r2
+ 8001926: 105b asrs r3, r3, #1
+ 8001928: 4610 mov r0, r2
+ 800192a: d301 bcc.n 8001930 <__divsi3+0x1b4>
+ 800192c: 4240 negs r0, r0
+ 800192e: 2b00 cmp r3, #0
+ 8001930: d500 bpl.n 8001934 <__divsi3+0x1b8>
+ 8001932: 4249 negs r1, r1
+ 8001934: 4770 bx lr
+ 8001936: 4663 mov r3, ip
+ 8001938: 105b asrs r3, r3, #1
+ 800193a: d300 bcc.n 800193e <__divsi3+0x1c2>
+ 800193c: 4240 negs r0, r0
+ 800193e: b501 push {r0, lr}
+ 8001940: 2000 movs r0, #0
+ 8001942: f000 f805 bl 8001950 <__aeabi_idiv0>
+ 8001946: bd02 pop {r1, pc}
+
+08001948 <__aeabi_idivmod>:
+ 8001948: 2900 cmp r1, #0
+ 800194a: d0f8 beq.n 800193e <__divsi3+0x1c2>
+ 800194c: e716 b.n 800177c <__divsi3>
+ 800194e: 4770 bx lr
+
+08001950 <__aeabi_idiv0>:
+ 8001950: 4770 bx lr
+ 8001952: 46c0 nop ; (mov r8, r8)
+
+08001954 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
- 8001894: 480c ldr r0, [pc, #48] ; (80018c8 <LoopForever+0x2>)
+ 8001954: 480c ldr r0, [pc, #48] ; (8001988 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
- 8001896: 4685 mov sp, r0
+ 8001956: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
- 8001898: 2100 movs r1, #0
+ 8001958: 2100 movs r1, #0
b LoopCopyDataInit
- 800189a: e003 b.n 80018a4 <LoopCopyDataInit>
+ 800195a: e003 b.n 8001964 <LoopCopyDataInit>
-0800189c <CopyDataInit>:
+0800195c <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
- 800189c: 4b0b ldr r3, [pc, #44] ; (80018cc <LoopForever+0x6>)
+ 800195c: 4b0b ldr r3, [pc, #44] ; (800198c <LoopForever+0x6>)
ldr r3, [r3, r1]
- 800189e: 585b ldr r3, [r3, r1]
+ 800195e: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
- 80018a0: 5043 str r3, [r0, r1]
+ 8001960: 5043 str r3, [r0, r1]
adds r1, r1, #4
- 80018a2: 3104 adds r1, #4
+ 8001962: 3104 adds r1, #4
-080018a4 <LoopCopyDataInit>:
+08001964 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
- 80018a4: 480a ldr r0, [pc, #40] ; (80018d0 <LoopForever+0xa>)
+ 8001964: 480a ldr r0, [pc, #40] ; (8001990 <LoopForever+0xa>)
ldr r3, =_edata
- 80018a6: 4b0b ldr r3, [pc, #44] ; (80018d4 <LoopForever+0xe>)
+ 8001966: 4b0b ldr r3, [pc, #44] ; (8001994 <LoopForever+0xe>)
adds r2, r0, r1
- 80018a8: 1842 adds r2, r0, r1
+ 8001968: 1842 adds r2, r0, r1
cmp r2, r3
- 80018aa: 429a cmp r2, r3
+ 800196a: 429a cmp r2, r3
bcc CopyDataInit
- 80018ac: d3f6 bcc.n 800189c <CopyDataInit>
+ 800196c: d3f6 bcc.n 800195c <CopyDataInit>
ldr r2, =_sbss
- 80018ae: 4a0a ldr r2, [pc, #40] ; (80018d8 <LoopForever+0x12>)
+ 800196e: 4a0a ldr r2, [pc, #40] ; (8001998 <LoopForever+0x12>)
b LoopFillZerobss
- 80018b0: e002 b.n 80018b8 <LoopFillZerobss>
+ 8001970: e002 b.n 8001978 <LoopFillZerobss>
-080018b2 <FillZerobss>:
+08001972 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
- 80018b2: 2300 movs r3, #0
+ 8001972: 2300 movs r3, #0
str r3, [r2]
- 80018b4: 6013 str r3, [r2, #0]
+ 8001974: 6013 str r3, [r2, #0]
adds r2, r2, #4
- 80018b6: 3204 adds r2, #4
+ 8001976: 3204 adds r2, #4
-080018b8 <LoopFillZerobss>:
+08001978 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
- 80018b8: 4b08 ldr r3, [pc, #32] ; (80018dc <LoopForever+0x16>)
+ 8001978: 4b08 ldr r3, [pc, #32] ; (800199c <LoopForever+0x16>)
cmp r2, r3
- 80018ba: 429a cmp r2, r3
+ 800197a: 429a cmp r2, r3
bcc FillZerobss
- 80018bc: d3f9 bcc.n 80018b2 <FillZerobss>
+ 800197c: d3f9 bcc.n 8001972 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
- 80018be: f7ff faad bl 8000e1c <SystemInit>
+ 800197e: f7ff faad bl 8000edc <SystemInit>
/* Call static constructors */
// bl __libc_init_array
/* Call the application's entry point.*/
bl main
- 80018c2: f7fe fcaa bl 800021a <main>
+ 8001982: f7fe fc4a bl 800021a <main>
-080018c6 <LoopForever>:
+08001986 <LoopForever>:
LoopForever:
b LoopForever
- 80018c6: e7fe b.n 80018c6 <LoopForever>
+ 8001986: e7fe b.n 8001986 <LoopForever>
ldr r0, =_estack
- 80018c8: 20001000 .word 0x20001000
+ 8001988: 20001000 .word 0x20001000
ldr r3, =_sidata
- 80018cc: 08001904 .word 0x08001904
+ 800198c: 080019bc .word 0x080019bc
ldr r0, =_sdata
- 80018d0: 20000000 .word 0x20000000
+ 8001990: 20000000 .word 0x20000000
ldr r3, =_edata
- 80018d4: 20000094 .word 0x20000094
+ 8001994: 20000094 .word 0x20000094
ldr r2, =_sbss
- 80018d8: 20000094 .word 0x20000094
+ 8001998: 20000094 .word 0x20000094
ldr r3, = _ebss
- 80018dc: 200009d4 .word 0x200009d4
+ 800199c: 2000051c .word 0x2000051c
-080018e0 <ADC1_IRQHandler>:
+080019a0 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 80018e0: e7fe b.n 80018e0 <ADC1_IRQHandler>
- 80018e2: 0000 movs r0, r0
- 80018e4: 424f4f46 .word 0x424f4f46
- 80018e8: 000a5241 .word 0x000a5241
+ 80019a0: e7fe b.n 80019a0 <ADC1_IRQHandler>
+ ...
-080018ec <AHBPrescTable>:
+080019a4 <AHBPrescTable>:
...
- 80018f4: 04030201 09080706 ........
+ 80019ac: 0201 0403 0706 0908 ........
-080018fc <APBPrescTable>:
- 80018fc: 00000000 04030201 ........
+080019b4 <APBPrescTable>:
+ 80019b4: 0000 0000 0201 0403 ........
diff --git a/gm_platform/fw/main.map b/gm_platform/fw/main.map
index ecbce31..0baea99 100644
--- a/gm_platform/fw/main.map
+++ b/gm_platform/fw/main.map
@@ -1,18 +1,18 @@
Archive member included to satisfy reference by file (symbol)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- /tmp/cchCmUnQ.o (__aeabi_uidiv)
+ /tmp/ccxtvPlT.o (__aeabi_uidiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- /tmp/cczzmF2c.o (__aeabi_idiv)
+ /tmp/ccrrpgrR.o (__aeabi_idiv)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
/usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0)
Allocating common symbols
Common symbol size file
-usart_tx_buf 0x10c /tmp/cc4OHQ7z.o
-leds 0x20 /tmp/cchCmUnQ.o
-adc_buf 0x800 /tmp/cczzmF2c.o
+usart_tx_buf 0x40c /tmp/ccXNIrIP.o
+leds 0x20 /tmp/ccxtvPlT.o
+adc_buf 0x40 /tmp/ccrrpgrR.o
Memory Configuration
@@ -25,151 +25,151 @@ RAM 0x0000000020000000 0x0000000000001000 xrw
Linker script and memory map
LOAD /home/user/resource/STM32CubeF0/Drivers/CMSIS/Lib/GCC/libarm_cortexM0l_math.a
-LOAD /tmp/cchCmUnQ.o
-LOAD /tmp/cczzmF2c.o
-LOAD /tmp/cc4OHQ7z.o
-LOAD /tmp/cc0OqFzX.o
-LOAD /tmp/ccTaPb5k.o
-LOAD /tmp/cc6XVkRI.o
-LOAD /tmp/ccvZIDd7.o
-LOAD /tmp/ccTEVTRv.o
-LOAD /tmp/ccvICuLU.o
+LOAD /tmp/ccxtvPlT.o
+LOAD /tmp/ccrrpgrR.o
+LOAD /tmp/ccXNIrIP.o
+LOAD /tmp/ccy0xC7N.o
+LOAD /tmp/ccr2qryM.o
+LOAD /tmp/ccJ50X5K.o
+LOAD /tmp/ccFUXyQJ.o
+LOAD /tmp/cc8rJnLI.o
+LOAD /tmp/ccDd2fMH.o
LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020001000 _estack = 0x20001000
.isr_vector 0x0000000008000000 0xc0
0x0000000008000000 . = ALIGN (0x4)
*(.isr_vector)
- .isr_vector 0x0000000008000000 0xc0 /tmp/ccTaPb5k.o
+ .isr_vector 0x0000000008000000 0xc0 /tmp/ccr2qryM.o
0x0000000008000000 g_pfnVectors
0x00000000080000c0 . = ALIGN (0x4)
-.text 0x00000000080000c0 0x1844
+.text 0x00000000080000c0 0x18fc
0x00000000080000c0 . = ALIGN (0x4)
*(.text)
- .text 0x00000000080000c0 0x454 /tmp/cchCmUnQ.o
+ .text 0x00000000080000c0 0x428 /tmp/ccxtvPlT.o
0x0000000008000210 update_leds
0x000000000800021a main
- 0x00000000080003c8 SPI1_IRQHandler
- 0x00000000080003f4 TIM16_IRQHandler
- 0x00000000080004b0 NMI_Handler
- 0x00000000080004bc HardFault_Handler
- 0x00000000080004c0 SVC_Handler
- 0x00000000080004cc PendSV_Handler
- 0x00000000080004d8 SysTick_Handler
- .text 0x0000000008000514 0x29c /tmp/cczzmF2c.o
- 0x000000000800061c adc_configure_scope_mode
- 0x0000000008000792 DMA1_Channel1_IRQHandler
- .text 0x00000000080007b0 0x31c /tmp/cc4OHQ7z.o
- 0x00000000080008e8 usart_dma_init
- 0x00000000080009d4 usart_dma_fifo_push
- 0x0000000008000a2c usart_putc
- 0x0000000008000a5c DMA1_Channel2_3_IRQHandler
- 0x0000000008000a9c usart_send_packet
- .text 0x0000000008000acc 0x33a /tmp/cc0OqFzX.o
- 0x0000000008000acc cobs_encode
- 0x0000000008000b92 cobs_encode_usart
- 0x0000000008000c32 cobs_decode
- 0x0000000008000d08 cobs_decode_incremental_initialize
- 0x0000000008000d24 cobs_decode_incremental
- .text 0x0000000008000e06 0x14 /tmp/ccTaPb5k.o
- *fill* 0x0000000008000e1a 0x2
- .text 0x0000000008000e1c 0x174 /tmp/cc6XVkRI.o
- 0x0000000008000e1c SystemInit
- 0x0000000008000ea4 SystemCoreClockUpdate
- .text 0x0000000008000f90 0x594 /tmp/ccvZIDd7.o
- 0x00000000080011e4 LL_Init1msTick
- 0x0000000008001202 LL_mDelay
- 0x0000000008001248 LL_SetSystemCoreClock
- 0x0000000008001264 LL_PLL_ConfigSystemClock_HSI
- 0x00000000080012f0 LL_PLL_ConfigSystemClock_HSE
- .text 0x0000000008001524 0x82 /tmp/ccTEVTRv.o
- 0x0000000008001524 __sinit
- 0x000000000800152e memset
- 0x0000000008001568 strlen
- 0x0000000008001592 __assert_func
- .text 0x00000000080015a6 0x0 /tmp/ccvICuLU.o
- *fill* 0x00000000080015a6 0x2
- .text 0x00000000080015a8 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- 0x00000000080015a8 __udivsi3
- 0x00000000080015a8 __aeabi_uidiv
- 0x00000000080016b4 __aeabi_uidivmod
- .text 0x00000000080016bc 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- 0x00000000080016bc __aeabi_idiv
- 0x00000000080016bc __divsi3
- 0x0000000008001888 __aeabi_idivmod
- .text 0x0000000008001890 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
- 0x0000000008001890 __aeabi_ldiv0
- 0x0000000008001890 __aeabi_idiv0
+ 0x000000000800039c SPI1_IRQHandler
+ 0x00000000080003c8 TIM16_IRQHandler
+ 0x0000000008000484 NMI_Handler
+ 0x0000000008000490 HardFault_Handler
+ 0x0000000008000494 SVC_Handler
+ 0x00000000080004a0 PendSV_Handler
+ 0x00000000080004ac SysTick_Handler
+ .text 0x00000000080004e8 0x2e4 /tmp/ccrrpgrR.o
+ 0x00000000080005f0 adc_configure_scope_mode
+ 0x0000000008000762 DMA1_Channel1_IRQHandler
+ .text 0x00000000080007cc 0x3a4 /tmp/ccXNIrIP.o
+ 0x0000000008000904 usart_dma_init
+ 0x00000000080009f8 usart_dma_fifo_push
+ 0x0000000008000a50 usart_putc
+ 0x0000000008000a80 usart_putc_nonblocking
+ 0x0000000008000aa8 DMA1_Channel2_3_IRQHandler
+ 0x0000000008000ae8 usart_send_packet
+ 0x0000000008000b1c usart_send_packet_nonblocking
+ .text 0x0000000008000b70 0x358 /tmp/ccy0xC7N.o
+ 0x0000000008000b70 cobs_encode
+ 0x0000000008000c36 cobs_encode_usart
+ 0x0000000008000cf4 cobs_decode
+ 0x0000000008000dca cobs_decode_incremental_initialize
+ 0x0000000008000de6 cobs_decode_incremental
+ .text 0x0000000008000ec8 0x14 /tmp/ccr2qryM.o
+ .text 0x0000000008000edc 0x174 /tmp/ccJ50X5K.o
+ 0x0000000008000edc SystemInit
+ 0x0000000008000f64 SystemCoreClockUpdate
+ .text 0x0000000008001050 0x594 /tmp/ccFUXyQJ.o
+ 0x00000000080012a4 LL_Init1msTick
+ 0x00000000080012c2 LL_mDelay
+ 0x0000000008001308 LL_SetSystemCoreClock
+ 0x0000000008001324 LL_PLL_ConfigSystemClock_HSI
+ 0x00000000080013b0 LL_PLL_ConfigSystemClock_HSE
+ .text 0x00000000080015e4 0x82 /tmp/cc8rJnLI.o
+ 0x00000000080015e4 __sinit
+ 0x00000000080015ee memset
+ 0x0000000008001628 strlen
+ 0x0000000008001652 __assert_func
+ .text 0x0000000008001666 0x0 /tmp/ccDd2fMH.o
+ *fill* 0x0000000008001666 0x2
+ .text 0x0000000008001668 0x114 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ 0x0000000008001668 __udivsi3
+ 0x0000000008001668 __aeabi_uidiv
+ 0x0000000008001774 __aeabi_uidivmod
+ .text 0x000000000800177c 0x1d4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ 0x000000000800177c __aeabi_idiv
+ 0x000000000800177c __divsi3
+ 0x0000000008001948 __aeabi_idivmod
+ .text 0x0000000008001950 0x4 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ 0x0000000008001950 __aeabi_ldiv0
+ 0x0000000008001950 __aeabi_idiv0
*(.text.*)
.text.Reset_Handler
- 0x0000000008001894 0x4c /tmp/ccTaPb5k.o
- 0x0000000008001894 Reset_Handler
+ 0x0000000008001954 0x4c /tmp/ccr2qryM.o
+ 0x0000000008001954 Reset_Handler
.text.Default_Handler
- 0x00000000080018e0 0x2 /tmp/ccTaPb5k.o
- 0x00000000080018e0 TIM1_CC_IRQHandler
- 0x00000000080018e0 I2C1_IRQHandler
- 0x00000000080018e0 EXTI2_3_IRQHandler
- 0x00000000080018e0 ADC1_IRQHandler
- 0x00000000080018e0 TIM17_IRQHandler
- 0x00000000080018e0 RTC_IRQHandler
- 0x00000000080018e0 TIM3_IRQHandler
- 0x00000000080018e0 EXTI4_15_IRQHandler
- 0x00000000080018e0 RCC_IRQHandler
- 0x00000000080018e0 Default_Handler
- 0x00000000080018e0 TIM14_IRQHandler
- 0x00000000080018e0 DMA1_Channel4_5_IRQHandler
- 0x00000000080018e0 EXTI0_1_IRQHandler
- 0x00000000080018e0 WWDG_IRQHandler
- 0x00000000080018e0 FLASH_IRQHandler
- 0x00000000080018e0 USART1_IRQHandler
- 0x00000000080018e0 TIM1_BRK_UP_TRG_COM_IRQHandler
+ 0x00000000080019a0 0x2 /tmp/ccr2qryM.o
+ 0x00000000080019a0 TIM1_CC_IRQHandler
+ 0x00000000080019a0 I2C1_IRQHandler
+ 0x00000000080019a0 EXTI2_3_IRQHandler
+ 0x00000000080019a0 ADC1_IRQHandler
+ 0x00000000080019a0 TIM17_IRQHandler
+ 0x00000000080019a0 RTC_IRQHandler
+ 0x00000000080019a0 TIM3_IRQHandler
+ 0x00000000080019a0 EXTI4_15_IRQHandler
+ 0x00000000080019a0 RCC_IRQHandler
+ 0x00000000080019a0 Default_Handler
+ 0x00000000080019a0 TIM14_IRQHandler
+ 0x00000000080019a0 DMA1_Channel4_5_IRQHandler
+ 0x00000000080019a0 EXTI0_1_IRQHandler
+ 0x00000000080019a0 WWDG_IRQHandler
+ 0x00000000080019a0 FLASH_IRQHandler
+ 0x00000000080019a0 USART1_IRQHandler
+ 0x00000000080019a0 TIM1_BRK_UP_TRG_COM_IRQHandler
*(.rodata)
- *fill* 0x00000000080018e2 0x2
- .rodata 0x00000000080018e4 0x8 /tmp/cchCmUnQ.o
- .rodata 0x00000000080018ec 0x18 /tmp/cc6XVkRI.o
- 0x00000000080018ec AHBPrescTable
- 0x00000000080018fc APBPrescTable
+ *fill* 0x00000000080019a2 0x2
+ .rodata 0x00000000080019a4 0x18 /tmp/ccJ50X5K.o
+ 0x00000000080019a4 AHBPrescTable
+ 0x00000000080019b4 APBPrescTable
*(.rodata*)
*(.glue_7)
- .glue_7 0x0000000008001904 0x0 linker stubs
+ .glue_7 0x00000000080019bc 0x0 linker stubs
*(.glue_7t)
- .glue_7t 0x0000000008001904 0x0 linker stubs
+ .glue_7t 0x00000000080019bc 0x0 linker stubs
*(.source_tarball)
*(.init)
*(.fini)
*(.source_tarball)
- 0x0000000008001904 . = ALIGN (0x4)
- 0x0000000008001904 _etext = .
- 0x0000000008001904 _sidata = _etext
+ 0x00000000080019bc . = ALIGN (0x4)
+ 0x00000000080019bc _etext = .
+ 0x00000000080019bc _sidata = _etext
-.vfp11_veneer 0x0000000008001904 0x0
- .vfp11_veneer 0x0000000008001904 0x0 linker stubs
+.vfp11_veneer 0x00000000080019bc 0x0
+ .vfp11_veneer 0x00000000080019bc 0x0 linker stubs
-.v4_bx 0x0000000008001904 0x0
- .v4_bx 0x0000000008001904 0x0 linker stubs
+.v4_bx 0x00000000080019bc 0x0
+ .v4_bx 0x00000000080019bc 0x0 linker stubs
-.iplt 0x0000000008001904 0x0
- .iplt 0x0000000008001904 0x0 /tmp/cchCmUnQ.o
+.iplt 0x00000000080019bc 0x0
+ .iplt 0x00000000080019bc 0x0 /tmp/ccxtvPlT.o
-.rel.dyn 0x0000000008001904 0x0
- .rel.iplt 0x0000000008001904 0x0 /tmp/cchCmUnQ.o
+.rel.dyn 0x00000000080019bc 0x0
+ .rel.iplt 0x00000000080019bc 0x0 /tmp/ccxtvPlT.o
-.data 0x0000000020000000 0x94 load address 0x0000000008001904
+.data 0x0000000020000000 0x94 load address 0x00000000080019bc
0x0000000020000000 . = ALIGN (0x4)
0x0000000020000000 _sdata = .
0x0000000020000000 _data = .
*(.data)
- .data 0x0000000020000000 0x0 /tmp/cchCmUnQ.o
- .data 0x0000000020000000 0x0 /tmp/cczzmF2c.o
- .data 0x0000000020000000 0x0 /tmp/cc4OHQ7z.o
- .data 0x0000000020000000 0x0 /tmp/cc0OqFzX.o
- .data 0x0000000020000000 0x0 /tmp/ccTaPb5k.o
- .data 0x0000000020000000 0x4 /tmp/cc6XVkRI.o
+ .data 0x0000000020000000 0x0 /tmp/ccxtvPlT.o
+ .data 0x0000000020000000 0x0 /tmp/ccrrpgrR.o
+ .data 0x0000000020000000 0x0 /tmp/ccXNIrIP.o
+ .data 0x0000000020000000 0x0 /tmp/ccy0xC7N.o
+ .data 0x0000000020000000 0x0 /tmp/ccr2qryM.o
+ .data 0x0000000020000000 0x4 /tmp/ccJ50X5K.o
0x0000000020000000 SystemCoreClock
- .data 0x0000000020000004 0x0 /tmp/ccvZIDd7.o
- .data 0x0000000020000004 0x0 /tmp/ccTEVTRv.o
- .data 0x0000000020000004 0x90 /tmp/ccvICuLU.o
+ .data 0x0000000020000004 0x0 /tmp/ccFUXyQJ.o
+ .data 0x0000000020000004 0x0 /tmp/cc8rJnLI.o
+ .data 0x0000000020000004 0x90 /tmp/ccDd2fMH.o
0x0000000020000004 tim3
0x0000000020000008 tim14
0x000000002000000c rtc
@@ -214,43 +214,45 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _edata = .
-.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001998
- .igot.plt 0x0000000020000094 0x0 /tmp/cchCmUnQ.o
+.igot.plt 0x0000000020000094 0x0 load address 0x0000000008001a50
+ .igot.plt 0x0000000020000094 0x0 /tmp/ccxtvPlT.o
-.bss 0x0000000020000094 0x940 load address 0x0000000008001998
+.bss 0x0000000020000094 0x488 load address 0x0000000008001a50
0x0000000020000094 . = ALIGN (0x4)
0x0000000020000094 _sbss = .
0x0000000020000094 _bss = .
*(.bss)
- .bss 0x0000000020000094 0xc /tmp/cchCmUnQ.o
+ .bss 0x0000000020000094 0xc /tmp/ccxtvPlT.o
0x0000000020000094 sys_time_seconds
- .bss 0x00000000200000a0 0x0 /tmp/cczzmF2c.o
- .bss 0x00000000200000a0 0x0 /tmp/cc4OHQ7z.o
- .bss 0x00000000200000a0 0x0 /tmp/cc0OqFzX.o
- .bss 0x00000000200000a0 0x0 /tmp/ccTaPb5k.o
- .bss 0x00000000200000a0 0x0 /tmp/cc6XVkRI.o
- .bss 0x00000000200000a0 0x0 /tmp/ccvZIDd7.o
- .bss 0x00000000200000a0 0x8 /tmp/ccTEVTRv.o
- 0x00000000200000a0 __errno
- 0x00000000200000a4 _impure_ptr
- .bss 0x00000000200000a8 0x0 /tmp/ccvICuLU.o
- .bss 0x00000000200000a8 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .bss 0x00000000200000a8 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .bss 0x00000000200000a8 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .bss 0x00000000200000a0 0x4 /tmp/ccrrpgrR.o
+ 0x00000000200000a0 usart_overruns
+ .bss 0x00000000200000a4 0x1 /tmp/ccXNIrIP.o
+ .bss 0x00000000200000a5 0x0 /tmp/ccy0xC7N.o
+ .bss 0x00000000200000a5 0x0 /tmp/ccr2qryM.o
+ .bss 0x00000000200000a5 0x0 /tmp/ccJ50X5K.o
+ .bss 0x00000000200000a5 0x0 /tmp/ccFUXyQJ.o
+ *fill* 0x00000000200000a5 0x3
+ .bss 0x00000000200000a8 0x8 /tmp/cc8rJnLI.o
+ 0x00000000200000a8 __errno
+ 0x00000000200000ac _impure_ptr
+ .bss 0x00000000200000b0 0x0 /tmp/ccDd2fMH.o
+ .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .bss 0x00000000200000b0 0x0 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
*(.bss.*)
*(COMMON)
- COMMON 0x00000000200000a8 0x20 /tmp/cchCmUnQ.o
- 0x00000000200000a8 leds
- COMMON 0x00000000200000c8 0x800 /tmp/cczzmF2c.o
- 0x00000000200000c8 adc_buf
- COMMON 0x00000000200008c8 0x10c /tmp/cc4OHQ7z.o
- 0x00000000200008c8 usart_tx_buf
- 0x00000000200009d4 . = ALIGN (0x4)
- 0x00000000200009d4 _ebss = .
+ COMMON 0x00000000200000b0 0x20 /tmp/ccxtvPlT.o
+ 0x00000000200000b0 leds
+ COMMON 0x00000000200000d0 0x40 /tmp/ccrrpgrR.o
+ 0x00000000200000d0 adc_buf
+ COMMON 0x0000000020000110 0x40c /tmp/ccXNIrIP.o
+ 0x0000000020000110 usart_tx_buf
+ 0x000000002000051c . = ALIGN (0x4)
+ 0x000000002000051c _ebss = .
[!provide] PROVIDE (end = _ebss)
[!provide] PROVIDE (_end = _ebss)
- 0x00000000200009d4 __exidx_start = .
- 0x00000000200009d4 __exidx_end = .
+ 0x000000002000051c __exidx_start = .
+ 0x000000002000051c __exidx_end = .
.stab
*(.stab)
@@ -272,36 +274,36 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.comment 0x0000000000000000 0x21
*(.comment)
- .comment 0x0000000000000000 0x21 /tmp/cchCmUnQ.o
+ .comment 0x0000000000000000 0x21 /tmp/ccxtvPlT.o
0x22 (size before relaxing)
- .comment 0x0000000000000021 0x22 /tmp/cczzmF2c.o
- .comment 0x0000000000000021 0x22 /tmp/cc4OHQ7z.o
- .comment 0x0000000000000021 0x22 /tmp/cc0OqFzX.o
- .comment 0x0000000000000021 0x22 /tmp/cc6XVkRI.o
- .comment 0x0000000000000021 0x22 /tmp/ccvZIDd7.o
- .comment 0x0000000000000021 0x22 /tmp/ccTEVTRv.o
- .comment 0x0000000000000021 0x22 /tmp/ccvICuLU.o
+ .comment 0x0000000000000021 0x22 /tmp/ccrrpgrR.o
+ .comment 0x0000000000000021 0x22 /tmp/ccXNIrIP.o
+ .comment 0x0000000000000021 0x22 /tmp/ccy0xC7N.o
+ .comment 0x0000000000000021 0x22 /tmp/ccJ50X5K.o
+ .comment 0x0000000000000021 0x22 /tmp/ccFUXyQJ.o
+ .comment 0x0000000000000021 0x22 /tmp/cc8rJnLI.o
+ .comment 0x0000000000000021 0x22 /tmp/ccDd2fMH.o
.ARM.attributes
0x0000000000000000 0x2f
.ARM.attributes
- 0x0000000000000000 0x2b /tmp/cchCmUnQ.o
+ 0x0000000000000000 0x2b /tmp/ccxtvPlT.o
.ARM.attributes
- 0x000000000000002b 0x2b /tmp/cczzmF2c.o
+ 0x000000000000002b 0x2b /tmp/ccrrpgrR.o
.ARM.attributes
- 0x0000000000000056 0x2b /tmp/cc4OHQ7z.o
+ 0x0000000000000056 0x2b /tmp/ccXNIrIP.o
.ARM.attributes
- 0x0000000000000081 0x2b /tmp/cc0OqFzX.o
+ 0x0000000000000081 0x2b /tmp/ccy0xC7N.o
.ARM.attributes
- 0x00000000000000ac 0x21 /tmp/ccTaPb5k.o
+ 0x00000000000000ac 0x21 /tmp/ccr2qryM.o
.ARM.attributes
- 0x00000000000000cd 0x2b /tmp/cc6XVkRI.o
+ 0x00000000000000cd 0x2b /tmp/ccJ50X5K.o
.ARM.attributes
- 0x00000000000000f8 0x2b /tmp/ccvZIDd7.o
+ 0x00000000000000f8 0x2b /tmp/ccFUXyQJ.o
.ARM.attributes
- 0x0000000000000123 0x2b /tmp/ccTEVTRv.o
+ 0x0000000000000123 0x2b /tmp/cc8rJnLI.o
.ARM.attributes
- 0x000000000000014e 0x31 /tmp/ccvICuLU.o
+ 0x000000000000014e 0x31 /tmp/ccDd2fMH.o
.ARM.attributes
0x000000000000017f 0x1e /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.ARM.attributes
@@ -324,23 +326,23 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_aranges 0x0000000000000000 0x180
*(.debug_aranges)
.debug_aranges
- 0x0000000000000000 0x20 /tmp/cchCmUnQ.o
+ 0x0000000000000000 0x20 /tmp/ccxtvPlT.o
.debug_aranges
- 0x0000000000000020 0x20 /tmp/cczzmF2c.o
+ 0x0000000000000020 0x20 /tmp/ccrrpgrR.o
.debug_aranges
- 0x0000000000000040 0x20 /tmp/cc4OHQ7z.o
+ 0x0000000000000040 0x20 /tmp/ccXNIrIP.o
.debug_aranges
- 0x0000000000000060 0x20 /tmp/cc0OqFzX.o
+ 0x0000000000000060 0x20 /tmp/ccy0xC7N.o
.debug_aranges
- 0x0000000000000080 0x28 /tmp/ccTaPb5k.o
+ 0x0000000000000080 0x28 /tmp/ccr2qryM.o
.debug_aranges
- 0x00000000000000a8 0x20 /tmp/cc6XVkRI.o
+ 0x00000000000000a8 0x20 /tmp/ccJ50X5K.o
.debug_aranges
- 0x00000000000000c8 0x20 /tmp/ccvZIDd7.o
+ 0x00000000000000c8 0x20 /tmp/ccFUXyQJ.o
.debug_aranges
- 0x00000000000000e8 0x20 /tmp/ccTEVTRv.o
+ 0x00000000000000e8 0x20 /tmp/cc8rJnLI.o
.debug_aranges
- 0x0000000000000108 0x18 /tmp/ccvICuLU.o
+ 0x0000000000000108 0x18 /tmp/ccDd2fMH.o
.debug_aranges
0x0000000000000120 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
.debug_aranges
@@ -351,87 +353,87 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
.debug_pubnames
*(.debug_pubnames)
-.debug_info 0x0000000000000000 0x5d8a
+.debug_info 0x0000000000000000 0x5eaf
*(.debug_info .gnu.linkonce.wi.*)
- .debug_info 0x0000000000000000 0x136b /tmp/cchCmUnQ.o
- .debug_info 0x000000000000136b 0x105f /tmp/cczzmF2c.o
- .debug_info 0x00000000000023ca 0x1019 /tmp/cc4OHQ7z.o
- .debug_info 0x00000000000033e3 0xcb1 /tmp/cc0OqFzX.o
- .debug_info 0x0000000000004094 0x22 /tmp/ccTaPb5k.o
- .debug_info 0x00000000000040b6 0x263 /tmp/cc6XVkRI.o
- .debug_info 0x0000000000004319 0x795 /tmp/ccvZIDd7.o
- .debug_info 0x0000000000004aae 0x1e9 /tmp/ccTEVTRv.o
- .debug_info 0x0000000000004c97 0x1081 /tmp/ccvICuLU.o
- .debug_info 0x0000000000005d18 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_info 0x0000000000005d3e 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_info 0x0000000000005d64 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_abbrev 0x0000000000000000 0x1204
+ .debug_info 0x0000000000000000 0x12f8 /tmp/ccxtvPlT.o
+ .debug_info 0x00000000000012f8 0x1129 /tmp/ccrrpgrR.o
+ .debug_info 0x0000000000002421 0x10a6 /tmp/ccXNIrIP.o
+ .debug_info 0x00000000000034c7 0xcf2 /tmp/ccy0xC7N.o
+ .debug_info 0x00000000000041b9 0x22 /tmp/ccr2qryM.o
+ .debug_info 0x00000000000041db 0x263 /tmp/ccJ50X5K.o
+ .debug_info 0x000000000000443e 0x795 /tmp/ccFUXyQJ.o
+ .debug_info 0x0000000000004bd3 0x1e9 /tmp/cc8rJnLI.o
+ .debug_info 0x0000000000004dbc 0x1081 /tmp/ccDd2fMH.o
+ .debug_info 0x0000000000005e3d 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_info 0x0000000000005e63 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_info 0x0000000000005e89 0x26 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_abbrev 0x0000000000000000 0x1221
*(.debug_abbrev)
- .debug_abbrev 0x0000000000000000 0x357 /tmp/cchCmUnQ.o
- .debug_abbrev 0x0000000000000357 0x320 /tmp/cczzmF2c.o
- .debug_abbrev 0x0000000000000677 0x319 /tmp/cc4OHQ7z.o
- .debug_abbrev 0x0000000000000990 0x287 /tmp/cc0OqFzX.o
- .debug_abbrev 0x0000000000000c17 0x12 /tmp/ccTaPb5k.o
- .debug_abbrev 0x0000000000000c29 0x113 /tmp/cc6XVkRI.o
- .debug_abbrev 0x0000000000000d3c 0x23c /tmp/ccvZIDd7.o
- .debug_abbrev 0x0000000000000f78 0x117 /tmp/ccTEVTRv.o
- .debug_abbrev 0x000000000000108f 0x139 /tmp/ccvICuLU.o
- .debug_abbrev 0x00000000000011c8 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_abbrev 0x00000000000011dc 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_abbrev 0x00000000000011f0 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_line 0x0000000000000000 0x17b1
+ .debug_abbrev 0x0000000000000000 0x355 /tmp/ccxtvPlT.o
+ .debug_abbrev 0x0000000000000355 0x322 /tmp/ccrrpgrR.o
+ .debug_abbrev 0x0000000000000677 0x32d /tmp/ccXNIrIP.o
+ .debug_abbrev 0x00000000000009a4 0x290 /tmp/ccy0xC7N.o
+ .debug_abbrev 0x0000000000000c34 0x12 /tmp/ccr2qryM.o
+ .debug_abbrev 0x0000000000000c46 0x113 /tmp/ccJ50X5K.o
+ .debug_abbrev 0x0000000000000d59 0x23c /tmp/ccFUXyQJ.o
+ .debug_abbrev 0x0000000000000f95 0x117 /tmp/cc8rJnLI.o
+ .debug_abbrev 0x00000000000010ac 0x139 /tmp/ccDd2fMH.o
+ .debug_abbrev 0x00000000000011e5 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_abbrev 0x00000000000011f9 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_abbrev 0x000000000000120d 0x14 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_line 0x0000000000000000 0x1806
*(.debug_line)
- .debug_line 0x0000000000000000 0x3ec /tmp/cchCmUnQ.o
- .debug_line 0x00000000000003ec 0x33d /tmp/cczzmF2c.o
- .debug_line 0x0000000000000729 0x36e /tmp/cc4OHQ7z.o
- .debug_line 0x0000000000000a97 0x2f9 /tmp/cc0OqFzX.o
- .debug_line 0x0000000000000d90 0x77 /tmp/ccTaPb5k.o
- .debug_line 0x0000000000000e07 0x1ab /tmp/cc6XVkRI.o
- .debug_line 0x0000000000000fb2 0x466 /tmp/ccvZIDd7.o
- .debug_line 0x0000000000001418 0xf4 /tmp/ccTEVTRv.o
- .debug_line 0x000000000000150c 0x148 /tmp/ccvICuLU.o
- .debug_line 0x0000000000001654 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_line 0x00000000000016ca 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_line 0x0000000000001747 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
-
-.debug_frame 0x0000000000000000 0x848
+ .debug_line 0x0000000000000000 0x3cb /tmp/ccxtvPlT.o
+ .debug_line 0x00000000000003cb 0x363 /tmp/ccrrpgrR.o
+ .debug_line 0x000000000000072e 0x3b2 /tmp/ccXNIrIP.o
+ .debug_line 0x0000000000000ae0 0x305 /tmp/ccy0xC7N.o
+ .debug_line 0x0000000000000de5 0x77 /tmp/ccr2qryM.o
+ .debug_line 0x0000000000000e5c 0x1ab /tmp/ccJ50X5K.o
+ .debug_line 0x0000000000001007 0x466 /tmp/ccFUXyQJ.o
+ .debug_line 0x000000000000146d 0xf4 /tmp/cc8rJnLI.o
+ .debug_line 0x0000000000001561 0x148 /tmp/ccDd2fMH.o
+ .debug_line 0x00000000000016a9 0x76 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_line 0x000000000000171f 0x7d /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_line 0x000000000000179c 0x6a /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+
+.debug_frame 0x0000000000000000 0x888
*(.debug_frame)
- .debug_frame 0x0000000000000000 0x168 /tmp/cchCmUnQ.o
- .debug_frame 0x0000000000000168 0xe8 /tmp/cczzmF2c.o
- .debug_frame 0x0000000000000250 0x128 /tmp/cc4OHQ7z.o
- .debug_frame 0x0000000000000378 0xb0 /tmp/cc0OqFzX.o
- .debug_frame 0x0000000000000428 0x4c /tmp/cc6XVkRI.o
- .debug_frame 0x0000000000000474 0x308 /tmp/ccvZIDd7.o
- .debug_frame 0x000000000000077c 0x8c /tmp/ccTEVTRv.o
- .debug_frame 0x0000000000000808 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
- .debug_frame 0x0000000000000828 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
-
-.debug_str 0x0000000000000000 0x12b2
+ .debug_frame 0x0000000000000000 0x164 /tmp/ccxtvPlT.o
+ .debug_frame 0x0000000000000164 0xec /tmp/ccrrpgrR.o
+ .debug_frame 0x0000000000000250 0x168 /tmp/ccXNIrIP.o
+ .debug_frame 0x00000000000003b8 0xb0 /tmp/ccy0xC7N.o
+ .debug_frame 0x0000000000000468 0x4c /tmp/ccJ50X5K.o
+ .debug_frame 0x00000000000004b4 0x308 /tmp/ccFUXyQJ.o
+ .debug_frame 0x00000000000007bc 0x8c /tmp/cc8rJnLI.o
+ .debug_frame 0x0000000000000848 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame 0x0000000000000868 0x20 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+
+.debug_str 0x0000000000000000 0x12fd
*(.debug_str)
- .debug_str 0x0000000000000000 0x965 /tmp/cchCmUnQ.o
- 0xa11 (size before relaxing)
- .debug_str 0x0000000000000965 0xdf /tmp/cczzmF2c.o
- 0x8fc (size before relaxing)
- .debug_str 0x0000000000000a44 0xa7 /tmp/cc4OHQ7z.o
- 0x904 (size before relaxing)
- .debug_str 0x0000000000000aeb 0xa2 /tmp/cc0OqFzX.o
- 0x658 (size before relaxing)
- .debug_str 0x0000000000000b8d 0x22 /tmp/ccTaPb5k.o
+ .debug_str 0x0000000000000000 0x952 /tmp/ccxtvPlT.o
+ 0x9f5 (size before relaxing)
+ .debug_str 0x0000000000000952 0x101 /tmp/ccrrpgrR.o
+ 0x95f (size before relaxing)
+ .debug_str 0x0000000000000a53 0xdc /tmp/ccXNIrIP.o
+ 0x939 (size before relaxing)
+ .debug_str 0x0000000000000b2f 0xa9 /tmp/ccy0xC7N.o
+ 0x65f (size before relaxing)
+ .debug_str 0x0000000000000bd8 0x22 /tmp/ccr2qryM.o
0x57 (size before relaxing)
- .debug_str 0x0000000000000baf 0x53 /tmp/cc6XVkRI.o
+ .debug_str 0x0000000000000bfa 0x53 /tmp/ccJ50X5K.o
0x219 (size before relaxing)
- .debug_str 0x0000000000000c02 0x3ae /tmp/ccvZIDd7.o
+ .debug_str 0x0000000000000c4d 0x3ae /tmp/ccFUXyQJ.o
0x5bf (size before relaxing)
- .debug_str 0x0000000000000fb0 0x39 /tmp/ccTEVTRv.o
+ .debug_str 0x0000000000000ffb 0x39 /tmp/cc8rJnLI.o
0x1b7 (size before relaxing)
- .debug_str 0x0000000000000fe9 0x227 /tmp/ccvICuLU.o
+ .debug_str 0x0000000000001034 0x227 /tmp/ccDd2fMH.o
0x5ca (size before relaxing)
- .debug_str 0x0000000000001210 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_str 0x000000000000125b 0xa2 /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
0xae (size before relaxing)
- .debug_str 0x00000000000012b2 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
- .debug_str 0x00000000000012b2 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ .debug_str 0x00000000000012fd 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_divsi3.o)
+ .debug_str 0x00000000000012fd 0xae /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
.debug_loc
*(.debug_loc)
@@ -453,5 +455,5 @@ LOAD /usr/lib/gcc/arm-none-eabi/9.2.0/thumb/v6-m/nofp/libgcc.a
OUTPUT(main.elf elf32-littlearm)
.debug_ranges 0x0000000000000000 0x38
- .debug_ranges 0x0000000000000000 0x18 /tmp/cc0OqFzX.o
- .debug_ranges 0x0000000000000018 0x20 /tmp/ccTaPb5k.o
+ .debug_ranges 0x0000000000000000 0x18 /tmp/ccy0xC7N.o
+ .debug_ranges 0x0000000000000018 0x20 /tmp/ccr2qryM.o
diff --git a/gm_platform/fw/serial.c b/gm_platform/fw/serial.c
index ae639c0..468c523 100644
--- a/gm_platform/fw/serial.c
+++ b/gm_platform/fw/serial.c
@@ -31,7 +31,9 @@
volatile struct dma_tx_buf usart_tx_buf;
-static void usart_schedule_dma();
+static void usart_schedule_dma(void);
+int usart_putc_nonblocking(char c);
+int usart_putc(char c);
void usart_dma_init() {
usart_tx_buf.xfr_start = -1,
@@ -39,7 +41,7 @@ void usart_dma_init() {
usart_tx_buf.wr_pos = 0,
/* Configure DMA 1 Channel 2 to handle uart transmission */
- DMA1_Channel2->CPAR = (unsigned int)&(USART1->TDR);
+ DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR);
DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos)
| DMA_CCR_DIR
| (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
@@ -47,6 +49,13 @@ void usart_dma_init() {
| DMA_CCR_MINC
| DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
+ DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR);
+ DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos)
+ | (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */
+ | (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */
+ | DMA_CCR_PINC
+ | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */
+
/* triggered on transfer completion. We use this to process the ADC data */
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5);
@@ -61,8 +70,13 @@ void usart_dma_init() {
/* other interrupts clear */
| USART_CR1_TE
| USART_CR1_RE;
- /* Set divider for 1MBd @48MHz system clock. */
- USART1->BRR = 48;
+ /* Set divider for 115.2kBd @48MHz system clock. */
+ //USART1->BRR = 417;
+
+ //USART1->BRR = 48; /* 1MBd */
+ USART1->BRR = 96; /* 500kBd */
+ USART1->BRR = 192; /* 250kBd */
+ //USART1->BRR = 208; /* 230400 */
USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV;
@@ -112,13 +126,19 @@ int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) {
return 0;
}
-void usart_putc(char c) {
+int usart_putc(char c) {
/* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */
while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) {
/* idle */
}
+ return 0;
}
+int usart_putc_nonblocking(char c) {
+ return usart_dma_fifo_push(&usart_tx_buf, c);
+}
+
+
void DMA1_Channel2_3_IRQHandler(void) {
/* Transfer complete */
DMA1->IFCR |= DMA_IFCR_CTCIF2;
@@ -130,10 +150,28 @@ void DMA1_Channel2_3_IRQHandler(void) {
void usart_send_packet(const uint8_t *data, size_t len) {
/* ignore return value as putf is blocking and always succeeds */
- (void)cobs_encode_usart((char *)data, len);
+ (void)cobs_encode_usart(usart_putc, (char *)data, len);
/* If the DMA stream is idle right now, schedule a transfer */
if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
usart_schedule_dma();
}
+int usart_send_packet_nonblocking(const uint8_t *data, size_t len) {
+ /* ignore return value as putf is blocking and always succeeds */
+ /* FIXME DEBUG */
+ //int rc = cobs_encode_usart(usart_putc_nonblocking, (char *)data, len);
+ //if (rc)
+ // return rc;
+ /* END */
+ static uint8_t x = 0;
+
+ for (size_t i=0; i<351; i++)
+ usart_putc_nonblocking(x++);
+
+ /* If the DMA stream is idle right now, schedule a transfer */
+ if (!(DMA1_Channel2->CCR & DMA_CCR_EN))
+ usart_schedule_dma();
+ return 0;
+}
+
diff --git a/gm_platform/fw/serial.h b/gm_platform/fw/serial.h
index 55eac9e..c10393a 100644
--- a/gm_platform/fw/serial.h
+++ b/gm_platform/fw/serial.h
@@ -31,14 +31,15 @@ struct dma_tx_buf {
size_t xfr_start; /* Start index of running DMA transfer */
size_t xfr_end; /* End index of running DMA transfer plus one */
size_t wr_pos; /* Next index to be written */
- uint8_t data[256];
+ uint8_t data[512];
+ size_t packet_starts[5];
};
extern volatile struct dma_tx_buf usart_tx_buf;
void usart_dma_init(void);
int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c);
-void usart_putc(char c);
void usart_send_packet(const uint8_t *data, size_t len);
+int usart_send_packet_nonblocking(const uint8_t *data, size_t len);
#endif // __SERIAL_H__
diff --git a/gm_platform/fw/test.py b/gm_platform/fw/test.py
new file mode 100644
index 0000000..cb243a5
--- /dev/null
+++ b/gm_platform/fw/test.py
@@ -0,0 +1,41 @@
+#!/usr/bin/env python3
+
+import serial
+import time
+
+#ser = serial.Serial('/dev/serial/by-id/usb-1a86_USB2.0-Serial-if00-port0', 230400)
+ser = serial.Serial('/dev/serial/by-id/usb-Silicon_Labs_CP2102_USB_to_UART_Bridge_Controller_0001-if00-port0', 250000)
+#while True:
+# ser.write(bytes(range(256)))
+start = time.time()
+
+last_val = None
+run = 0
+total_errors = 0
+rx_bytes = 0
+last_print = time.time()
+while True:
+ bytes = ser.read(256)
+ for byte in bytes:
+ if last_val is not None and byte != (last_val + 1) % 256:
+ if run > 0:
+ print(f'{time.time()-start:>8.3f} {run} {last_val:02x} {byte:02x}')
+ run = 0
+ total_errors += 1
+ else:
+ run += 1
+ rx_bytes += 1
+
+ if time.time() - last_print > 5:
+ last_print = time.time()
+ print(f'{time.time()-start:>8.3f} {run} [all good] err={total_errors}@rx={rx_bytes}B',
+ f'(rate 1/{rx_bytes/total_errors:.5g})' if total_errors > 0 else 'rate unknown')
+ last_val = byte
+
+#while True:
+# data = ser.read_until(b'\0')
+# print(f'{time.time()-start:>8.3f} {len(data)}')
+
+# while True:
+# data = ser.read(256)
+# print('YES' if b'\0' in data else 'NO ', data)
diff --git a/gm_platform/platform/platform.sch b/gm_platform/platform/platform.sch
index 8c0fc7d..8483ed7 100644
--- a/gm_platform/platform/platform.sch
+++ b/gm_platform/platform/platform.sch
@@ -3021,5 +3021,5 @@ F 5 "SDCIT/8GB" H 12700 7050 50 0001 C CNN "Reichelt"
1 0 0 -1
$EndComp
Text Notes 850 11050 0 50 ~ 0
-TO-DO\n* Add adc buffer op amp\n* join input resistors, adjust divider\n* earth secondary side\n* add slots for large isolation barrier\n* add slots for small isolation barrier\n* fixup/remove ocxo footprint\n* fixup converter footprint, use smaller part? use 5V one and power raspi?\n* remove uart isolation?\n* fix fuse rating\n* remove one fuse\n* remove lid switches?\n* fixup incorrect bom items
+TO-DO\n* Add adc buffer op amp\n* join input resistors, adjust divider\n* earth secondary side\n* add slots for large isolation barrier\n* add slots for small isolation barrier\n* fixup/remove ocxo footprint\n* fixup converter footprint, use smaller part? use 5V one and power raspi?\n* remove uart isolation?\n* fix fuse rating\n* remove one fuse\n* remove lid switches?\n* fixup incorrect bom items\n* CH340 V3 cap -> 100n\n* replace CH340 w/ silabs cp2102\n* replace optocoupler pullups w/ 350R
$EndSCHEMATC
generated by cgit (git 2.34.1) at 2024-11-21 17:28:10 +0000