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-rw-r--r--gm_platform/fw/adc.c15
-rw-r--r--gm_platform/fw/adc.h4
-rw-r--r--gm_platform/fw/main.c57
3 files changed, 42 insertions, 34 deletions
diff --git a/gm_platform/fw/adc.c b/gm_platform/fw/adc.c
index ab9d6b5..7e1b8cc 100644
--- a/gm_platform/fw/adc.c
+++ b/gm_platform/fw/adc.c
@@ -32,12 +32,11 @@ static uint16_t current_seq = 0;
static int current_buf = 0;
static void adc_dma_init(void);
-static void adc_timer_init(int psc, int ivl);
static void adc_dma_launch(void);
/* Mode that can be used for debugging */
-void adc_configure_scope_mode(int sampling_interval_ns) {
+void adc_init() {
adc_dma_init();
/* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */
@@ -56,14 +55,6 @@ void adc_configure_scope_mode(int sampling_interval_ns) {
/* Enable conversion */
ADC1->CR |= ADC_CR_ADEN;
ADC1->CR |= ADC_CR_ADSTART;
-
- /* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us.
- Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this
- would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */
- int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6;
- if (cycles > 0xffff)
- cycles = 0xffff;
- adc_timer_init(12/*250ns/tick*/, cycles);
}
static void adc_dma_init() {
@@ -91,8 +82,8 @@ void adc_dma_launch() {
DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */
}
-static void adc_timer_init(int psc, int ivl) {
- TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */
+void adc_timer_init(int psc, int ivl) {
+ TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal */
TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */
TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */
TIM1->CCR4 = 1; /* Trigger at start of timer cycle */
diff --git a/gm_platform/fw/adc.h b/gm_platform/fw/adc.h
index 0818169..cba18d1 100644
--- a/gm_platform/fw/adc.h
+++ b/gm_platform/fw/adc.h
@@ -20,7 +20,7 @@
#include "global.h"
-void adc_init(void);
-void adc_configure_scope_mode(int sampling_interval_ns);
+void adc_init();
+void adc_timer_init(int psc, int ivl);
#endif/*__ADC_H__*/
diff --git a/gm_platform/fw/main.c b/gm_platform/fw/main.c
index 811b27f..34c838b 100644
--- a/gm_platform/fw/main.c
+++ b/gm_platform/fw/main.c
@@ -25,6 +25,7 @@ volatile union leds leds;
volatile int32_t gps_1pps_period_sysclk = -1;
int main(void) {
+ /* Get GPIOA and SPI1 up to flash status LEDs */
RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
@@ -60,9 +61,11 @@ int main(void) {
SPI1->CR1 |= SPI_CR1_SPE;
*((volatile uint8_t*)&(SPI1->DR)) = 0xff;
+ /* Wait for OCXO to settle */
for (int i=0; i<1000000; i++)
;
+ /* Switch clock to PLL based on OCXO input */
RCC->CR |= RCC_CR_HSEBYP;
RCC->CR |= RCC_CR_HSEON;
RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk;
@@ -73,11 +76,13 @@ int main(void) {
while (!(RCC->CR&RCC_CR_PLLRDY));
RCC->CFGR |= (2<<RCC_CFGR_SW_Pos);
SystemCoreClockUpdate();
+
+ /* Start systick */
SysTick_Config(SystemCoreClock/10); /* 100ms interval */
NVIC_EnableIRQ(SysTick_IRQn);
NVIC_SetPriority(SysTick_IRQn, 3<<5);
- /* Turn on lots of neat things */
+ /* Turn on rest of periphery */
RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN | RCC_AHBENR_CRCEN;
RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_DBGMCUEN |\
RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN;
@@ -88,17 +93,17 @@ int main(void) {
GPIOB->AFR[0] = (0<<GPIO_AFRL_AFRL1_Pos);
GPIOB->PUPDR = 2<<GPIO_PUPDR_PUPDR1_Pos;
+ /* Configure TIM16 for LED update via SPI */
TIM16->CR2 = 0;
-
TIM16->DIER = TIM_DIER_UIE | TIM_DIER_CC1IE;
TIM16->CCMR1 = 0;
TIM16->CCR1 = 32;
TIM16->PSC = 48-1; /* 1us */
TIM16->ARR = 1000-1; /* 1ms */
TIM16->CR1 = TIM_CR1_CEN;
-
NVIC_EnableIRQ(TIM16_IRQn);
+ /* Configure TIM14 for GPS 1pps input capture */
TIM14->CCMR1 = (1<<TIM_CCMR1_CC1S_Pos) | (3<<TIM_CCMR1_IC1F_Pos);
TIM14->CCER = TIM_CCER_CC1E;
TIM14->PSC = 1;
@@ -106,10 +111,10 @@ int main(void) {
TIM14->DIER = TIM_DIER_CC1IE | TIM_DIER_UIE;
TIM14->EGR = TIM_EGR_UG;
TIM14->CR1 |= TIM_CR1_CEN;
-
NVIC_EnableIRQ(TIM14_IRQn);
- adc_configure_scope_mode(1000000);
+ adc_init(1000000);
+ adc_timer_init(243, 200); /* 19.44 MHz / 243 -> 200 kHz; /200 -> 1 kHz */
usart_dma_init();
@@ -129,7 +134,22 @@ void TIM14_IRQHandler(void) {
if (sr & TIM_SR_CC1OF) {
TIM14->SR &= ~(TIM_SR_CC1IF | TIM_SR_CC1OF);
tim14_sr_cc1of();
- } else if (sr & TIM_SR_CC1IF) { /* CC1 event (GPS 1pps input) */
+
+ }
+ if (sr & TIM_SR_UIF) {
+ TIM14->SR &= ~TIM_SR_UIF;
+ if (in_sync) {
+ gps_1pps_period += update_inc;
+ if (gps_1pps_period > 30000000) { /* Signal out of range */
+ in_sync = false;
+ gps_1pps_period_sysclk = -1;
+ gps_1pps_period = (uint32_t)-1;
+ }
+ }
+ update_inc = 0x10000;
+ }
+
+ if (sr & TIM_SR_CC1IF) { /* CC1 event (GPS 1pps input) */
/* Don't reset update event: If update event arrives while CC1 event is being processed leave UIF set to process
* update event immediately after return from ISR. */
uint16_t ccr = TIM14->CCR1;
@@ -140,9 +160,17 @@ void TIM14_IRQHandler(void) {
gps_1pps_period_sysclk = -1;
gps_1pps_period = (uint32_t)-1;
} else {
- gps_1pps_period_sysclk = new_period;
- gps_1pps_period = 0;
- update_inc = 0x10000 - ccr; /* remaining cycles in this period */
+ if ((sr & TIM_SR_UIF) /* we processed an update event in this ISR */
+ && (ccr > 0xc000) /* and the capture happened late in the cycle */
+ ) {
+ gps_1pps_period_sysclk = new_period - 0x10000;
+ update_inc = 0x10000;
+ gps_1pps_period = 0x10000 - ccr;
+ } else {
+ gps_1pps_period_sysclk = new_period;
+ update_inc = 0x10000 - ccr; /* remaining cycles in this period */
+ gps_1pps_period = 0;
+ }
leds.pps = 200; /* ms */
}
} else {
@@ -151,17 +179,6 @@ void TIM14_IRQHandler(void) {
in_sync = true;
}
- } else { /* update */
- TIM14->SR &= ~TIM_SR_UIF;
- if (in_sync) {
- gps_1pps_period += update_inc;
- if (gps_1pps_period > 30000000) { /* Signal out of range */
- in_sync = false;
- gps_1pps_period_sysclk = -1;
- gps_1pps_period = (uint32_t)-1;
- }
- }
- update_inc = 0x10000;
}
}
generated by cgit (git 2.34.1) at 2024-11-11 17:19:13 +0000