diff options
Diffstat (limited to 'gm_platform/fw/main.lst')
| -rw-r--r-- | gm_platform/fw/main.lst | 4459 |
1 files changed, 4459 insertions, 0 deletions
diff --git a/gm_platform/fw/main.lst b/gm_platform/fw/main.lst new file mode 100644 index 0000000..5be6e7e --- /dev/null +++ b/gm_platform/fw/main.lst @@ -0,0 +1,4459 @@ + +main.elf: file format elf32-littlearm + +SYMBOL TABLE: +08000000 l d .isr_vector 00000000 .isr_vector +080000c0 l d .text 00000000 .text +20000000 l d .data 00000000 .data +20000094 l d .bss 00000000 .bss +00000000 l d .comment 00000000 .comment +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l df *ABS* 00000000 /tmp/ccTaPb5k.o +080018a4 l .text 00000000 LoopCopyDataInit +0800189c l .text 00000000 CopyDataInit +080018b8 l .text 00000000 LoopFillZerobss +080018b2 l .text 00000000 FillZerobss +080018c6 l .text 00000000 LoopForever +080018e0 l .text 00000000 Infinite_Loop +00000000 l df *ABS* 00000000 main.c +080000c0 l F .text 0000002c NVIC_EnableIRQ +080000ec l F .text 000000dc NVIC_SetPriority +080001c8 l F .text 00000048 SysTick_Config +20000098 l .bss 00000004 leds_update_counter.5785 +2000009c l .bss 00000004 n.5808 +00000000 l df *ABS* 00000000 adc.c +08000514 l F .text 0000002c NVIC_EnableIRQ +08000540 l F .text 000000dc NVIC_SetPriority +080006c4 l F .text 00000060 adc_dma_init +08000724 l F .text 00000064 adc_timer_init +08000788 l F .text 0000000a gdb_dump +00000000 l df *ABS* 00000000 serial.c +080007b0 l F .text 0000002c NVIC_EnableIRQ +080007dc l F .text 00000030 NVIC_DisableIRQ +0800080c l F .text 000000dc NVIC_SetPriority +08000960 l F .text 00000074 usart_schedule_dma +00000000 l df *ABS* 00000000 cobs.c +00000000 l df *ABS* 00000000 system_stm32f0xx.c +00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c +08000f90 l F .text 0000001c LL_RCC_HSE_EnableBypass +08000fac l F .text 00000020 LL_RCC_HSE_DisableBypass +08000fcc l F .text 0000001c LL_RCC_HSE_Enable +08000fe8 l F .text 00000028 LL_RCC_HSE_IsReady +08001010 l F .text 0000001c LL_RCC_HSI_Enable +0800102c l F .text 00000020 LL_RCC_HSI_IsReady +0800104c l F .text 00000028 LL_RCC_SetSysClkSource +08001074 l F .text 00000018 LL_RCC_GetSysClkSource +0800108c l F .text 00000028 LL_RCC_SetAHBPrescaler +080010b4 l F .text 0000002c LL_RCC_SetAPB1Prescaler +080010e0 l F .text 0000001c LL_RCC_PLL_Enable +080010fc l F .text 00000028 LL_RCC_PLL_IsReady +08001124 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS +08001170 l F .text 00000034 LL_InitTick +080011a4 l F .text 00000028 LL_FLASH_SetLatency +080011cc l F .text 00000018 LL_FLASH_GetLatency +08001426 l F .text 00000026 UTILS_PLL_IsBusy +080013ec l F .text 0000003a UTILS_GetPLLOutputFrequency +0800144c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem +08001390 l F .text 0000005c UTILS_SetFlashLatency +00000000 l df *ABS* 00000000 base.c +00000000 l df *ABS* 00000000 cmsis_exports.c +00000000 l df *ABS* 00000000 _udivsi3.o +080015a8 l .text 00000000 .udivsi3_skip_div0_test +00000000 l df *ABS* 00000000 _divsi3.o +080016bc l .text 00000000 .divsi3_skip_div0_test +00000000 l df *ABS* 00000000 _dvmd_tls.o +080018fc g O .text 00000008 APBPrescTable +20000044 g O .data 00000004 tim17 +2000007c g O .data 00000004 gpioc +20000088 g O .data 00000004 scb +08001202 g F .text 00000046 LL_mDelay +08000a9c g F .text 00000030 usart_send_packet +080018e0 w F .text 00000002 TIM1_CC_IRQHandler +08001524 g F .text 0000000a __sinit +080004bc g F .text 00000004 HardFault_Handler +2000006c g O .data 00000004 rcc +080004d8 g F .text 0000003c SysTick_Handler +08001904 g .text 00000000 _sidata +080004cc g F .text 0000000c PendSV_Handler +20000020 g O .data 00000004 syscfg +080004b0 g F .text 0000000c NMI_Handler +200009d4 g .bss 00000000 __exidx_end +08001264 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI +080018e0 w F .text 00000002 I2C1_IRQHandler +08001248 g F .text 0000001c LL_SetSystemCoreClock +200000a0 g O .bss 00000004 __errno +20000008 g O .data 00000004 tim14 +20000048 g O .data 00000004 dbgmcu +2000003c g O .data 00000004 usart1 +08001904 g .text 00000000 _etext +20000094 g .bss 00000000 _sbss +08000c32 g F .text 000000d6 cobs_decode +200008c8 g O .bss 0000010c usart_tx_buf +20000094 g O .bss 00000004 sys_time_seconds +20000000 g O .data 00000004 SystemCoreClock +2000001c g O .data 00000004 pwr +080015a8 g F .text 0000010a .hidden __udivsi3 +08001592 g F .text 00000014 __assert_func +20000000 g .data 00000000 _sdata +080003c8 g F .text 0000002c SPI1_IRQHandler +20000060 g O .data 00000004 dma1_channel5 +20000058 g O .data 00000004 dma1_channel3 +200009d4 g .bss 00000000 __exidx_start +080011e4 g F .text 0000001e LL_Init1msTick +20000054 g O .data 00000004 dma1_channel2 +080018e0 w F .text 00000002 EXTI2_3_IRQHandler +080018e0 w F .text 00000002 ADC1_IRQHandler +08000d24 g F .text 000000e2 cobs_decode_incremental +2000004c g O .data 00000004 dma1 +080018e0 w F .text 00000002 TIM17_IRQHandler +080018e0 w F .text 00000002 RTC_IRQHandler +200009d4 g .bss 00000000 _ebss +2000002c g O .data 00000004 adc1_common +08001894 w F .text 00000034 Reset_Handler +20000070 g O .data 00000004 crc +20000024 g O .data 00000004 exti +08000210 g F .text 0000000a update_leds +20000028 g O .data 00000004 adc1 +080016bc g F .text 00000000 .hidden __aeabi_idiv +08000acc g F .text 000000c6 cobs_encode +200000a8 g O .bss 00000020 leds +20000074 g O .data 00000004 gpioa +080003f4 g F .text 000000bc TIM16_IRQHandler +080018e0 w F .text 00000002 TIM3_IRQHandler +080018e0 w F .text 00000002 EXTI4_15_IRQHandler +080018e0 w F .text 00000002 RCC_IRQHandler +20000094 g .bss 00000000 _bss +08000792 g F .text 0000001e DMA1_Channel1_IRQHandler +080018e0 g .text 00000002 Default_Handler +080018ec g O .text 00000010 AHBPrescTable +08000b92 g F .text 000000a0 cobs_encode_usart +20000010 g O .data 00000004 wwdg +080018e0 w F .text 00000002 TIM14_IRQHandler +080018e0 w F .text 00000002 DMA1_Channel4_5_IRQHandler +20000030 g O .data 00000004 adc +08000a2c g F .text 00000030 usart_putc +080018e0 w F .text 00000002 EXTI0_1_IRQHandler +08001890 w F .text 00000002 .hidden __aeabi_ldiv0 +20000004 g O .data 00000004 tim3 +2000000c g O .data 00000004 rtc +080008e8 g F .text 00000078 usart_dma_init +0800152e g F .text 0000003a memset +0800021a g F .text 000001ae main +20000064 g O .data 00000004 flash +080015a8 g F .text 00000000 .hidden __aeabi_uidiv +080004c0 g F .text 0000000c SVC_Handler +20000018 g O .data 00000004 i2c1 +20000050 g O .data 00000004 dma1_channel1 +080016bc g F .text 000001cc .hidden __divsi3 +20000090 g O .data 00000004 nvic +08000e1c g F .text 00000088 SystemInit +200000a4 g O .bss 00000004 _impure_ptr +080018e0 w F .text 00000002 WWDG_IRQHandler +20000000 g .data 00000000 _data +20000084 g O .data 00000004 gpiof +08000a5c g F .text 00000040 DMA1_Channel2_3_IRQHandler +200000c8 g O .bss 00000800 adc_buf +20000080 g O .data 00000004 gpiod +20001000 g *ABS* 00000000 _estack +080016b4 g F .text 00000008 .hidden __aeabi_uidivmod +20000068 g O .data 00000004 ob +20000094 g .data 00000000 _edata +20000038 g O .data 00000004 spi1 +080009d4 g F .text 00000058 usart_dma_fifo_push +2000005c g O .data 00000004 dma1_channel4 +08000000 g O .isr_vector 00000000 g_pfnVectors +08000ea4 g F .text 000000ec SystemCoreClockUpdate +080012f0 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE +08001890 w F .text 00000002 .hidden __aeabi_idiv0 +20000014 g O .data 00000004 iwdg +080018e0 w F .text 00000002 FLASH_IRQHandler +08000d08 g F .text 0000001c cobs_decode_incremental_initialize +080018e0 w F .text 00000002 USART1_IRQHandler +0800061c g F .text 000000a8 adc_configure_scope_mode +08001568 g F .text 0000002a strlen +080018e0 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler +20000078 g O .data 00000004 gpiob +20000034 g O .data 00000004 tim1 +2000008c g O .data 00000004 systick +08001888 g F .text 00000008 .hidden __aeabi_idivmod +20000040 g O .data 00000004 tim16 + + + +Disassembly of section .text: + +080000c0 <NVIC_EnableIRQ>: + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80000c0: b580 push {r7, lr} + 80000c2: b082 sub sp, #8 + 80000c4: af00 add r7, sp, #0 + 80000c6: 0002 movs r2, r0 + 80000c8: 1dfb adds r3, r7, #7 + 80000ca: 701a strb r2, [r3, #0] + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 80000cc: 1dfb adds r3, r7, #7 + 80000ce: 781b ldrb r3, [r3, #0] + 80000d0: 001a movs r2, r3 + 80000d2: 231f movs r3, #31 + 80000d4: 401a ands r2, r3 + 80000d6: 4b04 ldr r3, [pc, #16] ; (80000e8 <NVIC_EnableIRQ+0x28>) + 80000d8: 2101 movs r1, #1 + 80000da: 4091 lsls r1, r2 + 80000dc: 000a movs r2, r1 + 80000de: 601a str r2, [r3, #0] +} + 80000e0: 46c0 nop ; (mov r8, r8) + 80000e2: 46bd mov sp, r7 + 80000e4: b002 add sp, #8 + 80000e6: bd80 pop {r7, pc} + 80000e8: e000e100 .word 0xe000e100 + +080000ec <NVIC_SetPriority>: + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 80000ec: b590 push {r4, r7, lr} + 80000ee: b083 sub sp, #12 + 80000f0: af00 add r7, sp, #0 + 80000f2: 0002 movs r2, r0 + 80000f4: 6039 str r1, [r7, #0] + 80000f6: 1dfb adds r3, r7, #7 + 80000f8: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) < 0) + 80000fa: 1dfb adds r3, r7, #7 + 80000fc: 781b ldrb r3, [r3, #0] + 80000fe: 2b7f cmp r3, #127 ; 0x7f + 8000100: d932 bls.n 8000168 <NVIC_SetPriority+0x7c> + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000102: 4a2f ldr r2, [pc, #188] ; (80001c0 <NVIC_SetPriority+0xd4>) + 8000104: 1dfb adds r3, r7, #7 + 8000106: 781b ldrb r3, [r3, #0] + 8000108: 0019 movs r1, r3 + 800010a: 230f movs r3, #15 + 800010c: 400b ands r3, r1 + 800010e: 3b08 subs r3, #8 + 8000110: 089b lsrs r3, r3, #2 + 8000112: 3306 adds r3, #6 + 8000114: 009b lsls r3, r3, #2 + 8000116: 18d3 adds r3, r2, r3 + 8000118: 3304 adds r3, #4 + 800011a: 681b ldr r3, [r3, #0] + 800011c: 1dfa adds r2, r7, #7 + 800011e: 7812 ldrb r2, [r2, #0] + 8000120: 0011 movs r1, r2 + 8000122: 2203 movs r2, #3 + 8000124: 400a ands r2, r1 + 8000126: 00d2 lsls r2, r2, #3 + 8000128: 21ff movs r1, #255 ; 0xff + 800012a: 4091 lsls r1, r2 + 800012c: 000a movs r2, r1 + 800012e: 43d2 mvns r2, r2 + 8000130: 401a ands r2, r3 + 8000132: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000134: 683b ldr r3, [r7, #0] + 8000136: 019b lsls r3, r3, #6 + 8000138: 22ff movs r2, #255 ; 0xff + 800013a: 401a ands r2, r3 + 800013c: 1dfb adds r3, r7, #7 + 800013e: 781b ldrb r3, [r3, #0] + 8000140: 0018 movs r0, r3 + 8000142: 2303 movs r3, #3 + 8000144: 4003 ands r3, r0 + 8000146: 00db lsls r3, r3, #3 + 8000148: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800014a: 481d ldr r0, [pc, #116] ; (80001c0 <NVIC_SetPriority+0xd4>) + 800014c: 1dfb adds r3, r7, #7 + 800014e: 781b ldrb r3, [r3, #0] + 8000150: 001c movs r4, r3 + 8000152: 230f movs r3, #15 + 8000154: 4023 ands r3, r4 + 8000156: 3b08 subs r3, #8 + 8000158: 089b lsrs r3, r3, #2 + 800015a: 430a orrs r2, r1 + 800015c: 3306 adds r3, #6 + 800015e: 009b lsls r3, r3, #2 + 8000160: 18c3 adds r3, r0, r3 + 8000162: 3304 adds r3, #4 + 8000164: 601a str r2, [r3, #0] + else + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + 8000166: e027 b.n 80001b8 <NVIC_SetPriority+0xcc> + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000168: 4a16 ldr r2, [pc, #88] ; (80001c4 <NVIC_SetPriority+0xd8>) + 800016a: 1dfb adds r3, r7, #7 + 800016c: 781b ldrb r3, [r3, #0] + 800016e: b25b sxtb r3, r3 + 8000170: 089b lsrs r3, r3, #2 + 8000172: 33c0 adds r3, #192 ; 0xc0 + 8000174: 009b lsls r3, r3, #2 + 8000176: 589b ldr r3, [r3, r2] + 8000178: 1dfa adds r2, r7, #7 + 800017a: 7812 ldrb r2, [r2, #0] + 800017c: 0011 movs r1, r2 + 800017e: 2203 movs r2, #3 + 8000180: 400a ands r2, r1 + 8000182: 00d2 lsls r2, r2, #3 + 8000184: 21ff movs r1, #255 ; 0xff + 8000186: 4091 lsls r1, r2 + 8000188: 000a movs r2, r1 + 800018a: 43d2 mvns r2, r2 + 800018c: 401a ands r2, r3 + 800018e: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000190: 683b ldr r3, [r7, #0] + 8000192: 019b lsls r3, r3, #6 + 8000194: 22ff movs r2, #255 ; 0xff + 8000196: 401a ands r2, r3 + 8000198: 1dfb adds r3, r7, #7 + 800019a: 781b ldrb r3, [r3, #0] + 800019c: 0018 movs r0, r3 + 800019e: 2303 movs r3, #3 + 80001a0: 4003 ands r3, r0 + 80001a2: 00db lsls r3, r3, #3 + 80001a4: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80001a6: 4807 ldr r0, [pc, #28] ; (80001c4 <NVIC_SetPriority+0xd8>) + 80001a8: 1dfb adds r3, r7, #7 + 80001aa: 781b ldrb r3, [r3, #0] + 80001ac: b25b sxtb r3, r3 + 80001ae: 089b lsrs r3, r3, #2 + 80001b0: 430a orrs r2, r1 + 80001b2: 33c0 adds r3, #192 ; 0xc0 + 80001b4: 009b lsls r3, r3, #2 + 80001b6: 501a str r2, [r3, r0] +} + 80001b8: 46c0 nop ; (mov r8, r8) + 80001ba: 46bd mov sp, r7 + 80001bc: b003 add sp, #12 + 80001be: bd90 pop {r4, r7, pc} + 80001c0: e000ed00 .word 0xe000ed00 + 80001c4: e000e100 .word 0xe000e100 + +080001c8 <SysTick_Config>: + \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the + function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 80001c8: b580 push {r7, lr} + 80001ca: b082 sub sp, #8 + 80001cc: af00 add r7, sp, #0 + 80001ce: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 80001d0: 687b ldr r3, [r7, #4] + 80001d2: 1e5a subs r2, r3, #1 + 80001d4: 2380 movs r3, #128 ; 0x80 + 80001d6: 045b lsls r3, r3, #17 + 80001d8: 429a cmp r2, r3 + 80001da: d301 bcc.n 80001e0 <SysTick_Config+0x18> + { + return (1UL); /* Reload value impossible */ + 80001dc: 2301 movs r3, #1 + 80001de: e010 b.n 8000202 <SysTick_Config+0x3a> + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 80001e0: 4b0a ldr r3, [pc, #40] ; (800020c <SysTick_Config+0x44>) + 80001e2: 687a ldr r2, [r7, #4] + 80001e4: 3a01 subs r2, #1 + 80001e6: 605a str r2, [r3, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 80001e8: 2301 movs r3, #1 + 80001ea: 425b negs r3, r3 + 80001ec: 2103 movs r1, #3 + 80001ee: 0018 movs r0, r3 + 80001f0: f7ff ff7c bl 80000ec <NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80001f4: 4b05 ldr r3, [pc, #20] ; (800020c <SysTick_Config+0x44>) + 80001f6: 2200 movs r2, #0 + 80001f8: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 80001fa: 4b04 ldr r3, [pc, #16] ; (800020c <SysTick_Config+0x44>) + 80001fc: 2207 movs r2, #7 + 80001fe: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 8000200: 2300 movs r3, #0 +} + 8000202: 0018 movs r0, r3 + 8000204: 46bd mov sp, r7 + 8000206: b002 add sp, #8 + 8000208: bd80 pop {r7, pc} + 800020a: 46c0 nop ; (mov r8, r8) + 800020c: e000e010 .word 0xe000e010 + +08000210 <update_leds>: +#include "serial.h" + + +volatile unsigned int sys_time_seconds = 0; + +void update_leds() { + 8000210: b580 push {r7, lr} + 8000212: af00 add r7, sp, #0 + +} + 8000214: 46c0 nop ; (mov r8, r8) + 8000216: 46bd mov sp, r7 + 8000218: bd80 pop {r7, pc} + +0800021a <main>: + unsigned int usb, ocxo, error, _nc1, _nc2, _nc3, pps, sd_card; + }; + unsigned int arr[0]; +} leds; + +int main(void) { + 800021a: b580 push {r7, lr} + 800021c: b082 sub sp, #8 + 800021e: af00 add r7, sp, #0 + RCC->CR |= RCC_CR_HSEON; + 8000220: 4b5b ldr r3, [pc, #364] ; (8000390 <main+0x176>) + 8000222: 681a ldr r2, [r3, #0] + 8000224: 4b5a ldr r3, [pc, #360] ; (8000390 <main+0x176>) + 8000226: 2180 movs r1, #128 ; 0x80 + 8000228: 0249 lsls r1, r1, #9 + 800022a: 430a orrs r2, r1 + 800022c: 601a str r2, [r3, #0] + while (!(RCC->CR&RCC_CR_HSERDY)); + 800022e: 46c0 nop ; (mov r8, r8) + 8000230: 4b57 ldr r3, [pc, #348] ; (8000390 <main+0x176>) + 8000232: 681a ldr r2, [r3, #0] + 8000234: 2380 movs r3, #128 ; 0x80 + 8000236: 029b lsls r3, r3, #10 + 8000238: 4013 ands r3, r2 + 800023a: d0f9 beq.n 8000230 <main+0x16> + RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk; + 800023c: 4b54 ldr r3, [pc, #336] ; (8000390 <main+0x176>) + 800023e: 685a ldr r2, [r3, #4] + 8000240: 4b53 ldr r3, [pc, #332] ; (8000390 <main+0x176>) + 8000242: 4954 ldr r1, [pc, #336] ; (8000394 <main+0x17a>) + 8000244: 400a ands r2, r1 + 8000246: 605a str r2, [r3, #4] + RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */ + 8000248: 4b51 ldr r3, [pc, #324] ; (8000390 <main+0x176>) + 800024a: 685a ldr r2, [r3, #4] + 800024c: 4b50 ldr r3, [pc, #320] ; (8000390 <main+0x176>) + 800024e: 2188 movs r1, #136 ; 0x88 + 8000250: 0349 lsls r1, r1, #13 + 8000252: 430a orrs r2, r1 + 8000254: 605a str r2, [r3, #4] + RCC->CR |= RCC_CR_PLLON; + 8000256: 4b4e ldr r3, [pc, #312] ; (8000390 <main+0x176>) + 8000258: 681a ldr r2, [r3, #0] + 800025a: 4b4d ldr r3, [pc, #308] ; (8000390 <main+0x176>) + 800025c: 2180 movs r1, #128 ; 0x80 + 800025e: 0449 lsls r1, r1, #17 + 8000260: 430a orrs r2, r1 + 8000262: 601a str r2, [r3, #0] + while (!(RCC->CR&RCC_CR_PLLRDY)); + 8000264: 46c0 nop ; (mov r8, r8) + 8000266: 4b4a ldr r3, [pc, #296] ; (8000390 <main+0x176>) + 8000268: 681a ldr r2, [r3, #0] + 800026a: 2380 movs r3, #128 ; 0x80 + 800026c: 049b lsls r3, r3, #18 + 800026e: 4013 ands r3, r2 + 8000270: d0f9 beq.n 8000266 <main+0x4c> + RCC->CFGR |= (2<<RCC_CFGR_SW_Pos); + 8000272: 4b47 ldr r3, [pc, #284] ; (8000390 <main+0x176>) + 8000274: 685a ldr r2, [r3, #4] + 8000276: 4b46 ldr r3, [pc, #280] ; (8000390 <main+0x176>) + 8000278: 2102 movs r1, #2 + 800027a: 430a orrs r2, r1 + 800027c: 605a str r2, [r3, #4] + SystemCoreClockUpdate(); + 800027e: f000 fe11 bl 8000ea4 <SystemCoreClockUpdate> + SysTick_Config(SystemCoreClock/10); /* 100ms interval */ + 8000282: 4b45 ldr r3, [pc, #276] ; (8000398 <main+0x17e>) + 8000284: 681b ldr r3, [r3, #0] + 8000286: 210a movs r1, #10 + 8000288: 0018 movs r0, r3 + 800028a: f001 f98d bl 80015a8 <__udivsi3> + 800028e: 0003 movs r3, r0 + 8000290: 0018 movs r0, r3 + 8000292: f7ff ff99 bl 80001c8 <SysTick_Config> + NVIC_EnableIRQ(SysTick_IRQn); + 8000296: 2301 movs r3, #1 + 8000298: 425b negs r3, r3 + 800029a: 0018 movs r0, r3 + 800029c: f7ff ff10 bl 80000c0 <NVIC_EnableIRQ> + NVIC_SetPriority(SysTick_IRQn, 3<<5); + 80002a0: 2301 movs r3, #1 + 80002a2: 425b negs r3, r3 + 80002a4: 2160 movs r1, #96 ; 0x60 + 80002a6: 0018 movs r0, r3 + 80002a8: f7ff ff20 bl 80000ec <NVIC_SetPriority> + + /* Turn on lots of neat things */ + RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN; + 80002ac: 4b38 ldr r3, [pc, #224] ; (8000390 <main+0x176>) + 80002ae: 695a ldr r2, [r3, #20] + 80002b0: 4b37 ldr r3, [pc, #220] ; (8000390 <main+0x176>) + 80002b2: 493a ldr r1, [pc, #232] ; (800039c <main+0x182>) + 80002b4: 430a orrs r2, r1 + 80002b6: 615a str r2, [r3, #20] + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_DBGMCUEN |\ + 80002b8: 4b35 ldr r3, [pc, #212] ; (8000390 <main+0x176>) + 80002ba: 699a ldr r2, [r3, #24] + 80002bc: 4b34 ldr r3, [pc, #208] ; (8000390 <main+0x176>) + 80002be: 4938 ldr r1, [pc, #224] ; (80003a0 <main+0x186>) + 80002c0: 430a orrs r2, r1 + 80002c2: 619a str r2, [r3, #24] + RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN; + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + 80002c4: 4b32 ldr r3, [pc, #200] ; (8000390 <main+0x176>) + 80002c6: 69da ldr r2, [r3, #28] + 80002c8: 4b31 ldr r3, [pc, #196] ; (8000390 <main+0x176>) + 80002ca: 2102 movs r1, #2 + 80002cc: 430a orrs r2, r1 + 80002ce: 61da str r2, [r3, #28] + + GPIOA->MODER |= + 80002d0: 2390 movs r3, #144 ; 0x90 + 80002d2: 05db lsls r3, r3, #23 + 80002d4: 681a ldr r2, [r3, #0] + 80002d6: 2390 movs r3, #144 ; 0x90 + 80002d8: 05db lsls r3, r3, #23 + 80002da: 4932 ldr r1, [pc, #200] ; (80003a4 <main+0x18a>) + 80002dc: 430a orrs r2, r1 + 80002de: 601a str r2, [r3, #0] + | (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */ + | (2<<GPIO_MODER_MODER9_Pos) /* PA9 - HOST_RX */ + | (2<<GPIO_MODER_MODER10_Pos);/* PA10 - HOST_TX */ + + /* Set shift register IO GPIO output speed */ + GPIOA->OSPEEDR |= + 80002e0: 2390 movs r3, #144 ; 0x90 + 80002e2: 05db lsls r3, r3, #23 + 80002e4: 689a ldr r2, [r3, #8] + 80002e6: 2390 movs r3, #144 ; 0x90 + 80002e8: 05db lsls r3, r3, #23 + 80002ea: 492f ldr r1, [pc, #188] ; (80003a8 <main+0x18e>) + 80002ec: 430a orrs r2, r1 + 80002ee: 609a str r2, [r3, #8] + | (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* SD_CS */ + | (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCK */ + | (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */ + | (2<<GPIO_OSPEEDR_OSPEEDR9_Pos); /* HOST_RX */ + + GPIOA->AFR[0] = (0<<GPIO_AFRL_AFRL5_Pos) | (0<<GPIO_AFRL_AFRL6_Pos) | (0<<GPIO_AFRL_AFRL7_Pos); + 80002f0: 2390 movs r3, #144 ; 0x90 + 80002f2: 05db lsls r3, r3, #23 + 80002f4: 2200 movs r2, #0 + 80002f6: 621a str r2, [r3, #32] + GPIOA->AFR[1] = (1<<8) | (1<<4); + 80002f8: 2390 movs r3, #144 ; 0x90 + 80002fa: 05db lsls r3, r3, #23 + 80002fc: 2288 movs r2, #136 ; 0x88 + 80002fe: 0052 lsls r2, r2, #1 + 8000300: 625a str r2, [r3, #36] ; 0x24 + + GPIOB->MODER |= + 8000302: 4a2a ldr r2, [pc, #168] ; (80003ac <main+0x192>) + 8000304: 4b29 ldr r3, [pc, #164] ; (80003ac <main+0x192>) + 8000306: 6812 ldr r2, [r2, #0] + 8000308: 601a str r2, [r3, #0] + (0<<GPIO_MODER_MODER1_Pos); /* PB0 - LINE_POL */ + + SPI1->CR1 = + 800030a: 4b29 ldr r3, [pc, #164] ; (80003b0 <main+0x196>) + 800030c: 22c9 movs r2, #201 ; 0xc9 + 800030e: 0092 lsls r2, r2, #2 + 8000310: 601a str r2, [r3, #0] + SPI_CR1_SSM + | SPI_CR1_SSI + | (4<<SPI_CR1_BR_Pos) /* /32 ~1.5MHz */ + | SPI_CR1_MSTR; + SPI1->CR2 = (7<<SPI_CR2_DS_Pos); + 8000312: 4b27 ldr r3, [pc, #156] ; (80003b0 <main+0x196>) + 8000314: 22e0 movs r2, #224 ; 0xe0 + 8000316: 00d2 lsls r2, r2, #3 + 8000318: 605a str r2, [r3, #4] + SPI1->CR1 |= SPI_CR1_SPE; + 800031a: 4b25 ldr r3, [pc, #148] ; (80003b0 <main+0x196>) + 800031c: 681a ldr r2, [r3, #0] + 800031e: 4b24 ldr r3, [pc, #144] ; (80003b0 <main+0x196>) + 8000320: 2140 movs r1, #64 ; 0x40 + 8000322: 430a orrs r2, r1 + 8000324: 601a str r2, [r3, #0] + + NVIC_EnableIRQ(SPI1_IRQn); + 8000326: 2019 movs r0, #25 + 8000328: f7ff feca bl 80000c0 <NVIC_EnableIRQ> + NVIC_SetPriority(SPI1_IRQn, 2<<5); + 800032c: 2140 movs r1, #64 ; 0x40 + 800032e: 2019 movs r0, #25 + 8000330: f7ff fedc bl 80000ec <NVIC_SetPriority> + + TIM16->CR2 = 0; + 8000334: 4b1f ldr r3, [pc, #124] ; (80003b4 <main+0x19a>) + 8000336: 2200 movs r2, #0 + 8000338: 605a str r2, [r3, #4] + TIM16->DIER = TIM_DIER_UIE; + 800033a: 4b1e ldr r3, [pc, #120] ; (80003b4 <main+0x19a>) + 800033c: 2201 movs r2, #1 + 800033e: 60da str r2, [r3, #12] + TIM16->PSC = 48-1; /* 1us */ + 8000340: 4b1c ldr r3, [pc, #112] ; (80003b4 <main+0x19a>) + 8000342: 222f movs r2, #47 ; 0x2f + 8000344: 629a str r2, [r3, #40] ; 0x28 + TIM16->ARR = 1000-1; /* 1ms */ + 8000346: 4b1b ldr r3, [pc, #108] ; (80003b4 <main+0x19a>) + 8000348: 4a1b ldr r2, [pc, #108] ; (80003b8 <main+0x19e>) + 800034a: 62da str r2, [r3, #44] ; 0x2c + TIM16->CR1 = TIM_CR1_CEN; + 800034c: 4b19 ldr r3, [pc, #100] ; (80003b4 <main+0x19a>) + 800034e: 2201 movs r2, #1 + 8000350: 601a str r2, [r3, #0] + + NVIC_EnableIRQ(TIM16_IRQn); + 8000352: 2015 movs r0, #21 + 8000354: f7ff feb4 bl 80000c0 <NVIC_EnableIRQ> + NVIC_SetPriority(TIM16_IRQn, 2<<5); + 8000358: 2140 movs r1, #64 ; 0x40 + 800035a: 2015 movs r0, #21 + 800035c: f7ff fec6 bl 80000ec <NVIC_SetPriority> + + adc_configure_scope_mode(1000000); + 8000360: 4b16 ldr r3, [pc, #88] ; (80003bc <main+0x1a2>) + 8000362: 0018 movs r0, r3 + 8000364: f000 f95a bl 800061c <adc_configure_scope_mode> + + usart_dma_init(); + 8000368: f000 fabe bl 80008e8 <usart_dma_init> + + while (42) { + char *data = "FOOBAR\n"; + 800036c: 4b14 ldr r3, [pc, #80] ; (80003c0 <main+0x1a6>) + 800036e: 603b str r3, [r7, #0] + usart_send_packet((uint8_t*)data, 8); + 8000370: 683b ldr r3, [r7, #0] + 8000372: 2108 movs r1, #8 + 8000374: 0018 movs r0, r3 + 8000376: f000 fb91 bl 8000a9c <usart_send_packet> + for (int i=0; i<100000; i++); + 800037a: 2300 movs r3, #0 + 800037c: 607b str r3, [r7, #4] + 800037e: e002 b.n 8000386 <main+0x16c> + 8000380: 687b ldr r3, [r7, #4] + 8000382: 3301 adds r3, #1 + 8000384: 607b str r3, [r7, #4] + 8000386: 687b ldr r3, [r7, #4] + 8000388: 4a0e ldr r2, [pc, #56] ; (80003c4 <main+0x1aa>) + 800038a: 4293 cmp r3, r2 + 800038c: ddf8 ble.n 8000380 <main+0x166> + while (42) { + 800038e: e7ed b.n 800036c <main+0x152> + 8000390: 40021000 .word 0x40021000 + 8000394: ffc3f80c .word 0xffc3f80c + 8000398: 20000000 .word 0x20000000 + 800039c: 00060011 .word 0x00060011 + 80003a0: 00425a01 .word 0x00425a01 + 80003a4: 0028a970 .word 0x0028a970 + 80003a8: 00088a80 .word 0x00088a80 + 80003ac: 48000400 .word 0x48000400 + 80003b0: 40013000 .word 0x40013000 + 80003b4: 40014400 .word 0x40014400 + 80003b8: 000003e7 .word 0x000003e7 + 80003bc: 000f4240 .word 0x000f4240 + 80003c0: 080018e4 .word 0x080018e4 + 80003c4: 0001869f .word 0x0001869f + +080003c8 <SPI1_IRQHandler>: + //for (int i=0; i<10000; i++) ; + //leds.error = 100; + } +} + +void SPI1_IRQHandler(void) { + 80003c8: b580 push {r7, lr} + 80003ca: af00 add r7, sp, #0 + if (SPI1->SR & SPI_SR_TXE) { + 80003cc: 4b08 ldr r3, [pc, #32] ; (80003f0 <SPI1_IRQHandler+0x28>) + 80003ce: 689b ldr r3, [r3, #8] + 80003d0: 2202 movs r2, #2 + 80003d2: 4013 ands r3, r2 + 80003d4: d009 beq.n 80003ea <SPI1_IRQHandler+0x22> + /* LED_STB */ + GPIOA->BSRR = 1<<3; + 80003d6: 2390 movs r3, #144 ; 0x90 + 80003d8: 05db lsls r3, r3, #23 + 80003da: 2208 movs r2, #8 + 80003dc: 619a str r2, [r3, #24] + SPI1->CR2 &= ~SPI_CR2_TXEIE; + 80003de: 4b04 ldr r3, [pc, #16] ; (80003f0 <SPI1_IRQHandler+0x28>) + 80003e0: 685a ldr r2, [r3, #4] + 80003e2: 4b03 ldr r3, [pc, #12] ; (80003f0 <SPI1_IRQHandler+0x28>) + 80003e4: 2180 movs r1, #128 ; 0x80 + 80003e6: 438a bics r2, r1 + 80003e8: 605a str r2, [r3, #4] + } +} + 80003ea: 46c0 nop ; (mov r8, r8) + 80003ec: 46bd mov sp, r7 + 80003ee: bd80 pop {r7, pc} + 80003f0: 40013000 .word 0x40013000 + +080003f4 <TIM16_IRQHandler>: + +void TIM16_IRQHandler(void) { + 80003f4: b580 push {r7, lr} + 80003f6: b082 sub sp, #8 + 80003f8: af00 add r7, sp, #0 + static int leds_update_counter = 0; + if (TIM16->SR & TIM_SR_UIF) { + 80003fa: 4b28 ldr r3, [pc, #160] ; (800049c <TIM16_IRQHandler+0xa8>) + 80003fc: 691b ldr r3, [r3, #16] + 80003fe: 2201 movs r2, #1 + 8000400: 4013 ands r3, r2 + 8000402: d047 beq.n 8000494 <TIM16_IRQHandler+0xa0> + TIM16->SR &= ~TIM_SR_UIF; + 8000404: 4b25 ldr r3, [pc, #148] ; (800049c <TIM16_IRQHandler+0xa8>) + 8000406: 691a ldr r2, [r3, #16] + 8000408: 4b24 ldr r3, [pc, #144] ; (800049c <TIM16_IRQHandler+0xa8>) + 800040a: 2101 movs r1, #1 + 800040c: 438a bics r2, r1 + 800040e: 611a str r2, [r3, #16] + + uint8_t bits = 0, mask = 1; + 8000410: 1dfb adds r3, r7, #7 + 8000412: 2200 movs r2, #0 + 8000414: 701a strb r2, [r3, #0] + 8000416: 1dbb adds r3, r7, #6 + 8000418: 2201 movs r2, #1 + 800041a: 701a strb r2, [r3, #0] + for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) { + 800041c: 2300 movs r3, #0 + 800041e: 603b str r3, [r7, #0] + 8000420: e01d b.n 800045e <TIM16_IRQHandler+0x6a> + if (leds.arr[i]) { + 8000422: 4b1f ldr r3, [pc, #124] ; (80004a0 <TIM16_IRQHandler+0xac>) + 8000424: 683a ldr r2, [r7, #0] + 8000426: 0092 lsls r2, r2, #2 + 8000428: 58d3 ldr r3, [r2, r3] + 800042a: 2b00 cmp r3, #0 + 800042c: d00f beq.n 800044e <TIM16_IRQHandler+0x5a> + leds.arr[i]--; + 800042e: 4b1c ldr r3, [pc, #112] ; (80004a0 <TIM16_IRQHandler+0xac>) + 8000430: 683a ldr r2, [r7, #0] + 8000432: 0092 lsls r2, r2, #2 + 8000434: 58d3 ldr r3, [r2, r3] + 8000436: 1e59 subs r1, r3, #1 + 8000438: 4b19 ldr r3, [pc, #100] ; (80004a0 <TIM16_IRQHandler+0xac>) + 800043a: 683a ldr r2, [r7, #0] + 800043c: 0092 lsls r2, r2, #2 + 800043e: 50d1 str r1, [r2, r3] + bits |= mask; + 8000440: 1dfb adds r3, r7, #7 + 8000442: 1df9 adds r1, r7, #7 + 8000444: 1dba adds r2, r7, #6 + 8000446: 7809 ldrb r1, [r1, #0] + 8000448: 7812 ldrb r2, [r2, #0] + 800044a: 430a orrs r2, r1 + 800044c: 701a strb r2, [r3, #0] + } + mask <<= 1; + 800044e: 1dba adds r2, r7, #6 + 8000450: 1dbb adds r3, r7, #6 + 8000452: 781b ldrb r3, [r3, #0] + 8000454: 18db adds r3, r3, r3 + 8000456: 7013 strb r3, [r2, #0] + for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) { + 8000458: 683b ldr r3, [r7, #0] + 800045a: 3301 adds r3, #1 + 800045c: 603b str r3, [r7, #0] + 800045e: 683b ldr r3, [r7, #0] + 8000460: 2b07 cmp r3, #7 + 8000462: d9de bls.n 8000422 <TIM16_IRQHandler+0x2e> + } + + if (leds_update_counter++ == 10) { + 8000464: 4b0f ldr r3, [pc, #60] ; (80004a4 <TIM16_IRQHandler+0xb0>) + 8000466: 681b ldr r3, [r3, #0] + 8000468: 1c59 adds r1, r3, #1 + 800046a: 4a0e ldr r2, [pc, #56] ; (80004a4 <TIM16_IRQHandler+0xb0>) + 800046c: 6011 str r1, [r2, #0] + 800046e: 2b0a cmp r3, #10 + 8000470: d110 bne.n 8000494 <TIM16_IRQHandler+0xa0> + leds_update_counter = 0; + 8000472: 4b0c ldr r3, [pc, #48] ; (80004a4 <TIM16_IRQHandler+0xb0>) + 8000474: 2200 movs r2, #0 + 8000476: 601a str r2, [r3, #0] + + /* Workaround for SPI hardware bug: Even if configured to 8-bit mode, the SPI will do a 16-bit transfer if the + * data register is accessed through a 16-bit write. Unfortunately, the STMCube register defs define DR as an + * uint16_t, so we have to do some magic here to force an 8-bit write. */ + *((volatile uint8_t*)&(SPI1->DR)) = bits; + 8000478: 4a0b ldr r2, [pc, #44] ; (80004a8 <TIM16_IRQHandler+0xb4>) + 800047a: 1dfb adds r3, r7, #7 + 800047c: 781b ldrb r3, [r3, #0] + 800047e: 7013 strb r3, [r2, #0] + SPI1->CR2 |= SPI_CR2_TXEIE; + 8000480: 4b0a ldr r3, [pc, #40] ; (80004ac <TIM16_IRQHandler+0xb8>) + 8000482: 685a ldr r2, [r3, #4] + 8000484: 4b09 ldr r3, [pc, #36] ; (80004ac <TIM16_IRQHandler+0xb8>) + 8000486: 2180 movs r1, #128 ; 0x80 + 8000488: 430a orrs r2, r1 + 800048a: 605a str r2, [r3, #4] + GPIOA->BRR = 1<<3; + 800048c: 2390 movs r3, #144 ; 0x90 + 800048e: 05db lsls r3, r3, #23 + 8000490: 2208 movs r2, #8 + 8000492: 629a str r2, [r3, #40] ; 0x28 + } + } +} + 8000494: 46c0 nop ; (mov r8, r8) + 8000496: 46bd mov sp, r7 + 8000498: b002 add sp, #8 + 800049a: bd80 pop {r7, pc} + 800049c: 40014400 .word 0x40014400 + 80004a0: 200000a8 .word 0x200000a8 + 80004a4: 20000098 .word 0x20000098 + 80004a8: 4001300c .word 0x4001300c + 80004ac: 40013000 .word 0x40013000 + +080004b0 <NMI_Handler>: + +void NMI_Handler(void) { + 80004b0: b580 push {r7, lr} + 80004b2: af00 add r7, sp, #0 + asm volatile ("bkpt"); + 80004b4: be00 bkpt 0x0000 +} + 80004b6: 46c0 nop ; (mov r8, r8) + 80004b8: 46bd mov sp, r7 + 80004ba: bd80 pop {r7, pc} + +080004bc <HardFault_Handler>: + +void HardFault_Handler(void) __attribute__((naked)); +void HardFault_Handler() { + asm volatile ("bkpt"); + 80004bc: be00 bkpt 0x0000 +} + 80004be: 46c0 nop ; (mov r8, r8) + +080004c0 <SVC_Handler>: + +void SVC_Handler(void) { + 80004c0: b580 push {r7, lr} + 80004c2: af00 add r7, sp, #0 + asm volatile ("bkpt"); + 80004c4: be00 bkpt 0x0000 +} + 80004c6: 46c0 nop ; (mov r8, r8) + 80004c8: 46bd mov sp, r7 + 80004ca: bd80 pop {r7, pc} + +080004cc <PendSV_Handler>: + + +void PendSV_Handler(void) { + 80004cc: b580 push {r7, lr} + 80004ce: af00 add r7, sp, #0 + asm volatile ("bkpt"); + 80004d0: be00 bkpt 0x0000 +} + 80004d2: 46c0 nop ; (mov r8, r8) + 80004d4: 46bd mov sp, r7 + 80004d6: bd80 pop {r7, pc} + +080004d8 <SysTick_Handler>: + +void SysTick_Handler(void) { + 80004d8: b580 push {r7, lr} + 80004da: af00 add r7, sp, #0 + static int n = 0; + if (n++ == 10) { + 80004dc: 4b0a ldr r3, [pc, #40] ; (8000508 <SysTick_Handler+0x30>) + 80004de: 681b ldr r3, [r3, #0] + 80004e0: 1c59 adds r1, r3, #1 + 80004e2: 4a09 ldr r2, [pc, #36] ; (8000508 <SysTick_Handler+0x30>) + 80004e4: 6011 str r1, [r2, #0] + 80004e6: 2b0a cmp r3, #10 + 80004e8: d10a bne.n 8000500 <SysTick_Handler+0x28> + n = 0; + 80004ea: 4b07 ldr r3, [pc, #28] ; (8000508 <SysTick_Handler+0x30>) + 80004ec: 2200 movs r2, #0 + 80004ee: 601a str r2, [r3, #0] + sys_time_seconds++; + 80004f0: 4b06 ldr r3, [pc, #24] ; (800050c <SysTick_Handler+0x34>) + 80004f2: 681b ldr r3, [r3, #0] + 80004f4: 1c5a adds r2, r3, #1 + 80004f6: 4b05 ldr r3, [pc, #20] ; (800050c <SysTick_Handler+0x34>) + 80004f8: 601a str r2, [r3, #0] + leds.pps = 100; /* ms */ + 80004fa: 4b05 ldr r3, [pc, #20] ; (8000510 <SysTick_Handler+0x38>) + 80004fc: 2264 movs r2, #100 ; 0x64 + 80004fe: 619a str r2, [r3, #24] + } +} + 8000500: 46c0 nop ; (mov r8, r8) + 8000502: 46bd mov sp, r7 + 8000504: bd80 pop {r7, pc} + 8000506: 46c0 nop ; (mov r8, r8) + 8000508: 2000009c .word 0x2000009c + 800050c: 20000094 .word 0x20000094 + 8000510: 200000a8 .word 0x200000a8 + +08000514 <NVIC_EnableIRQ>: +{ + 8000514: b580 push {r7, lr} + 8000516: b082 sub sp, #8 + 8000518: af00 add r7, sp, #0 + 800051a: 0002 movs r2, r0 + 800051c: 1dfb adds r3, r7, #7 + 800051e: 701a strb r2, [r3, #0] + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 8000520: 1dfb adds r3, r7, #7 + 8000522: 781b ldrb r3, [r3, #0] + 8000524: 001a movs r2, r3 + 8000526: 231f movs r3, #31 + 8000528: 401a ands r2, r3 + 800052a: 4b04 ldr r3, [pc, #16] ; (800053c <NVIC_EnableIRQ+0x28>) + 800052c: 2101 movs r1, #1 + 800052e: 4091 lsls r1, r2 + 8000530: 000a movs r2, r1 + 8000532: 601a str r2, [r3, #0] +} + 8000534: 46c0 nop ; (mov r8, r8) + 8000536: 46bd mov sp, r7 + 8000538: b002 add sp, #8 + 800053a: bd80 pop {r7, pc} + 800053c: e000e100 .word 0xe000e100 + +08000540 <NVIC_SetPriority>: +{ + 8000540: b590 push {r4, r7, lr} + 8000542: b083 sub sp, #12 + 8000544: af00 add r7, sp, #0 + 8000546: 0002 movs r2, r0 + 8000548: 6039 str r1, [r7, #0] + 800054a: 1dfb adds r3, r7, #7 + 800054c: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) < 0) + 800054e: 1dfb adds r3, r7, #7 + 8000550: 781b ldrb r3, [r3, #0] + 8000552: 2b7f cmp r3, #127 ; 0x7f + 8000554: d932 bls.n 80005bc <NVIC_SetPriority+0x7c> + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000556: 4a2f ldr r2, [pc, #188] ; (8000614 <NVIC_SetPriority+0xd4>) + 8000558: 1dfb adds r3, r7, #7 + 800055a: 781b ldrb r3, [r3, #0] + 800055c: 0019 movs r1, r3 + 800055e: 230f movs r3, #15 + 8000560: 400b ands r3, r1 + 8000562: 3b08 subs r3, #8 + 8000564: 089b lsrs r3, r3, #2 + 8000566: 3306 adds r3, #6 + 8000568: 009b lsls r3, r3, #2 + 800056a: 18d3 adds r3, r2, r3 + 800056c: 3304 adds r3, #4 + 800056e: 681b ldr r3, [r3, #0] + 8000570: 1dfa adds r2, r7, #7 + 8000572: 7812 ldrb r2, [r2, #0] + 8000574: 0011 movs r1, r2 + 8000576: 2203 movs r2, #3 + 8000578: 400a ands r2, r1 + 800057a: 00d2 lsls r2, r2, #3 + 800057c: 21ff movs r1, #255 ; 0xff + 800057e: 4091 lsls r1, r2 + 8000580: 000a movs r2, r1 + 8000582: 43d2 mvns r2, r2 + 8000584: 401a ands r2, r3 + 8000586: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000588: 683b ldr r3, [r7, #0] + 800058a: 019b lsls r3, r3, #6 + 800058c: 22ff movs r2, #255 ; 0xff + 800058e: 401a ands r2, r3 + 8000590: 1dfb adds r3, r7, #7 + 8000592: 781b ldrb r3, [r3, #0] + 8000594: 0018 movs r0, r3 + 8000596: 2303 movs r3, #3 + 8000598: 4003 ands r3, r0 + 800059a: 00db lsls r3, r3, #3 + 800059c: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800059e: 481d ldr r0, [pc, #116] ; (8000614 <NVIC_SetPriority+0xd4>) + 80005a0: 1dfb adds r3, r7, #7 + 80005a2: 781b ldrb r3, [r3, #0] + 80005a4: 001c movs r4, r3 + 80005a6: 230f movs r3, #15 + 80005a8: 4023 ands r3, r4 + 80005aa: 3b08 subs r3, #8 + 80005ac: 089b lsrs r3, r3, #2 + 80005ae: 430a orrs r2, r1 + 80005b0: 3306 adds r3, #6 + 80005b2: 009b lsls r3, r3, #2 + 80005b4: 18c3 adds r3, r0, r3 + 80005b6: 3304 adds r3, #4 + 80005b8: 601a str r2, [r3, #0] +} + 80005ba: e027 b.n 800060c <NVIC_SetPriority+0xcc> + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80005bc: 4a16 ldr r2, [pc, #88] ; (8000618 <NVIC_SetPriority+0xd8>) + 80005be: 1dfb adds r3, r7, #7 + 80005c0: 781b ldrb r3, [r3, #0] + 80005c2: b25b sxtb r3, r3 + 80005c4: 089b lsrs r3, r3, #2 + 80005c6: 33c0 adds r3, #192 ; 0xc0 + 80005c8: 009b lsls r3, r3, #2 + 80005ca: 589b ldr r3, [r3, r2] + 80005cc: 1dfa adds r2, r7, #7 + 80005ce: 7812 ldrb r2, [r2, #0] + 80005d0: 0011 movs r1, r2 + 80005d2: 2203 movs r2, #3 + 80005d4: 400a ands r2, r1 + 80005d6: 00d2 lsls r2, r2, #3 + 80005d8: 21ff movs r1, #255 ; 0xff + 80005da: 4091 lsls r1, r2 + 80005dc: 000a movs r2, r1 + 80005de: 43d2 mvns r2, r2 + 80005e0: 401a ands r2, r3 + 80005e2: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 80005e4: 683b ldr r3, [r7, #0] + 80005e6: 019b lsls r3, r3, #6 + 80005e8: 22ff movs r2, #255 ; 0xff + 80005ea: 401a ands r2, r3 + 80005ec: 1dfb adds r3, r7, #7 + 80005ee: 781b ldrb r3, [r3, #0] + 80005f0: 0018 movs r0, r3 + 80005f2: 2303 movs r3, #3 + 80005f4: 4003 ands r3, r0 + 80005f6: 00db lsls r3, r3, #3 + 80005f8: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80005fa: 4807 ldr r0, [pc, #28] ; (8000618 <NVIC_SetPriority+0xd8>) + 80005fc: 1dfb adds r3, r7, #7 + 80005fe: 781b ldrb r3, [r3, #0] + 8000600: b25b sxtb r3, r3 + 8000602: 089b lsrs r3, r3, #2 + 8000604: 430a orrs r2, r1 + 8000606: 33c0 adds r3, #192 ; 0xc0 + 8000608: 009b lsls r3, r3, #2 + 800060a: 501a str r2, [r3, r0] +} + 800060c: 46c0 nop ; (mov r8, r8) + 800060e: 46bd mov sp, r7 + 8000610: b003 add sp, #12 + 8000612: bd90 pop {r4, r7, pc} + 8000614: e000ed00 .word 0xe000ed00 + 8000618: e000e100 .word 0xe000e100 + +0800061c <adc_configure_scope_mode>: +static void adc_dma_init(int burstlen); +static void adc_timer_init(int psc, int ivl); + + +/* Mode that can be used for debugging */ +void adc_configure_scope_mode(int sampling_interval_ns) { + 800061c: b580 push {r7, lr} + 800061e: b084 sub sp, #16 + 8000620: af00 add r7, sp, #0 + 8000622: 6078 str r0, [r7, #4] + adc_dma_init(sizeof(adc_buf)/sizeof(adc_buf[0])); + 8000624: 2380 movs r3, #128 ; 0x80 + 8000626: 00db lsls r3, r3, #3 + 8000628: 0018 movs r0, r3 + 800062a: f000 f84b bl 80006c4 <adc_dma_init> + + /* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */ + ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */ + 800062e: 4b21 ldr r3, [pc, #132] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000630: 2280 movs r2, #128 ; 0x80 + 8000632: 0612 lsls r2, r2, #24 + 8000634: 611a str r2, [r3, #16] + /* Sampling time 239.5 ADC clock cycles -> total conversion time 38.5us*/ + ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos); + 8000636: 4b1f ldr r3, [pc, #124] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000638: 2207 movs r2, #7 + 800063a: 615a str r2, [r3, #20] + + /* Setup DMA and triggering */ + /* Trigger from TIM1 TRGO */ + ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos); + 800063c: 4b1d ldr r3, [pc, #116] ; (80006b4 <adc_configure_scope_mode+0x98>) + 800063e: 4a1e ldr r2, [pc, #120] ; (80006b8 <adc_configure_scope_mode+0x9c>) + 8000640: 60da str r2, [r3, #12] + ADC1->CHSELR = ADC_CHSELR_CHSEL2; + 8000642: 4b1c ldr r3, [pc, #112] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000644: 2204 movs r2, #4 + 8000646: 629a str r2, [r3, #40] ; 0x28 + /* Perform self-calibration */ + ADC1->CR |= ADC_CR_ADCAL; + 8000648: 4b1a ldr r3, [pc, #104] ; (80006b4 <adc_configure_scope_mode+0x98>) + 800064a: 689a ldr r2, [r3, #8] + 800064c: 4b19 ldr r3, [pc, #100] ; (80006b4 <adc_configure_scope_mode+0x98>) + 800064e: 2180 movs r1, #128 ; 0x80 + 8000650: 0609 lsls r1, r1, #24 + 8000652: 430a orrs r2, r1 + 8000654: 609a str r2, [r3, #8] + while (ADC1->CR & ADC_CR_ADCAL) + 8000656: 46c0 nop ; (mov r8, r8) + 8000658: 4b16 ldr r3, [pc, #88] ; (80006b4 <adc_configure_scope_mode+0x98>) + 800065a: 689b ldr r3, [r3, #8] + 800065c: 2b00 cmp r3, #0 + 800065e: dbfb blt.n 8000658 <adc_configure_scope_mode+0x3c> + ; + /* Enable conversion */ + ADC1->CR |= ADC_CR_ADEN; + 8000660: 4b14 ldr r3, [pc, #80] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000662: 689a ldr r2, [r3, #8] + 8000664: 4b13 ldr r3, [pc, #76] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000666: 2101 movs r1, #1 + 8000668: 430a orrs r2, r1 + 800066a: 609a str r2, [r3, #8] + ADC1->CR |= ADC_CR_ADSTART; + 800066c: 4b11 ldr r3, [pc, #68] ; (80006b4 <adc_configure_scope_mode+0x98>) + 800066e: 689a ldr r2, [r3, #8] + 8000670: 4b10 ldr r3, [pc, #64] ; (80006b4 <adc_configure_scope_mode+0x98>) + 8000672: 2104 movs r1, #4 + 8000674: 430a orrs r2, r1 + 8000676: 609a str r2, [r3, #8] + + /* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us. + Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this + would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */ + int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6; + 8000678: 687b ldr r3, [r7, #4] + 800067a: 4a10 ldr r2, [pc, #64] ; (80006bc <adc_configure_scope_mode+0xa0>) + 800067c: 4293 cmp r3, r2 + 800067e: dd06 ble.n 800068e <adc_configure_scope_mode+0x72> + 8000680: 687b ldr r3, [r7, #4] + 8000682: 21fa movs r1, #250 ; 0xfa + 8000684: 0018 movs r0, r3 + 8000686: f001 f819 bl 80016bc <__divsi3> + 800068a: 0003 movs r3, r0 + 800068c: e000 b.n 8000690 <adc_configure_scope_mode+0x74> + 800068e: 2306 movs r3, #6 + 8000690: 60fb str r3, [r7, #12] + if (cycles > 0xffff) + 8000692: 68fa ldr r2, [r7, #12] + 8000694: 2380 movs r3, #128 ; 0x80 + 8000696: 025b lsls r3, r3, #9 + 8000698: 429a cmp r2, r3 + 800069a: db01 blt.n 80006a0 <adc_configure_scope_mode+0x84> + cycles = 0xffff; + 800069c: 4b08 ldr r3, [pc, #32] ; (80006c0 <adc_configure_scope_mode+0xa4>) + 800069e: 60fb str r3, [r7, #12] + adc_timer_init(12/*250ns/tick*/, cycles); + 80006a0: 68fb ldr r3, [r7, #12] + 80006a2: 0019 movs r1, r3 + 80006a4: 200c movs r0, #12 + 80006a6: f000 f83d bl 8000724 <adc_timer_init> +} + 80006aa: 46c0 nop ; (mov r8, r8) + 80006ac: 46bd mov sp, r7 + 80006ae: b004 add sp, #16 + 80006b0: bd80 pop {r7, pc} + 80006b2: 46c0 nop ; (mov r8, r8) + 80006b4: 40012400 .word 0x40012400 + 80006b8: 00000843 .word 0x00000843 + 80006bc: 000005dc .word 0x000005dc + 80006c0: 0000ffff .word 0x0000ffff + +080006c4 <adc_dma_init>: + +/* FIXME figure out the proper place to configure this. */ +#define ADC_TIMER_INTERVAL_US 20 + +static void adc_dma_init(int burstlen) { + 80006c4: b580 push {r7, lr} + 80006c6: b082 sub sp, #8 + 80006c8: af00 add r7, sp, #0 + 80006ca: 6078 str r0, [r7, #4] + /* Configure DMA 1 Channel 1 to get rid of all the data */ + DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR; + 80006cc: 4b11 ldr r3, [pc, #68] ; (8000714 <adc_dma_init+0x50>) + 80006ce: 4a12 ldr r2, [pc, #72] ; (8000718 <adc_dma_init+0x54>) + 80006d0: 609a str r2, [r3, #8] + DMA1_Channel1->CMAR = (unsigned int)&adc_buf; + 80006d2: 4b10 ldr r3, [pc, #64] ; (8000714 <adc_dma_init+0x50>) + 80006d4: 4a11 ldr r2, [pc, #68] ; (800071c <adc_dma_init+0x58>) + 80006d6: 60da str r2, [r3, #12] + DMA1_Channel1->CNDTR = burstlen; + 80006d8: 4b0e ldr r3, [pc, #56] ; (8000714 <adc_dma_init+0x50>) + 80006da: 687a ldr r2, [r7, #4] + 80006dc: 605a str r2, [r3, #4] + DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos); + 80006de: 4b0d ldr r3, [pc, #52] ; (8000714 <adc_dma_init+0x50>) + 80006e0: 2200 movs r2, #0 + 80006e2: 601a str r2, [r3, #0] + DMA1_Channel1->CCR |= + 80006e4: 4b0b ldr r3, [pc, #44] ; (8000714 <adc_dma_init+0x50>) + 80006e6: 681a ldr r2, [r3, #0] + 80006e8: 4b0a ldr r3, [pc, #40] ; (8000714 <adc_dma_init+0x50>) + 80006ea: 490d ldr r1, [pc, #52] ; (8000720 <adc_dma_init+0x5c>) + 80006ec: 430a orrs r2, r1 + 80006ee: 601a str r2, [r3, #0] + | (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */ + | DMA_CCR_MINC + | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ + + /* triggered on transfer completion. We use this to process the ADC data */ + NVIC_EnableIRQ(DMA1_Channel1_IRQn); + 80006f0: 2009 movs r0, #9 + 80006f2: f7ff ff0f bl 8000514 <NVIC_EnableIRQ> + NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5); + 80006f6: 2140 movs r1, #64 ; 0x40 + 80006f8: 2009 movs r0, #9 + 80006fa: f7ff ff21 bl 8000540 <NVIC_SetPriority> + + DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */ + 80006fe: 4b05 ldr r3, [pc, #20] ; (8000714 <adc_dma_init+0x50>) + 8000700: 681a ldr r2, [r3, #0] + 8000702: 4b04 ldr r3, [pc, #16] ; (8000714 <adc_dma_init+0x50>) + 8000704: 2101 movs r1, #1 + 8000706: 430a orrs r2, r1 + 8000708: 601a str r2, [r3, #0] +} + 800070a: 46c0 nop ; (mov r8, r8) + 800070c: 46bd mov sp, r7 + 800070e: b002 add sp, #8 + 8000710: bd80 pop {r7, pc} + 8000712: 46c0 nop ; (mov r8, r8) + 8000714: 40020008 .word 0x40020008 + 8000718: 40012440 .word 0x40012440 + 800071c: 200000c8 .word 0x200000c8 + 8000720: 000005a2 .word 0x000005a2 + +08000724 <adc_timer_init>: + +static void adc_timer_init(int psc, int ivl) { + 8000724: b580 push {r7, lr} + 8000726: b082 sub sp, #8 + 8000728: af00 add r7, sp, #0 + 800072a: 6078 str r0, [r7, #4] + 800072c: 6039 str r1, [r7, #0] + TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */ + 800072e: 4b15 ldr r3, [pc, #84] ; (8000784 <adc_timer_init+0x60>) + 8000730: 2280 movs r2, #128 ; 0x80 + 8000732: 0212 lsls r2, r2, #8 + 8000734: 645a str r2, [r3, #68] ; 0x44 + TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */ + 8000736: 4b13 ldr r3, [pc, #76] ; (8000784 <adc_timer_init+0x60>) + 8000738: 22c0 movs r2, #192 ; 0xc0 + 800073a: 01d2 lsls r2, r2, #7 + 800073c: 61da str r2, [r3, #28] + TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */ + 800073e: 4b11 ldr r3, [pc, #68] ; (8000784 <adc_timer_init+0x60>) + 8000740: 2280 movs r2, #128 ; 0x80 + 8000742: 0152 lsls r2, r2, #5 + 8000744: 621a str r2, [r3, #32] + TIM1->CCR4 = 1; /* Trigger at start of timer cycle */ + 8000746: 4b0f ldr r3, [pc, #60] ; (8000784 <adc_timer_init+0x60>) + 8000748: 2201 movs r2, #1 + 800074a: 641a str r2, [r3, #64] ; 0x40 + /* Set prescaler and interval */ + TIM1->PSC = psc-1; + 800074c: 687b ldr r3, [r7, #4] + 800074e: 1e5a subs r2, r3, #1 + 8000750: 4b0c ldr r3, [pc, #48] ; (8000784 <adc_timer_init+0x60>) + 8000752: 629a str r2, [r3, #40] ; 0x28 + TIM1->ARR = ivl-1; + 8000754: 683b ldr r3, [r7, #0] + 8000756: 1e5a subs r2, r3, #1 + 8000758: 4b0a ldr r3, [pc, #40] ; (8000784 <adc_timer_init+0x60>) + 800075a: 62da str r2, [r3, #44] ; 0x2c + /* Preload all values */ + TIM1->EGR |= TIM_EGR_UG; + 800075c: 4b09 ldr r3, [pc, #36] ; (8000784 <adc_timer_init+0x60>) + 800075e: 695a ldr r2, [r3, #20] + 8000760: 4b08 ldr r3, [pc, #32] ; (8000784 <adc_timer_init+0x60>) + 8000762: 2101 movs r1, #1 + 8000764: 430a orrs r2, r1 + 8000766: 615a str r2, [r3, #20] + TIM1->CR1 = TIM_CR1_ARPE; + 8000768: 4b06 ldr r3, [pc, #24] ; (8000784 <adc_timer_init+0x60>) + 800076a: 2280 movs r2, #128 ; 0x80 + 800076c: 601a str r2, [r3, #0] + /* And... go! */ + TIM1->CR1 |= TIM_CR1_CEN; + 800076e: 4b05 ldr r3, [pc, #20] ; (8000784 <adc_timer_init+0x60>) + 8000770: 681a ldr r2, [r3, #0] + 8000772: 4b04 ldr r3, [pc, #16] ; (8000784 <adc_timer_init+0x60>) + 8000774: 2101 movs r1, #1 + 8000776: 430a orrs r2, r1 + 8000778: 601a str r2, [r3, #0] +} + 800077a: 46c0 nop ; (mov r8, r8) + 800077c: 46bd mov sp, r7 + 800077e: b002 add sp, #8 + 8000780: bd80 pop {r7, pc} + 8000782: 46c0 nop ; (mov r8, r8) + 8000784: 40012c00 .word 0x40012c00 + +08000788 <gdb_dump>: + +/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */ +static void gdb_dump(void) { + 8000788: b580 push {r7, lr} + 800078a: af00 add r7, sp, #0 +} + 800078c: 46c0 nop ; (mov r8, r8) + 800078e: 46bd mov sp, r7 + 8000790: bd80 pop {r7, pc} + +08000792 <DMA1_Channel1_IRQHandler>: + +void DMA1_Channel1_IRQHandler(void) { + 8000792: b580 push {r7, lr} + 8000794: af00 add r7, sp, #0 + /* Clear the interrupt flag */ + DMA1->IFCR |= DMA_IFCR_CGIF1; + 8000796: 4b05 ldr r3, [pc, #20] ; (80007ac <DMA1_Channel1_IRQHandler+0x1a>) + 8000798: 685a ldr r2, [r3, #4] + 800079a: 4b04 ldr r3, [pc, #16] ; (80007ac <DMA1_Channel1_IRQHandler+0x1a>) + 800079c: 2101 movs r1, #1 + 800079e: 430a orrs r2, r1 + 80007a0: 605a str r2, [r3, #4] + gdb_dump(); + 80007a2: f7ff fff1 bl 8000788 <gdb_dump> + adc_buf[i] = -255; + } + } + } + */ +} + 80007a6: 46c0 nop ; (mov r8, r8) + 80007a8: 46bd mov sp, r7 + 80007aa: bd80 pop {r7, pc} + 80007ac: 40020000 .word 0x40020000 + +080007b0 <NVIC_EnableIRQ>: +{ + 80007b0: b580 push {r7, lr} + 80007b2: b082 sub sp, #8 + 80007b4: af00 add r7, sp, #0 + 80007b6: 0002 movs r2, r0 + 80007b8: 1dfb adds r3, r7, #7 + 80007ba: 701a strb r2, [r3, #0] + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 80007bc: 1dfb adds r3, r7, #7 + 80007be: 781b ldrb r3, [r3, #0] + 80007c0: 001a movs r2, r3 + 80007c2: 231f movs r3, #31 + 80007c4: 401a ands r2, r3 + 80007c6: 4b04 ldr r3, [pc, #16] ; (80007d8 <NVIC_EnableIRQ+0x28>) + 80007c8: 2101 movs r1, #1 + 80007ca: 4091 lsls r1, r2 + 80007cc: 000a movs r2, r1 + 80007ce: 601a str r2, [r3, #0] +} + 80007d0: 46c0 nop ; (mov r8, r8) + 80007d2: 46bd mov sp, r7 + 80007d4: b002 add sp, #8 + 80007d6: bd80 pop {r7, pc} + 80007d8: e000e100 .word 0xe000e100 + +080007dc <NVIC_DisableIRQ>: +{ + 80007dc: b580 push {r7, lr} + 80007de: b082 sub sp, #8 + 80007e0: af00 add r7, sp, #0 + 80007e2: 0002 movs r2, r0 + 80007e4: 1dfb adds r3, r7, #7 + 80007e6: 701a strb r2, [r3, #0] + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); + 80007e8: 1dfb adds r3, r7, #7 + 80007ea: 781b ldrb r3, [r3, #0] + 80007ec: 001a movs r2, r3 + 80007ee: 231f movs r3, #31 + 80007f0: 4013 ands r3, r2 + 80007f2: 4905 ldr r1, [pc, #20] ; (8000808 <NVIC_DisableIRQ+0x2c>) + 80007f4: 2201 movs r2, #1 + 80007f6: 409a lsls r2, r3 + 80007f8: 0013 movs r3, r2 + 80007fa: 2280 movs r2, #128 ; 0x80 + 80007fc: 508b str r3, [r1, r2] +} + 80007fe: 46c0 nop ; (mov r8, r8) + 8000800: 46bd mov sp, r7 + 8000802: b002 add sp, #8 + 8000804: bd80 pop {r7, pc} + 8000806: 46c0 nop ; (mov r8, r8) + 8000808: e000e100 .word 0xe000e100 + +0800080c <NVIC_SetPriority>: +{ + 800080c: b590 push {r4, r7, lr} + 800080e: b083 sub sp, #12 + 8000810: af00 add r7, sp, #0 + 8000812: 0002 movs r2, r0 + 8000814: 6039 str r1, [r7, #0] + 8000816: 1dfb adds r3, r7, #7 + 8000818: 701a strb r2, [r3, #0] + if ((int32_t)(IRQn) < 0) + 800081a: 1dfb adds r3, r7, #7 + 800081c: 781b ldrb r3, [r3, #0] + 800081e: 2b7f cmp r3, #127 ; 0x7f + 8000820: d932 bls.n 8000888 <NVIC_SetPriority+0x7c> + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000822: 4a2f ldr r2, [pc, #188] ; (80008e0 <NVIC_SetPriority+0xd4>) + 8000824: 1dfb adds r3, r7, #7 + 8000826: 781b ldrb r3, [r3, #0] + 8000828: 0019 movs r1, r3 + 800082a: 230f movs r3, #15 + 800082c: 400b ands r3, r1 + 800082e: 3b08 subs r3, #8 + 8000830: 089b lsrs r3, r3, #2 + 8000832: 3306 adds r3, #6 + 8000834: 009b lsls r3, r3, #2 + 8000836: 18d3 adds r3, r2, r3 + 8000838: 3304 adds r3, #4 + 800083a: 681b ldr r3, [r3, #0] + 800083c: 1dfa adds r2, r7, #7 + 800083e: 7812 ldrb r2, [r2, #0] + 8000840: 0011 movs r1, r2 + 8000842: 2203 movs r2, #3 + 8000844: 400a ands r2, r1 + 8000846: 00d2 lsls r2, r2, #3 + 8000848: 21ff movs r1, #255 ; 0xff + 800084a: 4091 lsls r1, r2 + 800084c: 000a movs r2, r1 + 800084e: 43d2 mvns r2, r2 + 8000850: 401a ands r2, r3 + 8000852: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 8000854: 683b ldr r3, [r7, #0] + 8000856: 019b lsls r3, r3, #6 + 8000858: 22ff movs r2, #255 ; 0xff + 800085a: 401a ands r2, r3 + 800085c: 1dfb adds r3, r7, #7 + 800085e: 781b ldrb r3, [r3, #0] + 8000860: 0018 movs r0, r3 + 8000862: 2303 movs r3, #3 + 8000864: 4003 ands r3, r0 + 8000866: 00db lsls r3, r3, #3 + 8000868: 409a lsls r2, r3 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 800086a: 481d ldr r0, [pc, #116] ; (80008e0 <NVIC_SetPriority+0xd4>) + 800086c: 1dfb adds r3, r7, #7 + 800086e: 781b ldrb r3, [r3, #0] + 8000870: 001c movs r4, r3 + 8000872: 230f movs r3, #15 + 8000874: 4023 ands r3, r4 + 8000876: 3b08 subs r3, #8 + 8000878: 089b lsrs r3, r3, #2 + 800087a: 430a orrs r2, r1 + 800087c: 3306 adds r3, #6 + 800087e: 009b lsls r3, r3, #2 + 8000880: 18c3 adds r3, r0, r3 + 8000882: 3304 adds r3, #4 + 8000884: 601a str r2, [r3, #0] +} + 8000886: e027 b.n 80008d8 <NVIC_SetPriority+0xcc> + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000888: 4a16 ldr r2, [pc, #88] ; (80008e4 <NVIC_SetPriority+0xd8>) + 800088a: 1dfb adds r3, r7, #7 + 800088c: 781b ldrb r3, [r3, #0] + 800088e: b25b sxtb r3, r3 + 8000890: 089b lsrs r3, r3, #2 + 8000892: 33c0 adds r3, #192 ; 0xc0 + 8000894: 009b lsls r3, r3, #2 + 8000896: 589b ldr r3, [r3, r2] + 8000898: 1dfa adds r2, r7, #7 + 800089a: 7812 ldrb r2, [r2, #0] + 800089c: 0011 movs r1, r2 + 800089e: 2203 movs r2, #3 + 80008a0: 400a ands r2, r1 + 80008a2: 00d2 lsls r2, r2, #3 + 80008a4: 21ff movs r1, #255 ; 0xff + 80008a6: 4091 lsls r1, r2 + 80008a8: 000a movs r2, r1 + 80008aa: 43d2 mvns r2, r2 + 80008ac: 401a ands r2, r3 + 80008ae: 0011 movs r1, r2 + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + 80008b0: 683b ldr r3, [r7, #0] + 80008b2: 019b lsls r3, r3, #6 + 80008b4: 22ff movs r2, #255 ; 0xff + 80008b6: 401a ands r2, r3 + 80008b8: 1dfb adds r3, r7, #7 + 80008ba: 781b ldrb r3, [r3, #0] + 80008bc: 0018 movs r0, r3 + 80008be: 2303 movs r3, #3 + 80008c0: 4003 ands r3, r0 + 80008c2: 00db lsls r3, r3, #3 + 80008c4: 409a lsls r2, r3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80008c6: 4807 ldr r0, [pc, #28] ; (80008e4 <NVIC_SetPriority+0xd8>) + 80008c8: 1dfb adds r3, r7, #7 + 80008ca: 781b ldrb r3, [r3, #0] + 80008cc: b25b sxtb r3, r3 + 80008ce: 089b lsrs r3, r3, #2 + 80008d0: 430a orrs r2, r1 + 80008d2: 33c0 adds r3, #192 ; 0xc0 + 80008d4: 009b lsls r3, r3, #2 + 80008d6: 501a str r2, [r3, r0] +} + 80008d8: 46c0 nop ; (mov r8, r8) + 80008da: 46bd mov sp, r7 + 80008dc: b003 add sp, #12 + 80008de: bd90 pop {r4, r7, pc} + 80008e0: e000ed00 .word 0xe000ed00 + 80008e4: e000e100 .word 0xe000e100 + +080008e8 <usart_dma_init>: + +volatile struct dma_tx_buf usart_tx_buf; + +static void usart_schedule_dma(); + +void usart_dma_init() { + 80008e8: b580 push {r7, lr} + 80008ea: af00 add r7, sp, #0 + usart_tx_buf.xfr_start = -1, + 80008ec: 4b17 ldr r3, [pc, #92] ; (800094c <usart_dma_init+0x64>) + 80008ee: 2201 movs r2, #1 + 80008f0: 4252 negs r2, r2 + 80008f2: 601a str r2, [r3, #0] + usart_tx_buf.xfr_end = 0, + 80008f4: 4b15 ldr r3, [pc, #84] ; (800094c <usart_dma_init+0x64>) + 80008f6: 2200 movs r2, #0 + 80008f8: 605a str r2, [r3, #4] + usart_tx_buf.wr_pos = 0, + 80008fa: 4b14 ldr r3, [pc, #80] ; (800094c <usart_dma_init+0x64>) + 80008fc: 2200 movs r2, #0 + 80008fe: 609a str r2, [r3, #8] + + /* Configure DMA 1 Channel 2 to handle uart transmission */ + DMA1_Channel2->CPAR = (unsigned int)&(USART1->TDR); + 8000900: 4b13 ldr r3, [pc, #76] ; (8000950 <usart_dma_init+0x68>) + 8000902: 4a14 ldr r2, [pc, #80] ; (8000954 <usart_dma_init+0x6c>) + 8000904: 609a str r2, [r3, #8] + DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos) + 8000906: 4b12 ldr r3, [pc, #72] ; (8000950 <usart_dma_init+0x68>) + 8000908: 2292 movs r2, #146 ; 0x92 + 800090a: 601a str r2, [r3, #0] + | (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */ + | DMA_CCR_MINC + | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ + + /* triggered on transfer completion. We use this to process the ADC data */ + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + 800090c: 200a movs r0, #10 + 800090e: f7ff ff4f bl 80007b0 <NVIC_EnableIRQ> + NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5); + 8000912: 2120 movs r1, #32 + 8000914: 200a movs r0, #10 + 8000916: f7ff ff79 bl 800080c <NVIC_SetPriority> + + USART1->CR1 = /* 8-bit -> M1, M0 clear */ + 800091a: 4b0f ldr r3, [pc, #60] ; (8000958 <usart_dma_init+0x70>) + 800091c: 4a0f ldr r2, [pc, #60] ; (800095c <usart_dma_init+0x74>) + 800091e: 601a str r2, [r3, #0] + | USART_CR1_RXNEIE /* Enable receive interrupt */ + /* other interrupts clear */ + | USART_CR1_TE + | USART_CR1_RE; + /* Set divider for 1MBd @48MHz system clock. */ + USART1->BRR = 48; + 8000920: 4b0d ldr r3, [pc, #52] ; (8000958 <usart_dma_init+0x70>) + 8000922: 2230 movs r2, #48 ; 0x30 + 8000924: 60da str r2, [r3, #12] + + USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV; + 8000926: 4b0c ldr r3, [pc, #48] ; (8000958 <usart_dma_init+0x70>) + 8000928: 22c0 movs r2, #192 ; 0xc0 + 800092a: 0292 lsls r2, r2, #10 + 800092c: 605a str r2, [r3, #4] + + USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */ + 800092e: 4b0a ldr r3, [pc, #40] ; (8000958 <usart_dma_init+0x70>) + 8000930: 689a ldr r2, [r3, #8] + 8000932: 4b09 ldr r3, [pc, #36] ; (8000958 <usart_dma_init+0x70>) + 8000934: 2180 movs r1, #128 ; 0x80 + 8000936: 430a orrs r2, r1 + 8000938: 609a str r2, [r3, #8] + /* Enable receive interrupt */ + //NVIC_EnableIRQ(USART1_IRQn); + //NVIC_SetPriority(USART1_IRQn, 1); + + /* And... go! */ + USART1->CR1 |= USART_CR1_UE; + 800093a: 4b07 ldr r3, [pc, #28] ; (8000958 <usart_dma_init+0x70>) + 800093c: 681a ldr r2, [r3, #0] + 800093e: 4b06 ldr r3, [pc, #24] ; (8000958 <usart_dma_init+0x70>) + 8000940: 2101 movs r1, #1 + 8000942: 430a orrs r2, r1 + 8000944: 601a str r2, [r3, #0] +} + 8000946: 46c0 nop ; (mov r8, r8) + 8000948: 46bd mov sp, r7 + 800094a: bd80 pop {r7, pc} + 800094c: 200008c8 .word 0x200008c8 + 8000950: 4002001c .word 0x4002001c + 8000954: 40013828 .word 0x40013828 + 8000958: 40013800 .word 0x40013800 + 800095c: 0000202c .word 0x0000202c + +08000960 <usart_schedule_dma>: + +void usart_schedule_dma() { + 8000960: b580 push {r7, lr} + 8000962: b084 sub sp, #16 + 8000964: af00 add r7, sp, #0 + /* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ + * disables. */ + volatile struct dma_tx_buf *buf = &usart_tx_buf; + 8000966: 4b19 ldr r3, [pc, #100] ; (80009cc <usart_schedule_dma+0x6c>) + 8000968: 60bb str r3, [r7, #8] + + size_t xfr_len, xfr_start = buf->xfr_end; + 800096a: 68bb ldr r3, [r7, #8] + 800096c: 685b ldr r3, [r3, #4] + 800096e: 607b str r3, [r7, #4] + if (buf->wr_pos > xfr_start) /* no wraparound */ + 8000970: 68bb ldr r3, [r7, #8] + 8000972: 689b ldr r3, [r3, #8] + 8000974: 687a ldr r2, [r7, #4] + 8000976: 429a cmp r2, r3 + 8000978: d205 bcs.n 8000986 <usart_schedule_dma+0x26> + xfr_len = buf->wr_pos - xfr_start; + 800097a: 68bb ldr r3, [r7, #8] + 800097c: 689a ldr r2, [r3, #8] + 800097e: 687b ldr r3, [r7, #4] + 8000980: 1ad3 subs r3, r2, r3 + 8000982: 60fb str r3, [r7, #12] + 8000984: e004 b.n 8000990 <usart_schedule_dma+0x30> + else /* wraparound */ + xfr_len = sizeof(buf->data) - xfr_start; /* schedule transfer until end of buffer */ + 8000986: 687b ldr r3, [r7, #4] + 8000988: 2280 movs r2, #128 ; 0x80 + 800098a: 0052 lsls r2, r2, #1 + 800098c: 1ad3 subs r3, r2, r3 + 800098e: 60fb str r3, [r7, #12] + + buf->xfr_start = xfr_start; + 8000990: 68bb ldr r3, [r7, #8] + 8000992: 687a ldr r2, [r7, #4] + 8000994: 601a str r2, [r3, #0] + buf->xfr_end = (xfr_start + xfr_len) % sizeof(buf->data); /* handle wraparound */ + 8000996: 687a ldr r2, [r7, #4] + 8000998: 68fb ldr r3, [r7, #12] + 800099a: 18d3 adds r3, r2, r3 + 800099c: 22ff movs r2, #255 ; 0xff + 800099e: 401a ands r2, r3 + 80009a0: 68bb ldr r3, [r7, #8] + 80009a2: 605a str r2, [r3, #4] + + /* initiate transmission of new buffer */ + DMA1_Channel2->CMAR = (uint32_t)(buf->data + xfr_start); + 80009a4: 68bb ldr r3, [r7, #8] + 80009a6: 330c adds r3, #12 + 80009a8: 001a movs r2, r3 + 80009aa: 687b ldr r3, [r7, #4] + 80009ac: 18d2 adds r2, r2, r3 + 80009ae: 4b08 ldr r3, [pc, #32] ; (80009d0 <usart_schedule_dma+0x70>) + 80009b0: 60da str r2, [r3, #12] + DMA1_Channel2->CNDTR = xfr_len; + 80009b2: 4b07 ldr r3, [pc, #28] ; (80009d0 <usart_schedule_dma+0x70>) + 80009b4: 68fa ldr r2, [r7, #12] + 80009b6: 605a str r2, [r3, #4] + DMA1_Channel2->CCR |= DMA_CCR_EN; + 80009b8: 4b05 ldr r3, [pc, #20] ; (80009d0 <usart_schedule_dma+0x70>) + 80009ba: 681a ldr r2, [r3, #0] + 80009bc: 4b04 ldr r3, [pc, #16] ; (80009d0 <usart_schedule_dma+0x70>) + 80009be: 2101 movs r1, #1 + 80009c0: 430a orrs r2, r1 + 80009c2: 601a str r2, [r3, #0] +} + 80009c4: 46c0 nop ; (mov r8, r8) + 80009c6: 46bd mov sp, r7 + 80009c8: b004 add sp, #16 + 80009ca: bd80 pop {r7, pc} + 80009cc: 200008c8 .word 0x200008c8 + 80009d0: 4002001c .word 0x4002001c + +080009d4 <usart_dma_fifo_push>: + +int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, char c) { + 80009d4: b580 push {r7, lr} + 80009d6: b082 sub sp, #8 + 80009d8: af00 add r7, sp, #0 + 80009da: 6078 str r0, [r7, #4] + 80009dc: 000a movs r2, r1 + 80009de: 1cfb adds r3, r7, #3 + 80009e0: 701a strb r2, [r3, #0] + /* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */ + NVIC_DisableIRQ(DMA1_Channel2_3_IRQn); + 80009e2: 200a movs r0, #10 + 80009e4: f7ff fefa bl 80007dc <NVIC_DisableIRQ> + + if (buf->wr_pos == buf->xfr_start) { + 80009e8: 687b ldr r3, [r7, #4] + 80009ea: 689a ldr r2, [r3, #8] + 80009ec: 687b ldr r3, [r7, #4] + 80009ee: 681b ldr r3, [r3, #0] + 80009f0: 429a cmp r2, r3 + 80009f2: d105 bne.n 8000a00 <usart_dma_fifo_push+0x2c> + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + 80009f4: 200a movs r0, #10 + 80009f6: f7ff fedb bl 80007b0 <NVIC_EnableIRQ> + return -EBUSY; + 80009fa: 2310 movs r3, #16 + 80009fc: 425b negs r3, r3 + 80009fe: e011 b.n 8000a24 <usart_dma_fifo_push+0x50> + } + + buf->data[buf->wr_pos] = c; + 8000a00: 687b ldr r3, [r7, #4] + 8000a02: 689b ldr r3, [r3, #8] + 8000a04: 687a ldr r2, [r7, #4] + 8000a06: 18d3 adds r3, r2, r3 + 8000a08: 1cfa adds r2, r7, #3 + 8000a0a: 7812 ldrb r2, [r2, #0] + 8000a0c: 731a strb r2, [r3, #12] + buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data); + 8000a0e: 687b ldr r3, [r7, #4] + 8000a10: 689b ldr r3, [r3, #8] + 8000a12: 3301 adds r3, #1 + 8000a14: 22ff movs r2, #255 ; 0xff + 8000a16: 401a ands r2, r3 + 8000a18: 687b ldr r3, [r7, #4] + 8000a1a: 609a str r2, [r3, #8] + + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + 8000a1c: 200a movs r0, #10 + 8000a1e: f7ff fec7 bl 80007b0 <NVIC_EnableIRQ> + return 0; + 8000a22: 2300 movs r3, #0 +} + 8000a24: 0018 movs r0, r3 + 8000a26: 46bd mov sp, r7 + 8000a28: b002 add sp, #8 + 8000a2a: bd80 pop {r7, pc} + +08000a2c <usart_putc>: + +void usart_putc(char c) { + 8000a2c: b580 push {r7, lr} + 8000a2e: b082 sub sp, #8 + 8000a30: af00 add r7, sp, #0 + 8000a32: 0002 movs r2, r0 + 8000a34: 1dfb adds r3, r7, #7 + 8000a36: 701a strb r2, [r3, #0] + /* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */ + while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) { + 8000a38: 46c0 nop ; (mov r8, r8) + 8000a3a: 1dfb adds r3, r7, #7 + 8000a3c: 781a ldrb r2, [r3, #0] + 8000a3e: 4b06 ldr r3, [pc, #24] ; (8000a58 <usart_putc+0x2c>) + 8000a40: 0011 movs r1, r2 + 8000a42: 0018 movs r0, r3 + 8000a44: f7ff ffc6 bl 80009d4 <usart_dma_fifo_push> + 8000a48: 0003 movs r3, r0 + 8000a4a: 3310 adds r3, #16 + 8000a4c: d0f5 beq.n 8000a3a <usart_putc+0xe> + /* idle */ + } +} + 8000a4e: 46c0 nop ; (mov r8, r8) + 8000a50: 46c0 nop ; (mov r8, r8) + 8000a52: 46bd mov sp, r7 + 8000a54: b002 add sp, #8 + 8000a56: bd80 pop {r7, pc} + 8000a58: 200008c8 .word 0x200008c8 + +08000a5c <DMA1_Channel2_3_IRQHandler>: + +void DMA1_Channel2_3_IRQHandler(void) { + 8000a5c: b580 push {r7, lr} + 8000a5e: af00 add r7, sp, #0 + /* Transfer complete */ + DMA1->IFCR |= DMA_IFCR_CTCIF2; + 8000a60: 4b0b ldr r3, [pc, #44] ; (8000a90 <DMA1_Channel2_3_IRQHandler+0x34>) + 8000a62: 685a ldr r2, [r3, #4] + 8000a64: 4b0a ldr r3, [pc, #40] ; (8000a90 <DMA1_Channel2_3_IRQHandler+0x34>) + 8000a66: 2120 movs r1, #32 + 8000a68: 430a orrs r2, r1 + 8000a6a: 605a str r2, [r3, #4] + + DMA1_Channel2->CCR &= ~DMA_CCR_EN; + 8000a6c: 4b09 ldr r3, [pc, #36] ; (8000a94 <DMA1_Channel2_3_IRQHandler+0x38>) + 8000a6e: 681a ldr r2, [r3, #0] + 8000a70: 4b08 ldr r3, [pc, #32] ; (8000a94 <DMA1_Channel2_3_IRQHandler+0x38>) + 8000a72: 2101 movs r1, #1 + 8000a74: 438a bics r2, r1 + 8000a76: 601a str r2, [r3, #0] + if (usart_tx_buf.wr_pos != usart_tx_buf.xfr_end) /* buffer not empty */ + 8000a78: 4b07 ldr r3, [pc, #28] ; (8000a98 <DMA1_Channel2_3_IRQHandler+0x3c>) + 8000a7a: 689a ldr r2, [r3, #8] + 8000a7c: 4b06 ldr r3, [pc, #24] ; (8000a98 <DMA1_Channel2_3_IRQHandler+0x3c>) + 8000a7e: 685b ldr r3, [r3, #4] + 8000a80: 429a cmp r2, r3 + 8000a82: d001 beq.n 8000a88 <DMA1_Channel2_3_IRQHandler+0x2c> + usart_schedule_dma(); + 8000a84: f7ff ff6c bl 8000960 <usart_schedule_dma> +} + 8000a88: 46c0 nop ; (mov r8, r8) + 8000a8a: 46bd mov sp, r7 + 8000a8c: bd80 pop {r7, pc} + 8000a8e: 46c0 nop ; (mov r8, r8) + 8000a90: 40020000 .word 0x40020000 + 8000a94: 4002001c .word 0x4002001c + 8000a98: 200008c8 .word 0x200008c8 + +08000a9c <usart_send_packet>: + +void usart_send_packet(const uint8_t *data, size_t len) { + 8000a9c: b580 push {r7, lr} + 8000a9e: b082 sub sp, #8 + 8000aa0: af00 add r7, sp, #0 + 8000aa2: 6078 str r0, [r7, #4] + 8000aa4: 6039 str r1, [r7, #0] + /* ignore return value as putf is blocking and always succeeds */ + (void)cobs_encode_usart((char *)data, len); + 8000aa6: 683a ldr r2, [r7, #0] + 8000aa8: 687b ldr r3, [r7, #4] + 8000aaa: 0011 movs r1, r2 + 8000aac: 0018 movs r0, r3 + 8000aae: f000 f870 bl 8000b92 <cobs_encode_usart> + + /* If the DMA stream is idle right now, schedule a transfer */ + if (!(DMA1_Channel2->CCR & DMA_CCR_EN)) + 8000ab2: 4b05 ldr r3, [pc, #20] ; (8000ac8 <usart_send_packet+0x2c>) + 8000ab4: 681b ldr r3, [r3, #0] + 8000ab6: 2201 movs r2, #1 + 8000ab8: 4013 ands r3, r2 + 8000aba: d101 bne.n 8000ac0 <usart_send_packet+0x24> + usart_schedule_dma(); + 8000abc: f7ff ff50 bl 8000960 <usart_schedule_dma> +} + 8000ac0: 46c0 nop ; (mov r8, r8) + 8000ac2: 46bd mov sp, r7 + 8000ac4: b002 add sp, #8 + 8000ac6: bd80 pop {r7, pc} + 8000ac8: 4002001c .word 0x4002001c + +08000acc <cobs_encode>: + @ ensures \result == -1; + @ + @ complete behaviors; + @ disjoint behaviors; + @*/ +ssize_t cobs_encode(char *dst, size_t dstlen, char *src, size_t srclen) { + 8000acc: b580 push {r7, lr} + 8000ace: b088 sub sp, #32 + 8000ad0: af00 add r7, sp, #0 + 8000ad2: 60f8 str r0, [r7, #12] + 8000ad4: 60b9 str r1, [r7, #8] + 8000ad6: 607a str r2, [r7, #4] + 8000ad8: 603b str r3, [r7, #0] + if (dstlen > 65535 || srclen > 254) + 8000ada: 68ba ldr r2, [r7, #8] + 8000adc: 2380 movs r3, #128 ; 0x80 + 8000ade: 025b lsls r3, r3, #9 + 8000ae0: 429a cmp r2, r3 + 8000ae2: d202 bcs.n 8000aea <cobs_encode+0x1e> + 8000ae4: 683b ldr r3, [r7, #0] + 8000ae6: 2bfe cmp r3, #254 ; 0xfe + 8000ae8: d902 bls.n 8000af0 <cobs_encode+0x24> + return -1; + 8000aea: 2301 movs r3, #1 + 8000aec: 425b negs r3, r3 + 8000aee: e04c b.n 8000b8a <cobs_encode+0xbe> + //@ assert 0 <= dstlen <= 65535 && 0 <= srclen <= 254; + + if (dstlen < srclen+2) + 8000af0: 683b ldr r3, [r7, #0] + 8000af2: 3302 adds r3, #2 + 8000af4: 68ba ldr r2, [r7, #8] + 8000af6: 429a cmp r2, r3 + 8000af8: d202 bcs.n 8000b00 <cobs_encode+0x34> + return -1; + 8000afa: 2301 movs r3, #1 + 8000afc: 425b negs r3, r3 + 8000afe: e044 b.n 8000b8a <cobs_encode+0xbe> + //@ assert 0 <= srclen < srclen+2 <= dstlen; + + size_t p = 0; + 8000b00: 2300 movs r3, #0 + 8000b02: 61fb str r3, [r7, #28] + @ loop invariant \forall integer i; 0 <= i < p ==> dst[i] != 0; + @ loop invariant \forall integer i; 0 < i < p ==> (src[i-1] != 0 ==> dst[i] == src[i-1]); + @ loop assigns p, dst[0..srclen+1]; + @ loop variant srclen-p+1; + @*/ + while (p <= srclen) { + 8000b04: e036 b.n 8000b74 <cobs_encode+0xa8> + + char val; + if (p != 0 && src[p-1] != 0) { + 8000b06: 69fb ldr r3, [r7, #28] + 8000b08: 2b00 cmp r3, #0 + 8000b0a: d00f beq.n 8000b2c <cobs_encode+0x60> + 8000b0c: 69fb ldr r3, [r7, #28] + 8000b0e: 3b01 subs r3, #1 + 8000b10: 687a ldr r2, [r7, #4] + 8000b12: 18d3 adds r3, r2, r3 + 8000b14: 781b ldrb r3, [r3, #0] + 8000b16: 2b00 cmp r3, #0 + 8000b18: d008 beq.n 8000b2c <cobs_encode+0x60> + val = src[p-1]; + 8000b1a: 69fb ldr r3, [r7, #28] + 8000b1c: 3b01 subs r3, #1 + 8000b1e: 687a ldr r2, [r7, #4] + 8000b20: 18d2 adds r2, r2, r3 + 8000b22: 231b movs r3, #27 + 8000b24: 18fb adds r3, r7, r3 + 8000b26: 7812 ldrb r2, [r2, #0] + 8000b28: 701a strb r2, [r3, #0] + 8000b2a: e019 b.n 8000b60 <cobs_encode+0x94> + + } else { + size_t q = p; + 8000b2c: 69fb ldr r3, [r7, #28] + 8000b2e: 617b str r3, [r7, #20] + /*@ loop invariant 0 <= p <= q <= srclen; + @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0; + @ loop assigns q; + @ loop variant srclen-q; + @*/ + while (q < srclen && src[q] != 0) + 8000b30: e002 b.n 8000b38 <cobs_encode+0x6c> + q++; + 8000b32: 697b ldr r3, [r7, #20] + 8000b34: 3301 adds r3, #1 + 8000b36: 617b str r3, [r7, #20] + while (q < srclen && src[q] != 0) + 8000b38: 697a ldr r2, [r7, #20] + 8000b3a: 683b ldr r3, [r7, #0] + 8000b3c: 429a cmp r2, r3 + 8000b3e: d205 bcs.n 8000b4c <cobs_encode+0x80> + 8000b40: 687a ldr r2, [r7, #4] + 8000b42: 697b ldr r3, [r7, #20] + 8000b44: 18d3 adds r3, r2, r3 + 8000b46: 781b ldrb r3, [r3, #0] + 8000b48: 2b00 cmp r3, #0 + 8000b4a: d1f2 bne.n 8000b32 <cobs_encode+0x66> + //@ assert q == srclen || src[q] == 0; + //@ assert q <= srclen <= 254; + val = (char)q-p+1; + 8000b4c: 697b ldr r3, [r7, #20] + 8000b4e: b2da uxtb r2, r3 + 8000b50: 69fb ldr r3, [r7, #28] + 8000b52: b2db uxtb r3, r3 + 8000b54: 1ad3 subs r3, r2, r3 + 8000b56: b2da uxtb r2, r3 + 8000b58: 231b movs r3, #27 + 8000b5a: 18fb adds r3, r7, r3 + 8000b5c: 3201 adds r2, #1 + 8000b5e: 701a strb r2, [r3, #0] + //@ assert val != 0; + } + + dst[p] = val; + 8000b60: 68fa ldr r2, [r7, #12] + 8000b62: 69fb ldr r3, [r7, #28] + 8000b64: 18d3 adds r3, r2, r3 + 8000b66: 221b movs r2, #27 + 8000b68: 18ba adds r2, r7, r2 + 8000b6a: 7812 ldrb r2, [r2, #0] + 8000b6c: 701a strb r2, [r3, #0] + p++; + 8000b6e: 69fb ldr r3, [r7, #28] + 8000b70: 3301 adds r3, #1 + 8000b72: 61fb str r3, [r7, #28] + while (p <= srclen) { + 8000b74: 69fa ldr r2, [r7, #28] + 8000b76: 683b ldr r3, [r7, #0] + 8000b78: 429a cmp r2, r3 + 8000b7a: d9c4 bls.n 8000b06 <cobs_encode+0x3a> + } + + dst[p] = 0; + 8000b7c: 68fa ldr r2, [r7, #12] + 8000b7e: 69fb ldr r3, [r7, #28] + 8000b80: 18d3 adds r3, r2, r3 + 8000b82: 2200 movs r2, #0 + 8000b84: 701a strb r2, [r3, #0] + //@ assert p == srclen+1; + + return srclen+2; + 8000b86: 683b ldr r3, [r7, #0] + 8000b88: 3302 adds r3, #2 +} + 8000b8a: 0018 movs r0, r3 + 8000b8c: 46bd mov sp, r7 + 8000b8e: b008 add sp, #32 + 8000b90: bd80 pop {r7, pc} + +08000b92 <cobs_encode_usart>: + +int cobs_encode_usart(char *src, size_t srclen) { + 8000b92: b580 push {r7, lr} + 8000b94: b086 sub sp, #24 + 8000b96: af00 add r7, sp, #0 + 8000b98: 6078 str r0, [r7, #4] + 8000b9a: 6039 str r1, [r7, #0] + if (srclen > 254) + 8000b9c: 683b ldr r3, [r7, #0] + 8000b9e: 2bfe cmp r3, #254 ; 0xfe + 8000ba0: d902 bls.n 8000ba8 <cobs_encode_usart+0x16> + return -1; + 8000ba2: 2301 movs r3, #1 + 8000ba4: 425b negs r3, r3 + 8000ba6: e040 b.n 8000c2a <cobs_encode_usart+0x98> + //@ assert 0 <= srclen <= 254; + + size_t p = 0; + 8000ba8: 2300 movs r3, #0 + 8000baa: 617b str r3, [r7, #20] + /*@ loop invariant 0 <= p <= srclen+1; + @ loop assigns p; + @ loop variant srclen-p+1; + @*/ + while (p <= srclen) { + 8000bac: e035 b.n 8000c1a <cobs_encode_usart+0x88> + + char val; + if (p != 0 && src[p-1] != 0) { + 8000bae: 697b ldr r3, [r7, #20] + 8000bb0: 2b00 cmp r3, #0 + 8000bb2: d00f beq.n 8000bd4 <cobs_encode_usart+0x42> + 8000bb4: 697b ldr r3, [r7, #20] + 8000bb6: 3b01 subs r3, #1 + 8000bb8: 687a ldr r2, [r7, #4] + 8000bba: 18d3 adds r3, r2, r3 + 8000bbc: 781b ldrb r3, [r3, #0] + 8000bbe: 2b00 cmp r3, #0 + 8000bc0: d008 beq.n 8000bd4 <cobs_encode_usart+0x42> + val = src[p-1]; + 8000bc2: 697b ldr r3, [r7, #20] + 8000bc4: 3b01 subs r3, #1 + 8000bc6: 687a ldr r2, [r7, #4] + 8000bc8: 18d2 adds r2, r2, r3 + 8000bca: 2313 movs r3, #19 + 8000bcc: 18fb adds r3, r7, r3 + 8000bce: 7812 ldrb r2, [r2, #0] + 8000bd0: 701a strb r2, [r3, #0] + 8000bd2: e019 b.n 8000c08 <cobs_encode_usart+0x76> + + } else { + size_t q = p; + 8000bd4: 697b ldr r3, [r7, #20] + 8000bd6: 60fb str r3, [r7, #12] + /*@ loop invariant 0 <= p <= q <= srclen; + @ loop invariant \forall integer i; p <= i < q ==> src[i] != 0; + @ loop assigns q; + @ loop variant srclen-q; + @*/ + while (q < srclen && src[q] != 0) + 8000bd8: e002 b.n 8000be0 <cobs_encode_usart+0x4e> + q++; + 8000bda: 68fb ldr r3, [r7, #12] + 8000bdc: 3301 adds r3, #1 + 8000bde: 60fb str r3, [r7, #12] + while (q < srclen && src[q] != 0) + 8000be0: 68fa ldr r2, [r7, #12] + 8000be2: 683b ldr r3, [r7, #0] + 8000be4: 429a cmp r2, r3 + 8000be6: d205 bcs.n 8000bf4 <cobs_encode_usart+0x62> + 8000be8: 687a ldr r2, [r7, #4] + 8000bea: 68fb ldr r3, [r7, #12] + 8000bec: 18d3 adds r3, r2, r3 + 8000bee: 781b ldrb r3, [r3, #0] + 8000bf0: 2b00 cmp r3, #0 + 8000bf2: d1f2 bne.n 8000bda <cobs_encode_usart+0x48> + //@ assert q == srclen || src[q] == 0; + //@ assert q <= srclen <= 254; + val = (char)q-p+1; + 8000bf4: 68fb ldr r3, [r7, #12] + 8000bf6: b2da uxtb r2, r3 + 8000bf8: 697b ldr r3, [r7, #20] + 8000bfa: b2db uxtb r3, r3 + 8000bfc: 1ad3 subs r3, r2, r3 + 8000bfe: b2da uxtb r2, r3 + 8000c00: 2313 movs r3, #19 + 8000c02: 18fb adds r3, r7, r3 + 8000c04: 3201 adds r2, #1 + 8000c06: 701a strb r2, [r3, #0] + //@ assert val != 0; + } + + usart_putc(val); + 8000c08: 2313 movs r3, #19 + 8000c0a: 18fb adds r3, r7, r3 + 8000c0c: 781b ldrb r3, [r3, #0] + 8000c0e: 0018 movs r0, r3 + 8000c10: f7ff ff0c bl 8000a2c <usart_putc> + p++; + 8000c14: 697b ldr r3, [r7, #20] + 8000c16: 3301 adds r3, #1 + 8000c18: 617b str r3, [r7, #20] + while (p <= srclen) { + 8000c1a: 697a ldr r2, [r7, #20] + 8000c1c: 683b ldr r3, [r7, #0] + 8000c1e: 429a cmp r2, r3 + 8000c20: d9c5 bls.n 8000bae <cobs_encode_usart+0x1c> + } + + usart_putc(0); + 8000c22: 2000 movs r0, #0 + 8000c24: f7ff ff02 bl 8000a2c <usart_putc> + //@ assert p == srclen+1; + + return 0; + 8000c28: 2300 movs r3, #0 +} + 8000c2a: 0018 movs r0, r3 + 8000c2c: 46bd mov sp, r7 + 8000c2e: b006 add sp, #24 + 8000c30: bd80 pop {r7, pc} + +08000c32 <cobs_decode>: + @ ensures \result == -1; + @ + @ complete behaviors; + @ disjoint behaviors; + @*/ +ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) { + 8000c32: b580 push {r7, lr} + 8000c34: b088 sub sp, #32 + 8000c36: af00 add r7, sp, #0 + 8000c38: 60f8 str r0, [r7, #12] + 8000c3a: 60b9 str r1, [r7, #8] + 8000c3c: 607a str r2, [r7, #4] + 8000c3e: 603b str r3, [r7, #0] + if (dstlen > 65535 || srclen > 65535) + 8000c40: 68ba ldr r2, [r7, #8] + 8000c42: 2380 movs r3, #128 ; 0x80 + 8000c44: 025b lsls r3, r3, #9 + 8000c46: 429a cmp r2, r3 + 8000c48: d204 bcs.n 8000c54 <cobs_decode+0x22> + 8000c4a: 683a ldr r2, [r7, #0] + 8000c4c: 2380 movs r3, #128 ; 0x80 + 8000c4e: 025b lsls r3, r3, #9 + 8000c50: 429a cmp r2, r3 + 8000c52: d302 bcc.n 8000c5a <cobs_decode+0x28> + return -1; + 8000c54: 2301 movs r3, #1 + 8000c56: 425b negs r3, r3 + 8000c58: e052 b.n 8000d00 <cobs_decode+0xce> + + if (srclen < 1) + 8000c5a: 683b ldr r3, [r7, #0] + 8000c5c: 2b00 cmp r3, #0 + 8000c5e: d102 bne.n 8000c66 <cobs_decode+0x34> + return -1; + 8000c60: 2301 movs r3, #1 + 8000c62: 425b negs r3, r3 + 8000c64: e04c b.n 8000d00 <cobs_decode+0xce> + + if (dstlen < srclen) + 8000c66: 68ba ldr r2, [r7, #8] + 8000c68: 683b ldr r3, [r7, #0] + 8000c6a: 429a cmp r2, r3 + 8000c6c: d202 bcs.n 8000c74 <cobs_decode+0x42> + return -1; + 8000c6e: 2301 movs r3, #1 + 8000c70: 425b negs r3, r3 + 8000c72: e045 b.n 8000d00 <cobs_decode+0xce> + + size_t p = 1; + 8000c74: 2301 movs r3, #1 + 8000c76: 61fb str r3, [r7, #28] + size_t c = (unsigned char)src[0]; + 8000c78: 687b ldr r3, [r7, #4] + 8000c7a: 781b ldrb r3, [r3, #0] + 8000c7c: 61bb str r3, [r7, #24] + //@ assert 0 <= c < 256; + //@ assert 0 <= c; + //@ assert c < 256; + if (c == 0) + 8000c7e: 69bb ldr r3, [r7, #24] + 8000c80: 2b00 cmp r3, #0 + 8000c82: d124 bne.n 8000cce <cobs_decode+0x9c> + return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ + 8000c84: 2302 movs r3, #2 + 8000c86: 425b negs r3, r3 + 8000c88: e03a b.n 8000d00 <cobs_decode+0xce> + @ loop assigns dst[0..dstlen-1], p, c; + @ loop variant srclen-p; + @*/ + while (p < srclen && src[p]) { + char val; + c--; + 8000c8a: 69bb ldr r3, [r7, #24] + 8000c8c: 3b01 subs r3, #1 + 8000c8e: 61bb str r3, [r7, #24] + + //@ assert src[p] != 0; + if (c == 0) { + 8000c90: 69bb ldr r3, [r7, #24] + 8000c92: 2b00 cmp r3, #0 + 8000c94: d109 bne.n 8000caa <cobs_decode+0x78> + c = (unsigned char)src[p]; + 8000c96: 687a ldr r2, [r7, #4] + 8000c98: 69fb ldr r3, [r7, #28] + 8000c9a: 18d3 adds r3, r2, r3 + 8000c9c: 781b ldrb r3, [r3, #0] + 8000c9e: 61bb str r3, [r7, #24] + val = 0; + 8000ca0: 2317 movs r3, #23 + 8000ca2: 18fb adds r3, r7, r3 + 8000ca4: 2200 movs r2, #0 + 8000ca6: 701a strb r2, [r3, #0] + 8000ca8: e006 b.n 8000cb8 <cobs_decode+0x86> + } else { + val = src[p]; + 8000caa: 687a ldr r2, [r7, #4] + 8000cac: 69fb ldr r3, [r7, #28] + 8000cae: 18d2 adds r2, r2, r3 + 8000cb0: 2317 movs r3, #23 + 8000cb2: 18fb adds r3, r7, r3 + 8000cb4: 7812 ldrb r2, [r2, #0] + 8000cb6: 701a strb r2, [r3, #0] + } + + //@ assert 0 <= p-1 <= dstlen-1; + dst[p-1] = val; + 8000cb8: 69fb ldr r3, [r7, #28] + 8000cba: 3b01 subs r3, #1 + 8000cbc: 68fa ldr r2, [r7, #12] + 8000cbe: 18d3 adds r3, r2, r3 + 8000cc0: 2217 movs r2, #23 + 8000cc2: 18ba adds r2, r7, r2 + 8000cc4: 7812 ldrb r2, [r2, #0] + 8000cc6: 701a strb r2, [r3, #0] + p++; + 8000cc8: 69fb ldr r3, [r7, #28] + 8000cca: 3301 adds r3, #1 + 8000ccc: 61fb str r3, [r7, #28] + while (p < srclen && src[p]) { + 8000cce: 69fa ldr r2, [r7, #28] + 8000cd0: 683b ldr r3, [r7, #0] + 8000cd2: 429a cmp r2, r3 + 8000cd4: d205 bcs.n 8000ce2 <cobs_decode+0xb0> + 8000cd6: 687a ldr r2, [r7, #4] + 8000cd8: 69fb ldr r3, [r7, #28] + 8000cda: 18d3 adds r3, r2, r3 + 8000cdc: 781b ldrb r3, [r3, #0] + 8000cde: 2b00 cmp r3, #0 + 8000ce0: d1d3 bne.n 8000c8a <cobs_decode+0x58> + } + + if (p == srclen) + 8000ce2: 69fa ldr r2, [r7, #28] + 8000ce4: 683b ldr r3, [r7, #0] + 8000ce6: 429a cmp r2, r3 + 8000ce8: d102 bne.n 8000cf0 <cobs_decode+0xbe> + return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */ + 8000cea: 2302 movs r3, #2 + 8000cec: 425b negs r3, r3 + 8000cee: e007 b.n 8000d00 <cobs_decode+0xce> + + if (c != 1) + 8000cf0: 69bb ldr r3, [r7, #24] + 8000cf2: 2b01 cmp r3, #1 + 8000cf4: d002 beq.n 8000cfc <cobs_decode+0xca> + return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */ + 8000cf6: 2303 movs r3, #3 + 8000cf8: 425b negs r3, r3 + 8000cfa: e001 b.n 8000d00 <cobs_decode+0xce> + + //@ assert 0 < p <= srclen <= 65535; + //@ assert src[p] == 0; + //@ assert \forall integer i; 1 <= i < p ==> src[i] != 0; + return p-1; + 8000cfc: 69fb ldr r3, [r7, #28] + 8000cfe: 3b01 subs r3, #1 +} + 8000d00: 0018 movs r0, r3 + 8000d02: 46bd mov sp, r7 + 8000d04: b008 add sp, #32 + 8000d06: bd80 pop {r7, pc} + +08000d08 <cobs_decode_incremental_initialize>: + +void cobs_decode_incremental_initialize(struct cobs_decode_state *state) { + 8000d08: b580 push {r7, lr} + 8000d0a: b082 sub sp, #8 + 8000d0c: af00 add r7, sp, #0 + 8000d0e: 6078 str r0, [r7, #4] + state->p = 0; + 8000d10: 687b ldr r3, [r7, #4] + 8000d12: 2200 movs r2, #0 + 8000d14: 601a str r2, [r3, #0] + state->c = 0; + 8000d16: 687b ldr r3, [r7, #4] + 8000d18: 2200 movs r2, #0 + 8000d1a: 605a str r2, [r3, #4] +} + 8000d1c: 46c0 nop ; (mov r8, r8) + 8000d1e: 46bd mov sp, r7 + 8000d20: b002 add sp, #8 + 8000d22: bd80 pop {r7, pc} + +08000d24 <cobs_decode_incremental>: + +int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) { + 8000d24: b580 push {r7, lr} + 8000d26: b088 sub sp, #32 + 8000d28: af00 add r7, sp, #0 + 8000d2a: 60f8 str r0, [r7, #12] + 8000d2c: 60b9 str r1, [r7, #8] + 8000d2e: 607a str r2, [r7, #4] + 8000d30: 001a movs r2, r3 + 8000d32: 1cfb adds r3, r7, #3 + 8000d34: 701a strb r2, [r3, #0] + if (state->p == 0) { + 8000d36: 68fb ldr r3, [r7, #12] + 8000d38: 681b ldr r3, [r3, #0] + 8000d3a: 2b00 cmp r3, #0 + 8000d3c: d10e bne.n 8000d5c <cobs_decode_incremental+0x38> + if (src == 0) + 8000d3e: 1cfb adds r3, r7, #3 + 8000d40: 781b ldrb r3, [r3, #0] + 8000d42: 2b00 cmp r3, #0 + 8000d44: d054 beq.n 8000df0 <cobs_decode_incremental+0xcc> + goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ + state->c = (unsigned char)src; + 8000d46: 1cfb adds r3, r7, #3 + 8000d48: 781a ldrb r2, [r3, #0] + 8000d4a: 68fb ldr r3, [r7, #12] + 8000d4c: 605a str r2, [r3, #4] + state->p++; + 8000d4e: 68fb ldr r3, [r7, #12] + 8000d50: 681b ldr r3, [r3, #0] + 8000d52: 1c5a adds r2, r3, #1 + 8000d54: 68fb ldr r3, [r7, #12] + 8000d56: 601a str r2, [r3, #0] + return 0; + 8000d58: 2300 movs r3, #0 + 8000d5a: e050 b.n 8000dfe <cobs_decode_incremental+0xda> + } + + if (!src) { + 8000d5c: 1cfb adds r3, r7, #3 + 8000d5e: 781b ldrb r3, [r3, #0] + 8000d60: 2b00 cmp r3, #0 + 8000d62: d10d bne.n 8000d80 <cobs_decode_incremental+0x5c> + if (state->c != 1) + 8000d64: 68fb ldr r3, [r7, #12] + 8000d66: 685b ldr r3, [r3, #4] + 8000d68: 2b01 cmp r3, #1 + 8000d6a: d139 bne.n 8000de0 <cobs_decode_incremental+0xbc> + goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */ + int rv = state->p-1; + 8000d6c: 68fb ldr r3, [r7, #12] + 8000d6e: 681b ldr r3, [r3, #0] + 8000d70: 3b01 subs r3, #1 + 8000d72: 617b str r3, [r7, #20] + cobs_decode_incremental_initialize(state); + 8000d74: 68fb ldr r3, [r7, #12] + 8000d76: 0018 movs r0, r3 + 8000d78: f7ff ffc6 bl 8000d08 <cobs_decode_incremental_initialize> + return rv; + 8000d7c: 697b ldr r3, [r7, #20] + 8000d7e: e03e b.n 8000dfe <cobs_decode_incremental+0xda> + } + + char val; + state->c--; + 8000d80: 68fb ldr r3, [r7, #12] + 8000d82: 685b ldr r3, [r3, #4] + 8000d84: 1e5a subs r2, r3, #1 + 8000d86: 68fb ldr r3, [r7, #12] + 8000d88: 605a str r2, [r3, #4] + + if (state->c == 0) { + 8000d8a: 68fb ldr r3, [r7, #12] + 8000d8c: 685b ldr r3, [r3, #4] + 8000d8e: 2b00 cmp r3, #0 + 8000d90: d108 bne.n 8000da4 <cobs_decode_incremental+0x80> + state->c = (unsigned char)src; + 8000d92: 1cfb adds r3, r7, #3 + 8000d94: 781a ldrb r2, [r3, #0] + 8000d96: 68fb ldr r3, [r7, #12] + 8000d98: 605a str r2, [r3, #4] + val = 0; + 8000d9a: 231f movs r3, #31 + 8000d9c: 18fb adds r3, r7, r3 + 8000d9e: 2200 movs r2, #0 + 8000da0: 701a strb r2, [r3, #0] + 8000da2: e004 b.n 8000dae <cobs_decode_incremental+0x8a> + } else { + val = src; + 8000da4: 231f movs r3, #31 + 8000da6: 18fb adds r3, r7, r3 + 8000da8: 1cfa adds r2, r7, #3 + 8000daa: 7812 ldrb r2, [r2, #0] + 8000dac: 701a strb r2, [r3, #0] + } + + size_t pos = state->p-1; + 8000dae: 68fb ldr r3, [r7, #12] + 8000db0: 681b ldr r3, [r3, #0] + 8000db2: 3b01 subs r3, #1 + 8000db4: 61bb str r3, [r7, #24] + if (pos >= dstlen) + 8000db6: 69ba ldr r2, [r7, #24] + 8000db8: 687b ldr r3, [r7, #4] + 8000dba: 429a cmp r2, r3 + 8000dbc: d302 bcc.n 8000dc4 <cobs_decode_incremental+0xa0> + return -2; /* output buffer too small */ + 8000dbe: 2302 movs r3, #2 + 8000dc0: 425b negs r3, r3 + 8000dc2: e01c b.n 8000dfe <cobs_decode_incremental+0xda> + dst[pos] = val; + 8000dc4: 68ba ldr r2, [r7, #8] + 8000dc6: 69bb ldr r3, [r7, #24] + 8000dc8: 18d3 adds r3, r2, r3 + 8000dca: 221f movs r2, #31 + 8000dcc: 18ba adds r2, r7, r2 + 8000dce: 7812 ldrb r2, [r2, #0] + 8000dd0: 701a strb r2, [r3, #0] + state->p++; + 8000dd2: 68fb ldr r3, [r7, #12] + 8000dd4: 681b ldr r3, [r3, #0] + 8000dd6: 1c5a adds r2, r3, #1 + 8000dd8: 68fb ldr r3, [r7, #12] + 8000dda: 601a str r2, [r3, #0] + return 0; + 8000ddc: 2300 movs r3, #0 + 8000dde: e00e b.n 8000dfe <cobs_decode_incremental+0xda> + goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */ + 8000de0: 46c0 nop ; (mov r8, r8) + +errout: + cobs_decode_incremental_initialize(state); + 8000de2: 68fb ldr r3, [r7, #12] + 8000de4: 0018 movs r0, r3 + 8000de6: f7ff ff8f bl 8000d08 <cobs_decode_incremental_initialize> + return -1; + 8000dea: 2301 movs r3, #1 + 8000dec: 425b negs r3, r3 + 8000dee: e006 b.n 8000dfe <cobs_decode_incremental+0xda> + goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ + 8000df0: 46c0 nop ; (mov r8, r8) + +empty_errout: + cobs_decode_incremental_initialize(state); + 8000df2: 68fb ldr r3, [r7, #12] + 8000df4: 0018 movs r0, r3 + 8000df6: f7ff ff87 bl 8000d08 <cobs_decode_incremental_initialize> + return -3; + 8000dfa: 2303 movs r3, #3 + 8000dfc: 425b negs r3, r3 +} + 8000dfe: 0018 movs r0, r3 + 8000e00: 46bd mov sp, r7 + 8000e02: b008 add sp, #32 + 8000e04: bd80 pop {r7, pc} + 8000e06: 1904 .short 0x1904 + 8000e08: 00000800 .word 0x00000800 + 8000e0c: 00942000 .word 0x00942000 + 8000e10: 00942000 .word 0x00942000 + 8000e14: 09d42000 .word 0x09d42000 + 8000e18: 00002000 .word 0x00002000 + +08000e1c <SystemInit>: + * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000e1c: b580 push {r7, lr} + 8000e1e: af00 add r7, sp, #0 + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001U; + 8000e20: 4b1a ldr r3, [pc, #104] ; (8000e8c <SystemInit+0x70>) + 8000e22: 681a ldr r2, [r3, #0] + 8000e24: 4b19 ldr r3, [pc, #100] ; (8000e8c <SystemInit+0x70>) + 8000e26: 2101 movs r1, #1 + 8000e28: 430a orrs r2, r1 + 8000e2a: 601a str r2, [r3, #0] +#if defined (STM32F051x8) || defined (STM32F058x8) + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0xF8FFB80CU; +#else + /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ + RCC->CFGR &= (uint32_t)0x08FFB80CU; + 8000e2c: 4b17 ldr r3, [pc, #92] ; (8000e8c <SystemInit+0x70>) + 8000e2e: 685a ldr r2, [r3, #4] + 8000e30: 4b16 ldr r3, [pc, #88] ; (8000e8c <SystemInit+0x70>) + 8000e32: 4917 ldr r1, [pc, #92] ; (8000e90 <SystemInit+0x74>) + 8000e34: 400a ands r2, r1 + 8000e36: 605a str r2, [r3, #4] +#endif /* STM32F051x8 or STM32F058x8 */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFFU; + 8000e38: 4b14 ldr r3, [pc, #80] ; (8000e8c <SystemInit+0x70>) + 8000e3a: 681a ldr r2, [r3, #0] + 8000e3c: 4b13 ldr r3, [pc, #76] ; (8000e8c <SystemInit+0x70>) + 8000e3e: 4915 ldr r1, [pc, #84] ; (8000e94 <SystemInit+0x78>) + 8000e40: 400a ands r2, r1 + 8000e42: 601a str r2, [r3, #0] + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFFU; + 8000e44: 4b11 ldr r3, [pc, #68] ; (8000e8c <SystemInit+0x70>) + 8000e46: 681a ldr r2, [r3, #0] + 8000e48: 4b10 ldr r3, [pc, #64] ; (8000e8c <SystemInit+0x70>) + 8000e4a: 4913 ldr r1, [pc, #76] ; (8000e98 <SystemInit+0x7c>) + 8000e4c: 400a ands r2, r1 + 8000e4e: 601a str r2, [r3, #0] + + /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + RCC->CFGR &= (uint32_t)0xFFC0FFFFU; + 8000e50: 4b0e ldr r3, [pc, #56] ; (8000e8c <SystemInit+0x70>) + 8000e52: 685a ldr r2, [r3, #4] + 8000e54: 4b0d ldr r3, [pc, #52] ; (8000e8c <SystemInit+0x70>) + 8000e56: 4911 ldr r1, [pc, #68] ; (8000e9c <SystemInit+0x80>) + 8000e58: 400a ands r2, r1 + 8000e5a: 605a str r2, [r3, #4] + + /* Reset PREDIV[3:0] bits */ + RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; + 8000e5c: 4b0b ldr r3, [pc, #44] ; (8000e8c <SystemInit+0x70>) + 8000e5e: 6ada ldr r2, [r3, #44] ; 0x2c + 8000e60: 4b0a ldr r3, [pc, #40] ; (8000e8c <SystemInit+0x70>) + 8000e62: 210f movs r1, #15 + 8000e64: 438a bics r2, r1 + 8000e66: 62da str r2, [r3, #44] ; 0x2c +#elif defined (STM32F091xC) || defined (STM32F098xx) + /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; +#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) + /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ + RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; + 8000e68: 4b08 ldr r3, [pc, #32] ; (8000e8c <SystemInit+0x70>) + 8000e6a: 6b1a ldr r2, [r3, #48] ; 0x30 + 8000e6c: 4b07 ldr r3, [pc, #28] ; (8000e8c <SystemInit+0x70>) + 8000e6e: 490c ldr r1, [pc, #48] ; (8000ea0 <SystemInit+0x84>) + 8000e70: 400a ands r2, r1 + 8000e72: 631a str r2, [r3, #48] ; 0x30 +#else + #warning "No target selected" +#endif + + /* Reset HSI14 bit */ + RCC->CR2 &= (uint32_t)0xFFFFFFFEU; + 8000e74: 4b05 ldr r3, [pc, #20] ; (8000e8c <SystemInit+0x70>) + 8000e76: 6b5a ldr r2, [r3, #52] ; 0x34 + 8000e78: 4b04 ldr r3, [pc, #16] ; (8000e8c <SystemInit+0x70>) + 8000e7a: 2101 movs r1, #1 + 8000e7c: 438a bics r2, r1 + 8000e7e: 635a str r2, [r3, #52] ; 0x34 + + /* Disable all interrupts */ + RCC->CIR = 0x00000000U; + 8000e80: 4b02 ldr r3, [pc, #8] ; (8000e8c <SystemInit+0x70>) + 8000e82: 2200 movs r2, #0 + 8000e84: 609a str r2, [r3, #8] + +} + 8000e86: 46c0 nop ; (mov r8, r8) + 8000e88: 46bd mov sp, r7 + 8000e8a: bd80 pop {r7, pc} + 8000e8c: 40021000 .word 0x40021000 + 8000e90: 08ffb80c .word 0x08ffb80c + 8000e94: fef6ffff .word 0xfef6ffff + 8000e98: fffbffff .word 0xfffbffff + 8000e9c: ffc0ffff .word 0xffc0ffff + 8000ea0: fffffeec .word 0xfffffeec + +08000ea4 <SystemCoreClockUpdate>: + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + 8000ea4: b580 push {r7, lr} + 8000ea6: b084 sub sp, #16 + 8000ea8: af00 add r7, sp, #0 + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + 8000eaa: 2300 movs r3, #0 + 8000eac: 60fb str r3, [r7, #12] + 8000eae: 2300 movs r3, #0 + 8000eb0: 60bb str r3, [r7, #8] + 8000eb2: 2300 movs r3, #0 + 8000eb4: 607b str r3, [r7, #4] + 8000eb6: 2300 movs r3, #0 + 8000eb8: 603b str r3, [r7, #0] + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + 8000eba: 4b31 ldr r3, [pc, #196] ; (8000f80 <SystemCoreClockUpdate+0xdc>) + 8000ebc: 685b ldr r3, [r3, #4] + 8000ebe: 220c movs r2, #12 + 8000ec0: 4013 ands r3, r2 + 8000ec2: 60fb str r3, [r7, #12] + + switch (tmp) + 8000ec4: 68fb ldr r3, [r7, #12] + 8000ec6: 2b08 cmp r3, #8 + 8000ec8: d011 beq.n 8000eee <SystemCoreClockUpdate+0x4a> + 8000eca: 68fb ldr r3, [r7, #12] + 8000ecc: 2b08 cmp r3, #8 + 8000ece: d841 bhi.n 8000f54 <SystemCoreClockUpdate+0xb0> + 8000ed0: 68fb ldr r3, [r7, #12] + 8000ed2: 2b00 cmp r3, #0 + 8000ed4: d003 beq.n 8000ede <SystemCoreClockUpdate+0x3a> + 8000ed6: 68fb ldr r3, [r7, #12] + 8000ed8: 2b04 cmp r3, #4 + 8000eda: d004 beq.n 8000ee6 <SystemCoreClockUpdate+0x42> + 8000edc: e03a b.n 8000f54 <SystemCoreClockUpdate+0xb0> + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + 8000ede: 4b29 ldr r3, [pc, #164] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000ee0: 4a29 ldr r2, [pc, #164] ; (8000f88 <SystemCoreClockUpdate+0xe4>) + 8000ee2: 601a str r2, [r3, #0] + break; + 8000ee4: e03a b.n 8000f5c <SystemCoreClockUpdate+0xb8> + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + 8000ee6: 4b27 ldr r3, [pc, #156] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000ee8: 4a27 ldr r2, [pc, #156] ; (8000f88 <SystemCoreClockUpdate+0xe4>) + 8000eea: 601a str r2, [r3, #0] + break; + 8000eec: e036 b.n 8000f5c <SystemCoreClockUpdate+0xb8> + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + 8000eee: 4b24 ldr r3, [pc, #144] ; (8000f80 <SystemCoreClockUpdate+0xdc>) + 8000ef0: 685a ldr r2, [r3, #4] + 8000ef2: 23f0 movs r3, #240 ; 0xf0 + 8000ef4: 039b lsls r3, r3, #14 + 8000ef6: 4013 ands r3, r2 + 8000ef8: 60bb str r3, [r7, #8] + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 8000efa: 4b21 ldr r3, [pc, #132] ; (8000f80 <SystemCoreClockUpdate+0xdc>) + 8000efc: 685a ldr r2, [r3, #4] + 8000efe: 2380 movs r3, #128 ; 0x80 + 8000f00: 025b lsls r3, r3, #9 + 8000f02: 4013 ands r3, r2 + 8000f04: 607b str r3, [r7, #4] + pllmull = ( pllmull >> 18) + 2; + 8000f06: 68bb ldr r3, [r7, #8] + 8000f08: 0c9b lsrs r3, r3, #18 + 8000f0a: 3302 adds r3, #2 + 8000f0c: 60bb str r3, [r7, #8] + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 8000f0e: 4b1c ldr r3, [pc, #112] ; (8000f80 <SystemCoreClockUpdate+0xdc>) + 8000f10: 6adb ldr r3, [r3, #44] ; 0x2c + 8000f12: 220f movs r2, #15 + 8000f14: 4013 ands r3, r2 + 8000f16: 3301 adds r3, #1 + 8000f18: 603b str r3, [r7, #0] + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + 8000f1a: 687a ldr r2, [r7, #4] + 8000f1c: 2380 movs r3, #128 ; 0x80 + 8000f1e: 025b lsls r3, r3, #9 + 8000f20: 429a cmp r2, r3 + 8000f22: d10a bne.n 8000f3a <SystemCoreClockUpdate+0x96> + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; + 8000f24: 6839 ldr r1, [r7, #0] + 8000f26: 4818 ldr r0, [pc, #96] ; (8000f88 <SystemCoreClockUpdate+0xe4>) + 8000f28: f000 fb3e bl 80015a8 <__udivsi3> + 8000f2c: 0003 movs r3, r0 + 8000f2e: 001a movs r2, r3 + 8000f30: 68bb ldr r3, [r7, #8] + 8000f32: 435a muls r2, r3 + 8000f34: 4b13 ldr r3, [pc, #76] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000f36: 601a str r2, [r3, #0] + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + 8000f38: e010 b.n 8000f5c <SystemCoreClockUpdate+0xb8> + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + 8000f3a: 68b9 ldr r1, [r7, #8] + 8000f3c: 000a movs r2, r1 + 8000f3e: 0152 lsls r2, r2, #5 + 8000f40: 1a52 subs r2, r2, r1 + 8000f42: 0193 lsls r3, r2, #6 + 8000f44: 1a9b subs r3, r3, r2 + 8000f46: 00db lsls r3, r3, #3 + 8000f48: 185b adds r3, r3, r1 + 8000f4a: 021b lsls r3, r3, #8 + 8000f4c: 001a movs r2, r3 + 8000f4e: 4b0d ldr r3, [pc, #52] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000f50: 601a str r2, [r3, #0] + break; + 8000f52: e003 b.n 8000f5c <SystemCoreClockUpdate+0xb8> + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + 8000f54: 4b0b ldr r3, [pc, #44] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000f56: 4a0c ldr r2, [pc, #48] ; (8000f88 <SystemCoreClockUpdate+0xe4>) + 8000f58: 601a str r2, [r3, #0] + break; + 8000f5a: 46c0 nop ; (mov r8, r8) + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + 8000f5c: 4b08 ldr r3, [pc, #32] ; (8000f80 <SystemCoreClockUpdate+0xdc>) + 8000f5e: 685b ldr r3, [r3, #4] + 8000f60: 091b lsrs r3, r3, #4 + 8000f62: 220f movs r2, #15 + 8000f64: 4013 ands r3, r2 + 8000f66: 4a09 ldr r2, [pc, #36] ; (8000f8c <SystemCoreClockUpdate+0xe8>) + 8000f68: 5cd3 ldrb r3, [r2, r3] + 8000f6a: 60fb str r3, [r7, #12] + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; + 8000f6c: 4b05 ldr r3, [pc, #20] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000f6e: 681a ldr r2, [r3, #0] + 8000f70: 68fb ldr r3, [r7, #12] + 8000f72: 40da lsrs r2, r3 + 8000f74: 4b03 ldr r3, [pc, #12] ; (8000f84 <SystemCoreClockUpdate+0xe0>) + 8000f76: 601a str r2, [r3, #0] +} + 8000f78: 46c0 nop ; (mov r8, r8) + 8000f7a: 46bd mov sp, r7 + 8000f7c: b004 add sp, #16 + 8000f7e: bd80 pop {r7, pc} + 8000f80: 40021000 .word 0x40021000 + 8000f84: 20000000 .word 0x20000000 + 8000f88: 007a1200 .word 0x007a1200 + 8000f8c: 080018ec .word 0x080018ec + +08000f90 <LL_RCC_HSE_EnableBypass>: + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + 8000f90: b580 push {r7, lr} + 8000f92: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEBYP); + 8000f94: 4b04 ldr r3, [pc, #16] ; (8000fa8 <LL_RCC_HSE_EnableBypass+0x18>) + 8000f96: 681a ldr r2, [r3, #0] + 8000f98: 4b03 ldr r3, [pc, #12] ; (8000fa8 <LL_RCC_HSE_EnableBypass+0x18>) + 8000f9a: 2180 movs r1, #128 ; 0x80 + 8000f9c: 02c9 lsls r1, r1, #11 + 8000f9e: 430a orrs r2, r1 + 8000fa0: 601a str r2, [r3, #0] +} + 8000fa2: 46c0 nop ; (mov r8, r8) + 8000fa4: 46bd mov sp, r7 + 8000fa6: bd80 pop {r7, pc} + 8000fa8: 40021000 .word 0x40021000 + +08000fac <LL_RCC_HSE_DisableBypass>: + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + 8000fac: b580 push {r7, lr} + 8000fae: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 8000fb0: 4b04 ldr r3, [pc, #16] ; (8000fc4 <LL_RCC_HSE_DisableBypass+0x18>) + 8000fb2: 681a ldr r2, [r3, #0] + 8000fb4: 4b03 ldr r3, [pc, #12] ; (8000fc4 <LL_RCC_HSE_DisableBypass+0x18>) + 8000fb6: 4904 ldr r1, [pc, #16] ; (8000fc8 <LL_RCC_HSE_DisableBypass+0x1c>) + 8000fb8: 400a ands r2, r1 + 8000fba: 601a str r2, [r3, #0] +} + 8000fbc: 46c0 nop ; (mov r8, r8) + 8000fbe: 46bd mov sp, r7 + 8000fc0: bd80 pop {r7, pc} + 8000fc2: 46c0 nop ; (mov r8, r8) + 8000fc4: 40021000 .word 0x40021000 + 8000fc8: fffbffff .word 0xfffbffff + +08000fcc <LL_RCC_HSE_Enable>: + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + 8000fcc: b580 push {r7, lr} + 8000fce: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 8000fd0: 4b04 ldr r3, [pc, #16] ; (8000fe4 <LL_RCC_HSE_Enable+0x18>) + 8000fd2: 681a ldr r2, [r3, #0] + 8000fd4: 4b03 ldr r3, [pc, #12] ; (8000fe4 <LL_RCC_HSE_Enable+0x18>) + 8000fd6: 2180 movs r1, #128 ; 0x80 + 8000fd8: 0249 lsls r1, r1, #9 + 8000fda: 430a orrs r2, r1 + 8000fdc: 601a str r2, [r3, #0] +} + 8000fde: 46c0 nop ; (mov r8, r8) + 8000fe0: 46bd mov sp, r7 + 8000fe2: bd80 pop {r7, pc} + 8000fe4: 40021000 .word 0x40021000 + +08000fe8 <LL_RCC_HSE_IsReady>: + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + 8000fe8: b580 push {r7, lr} + 8000fea: af00 add r7, sp, #0 + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); + 8000fec: 4b06 ldr r3, [pc, #24] ; (8001008 <LL_RCC_HSE_IsReady+0x20>) + 8000fee: 681a ldr r2, [r3, #0] + 8000ff0: 2380 movs r3, #128 ; 0x80 + 8000ff2: 029b lsls r3, r3, #10 + 8000ff4: 4013 ands r3, r2 + 8000ff6: 4a05 ldr r2, [pc, #20] ; (800100c <LL_RCC_HSE_IsReady+0x24>) + 8000ff8: 4694 mov ip, r2 + 8000ffa: 4463 add r3, ip + 8000ffc: 425a negs r2, r3 + 8000ffe: 4153 adcs r3, r2 + 8001000: b2db uxtb r3, r3 +} + 8001002: 0018 movs r0, r3 + 8001004: 46bd mov sp, r7 + 8001006: bd80 pop {r7, pc} + 8001008: 40021000 .word 0x40021000 + 800100c: fffe0000 .word 0xfffe0000 + +08001010 <LL_RCC_HSI_Enable>: + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + 8001010: b580 push {r7, lr} + 8001012: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 8001014: 4b04 ldr r3, [pc, #16] ; (8001028 <LL_RCC_HSI_Enable+0x18>) + 8001016: 681a ldr r2, [r3, #0] + 8001018: 4b03 ldr r3, [pc, #12] ; (8001028 <LL_RCC_HSI_Enable+0x18>) + 800101a: 2101 movs r1, #1 + 800101c: 430a orrs r2, r1 + 800101e: 601a str r2, [r3, #0] +} + 8001020: 46c0 nop ; (mov r8, r8) + 8001022: 46bd mov sp, r7 + 8001024: bd80 pop {r7, pc} + 8001026: 46c0 nop ; (mov r8, r8) + 8001028: 40021000 .word 0x40021000 + +0800102c <LL_RCC_HSI_IsReady>: + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + 800102c: b580 push {r7, lr} + 800102e: af00 add r7, sp, #0 + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); + 8001030: 4b05 ldr r3, [pc, #20] ; (8001048 <LL_RCC_HSI_IsReady+0x1c>) + 8001032: 681b ldr r3, [r3, #0] + 8001034: 2202 movs r2, #2 + 8001036: 4013 ands r3, r2 + 8001038: 3b02 subs r3, #2 + 800103a: 425a negs r2, r3 + 800103c: 4153 adcs r3, r2 + 800103e: b2db uxtb r3, r3 +} + 8001040: 0018 movs r0, r3 + 8001042: 46bd mov sp, r7 + 8001044: bd80 pop {r7, pc} + 8001046: 46c0 nop ; (mov r8, r8) + 8001048: 40021000 .word 0x40021000 + +0800104c <LL_RCC_SetSysClkSource>: + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + 800104c: b580 push {r7, lr} + 800104e: b082 sub sp, #8 + 8001050: af00 add r7, sp, #0 + 8001052: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 8001054: 4b06 ldr r3, [pc, #24] ; (8001070 <LL_RCC_SetSysClkSource+0x24>) + 8001056: 685b ldr r3, [r3, #4] + 8001058: 2203 movs r2, #3 + 800105a: 4393 bics r3, r2 + 800105c: 0019 movs r1, r3 + 800105e: 4b04 ldr r3, [pc, #16] ; (8001070 <LL_RCC_SetSysClkSource+0x24>) + 8001060: 687a ldr r2, [r7, #4] + 8001062: 430a orrs r2, r1 + 8001064: 605a str r2, [r3, #4] +} + 8001066: 46c0 nop ; (mov r8, r8) + 8001068: 46bd mov sp, r7 + 800106a: b002 add sp, #8 + 800106c: bd80 pop {r7, pc} + 800106e: 46c0 nop ; (mov r8, r8) + 8001070: 40021000 .word 0x40021000 + +08001074 <LL_RCC_GetSysClkSource>: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + 8001074: b580 push {r7, lr} + 8001076: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 8001078: 4b03 ldr r3, [pc, #12] ; (8001088 <LL_RCC_GetSysClkSource+0x14>) + 800107a: 685b ldr r3, [r3, #4] + 800107c: 220c movs r2, #12 + 800107e: 4013 ands r3, r2 +} + 8001080: 0018 movs r0, r3 + 8001082: 46bd mov sp, r7 + 8001084: bd80 pop {r7, pc} + 8001086: 46c0 nop ; (mov r8, r8) + 8001088: 40021000 .word 0x40021000 + +0800108c <LL_RCC_SetAHBPrescaler>: + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + 800108c: b580 push {r7, lr} + 800108e: b082 sub sp, #8 + 8001090: af00 add r7, sp, #0 + 8001092: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 8001094: 4b06 ldr r3, [pc, #24] ; (80010b0 <LL_RCC_SetAHBPrescaler+0x24>) + 8001096: 685b ldr r3, [r3, #4] + 8001098: 22f0 movs r2, #240 ; 0xf0 + 800109a: 4393 bics r3, r2 + 800109c: 0019 movs r1, r3 + 800109e: 4b04 ldr r3, [pc, #16] ; (80010b0 <LL_RCC_SetAHBPrescaler+0x24>) + 80010a0: 687a ldr r2, [r7, #4] + 80010a2: 430a orrs r2, r1 + 80010a4: 605a str r2, [r3, #4] +} + 80010a6: 46c0 nop ; (mov r8, r8) + 80010a8: 46bd mov sp, r7 + 80010aa: b002 add sp, #8 + 80010ac: bd80 pop {r7, pc} + 80010ae: 46c0 nop ; (mov r8, r8) + 80010b0: 40021000 .word 0x40021000 + +080010b4 <LL_RCC_SetAPB1Prescaler>: + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + 80010b4: b580 push {r7, lr} + 80010b6: b082 sub sp, #8 + 80010b8: af00 add r7, sp, #0 + 80010ba: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); + 80010bc: 4b06 ldr r3, [pc, #24] ; (80010d8 <LL_RCC_SetAPB1Prescaler+0x24>) + 80010be: 685b ldr r3, [r3, #4] + 80010c0: 4a06 ldr r2, [pc, #24] ; (80010dc <LL_RCC_SetAPB1Prescaler+0x28>) + 80010c2: 4013 ands r3, r2 + 80010c4: 0019 movs r1, r3 + 80010c6: 4b04 ldr r3, [pc, #16] ; (80010d8 <LL_RCC_SetAPB1Prescaler+0x24>) + 80010c8: 687a ldr r2, [r7, #4] + 80010ca: 430a orrs r2, r1 + 80010cc: 605a str r2, [r3, #4] +} + 80010ce: 46c0 nop ; (mov r8, r8) + 80010d0: 46bd mov sp, r7 + 80010d2: b002 add sp, #8 + 80010d4: bd80 pop {r7, pc} + 80010d6: 46c0 nop ; (mov r8, r8) + 80010d8: 40021000 .word 0x40021000 + 80010dc: fffff8ff .word 0xfffff8ff + +080010e0 <LL_RCC_PLL_Enable>: + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 80010e0: b580 push {r7, lr} + 80010e2: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 80010e4: 4b04 ldr r3, [pc, #16] ; (80010f8 <LL_RCC_PLL_Enable+0x18>) + 80010e6: 681a ldr r2, [r3, #0] + 80010e8: 4b03 ldr r3, [pc, #12] ; (80010f8 <LL_RCC_PLL_Enable+0x18>) + 80010ea: 2180 movs r1, #128 ; 0x80 + 80010ec: 0449 lsls r1, r1, #17 + 80010ee: 430a orrs r2, r1 + 80010f0: 601a str r2, [r3, #0] +} + 80010f2: 46c0 nop ; (mov r8, r8) + 80010f4: 46bd mov sp, r7 + 80010f6: bd80 pop {r7, pc} + 80010f8: 40021000 .word 0x40021000 + +080010fc <LL_RCC_PLL_IsReady>: + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 80010fc: b580 push {r7, lr} + 80010fe: af00 add r7, sp, #0 + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); + 8001100: 4b07 ldr r3, [pc, #28] ; (8001120 <LL_RCC_PLL_IsReady+0x24>) + 8001102: 681a ldr r2, [r3, #0] + 8001104: 2380 movs r3, #128 ; 0x80 + 8001106: 049b lsls r3, r3, #18 + 8001108: 4013 ands r3, r2 + 800110a: 22fe movs r2, #254 ; 0xfe + 800110c: 0612 lsls r2, r2, #24 + 800110e: 4694 mov ip, r2 + 8001110: 4463 add r3, ip + 8001112: 425a negs r2, r3 + 8001114: 4153 adcs r3, r2 + 8001116: b2db uxtb r3, r3 +} + 8001118: 0018 movs r0, r3 + 800111a: 46bd mov sp, r7 + 800111c: bd80 pop {r7, pc} + 800111e: 46c0 nop ; (mov r8, r8) + 8001120: 40021000 .word 0x40021000 + +08001124 <LL_RCC_PLL_ConfigDomain_SYS>: + * @arg @ref LL_RCC_PLL_MUL_15 + * @arg @ref LL_RCC_PLL_MUL_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) +{ + 8001124: b580 push {r7, lr} + 8001126: b082 sub sp, #8 + 8001128: af00 add r7, sp, #0 + 800112a: 6078 str r0, [r7, #4] + 800112c: 6039 str r1, [r7, #0] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); + 800112e: 4b0e ldr r3, [pc, #56] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) + 8001130: 685b ldr r3, [r3, #4] + 8001132: 4a0e ldr r2, [pc, #56] ; (800116c <LL_RCC_PLL_ConfigDomain_SYS+0x48>) + 8001134: 4013 ands r3, r2 + 8001136: 0019 movs r1, r3 + 8001138: 687a ldr r2, [r7, #4] + 800113a: 2380 movs r3, #128 ; 0x80 + 800113c: 025b lsls r3, r3, #9 + 800113e: 401a ands r2, r3 + 8001140: 683b ldr r3, [r7, #0] + 8001142: 431a orrs r2, r3 + 8001144: 4b08 ldr r3, [pc, #32] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) + 8001146: 430a orrs r2, r1 + 8001148: 605a str r2, [r3, #4] + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); + 800114a: 4b07 ldr r3, [pc, #28] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) + 800114c: 6adb ldr r3, [r3, #44] ; 0x2c + 800114e: 220f movs r2, #15 + 8001150: 4393 bics r3, r2 + 8001152: 0019 movs r1, r3 + 8001154: 687b ldr r3, [r7, #4] + 8001156: 220f movs r2, #15 + 8001158: 401a ands r2, r3 + 800115a: 4b03 ldr r3, [pc, #12] ; (8001168 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) + 800115c: 430a orrs r2, r1 + 800115e: 62da str r2, [r3, #44] ; 0x2c +} + 8001160: 46c0 nop ; (mov r8, r8) + 8001162: 46bd mov sp, r7 + 8001164: b002 add sp, #8 + 8001166: bd80 pop {r7, pc} + 8001168: 40021000 .word 0x40021000 + 800116c: ffc2ffff .word 0xffc2ffff + +08001170 <LL_InitTick>: + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + 8001170: b580 push {r7, lr} + 8001172: b082 sub sp, #8 + 8001174: af00 add r7, sp, #0 + 8001176: 6078 str r0, [r7, #4] + 8001178: 6039 str r1, [r7, #0] + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + 800117a: 6839 ldr r1, [r7, #0] + 800117c: 6878 ldr r0, [r7, #4] + 800117e: f000 fa13 bl 80015a8 <__udivsi3> + 8001182: 0003 movs r3, r0 + 8001184: 001a movs r2, r3 + 8001186: 4b06 ldr r3, [pc, #24] ; (80011a0 <LL_InitTick+0x30>) + 8001188: 3a01 subs r2, #1 + 800118a: 605a str r2, [r3, #4] + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 800118c: 4b04 ldr r3, [pc, #16] ; (80011a0 <LL_InitTick+0x30>) + 800118e: 2200 movs r2, #0 + 8001190: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8001192: 4b03 ldr r3, [pc, #12] ; (80011a0 <LL_InitTick+0x30>) + 8001194: 2205 movs r2, #5 + 8001196: 601a str r2, [r3, #0] + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + 8001198: 46c0 nop ; (mov r8, r8) + 800119a: 46bd mov sp, r7 + 800119c: b002 add sp, #8 + 800119e: bd80 pop {r7, pc} + 80011a0: e000e010 .word 0xe000e010 + +080011a4 <LL_FLASH_SetLatency>: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + 80011a4: b580 push {r7, lr} + 80011a6: b082 sub sp, #8 + 80011a8: af00 add r7, sp, #0 + 80011aa: 6078 str r0, [r7, #4] + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); + 80011ac: 4b06 ldr r3, [pc, #24] ; (80011c8 <LL_FLASH_SetLatency+0x24>) + 80011ae: 681b ldr r3, [r3, #0] + 80011b0: 2201 movs r2, #1 + 80011b2: 4393 bics r3, r2 + 80011b4: 0019 movs r1, r3 + 80011b6: 4b04 ldr r3, [pc, #16] ; (80011c8 <LL_FLASH_SetLatency+0x24>) + 80011b8: 687a ldr r2, [r7, #4] + 80011ba: 430a orrs r2, r1 + 80011bc: 601a str r2, [r3, #0] +} + 80011be: 46c0 nop ; (mov r8, r8) + 80011c0: 46bd mov sp, r7 + 80011c2: b002 add sp, #8 + 80011c4: bd80 pop {r7, pc} + 80011c6: 46c0 nop ; (mov r8, r8) + 80011c8: 40022000 .word 0x40022000 + +080011cc <LL_FLASH_GetLatency>: + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + 80011cc: b580 push {r7, lr} + 80011ce: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); + 80011d0: 4b03 ldr r3, [pc, #12] ; (80011e0 <LL_FLASH_GetLatency+0x14>) + 80011d2: 681b ldr r3, [r3, #0] + 80011d4: 2201 movs r2, #1 + 80011d6: 4013 ands r3, r2 +} + 80011d8: 0018 movs r0, r3 + 80011da: 46bd mov sp, r7 + 80011dc: bd80 pop {r7, pc} + 80011de: 46c0 nop ; (mov r8, r8) + 80011e0: 40022000 .word 0x40022000 + +080011e4 <LL_Init1msTick>: + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + 80011e4: b580 push {r7, lr} + 80011e6: b082 sub sp, #8 + 80011e8: af00 add r7, sp, #0 + 80011ea: 6078 str r0, [r7, #4] + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); + 80011ec: 23fa movs r3, #250 ; 0xfa + 80011ee: 009a lsls r2, r3, #2 + 80011f0: 687b ldr r3, [r7, #4] + 80011f2: 0011 movs r1, r2 + 80011f4: 0018 movs r0, r3 + 80011f6: f7ff ffbb bl 8001170 <LL_InitTick> +} + 80011fa: 46c0 nop ; (mov r8, r8) + 80011fc: 46bd mov sp, r7 + 80011fe: b002 add sp, #8 + 8001200: bd80 pop {r7, pc} + +08001202 <LL_mDelay>: + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + 8001202: b580 push {r7, lr} + 8001204: b084 sub sp, #16 + 8001206: af00 add r7, sp, #0 + 8001208: 6078 str r0, [r7, #4] + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + 800120a: 4b0e ldr r3, [pc, #56] ; (8001244 <LL_mDelay+0x42>) + 800120c: 681b ldr r3, [r3, #0] + 800120e: 60fb str r3, [r7, #12] + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + 8001210: 68fb ldr r3, [r7, #12] + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + 8001212: 687b ldr r3, [r7, #4] + 8001214: 3301 adds r3, #1 + 8001216: d00c beq.n 8001232 <LL_mDelay+0x30> + { + Delay++; + 8001218: 687b ldr r3, [r7, #4] + 800121a: 3301 adds r3, #1 + 800121c: 607b str r3, [r7, #4] + } + + while (Delay) + 800121e: e008 b.n 8001232 <LL_mDelay+0x30> + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + 8001220: 4b08 ldr r3, [pc, #32] ; (8001244 <LL_mDelay+0x42>) + 8001222: 681a ldr r2, [r3, #0] + 8001224: 2380 movs r3, #128 ; 0x80 + 8001226: 025b lsls r3, r3, #9 + 8001228: 4013 ands r3, r2 + 800122a: d002 beq.n 8001232 <LL_mDelay+0x30> + { + Delay--; + 800122c: 687b ldr r3, [r7, #4] + 800122e: 3b01 subs r3, #1 + 8001230: 607b str r3, [r7, #4] + while (Delay) + 8001232: 687b ldr r3, [r7, #4] + 8001234: 2b00 cmp r3, #0 + 8001236: d1f3 bne.n 8001220 <LL_mDelay+0x1e> + } + } +} + 8001238: 46c0 nop ; (mov r8, r8) + 800123a: 46c0 nop ; (mov r8, r8) + 800123c: 46bd mov sp, r7 + 800123e: b004 add sp, #16 + 8001240: bd80 pop {r7, pc} + 8001242: 46c0 nop ; (mov r8, r8) + 8001244: e000e010 .word 0xe000e010 + +08001248 <LL_SetSystemCoreClock>: + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + 8001248: b580 push {r7, lr} + 800124a: b082 sub sp, #8 + 800124c: af00 add r7, sp, #0 + 800124e: 6078 str r0, [r7, #4] + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; + 8001250: 4b03 ldr r3, [pc, #12] ; (8001260 <LL_SetSystemCoreClock+0x18>) + 8001252: 687a ldr r2, [r7, #4] + 8001254: 601a str r2, [r3, #0] +} + 8001256: 46c0 nop ; (mov r8, r8) + 8001258: 46bd mov sp, r7 + 800125a: b002 add sp, #8 + 800125c: bd80 pop {r7, pc} + 800125e: 46c0 nop ; (mov r8, r8) + 8001260: 20000000 .word 0x20000000 + +08001264 <LL_PLL_ConfigSystemClock_HSI>: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + 8001264: b590 push {r4, r7, lr} + 8001266: b085 sub sp, #20 + 8001268: af00 add r7, sp, #0 + 800126a: 6078 str r0, [r7, #4] + 800126c: 6039 str r1, [r7, #0] + ErrorStatus status = SUCCESS; + 800126e: 230f movs r3, #15 + 8001270: 18fb adds r3, r7, r3 + 8001272: 2201 movs r2, #1 + 8001274: 701a strb r2, [r3, #0] + uint32_t pllfreq = 0U; + 8001276: 2300 movs r3, #0 + 8001278: 60bb str r3, [r7, #8] + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + 800127a: f000 f8d4 bl 8001426 <UTILS_PLL_IsBusy> + 800127e: 0003 movs r3, r0 + 8001280: 2b01 cmp r3, #1 + 8001282: d128 bne.n 80012d6 <LL_PLL_ConfigSystemClock_HSI+0x72> +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + /* Check PREDIV value */ + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); +#else + /* Force PREDIV value to 2 */ + UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; + 8001284: 687b ldr r3, [r7, #4] + 8001286: 2201 movs r2, #1 + 8001288: 605a str r2, [r3, #4] +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + 800128a: 687b ldr r3, [r7, #4] + 800128c: 4a17 ldr r2, [pc, #92] ; (80012ec <LL_PLL_ConfigSystemClock_HSI+0x88>) + 800128e: 0019 movs r1, r3 + 8001290: 0010 movs r0, r2 + 8001292: f000 f8ab bl 80013ec <UTILS_GetPLLOutputFrequency> + 8001296: 0003 movs r3, r0 + 8001298: 60bb str r3, [r7, #8] + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + 800129a: f7ff fec7 bl 800102c <LL_RCC_HSI_IsReady> + 800129e: 0003 movs r3, r0 + 80012a0: 2b01 cmp r3, #1 + 80012a2: d007 beq.n 80012b4 <LL_PLL_ConfigSystemClock_HSI+0x50> + { + LL_RCC_HSI_Enable(); + 80012a4: f7ff feb4 bl 8001010 <LL_RCC_HSI_Enable> + while (LL_RCC_HSI_IsReady() != 1U) + 80012a8: 46c0 nop ; (mov r8, r8) + 80012aa: f7ff febf bl 800102c <LL_RCC_HSI_IsReady> + 80012ae: 0003 movs r3, r0 + 80012b0: 2b01 cmp r3, #1 + 80012b2: d1fa bne.n 80012aa <LL_PLL_ConfigSystemClock_HSI+0x46> + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); + 80012b4: 687b ldr r3, [r7, #4] + 80012b6: 681b ldr r3, [r3, #0] + 80012b8: 0019 movs r1, r3 + 80012ba: 2000 movs r0, #0 + 80012bc: f7ff ff32 bl 8001124 <LL_RCC_PLL_ConfigDomain_SYS> +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 80012c0: 230f movs r3, #15 + 80012c2: 18fc adds r4, r7, r3 + 80012c4: 683a ldr r2, [r7, #0] + 80012c6: 68bb ldr r3, [r7, #8] + 80012c8: 0011 movs r1, r2 + 80012ca: 0018 movs r0, r3 + 80012cc: f000 f8be bl 800144c <UTILS_EnablePLLAndSwitchSystem> + 80012d0: 0003 movs r3, r0 + 80012d2: 7023 strb r3, [r4, #0] + 80012d4: e003 b.n 80012de <LL_PLL_ConfigSystemClock_HSI+0x7a> + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + 80012d6: 230f movs r3, #15 + 80012d8: 18fb adds r3, r7, r3 + 80012da: 2200 movs r2, #0 + 80012dc: 701a strb r2, [r3, #0] + } + + return status; + 80012de: 230f movs r3, #15 + 80012e0: 18fb adds r3, r7, r3 + 80012e2: 781b ldrb r3, [r3, #0] +} + 80012e4: 0018 movs r0, r3 + 80012e6: 46bd mov sp, r7 + 80012e8: b005 add sp, #20 + 80012ea: bd90 pop {r4, r7, pc} + 80012ec: 007a1200 .word 0x007a1200 + +080012f0 <LL_PLL_ConfigSystemClock_HSE>: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + 80012f0: b590 push {r4, r7, lr} + 80012f2: b087 sub sp, #28 + 80012f4: af00 add r7, sp, #0 + 80012f6: 60f8 str r0, [r7, #12] + 80012f8: 60b9 str r1, [r7, #8] + 80012fa: 607a str r2, [r7, #4] + 80012fc: 603b str r3, [r7, #0] + ErrorStatus status = SUCCESS; + 80012fe: 2317 movs r3, #23 + 8001300: 18fb adds r3, r7, r3 + 8001302: 2201 movs r2, #1 + 8001304: 701a strb r2, [r3, #0] + uint32_t pllfreq = 0U; + 8001306: 2300 movs r3, #0 + 8001308: 613b str r3, [r7, #16] + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + 800130a: f000 f88c bl 8001426 <UTILS_PLL_IsBusy> + 800130e: 0003 movs r3, r0 + 8001310: 2b01 cmp r3, #1 + 8001312: d132 bne.n 800137a <LL_PLL_ConfigSystemClock_HSE+0x8a> +#else + assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + 8001314: 687a ldr r2, [r7, #4] + 8001316: 68fb ldr r3, [r7, #12] + 8001318: 0011 movs r1, r2 + 800131a: 0018 movs r0, r3 + 800131c: f000 f866 bl 80013ec <UTILS_GetPLLOutputFrequency> + 8001320: 0003 movs r3, r0 + 8001322: 613b str r3, [r7, #16] + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + 8001324: f7ff fe60 bl 8000fe8 <LL_RCC_HSE_IsReady> + 8001328: 0003 movs r3, r0 + 800132a: 2b01 cmp r3, #1 + 800132c: d00f beq.n 800134e <LL_PLL_ConfigSystemClock_HSE+0x5e> + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + 800132e: 68bb ldr r3, [r7, #8] + 8001330: 2b01 cmp r3, #1 + 8001332: d102 bne.n 800133a <LL_PLL_ConfigSystemClock_HSE+0x4a> + { + LL_RCC_HSE_EnableBypass(); + 8001334: f7ff fe2c bl 8000f90 <LL_RCC_HSE_EnableBypass> + 8001338: e001 b.n 800133e <LL_PLL_ConfigSystemClock_HSE+0x4e> + } + else + { + LL_RCC_HSE_DisableBypass(); + 800133a: f7ff fe37 bl 8000fac <LL_RCC_HSE_DisableBypass> + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + 800133e: f7ff fe45 bl 8000fcc <LL_RCC_HSE_Enable> + while (LL_RCC_HSE_IsReady() != 1U) + 8001342: 46c0 nop ; (mov r8, r8) + 8001344: f7ff fe50 bl 8000fe8 <LL_RCC_HSE_IsReady> + 8001348: 0003 movs r3, r0 + 800134a: 2b01 cmp r3, #1 + 800134c: d1fa bne.n 8001344 <LL_PLL_ConfigSystemClock_HSE+0x54> + + /* Configure PLL */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); + 800134e: 687b ldr r3, [r7, #4] + 8001350: 685b ldr r3, [r3, #4] + 8001352: 2280 movs r2, #128 ; 0x80 + 8001354: 0252 lsls r2, r2, #9 + 8001356: 431a orrs r2, r3 + 8001358: 687b ldr r3, [r7, #4] + 800135a: 681b ldr r3, [r3, #0] + 800135c: 0019 movs r1, r3 + 800135e: 0010 movs r0, r2 + 8001360: f7ff fee0 bl 8001124 <LL_RCC_PLL_ConfigDomain_SYS> +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + 8001364: 2317 movs r3, #23 + 8001366: 18fc adds r4, r7, r3 + 8001368: 683a ldr r2, [r7, #0] + 800136a: 693b ldr r3, [r7, #16] + 800136c: 0011 movs r1, r2 + 800136e: 0018 movs r0, r3 + 8001370: f000 f86c bl 800144c <UTILS_EnablePLLAndSwitchSystem> + 8001374: 0003 movs r3, r0 + 8001376: 7023 strb r3, [r4, #0] + 8001378: e003 b.n 8001382 <LL_PLL_ConfigSystemClock_HSE+0x92> + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + 800137a: 2317 movs r3, #23 + 800137c: 18fb adds r3, r7, r3 + 800137e: 2200 movs r2, #0 + 8001380: 701a strb r2, [r3, #0] + } + + return status; + 8001382: 2317 movs r3, #23 + 8001384: 18fb adds r3, r7, r3 + 8001386: 781b ldrb r3, [r3, #0] +} + 8001388: 0018 movs r0, r3 + 800138a: 46bd mov sp, r7 + 800138c: b007 add sp, #28 + 800138e: bd90 pop {r4, r7, pc} + +08001390 <UTILS_SetFlashLatency>: + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) +{ + 8001390: b580 push {r7, lr} + 8001392: b084 sub sp, #16 + 8001394: af00 add r7, sp, #0 + 8001396: 6078 str r0, [r7, #4] + ErrorStatus status = SUCCESS; + 8001398: 210f movs r1, #15 + 800139a: 187b adds r3, r7, r1 + 800139c: 2201 movs r2, #1 + 800139e: 701a strb r2, [r3, #0] + + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + 80013a0: 2300 movs r3, #0 + 80013a2: 60bb str r3, [r7, #8] + + /* Frequency cannot be equal to 0 */ + if (Frequency == 0U) + 80013a4: 687b ldr r3, [r7, #4] + 80013a6: 2b00 cmp r3, #0 + 80013a8: d103 bne.n 80013b2 <UTILS_SetFlashLatency+0x22> + { + status = ERROR; + 80013aa: 187b adds r3, r7, r1 + 80013ac: 2200 movs r2, #0 + 80013ae: 701a strb r2, [r3, #0] + 80013b0: e013 b.n 80013da <UTILS_SetFlashLatency+0x4a> + } + else + { + if (Frequency > UTILS_LATENCY1_FREQ) + 80013b2: 687b ldr r3, [r7, #4] + 80013b4: 4a0c ldr r2, [pc, #48] ; (80013e8 <UTILS_SetFlashLatency+0x58>) + 80013b6: 4293 cmp r3, r2 + 80013b8: d901 bls.n 80013be <UTILS_SetFlashLatency+0x2e> + { + /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + 80013ba: 2301 movs r3, #1 + 80013bc: 60bb str r3, [r7, #8] + } + /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ + + LL_FLASH_SetLatency(latency); + 80013be: 68bb ldr r3, [r7, #8] + 80013c0: 0018 movs r0, r3 + 80013c2: f7ff feef bl 80011a4 <LL_FLASH_SetLatency> + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (LL_FLASH_GetLatency() != latency) + 80013c6: f7ff ff01 bl 80011cc <LL_FLASH_GetLatency> + 80013ca: 0002 movs r2, r0 + 80013cc: 68bb ldr r3, [r7, #8] + 80013ce: 4293 cmp r3, r2 + 80013d0: d003 beq.n 80013da <UTILS_SetFlashLatency+0x4a> + { + status = ERROR; + 80013d2: 230f movs r3, #15 + 80013d4: 18fb adds r3, r7, r3 + 80013d6: 2200 movs r2, #0 + 80013d8: 701a strb r2, [r3, #0] + } + } + return status; + 80013da: 230f movs r3, #15 + 80013dc: 18fb adds r3, r7, r3 + 80013de: 781b ldrb r3, [r3, #0] +} + 80013e0: 0018 movs r0, r3 + 80013e2: 46bd mov sp, r7 + 80013e4: b004 add sp, #16 + 80013e6: bd80 pop {r7, pc} + 80013e8: 016e3600 .word 0x016e3600 + +080013ec <UTILS_GetPLLOutputFrequency>: + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + 80013ec: b580 push {r7, lr} + 80013ee: b084 sub sp, #16 + 80013f0: af00 add r7, sp, #0 + 80013f2: 6078 str r0, [r7, #4] + 80013f4: 6039 str r1, [r7, #0] + uint32_t pllfreq = 0U; + 80013f6: 2300 movs r3, #0 + 80013f8: 60fb str r3, [r7, #12] + /* The application software must set correctly the PLL multiplication factor to + be in the range 16-48MHz */ +#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); +#else + pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); + 80013fa: 683b ldr r3, [r7, #0] + 80013fc: 685b ldr r3, [r3, #4] + 80013fe: 3301 adds r3, #1 + 8001400: 0019 movs r1, r3 + 8001402: 6878 ldr r0, [r7, #4] + 8001404: f000 f8d0 bl 80015a8 <__udivsi3> + 8001408: 0003 movs r3, r0 + 800140a: 0019 movs r1, r3 + 800140c: 683b ldr r3, [r7, #0] + 800140e: 681b ldr r3, [r3, #0] + 8001410: 0c9b lsrs r3, r3, #18 + 8001412: 220f movs r2, #15 + 8001414: 4013 ands r3, r2 + 8001416: 3302 adds r3, #2 + 8001418: 434b muls r3, r1 + 800141a: 60fb str r3, [r7, #12] +#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; + 800141c: 68fb ldr r3, [r7, #12] +} + 800141e: 0018 movs r0, r3 + 8001420: 46bd mov sp, r7 + 8001422: b004 add sp, #16 + 8001424: bd80 pop {r7, pc} + +08001426 <UTILS_PLL_IsBusy>: + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + 8001426: b580 push {r7, lr} + 8001428: b082 sub sp, #8 + 800142a: af00 add r7, sp, #0 + ErrorStatus status = SUCCESS; + 800142c: 1dfb adds r3, r7, #7 + 800142e: 2201 movs r2, #1 + 8001430: 701a strb r2, [r3, #0] + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + 8001432: f7ff fe63 bl 80010fc <LL_RCC_PLL_IsReady> + 8001436: 1e03 subs r3, r0, #0 + 8001438: d002 beq.n 8001440 <UTILS_PLL_IsBusy+0x1a> + { + /* PLL configuration cannot be modified */ + status = ERROR; + 800143a: 1dfb adds r3, r7, #7 + 800143c: 2200 movs r2, #0 + 800143e: 701a strb r2, [r3, #0] + } + + + return status; + 8001440: 1dfb adds r3, r7, #7 + 8001442: 781b ldrb r3, [r3, #0] +} + 8001444: 0018 movs r0, r3 + 8001446: 46bd mov sp, r7 + 8001448: b002 add sp, #8 + 800144a: bd80 pop {r7, pc} + +0800144c <UTILS_EnablePLLAndSwitchSystem>: + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + 800144c: b590 push {r4, r7, lr} + 800144e: b085 sub sp, #20 + 8001450: af00 add r7, sp, #0 + 8001452: 6078 str r0, [r7, #4] + 8001454: 6039 str r1, [r7, #0] + ErrorStatus status = SUCCESS; + 8001456: 200f movs r0, #15 + 8001458: 183b adds r3, r7, r0 + 800145a: 2201 movs r2, #1 + 800145c: 701a strb r2, [r3, #0] + uint32_t sysclk_frequency_current = 0U; + 800145e: 2300 movs r3, #0 + 8001460: 60bb str r3, [r7, #8] + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + + /* Calculate current SYSCLK frequency */ + sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); + 8001462: 4b2e ldr r3, [pc, #184] ; (800151c <UTILS_EnablePLLAndSwitchSystem+0xd0>) + 8001464: 681a ldr r2, [r3, #0] + 8001466: 683b ldr r3, [r7, #0] + 8001468: 681b ldr r3, [r3, #0] + 800146a: 091b lsrs r3, r3, #4 + 800146c: 210f movs r1, #15 + 800146e: 400b ands r3, r1 + 8001470: 492b ldr r1, [pc, #172] ; (8001520 <UTILS_EnablePLLAndSwitchSystem+0xd4>) + 8001472: 5ccb ldrb r3, [r1, r3] + 8001474: 409a lsls r2, r3 + 8001476: 0013 movs r3, r2 + 8001478: 60bb str r3, [r7, #8] + + /* Increasing the number of wait states because of higher CPU frequency */ + if (sysclk_frequency_current < SYSCLK_Frequency) + 800147a: 68ba ldr r2, [r7, #8] + 800147c: 687b ldr r3, [r7, #4] + 800147e: 429a cmp r2, r3 + 8001480: d206 bcs.n 8001490 <UTILS_EnablePLLAndSwitchSystem+0x44> + { + /* Set FLASH latency to highest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + 8001482: 183c adds r4, r7, r0 + 8001484: 687b ldr r3, [r7, #4] + 8001486: 0018 movs r0, r3 + 8001488: f7ff ff82 bl 8001390 <UTILS_SetFlashLatency> + 800148c: 0003 movs r3, r0 + 800148e: 7023 strb r3, [r4, #0] + } + + /* Update system clock configuration */ + if (status == SUCCESS) + 8001490: 230f movs r3, #15 + 8001492: 18fb adds r3, r7, r3 + 8001494: 781b ldrb r3, [r3, #0] + 8001496: 2b01 cmp r3, #1 + 8001498: d11a bne.n 80014d0 <UTILS_EnablePLLAndSwitchSystem+0x84> + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + 800149a: f7ff fe21 bl 80010e0 <LL_RCC_PLL_Enable> + while (LL_RCC_PLL_IsReady() != 1U) + 800149e: 46c0 nop ; (mov r8, r8) + 80014a0: f7ff fe2c bl 80010fc <LL_RCC_PLL_IsReady> + 80014a4: 0003 movs r3, r0 + 80014a6: 2b01 cmp r3, #1 + 80014a8: d1fa bne.n 80014a0 <UTILS_EnablePLLAndSwitchSystem+0x54> + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + 80014aa: 683b ldr r3, [r7, #0] + 80014ac: 681b ldr r3, [r3, #0] + 80014ae: 0018 movs r0, r3 + 80014b0: f7ff fdec bl 800108c <LL_RCC_SetAHBPrescaler> + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + 80014b4: 2002 movs r0, #2 + 80014b6: f7ff fdc9 bl 800104c <LL_RCC_SetSysClkSource> + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + 80014ba: 46c0 nop ; (mov r8, r8) + 80014bc: f7ff fdda bl 8001074 <LL_RCC_GetSysClkSource> + 80014c0: 0003 movs r3, r0 + 80014c2: 2b08 cmp r3, #8 + 80014c4: d1fa bne.n 80014bc <UTILS_EnablePLLAndSwitchSystem+0x70> + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + 80014c6: 683b ldr r3, [r7, #0] + 80014c8: 685b ldr r3, [r3, #4] + 80014ca: 0018 movs r0, r3 + 80014cc: f7ff fdf2 bl 80010b4 <LL_RCC_SetAPB1Prescaler> + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (sysclk_frequency_current > SYSCLK_Frequency) + 80014d0: 68ba ldr r2, [r7, #8] + 80014d2: 687b ldr r3, [r7, #4] + 80014d4: 429a cmp r2, r3 + 80014d6: d907 bls.n 80014e8 <UTILS_EnablePLLAndSwitchSystem+0x9c> + { + /* Set FLASH latency to lowest latency */ + status = UTILS_SetFlashLatency(SYSCLK_Frequency); + 80014d8: 230f movs r3, #15 + 80014da: 18fc adds r4, r7, r3 + 80014dc: 687b ldr r3, [r7, #4] + 80014de: 0018 movs r0, r3 + 80014e0: f7ff ff56 bl 8001390 <UTILS_SetFlashLatency> + 80014e4: 0003 movs r3, r0 + 80014e6: 7023 strb r3, [r4, #0] + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + 80014e8: 230f movs r3, #15 + 80014ea: 18fb adds r3, r7, r3 + 80014ec: 781b ldrb r3, [r3, #0] + 80014ee: 2b01 cmp r3, #1 + 80014f0: d10c bne.n 800150c <UTILS_EnablePLLAndSwitchSystem+0xc0> + { + LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); + 80014f2: 683b ldr r3, [r7, #0] + 80014f4: 681b ldr r3, [r3, #0] + 80014f6: 091b lsrs r3, r3, #4 + 80014f8: 220f movs r2, #15 + 80014fa: 4013 ands r3, r2 + 80014fc: 4a08 ldr r2, [pc, #32] ; (8001520 <UTILS_EnablePLLAndSwitchSystem+0xd4>) + 80014fe: 5cd3 ldrb r3, [r2, r3] + 8001500: 001a movs r2, r3 + 8001502: 687b ldr r3, [r7, #4] + 8001504: 40d3 lsrs r3, r2 + 8001506: 0018 movs r0, r3 + 8001508: f7ff fe9e bl 8001248 <LL_SetSystemCoreClock> + } + + return status; + 800150c: 230f movs r3, #15 + 800150e: 18fb adds r3, r7, r3 + 8001510: 781b ldrb r3, [r3, #0] +} + 8001512: 0018 movs r0, r3 + 8001514: 46bd mov sp, r7 + 8001516: b005 add sp, #20 + 8001518: bd90 pop {r4, r7, pc} + 800151a: 46c0 nop ; (mov r8, r8) + 800151c: 20000000 .word 0x20000000 + 8001520: 080018ec .word 0x080018ec + +08001524 <__sinit>: +#include <stdbool.h> + +int __errno = 0; +void *_impure_ptr = NULL; + +void __sinit(void) { + 8001524: b580 push {r7, lr} + 8001526: af00 add r7, sp, #0 +} + 8001528: 46c0 nop ; (mov r8, r8) + 800152a: 46bd mov sp, r7 + 800152c: bd80 pop {r7, pc} + +0800152e <memset>: + +void *memset(void *s, int c, size_t n) { + 800152e: b580 push {r7, lr} + 8001530: b086 sub sp, #24 + 8001532: af00 add r7, sp, #0 + 8001534: 60f8 str r0, [r7, #12] + 8001536: 60b9 str r1, [r7, #8] + 8001538: 607a str r2, [r7, #4] + char *end = (char *)s + n; + 800153a: 68fa ldr r2, [r7, #12] + 800153c: 687b ldr r3, [r7, #4] + 800153e: 18d3 adds r3, r2, r3 + 8001540: 613b str r3, [r7, #16] + for (char *p = (char *)s; p < end; p++) + 8001542: 68fb ldr r3, [r7, #12] + 8001544: 617b str r3, [r7, #20] + 8001546: e006 b.n 8001556 <memset+0x28> + *p = (char)c; + 8001548: 68bb ldr r3, [r7, #8] + 800154a: b2da uxtb r2, r3 + 800154c: 697b ldr r3, [r7, #20] + 800154e: 701a strb r2, [r3, #0] + for (char *p = (char *)s; p < end; p++) + 8001550: 697b ldr r3, [r7, #20] + 8001552: 3301 adds r3, #1 + 8001554: 617b str r3, [r7, #20] + 8001556: 697a ldr r2, [r7, #20] + 8001558: 693b ldr r3, [r7, #16] + 800155a: 429a cmp r2, r3 + 800155c: d3f4 bcc.n 8001548 <memset+0x1a> + return s; + 800155e: 68fb ldr r3, [r7, #12] +} + 8001560: 0018 movs r0, r3 + 8001562: 46bd mov sp, r7 + 8001564: b006 add sp, #24 + 8001566: bd80 pop {r7, pc} + +08001568 <strlen>: + +size_t strlen(const char *s) { + 8001568: b580 push {r7, lr} + 800156a: b084 sub sp, #16 + 800156c: af00 add r7, sp, #0 + 800156e: 6078 str r0, [r7, #4] + const char *start = s; + 8001570: 687b ldr r3, [r7, #4] + 8001572: 60fb str r3, [r7, #12] + while (*s++); + 8001574: 46c0 nop ; (mov r8, r8) + 8001576: 687b ldr r3, [r7, #4] + 8001578: 1c5a adds r2, r3, #1 + 800157a: 607a str r2, [r7, #4] + 800157c: 781b ldrb r3, [r3, #0] + 800157e: 2b00 cmp r3, #0 + 8001580: d1f9 bne.n 8001576 <strlen+0xe> + return s - start - 1; + 8001582: 687a ldr r2, [r7, #4] + 8001584: 68fb ldr r3, [r7, #12] + 8001586: 1ad3 subs r3, r2, r3 + 8001588: 3b01 subs r3, #1 +} + 800158a: 0018 movs r0, r3 + 800158c: 46bd mov sp, r7 + 800158e: b004 add sp, #16 + 8001590: bd80 pop {r7, pc} + +08001592 <__assert_func>: + +void __assert_func(bool value) { + 8001592: b580 push {r7, lr} + 8001594: b082 sub sp, #8 + 8001596: af00 add r7, sp, #0 + 8001598: 0002 movs r2, r0 + 800159a: 1dfb adds r3, r7, #7 + 800159c: 701a strb r2, [r3, #0] +} + 800159e: 46c0 nop ; (mov r8, r8) + 80015a0: 46bd mov sp, r7 + 80015a2: b002 add sp, #8 + 80015a4: bd80 pop {r7, pc} + ... + +080015a8 <__udivsi3>: + 80015a8: 2200 movs r2, #0 + 80015aa: 0843 lsrs r3, r0, #1 + 80015ac: 428b cmp r3, r1 + 80015ae: d374 bcc.n 800169a <__udivsi3+0xf2> + 80015b0: 0903 lsrs r3, r0, #4 + 80015b2: 428b cmp r3, r1 + 80015b4: d35f bcc.n 8001676 <__udivsi3+0xce> + 80015b6: 0a03 lsrs r3, r0, #8 + 80015b8: 428b cmp r3, r1 + 80015ba: d344 bcc.n 8001646 <__udivsi3+0x9e> + 80015bc: 0b03 lsrs r3, r0, #12 + 80015be: 428b cmp r3, r1 + 80015c0: d328 bcc.n 8001614 <__udivsi3+0x6c> + 80015c2: 0c03 lsrs r3, r0, #16 + 80015c4: 428b cmp r3, r1 + 80015c6: d30d bcc.n 80015e4 <__udivsi3+0x3c> + 80015c8: 22ff movs r2, #255 ; 0xff + 80015ca: 0209 lsls r1, r1, #8 + 80015cc: ba12 rev r2, r2 + 80015ce: 0c03 lsrs r3, r0, #16 + 80015d0: 428b cmp r3, r1 + 80015d2: d302 bcc.n 80015da <__udivsi3+0x32> + 80015d4: 1212 asrs r2, r2, #8 + 80015d6: 0209 lsls r1, r1, #8 + 80015d8: d065 beq.n 80016a6 <__udivsi3+0xfe> + 80015da: 0b03 lsrs r3, r0, #12 + 80015dc: 428b cmp r3, r1 + 80015de: d319 bcc.n 8001614 <__udivsi3+0x6c> + 80015e0: e000 b.n 80015e4 <__udivsi3+0x3c> + 80015e2: 0a09 lsrs r1, r1, #8 + 80015e4: 0bc3 lsrs r3, r0, #15 + 80015e6: 428b cmp r3, r1 + 80015e8: d301 bcc.n 80015ee <__udivsi3+0x46> + 80015ea: 03cb lsls r3, r1, #15 + 80015ec: 1ac0 subs r0, r0, r3 + 80015ee: 4152 adcs r2, r2 + 80015f0: 0b83 lsrs r3, r0, #14 + 80015f2: 428b cmp r3, r1 + 80015f4: d301 bcc.n 80015fa <__udivsi3+0x52> + 80015f6: 038b lsls r3, r1, #14 + 80015f8: 1ac0 subs r0, r0, r3 + 80015fa: 4152 adcs r2, r2 + 80015fc: 0b43 lsrs r3, r0, #13 + 80015fe: 428b cmp r3, r1 + 8001600: d301 bcc.n 8001606 <__udivsi3+0x5e> + 8001602: 034b lsls r3, r1, #13 + 8001604: 1ac0 subs r0, r0, r3 + 8001606: 4152 adcs r2, r2 + 8001608: 0b03 lsrs r3, r0, #12 + 800160a: 428b cmp r3, r1 + 800160c: d301 bcc.n 8001612 <__udivsi3+0x6a> + 800160e: 030b lsls r3, r1, #12 + 8001610: 1ac0 subs r0, r0, r3 + 8001612: 4152 adcs r2, r2 + 8001614: 0ac3 lsrs r3, r0, #11 + 8001616: 428b cmp r3, r1 + 8001618: d301 bcc.n 800161e <__udivsi3+0x76> + 800161a: 02cb lsls r3, r1, #11 + 800161c: 1ac0 subs r0, r0, r3 + 800161e: 4152 adcs r2, r2 + 8001620: 0a83 lsrs r3, r0, #10 + 8001622: 428b cmp r3, r1 + 8001624: d301 bcc.n 800162a <__udivsi3+0x82> + 8001626: 028b lsls r3, r1, #10 + 8001628: 1ac0 subs r0, r0, r3 + 800162a: 4152 adcs r2, r2 + 800162c: 0a43 lsrs r3, r0, #9 + 800162e: 428b cmp r3, r1 + 8001630: d301 bcc.n 8001636 <__udivsi3+0x8e> + 8001632: 024b lsls r3, r1, #9 + 8001634: 1ac0 subs r0, r0, r3 + 8001636: 4152 adcs r2, r2 + 8001638: 0a03 lsrs r3, r0, #8 + 800163a: 428b cmp r3, r1 + 800163c: d301 bcc.n 8001642 <__udivsi3+0x9a> + 800163e: 020b lsls r3, r1, #8 + 8001640: 1ac0 subs r0, r0, r3 + 8001642: 4152 adcs r2, r2 + 8001644: d2cd bcs.n 80015e2 <__udivsi3+0x3a> + 8001646: 09c3 lsrs r3, r0, #7 + 8001648: 428b cmp r3, r1 + 800164a: d301 bcc.n 8001650 <__udivsi3+0xa8> + 800164c: 01cb lsls r3, r1, #7 + 800164e: 1ac0 subs r0, r0, r3 + 8001650: 4152 adcs r2, r2 + 8001652: 0983 lsrs r3, r0, #6 + 8001654: 428b cmp r3, r1 + 8001656: d301 bcc.n 800165c <__udivsi3+0xb4> + 8001658: 018b lsls r3, r1, #6 + 800165a: 1ac0 subs r0, r0, r3 + 800165c: 4152 adcs r2, r2 + 800165e: 0943 lsrs r3, r0, #5 + 8001660: 428b cmp r3, r1 + 8001662: d301 bcc.n 8001668 <__udivsi3+0xc0> + 8001664: 014b lsls r3, r1, #5 + 8001666: 1ac0 subs r0, r0, r3 + 8001668: 4152 adcs r2, r2 + 800166a: 0903 lsrs r3, r0, #4 + 800166c: 428b cmp r3, r1 + 800166e: d301 bcc.n 8001674 <__udivsi3+0xcc> + 8001670: 010b lsls r3, r1, #4 + 8001672: 1ac0 subs r0, r0, r3 + 8001674: 4152 adcs r2, r2 + 8001676: 08c3 lsrs r3, r0, #3 + 8001678: 428b cmp r3, r1 + 800167a: d301 bcc.n 8001680 <__udivsi3+0xd8> + 800167c: 00cb lsls r3, r1, #3 + 800167e: 1ac0 subs r0, r0, r3 + 8001680: 4152 adcs r2, r2 + 8001682: 0883 lsrs r3, r0, #2 + 8001684: 428b cmp r3, r1 + 8001686: d301 bcc.n 800168c <__udivsi3+0xe4> + 8001688: 008b lsls r3, r1, #2 + 800168a: 1ac0 subs r0, r0, r3 + 800168c: 4152 adcs r2, r2 + 800168e: 0843 lsrs r3, r0, #1 + 8001690: 428b cmp r3, r1 + 8001692: d301 bcc.n 8001698 <__udivsi3+0xf0> + 8001694: 004b lsls r3, r1, #1 + 8001696: 1ac0 subs r0, r0, r3 + 8001698: 4152 adcs r2, r2 + 800169a: 1a41 subs r1, r0, r1 + 800169c: d200 bcs.n 80016a0 <__udivsi3+0xf8> + 800169e: 4601 mov r1, r0 + 80016a0: 4152 adcs r2, r2 + 80016a2: 4610 mov r0, r2 + 80016a4: 4770 bx lr + 80016a6: e7ff b.n 80016a8 <__udivsi3+0x100> + 80016a8: b501 push {r0, lr} + 80016aa: 2000 movs r0, #0 + 80016ac: f000 f8f0 bl 8001890 <__aeabi_idiv0> + 80016b0: bd02 pop {r1, pc} + 80016b2: 46c0 nop ; (mov r8, r8) + +080016b4 <__aeabi_uidivmod>: + 80016b4: 2900 cmp r1, #0 + 80016b6: d0f7 beq.n 80016a8 <__udivsi3+0x100> + 80016b8: e776 b.n 80015a8 <__udivsi3> + 80016ba: 4770 bx lr + +080016bc <__divsi3>: + 80016bc: 4603 mov r3, r0 + 80016be: 430b orrs r3, r1 + 80016c0: d47f bmi.n 80017c2 <__divsi3+0x106> + 80016c2: 2200 movs r2, #0 + 80016c4: 0843 lsrs r3, r0, #1 + 80016c6: 428b cmp r3, r1 + 80016c8: d374 bcc.n 80017b4 <__divsi3+0xf8> + 80016ca: 0903 lsrs r3, r0, #4 + 80016cc: 428b cmp r3, r1 + 80016ce: d35f bcc.n 8001790 <__divsi3+0xd4> + 80016d0: 0a03 lsrs r3, r0, #8 + 80016d2: 428b cmp r3, r1 + 80016d4: d344 bcc.n 8001760 <__divsi3+0xa4> + 80016d6: 0b03 lsrs r3, r0, #12 + 80016d8: 428b cmp r3, r1 + 80016da: d328 bcc.n 800172e <__divsi3+0x72> + 80016dc: 0c03 lsrs r3, r0, #16 + 80016de: 428b cmp r3, r1 + 80016e0: d30d bcc.n 80016fe <__divsi3+0x42> + 80016e2: 22ff movs r2, #255 ; 0xff + 80016e4: 0209 lsls r1, r1, #8 + 80016e6: ba12 rev r2, r2 + 80016e8: 0c03 lsrs r3, r0, #16 + 80016ea: 428b cmp r3, r1 + 80016ec: d302 bcc.n 80016f4 <__divsi3+0x38> + 80016ee: 1212 asrs r2, r2, #8 + 80016f0: 0209 lsls r1, r1, #8 + 80016f2: d065 beq.n 80017c0 <__divsi3+0x104> + 80016f4: 0b03 lsrs r3, r0, #12 + 80016f6: 428b cmp r3, r1 + 80016f8: d319 bcc.n 800172e <__divsi3+0x72> + 80016fa: e000 b.n 80016fe <__divsi3+0x42> + 80016fc: 0a09 lsrs r1, r1, #8 + 80016fe: 0bc3 lsrs r3, r0, #15 + 8001700: 428b cmp r3, r1 + 8001702: d301 bcc.n 8001708 <__divsi3+0x4c> + 8001704: 03cb lsls r3, r1, #15 + 8001706: 1ac0 subs r0, r0, r3 + 8001708: 4152 adcs r2, r2 + 800170a: 0b83 lsrs r3, r0, #14 + 800170c: 428b cmp r3, r1 + 800170e: d301 bcc.n 8001714 <__divsi3+0x58> + 8001710: 038b lsls r3, r1, #14 + 8001712: 1ac0 subs r0, r0, r3 + 8001714: 4152 adcs r2, r2 + 8001716: 0b43 lsrs r3, r0, #13 + 8001718: 428b cmp r3, r1 + 800171a: d301 bcc.n 8001720 <__divsi3+0x64> + 800171c: 034b lsls r3, r1, #13 + 800171e: 1ac0 subs r0, r0, r3 + 8001720: 4152 adcs r2, r2 + 8001722: 0b03 lsrs r3, r0, #12 + 8001724: 428b cmp r3, r1 + 8001726: d301 bcc.n 800172c <__divsi3+0x70> + 8001728: 030b lsls r3, r1, #12 + 800172a: 1ac0 subs r0, r0, r3 + 800172c: 4152 adcs r2, r2 + 800172e: 0ac3 lsrs r3, r0, #11 + 8001730: 428b cmp r3, r1 + 8001732: d301 bcc.n 8001738 <__divsi3+0x7c> + 8001734: 02cb lsls r3, r1, #11 + 8001736: 1ac0 subs r0, r0, r3 + 8001738: 4152 adcs r2, r2 + 800173a: 0a83 lsrs r3, r0, #10 + 800173c: 428b cmp r3, r1 + 800173e: d301 bcc.n 8001744 <__divsi3+0x88> + 8001740: 028b lsls r3, r1, #10 + 8001742: 1ac0 subs r0, r0, r3 + 8001744: 4152 adcs r2, r2 + 8001746: 0a43 lsrs r3, r0, #9 + 8001748: 428b cmp r3, r1 + 800174a: d301 bcc.n 8001750 <__divsi3+0x94> + 800174c: 024b lsls r3, r1, #9 + 800174e: 1ac0 subs r0, r0, r3 + 8001750: 4152 adcs r2, r2 + 8001752: 0a03 lsrs r3, r0, #8 + 8001754: 428b cmp r3, r1 + 8001756: d301 bcc.n 800175c <__divsi3+0xa0> + 8001758: 020b lsls r3, r1, #8 + 800175a: 1ac0 subs r0, r0, r3 + 800175c: 4152 adcs r2, r2 + 800175e: d2cd bcs.n 80016fc <__divsi3+0x40> + 8001760: 09c3 lsrs r3, r0, #7 + 8001762: 428b cmp r3, r1 + 8001764: d301 bcc.n 800176a <__divsi3+0xae> + 8001766: 01cb lsls r3, r1, #7 + 8001768: 1ac0 subs r0, r0, r3 + 800176a: 4152 adcs r2, r2 + 800176c: 0983 lsrs r3, r0, #6 + 800176e: 428b cmp r3, r1 + 8001770: d301 bcc.n 8001776 <__divsi3+0xba> + 8001772: 018b lsls r3, r1, #6 + 8001774: 1ac0 subs r0, r0, r3 + 8001776: 4152 adcs r2, r2 + 8001778: 0943 lsrs r3, r0, #5 + 800177a: 428b cmp r3, r1 + 800177c: d301 bcc.n 8001782 <__divsi3+0xc6> + 800177e: 014b lsls r3, r1, #5 + 8001780: 1ac0 subs r0, r0, r3 + 8001782: 4152 adcs r2, r2 + 8001784: 0903 lsrs r3, r0, #4 + 8001786: 428b cmp r3, r1 + 8001788: d301 bcc.n 800178e <__divsi3+0xd2> + 800178a: 010b lsls r3, r1, #4 + 800178c: 1ac0 subs r0, r0, r3 + 800178e: 4152 adcs r2, r2 + 8001790: 08c3 lsrs r3, r0, #3 + 8001792: 428b cmp r3, r1 + 8001794: d301 bcc.n 800179a <__divsi3+0xde> + 8001796: 00cb lsls r3, r1, #3 + 8001798: 1ac0 subs r0, r0, r3 + 800179a: 4152 adcs r2, r2 + 800179c: 0883 lsrs r3, r0, #2 + 800179e: 428b cmp r3, r1 + 80017a0: d301 bcc.n 80017a6 <__divsi3+0xea> + 80017a2: 008b lsls r3, r1, #2 + 80017a4: 1ac0 subs r0, r0, r3 + 80017a6: 4152 adcs r2, r2 + 80017a8: 0843 lsrs r3, r0, #1 + 80017aa: 428b cmp r3, r1 + 80017ac: d301 bcc.n 80017b2 <__divsi3+0xf6> + 80017ae: 004b lsls r3, r1, #1 + 80017b0: 1ac0 subs r0, r0, r3 + 80017b2: 4152 adcs r2, r2 + 80017b4: 1a41 subs r1, r0, r1 + 80017b6: d200 bcs.n 80017ba <__divsi3+0xfe> + 80017b8: 4601 mov r1, r0 + 80017ba: 4152 adcs r2, r2 + 80017bc: 4610 mov r0, r2 + 80017be: 4770 bx lr + 80017c0: e05d b.n 800187e <__divsi3+0x1c2> + 80017c2: 0fca lsrs r2, r1, #31 + 80017c4: d000 beq.n 80017c8 <__divsi3+0x10c> + 80017c6: 4249 negs r1, r1 + 80017c8: 1003 asrs r3, r0, #32 + 80017ca: d300 bcc.n 80017ce <__divsi3+0x112> + 80017cc: 4240 negs r0, r0 + 80017ce: 4053 eors r3, r2 + 80017d0: 2200 movs r2, #0 + 80017d2: 469c mov ip, r3 + 80017d4: 0903 lsrs r3, r0, #4 + 80017d6: 428b cmp r3, r1 + 80017d8: d32d bcc.n 8001836 <__divsi3+0x17a> + 80017da: 0a03 lsrs r3, r0, #8 + 80017dc: 428b cmp r3, r1 + 80017de: d312 bcc.n 8001806 <__divsi3+0x14a> + 80017e0: 22fc movs r2, #252 ; 0xfc + 80017e2: 0189 lsls r1, r1, #6 + 80017e4: ba12 rev r2, r2 + 80017e6: 0a03 lsrs r3, r0, #8 + 80017e8: 428b cmp r3, r1 + 80017ea: d30c bcc.n 8001806 <__divsi3+0x14a> + 80017ec: 0189 lsls r1, r1, #6 + 80017ee: 1192 asrs r2, r2, #6 + 80017f0: 428b cmp r3, r1 + 80017f2: d308 bcc.n 8001806 <__divsi3+0x14a> + 80017f4: 0189 lsls r1, r1, #6 + 80017f6: 1192 asrs r2, r2, #6 + 80017f8: 428b cmp r3, r1 + 80017fa: d304 bcc.n 8001806 <__divsi3+0x14a> + 80017fc: 0189 lsls r1, r1, #6 + 80017fe: d03a beq.n 8001876 <__divsi3+0x1ba> + 8001800: 1192 asrs r2, r2, #6 + 8001802: e000 b.n 8001806 <__divsi3+0x14a> + 8001804: 0989 lsrs r1, r1, #6 + 8001806: 09c3 lsrs r3, r0, #7 + 8001808: 428b cmp r3, r1 + 800180a: d301 bcc.n 8001810 <__divsi3+0x154> + 800180c: 01cb lsls r3, r1, #7 + 800180e: 1ac0 subs r0, r0, r3 + 8001810: 4152 adcs r2, r2 + 8001812: 0983 lsrs r3, r0, #6 + 8001814: 428b cmp r3, r1 + 8001816: d301 bcc.n 800181c <__divsi3+0x160> + 8001818: 018b lsls r3, r1, #6 + 800181a: 1ac0 subs r0, r0, r3 + 800181c: 4152 adcs r2, r2 + 800181e: 0943 lsrs r3, r0, #5 + 8001820: 428b cmp r3, r1 + 8001822: d301 bcc.n 8001828 <__divsi3+0x16c> + 8001824: 014b lsls r3, r1, #5 + 8001826: 1ac0 subs r0, r0, r3 + 8001828: 4152 adcs r2, r2 + 800182a: 0903 lsrs r3, r0, #4 + 800182c: 428b cmp r3, r1 + 800182e: d301 bcc.n 8001834 <__divsi3+0x178> + 8001830: 010b lsls r3, r1, #4 + 8001832: 1ac0 subs r0, r0, r3 + 8001834: 4152 adcs r2, r2 + 8001836: 08c3 lsrs r3, r0, #3 + 8001838: 428b cmp r3, r1 + 800183a: d301 bcc.n 8001840 <__divsi3+0x184> + 800183c: 00cb lsls r3, r1, #3 + 800183e: 1ac0 subs r0, r0, r3 + 8001840: 4152 adcs r2, r2 + 8001842: 0883 lsrs r3, r0, #2 + 8001844: 428b cmp r3, r1 + 8001846: d301 bcc.n 800184c <__divsi3+0x190> + 8001848: 008b lsls r3, r1, #2 + 800184a: 1ac0 subs r0, r0, r3 + 800184c: 4152 adcs r2, r2 + 800184e: d2d9 bcs.n 8001804 <__divsi3+0x148> + 8001850: 0843 lsrs r3, r0, #1 + 8001852: 428b cmp r3, r1 + 8001854: d301 bcc.n 800185a <__divsi3+0x19e> + 8001856: 004b lsls r3, r1, #1 + 8001858: 1ac0 subs r0, r0, r3 + 800185a: 4152 adcs r2, r2 + 800185c: 1a41 subs r1, r0, r1 + 800185e: d200 bcs.n 8001862 <__divsi3+0x1a6> + 8001860: 4601 mov r1, r0 + 8001862: 4663 mov r3, ip + 8001864: 4152 adcs r2, r2 + 8001866: 105b asrs r3, r3, #1 + 8001868: 4610 mov r0, r2 + 800186a: d301 bcc.n 8001870 <__divsi3+0x1b4> + 800186c: 4240 negs r0, r0 + 800186e: 2b00 cmp r3, #0 + 8001870: d500 bpl.n 8001874 <__divsi3+0x1b8> + 8001872: 4249 negs r1, r1 + 8001874: 4770 bx lr + 8001876: 4663 mov r3, ip + 8001878: 105b asrs r3, r3, #1 + 800187a: d300 bcc.n 800187e <__divsi3+0x1c2> + 800187c: 4240 negs r0, r0 + 800187e: b501 push {r0, lr} + 8001880: 2000 movs r0, #0 + 8001882: f000 f805 bl 8001890 <__aeabi_idiv0> + 8001886: bd02 pop {r1, pc} + +08001888 <__aeabi_idivmod>: + 8001888: 2900 cmp r1, #0 + 800188a: d0f8 beq.n 800187e <__divsi3+0x1c2> + 800188c: e716 b.n 80016bc <__divsi3> + 800188e: 4770 bx lr + +08001890 <__aeabi_idiv0>: + 8001890: 4770 bx lr + 8001892: 46c0 nop ; (mov r8, r8) + +08001894 <Reset_Handler>: + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8001894: 480c ldr r0, [pc, #48] ; (80018c8 <LoopForever+0x2>) + mov sp, r0 /* set stack pointer */ + 8001896: 4685 mov sp, r0 + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + 8001898: 2100 movs r1, #0 + b LoopCopyDataInit + 800189a: e003 b.n 80018a4 <LoopCopyDataInit> + +0800189c <CopyDataInit>: + +CopyDataInit: + ldr r3, =_sidata + 800189c: 4b0b ldr r3, [pc, #44] ; (80018cc <LoopForever+0x6>) + ldr r3, [r3, r1] + 800189e: 585b ldr r3, [r3, r1] + str r3, [r0, r1] + 80018a0: 5043 str r3, [r0, r1] + adds r1, r1, #4 + 80018a2: 3104 adds r1, #4 + +080018a4 <LoopCopyDataInit>: + +LoopCopyDataInit: + ldr r0, =_sdata + 80018a4: 480a ldr r0, [pc, #40] ; (80018d0 <LoopForever+0xa>) + ldr r3, =_edata + 80018a6: 4b0b ldr r3, [pc, #44] ; (80018d4 <LoopForever+0xe>) + adds r2, r0, r1 + 80018a8: 1842 adds r2, r0, r1 + cmp r2, r3 + 80018aa: 429a cmp r2, r3 + bcc CopyDataInit + 80018ac: d3f6 bcc.n 800189c <CopyDataInit> + ldr r2, =_sbss + 80018ae: 4a0a ldr r2, [pc, #40] ; (80018d8 <LoopForever+0x12>) + b LoopFillZerobss + 80018b0: e002 b.n 80018b8 <LoopFillZerobss> + +080018b2 <FillZerobss>: +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + 80018b2: 2300 movs r3, #0 + str r3, [r2] + 80018b4: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80018b6: 3204 adds r2, #4 + +080018b8 <LoopFillZerobss>: + + +LoopFillZerobss: + ldr r3, = _ebss + 80018b8: 4b08 ldr r3, [pc, #32] ; (80018dc <LoopForever+0x16>) + cmp r2, r3 + 80018ba: 429a cmp r2, r3 + bcc FillZerobss + 80018bc: d3f9 bcc.n 80018b2 <FillZerobss> + +/* Call the clock system intitialization function.*/ + bl SystemInit + 80018be: f7ff faad bl 8000e1c <SystemInit> +/* Call static constructors */ +// bl __libc_init_array +/* Call the application's entry point.*/ + bl main + 80018c2: f7fe fcaa bl 800021a <main> + +080018c6 <LoopForever>: + +LoopForever: + b LoopForever + 80018c6: e7fe b.n 80018c6 <LoopForever> + ldr r0, =_estack + 80018c8: 20001000 .word 0x20001000 + ldr r3, =_sidata + 80018cc: 08001904 .word 0x08001904 + ldr r0, =_sdata + 80018d0: 20000000 .word 0x20000000 + ldr r3, =_edata + 80018d4: 20000094 .word 0x20000094 + ldr r2, =_sbss + 80018d8: 20000094 .word 0x20000094 + ldr r3, = _ebss + 80018dc: 200009d4 .word 0x200009d4 + +080018e0 <ADC1_IRQHandler>: + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 80018e0: e7fe b.n 80018e0 <ADC1_IRQHandler> + 80018e2: 0000 movs r0, r0 + 80018e4: 424f4f46 .word 0x424f4f46 + 80018e8: 000a5241 .word 0x000a5241 + +080018ec <AHBPrescTable>: + ... + 80018f4: 04030201 09080706 ........ + +080018fc <APBPrescTable>: + 80018fc: 00000000 04030201 ........ |