diff options
Diffstat (limited to 'gm_platform/fw/main.lst')
| -rw-r--r-- | gm_platform/fw/main.lst | 4951 |
1 files changed, 0 insertions, 4951 deletions
diff --git a/gm_platform/fw/main.lst b/gm_platform/fw/main.lst deleted file mode 100644 index 1fc34f4..0000000 --- a/gm_platform/fw/main.lst +++ /dev/null @@ -1,4951 +0,0 @@ - -main.elf: file format elf32-littlearm - -SYMBOL TABLE: -08000000 l d .isr_vector 00000000 .isr_vector -080000c0 l d .text 00000000 .text -20000000 l d .data 00000000 .data -20000094 l d .bss 00000000 .bss -00000000 l d .comment 00000000 .comment -00000000 l d .ARM.attributes 00000000 .ARM.attributes -00000000 l d .debug_aranges 00000000 .debug_aranges -00000000 l d .debug_info 00000000 .debug_info -00000000 l d .debug_abbrev 00000000 .debug_abbrev -00000000 l d .debug_line 00000000 .debug_line -00000000 l d .debug_frame 00000000 .debug_frame -00000000 l d .debug_str 00000000 .debug_str -00000000 l d .debug_ranges 00000000 .debug_ranges -00000000 l df *ABS* 00000000 /tmp/ccNO0bzV.o -08001be4 l .text 00000000 LoopCopyDataInit -08001bdc l .text 00000000 CopyDataInit -08001bf8 l .text 00000000 LoopFillZerobss -08001bf2 l .text 00000000 FillZerobss -08001c06 l .text 00000000 LoopForever -08001c20 l .text 00000000 Infinite_Loop -00000000 l df *ABS* 00000000 main.c -080000c0 l F .text 0000002c NVIC_EnableIRQ -080000ec l F .text 000000dc NVIC_SetPriority -080001c8 l F .text 00000048 SysTick_Config -20000098 l .bss 00000004 leds_update_counter.5796 -2000009c l .bss 00000004 n.5819 -00000000 l df *ABS* 00000000 adc.c -080004e8 l F .text 0000002c NVIC_EnableIRQ -08000514 l F .text 000000dc NVIC_SetPriority -200000a0 l .bss 00000090 adc_pkt -20000130 l .bss 00000002 current_seq -20000134 l .bss 00000004 current_buf -08000690 l F .text 00000040 adc_dma_init -0800072c l F .text 00000064 adc_timer_init -080006d0 l F .text 0000005c adc_dma_launch -08000790 l F .text 0000000a gdb_dump -00000000 l df *ABS* 00000000 serial.c -0800081c l F .text 0000002c NVIC_EnableIRQ -08000848 l F .text 00000030 NVIC_DisableIRQ -08000878 l F .text 000000dc NVIC_SetPriority -20000138 l .bss 00000004 tx_overruns -2000013c l .bss 00000004 rx_overruns -20000140 l .bss 00000004 rx_framing_errors -20000144 l .bss 00000004 rx_protocol_errors -20000148 l .bss 00000008 cobs_state -20000150 l .bss 00000020 rx_buf -08000b68 l F .text 000000d0 usart_schedule_dma -08000d24 l F .text 00000028 usart_putc_nonblocking -00000000 l df *ABS* 00000000 cobs.c -00000000 l df *ABS* 00000000 system_stm32f0xx.c -00000000 l df *ABS* 00000000 stm32f0xx_ll_utils.c -080012d0 l F .text 0000001c LL_RCC_HSE_EnableBypass -080012ec l F .text 00000020 LL_RCC_HSE_DisableBypass -0800130c l F .text 0000001c LL_RCC_HSE_Enable -08001328 l F .text 00000028 LL_RCC_HSE_IsReady -08001350 l F .text 0000001c LL_RCC_HSI_Enable -0800136c l F .text 00000020 LL_RCC_HSI_IsReady -0800138c l F .text 00000028 LL_RCC_SetSysClkSource -080013b4 l F .text 00000018 LL_RCC_GetSysClkSource -080013cc l F .text 00000028 LL_RCC_SetAHBPrescaler -080013f4 l F .text 0000002c LL_RCC_SetAPB1Prescaler -08001420 l F .text 0000001c LL_RCC_PLL_Enable -0800143c l F .text 00000028 LL_RCC_PLL_IsReady -08001464 l F .text 0000004c LL_RCC_PLL_ConfigDomain_SYS -080014b0 l F .text 00000034 LL_InitTick -080014e4 l F .text 00000028 LL_FLASH_SetLatency -0800150c l F .text 00000018 LL_FLASH_GetLatency -08001766 l F .text 00000026 UTILS_PLL_IsBusy -0800172c l F .text 0000003a UTILS_GetPLLOutputFrequency -0800178c l F .text 000000d8 UTILS_EnablePLLAndSwitchSystem -080016d0 l F .text 0000005c UTILS_SetFlashLatency -00000000 l df *ABS* 00000000 base.c -00000000 l df *ABS* 00000000 cmsis_exports.c -00000000 l df *ABS* 00000000 _udivsi3.o -080018e8 l .text 00000000 .udivsi3_skip_div0_test -00000000 l df *ABS* 00000000 _divsi3.o -080019fc l .text 00000000 .divsi3_skip_div0_test -00000000 l df *ABS* 00000000 _dvmd_tls.o -08001c34 g O .text 00000008 APBPrescTable -20000044 g O .data 00000004 tim17 -2000007c g O .data 00000004 gpioc -20000088 g O .data 00000004 scb -08001542 g F .text 00000046 LL_mDelay -08001c20 w F .text 00000002 TIM1_CC_IRQHandler -08001864 g F .text 0000000a __sinit -08000490 g F .text 00000004 HardFault_Handler -2000006c g O .data 00000004 rcc -080004ac g F .text 0000003c SysTick_Handler -08001c3c g .text 00000000 _sidata -080004a0 g F .text 0000000c PendSV_Handler -20000020 g O .data 00000004 syscfg -08000484 g F .text 0000000c NMI_Handler -200003d4 g .bss 00000000 __exidx_end -080015a4 g F .text 0000008c LL_PLL_ConfigSystemClock_HSI -08001c20 w F .text 00000002 I2C1_IRQHandler -08001588 g F .text 0000001c LL_SetSystemCoreClock -20000170 g O .bss 00000004 __errno -20000008 g O .data 00000004 tim14 -20000048 g O .data 00000004 dbgmcu -2000003c g O .data 00000004 usart1 -08001c3c g .text 00000000 _etext -20000094 g .bss 00000000 _sbss -08000f72 g F .text 000000d6 cobs_decode -20000198 g O .bss 0000023c usart_tx_buf -20000094 g O .bss 00000004 sys_time_seconds -20000000 g O .data 00000004 SystemCoreClock -2000001c g O .data 00000004 pwr -080018e8 g F .text 0000010a .hidden __udivsi3 -080018d2 g F .text 00000014 __assert_func -20000000 g .data 00000000 _sdata -0800039c g F .text 0000002c SPI1_IRQHandler -20000060 g O .data 00000004 dma1_channel5 -20000058 g O .data 00000004 dma1_channel3 -200003d4 g .bss 00000000 __exidx_start -08001524 g F .text 0000001e LL_Init1msTick -20000054 g O .data 00000004 dma1_channel2 -08001c20 w F .text 00000002 EXTI2_3_IRQHandler -08001c20 w F .text 00000002 ADC1_IRQHandler -08001064 g F .text 000000e2 cobs_decode_incremental -2000004c g O .data 00000004 dma1 -08001c20 w F .text 00000002 TIM17_IRQHandler -08001c20 w F .text 00000002 RTC_IRQHandler -200003d4 g .bss 00000000 _ebss -2000002c g O .data 00000004 adc1_common -08001bd4 w F .text 00000034 Reset_Handler -20000070 g O .data 00000004 crc -20000024 g O .data 00000004 exti -08000210 g F .text 0000000a update_leds -20000028 g O .data 00000004 adc1 -080019fc g F .text 00000000 .hidden __aeabi_idiv -20000178 g O .bss 00000020 leds -20000074 g O .data 00000004 gpioa -080003c8 g F .text 000000bc TIM16_IRQHandler -08001c20 w F .text 00000002 TIM3_IRQHandler -08001c20 w F .text 00000002 EXTI4_15_IRQHandler -08001c20 w F .text 00000002 RCC_IRQHandler -08000d90 g F .text 00000124 usart_send_packet_nonblocking -20000094 g .bss 00000000 _bss -0800079a g F .text 00000082 DMA1_Channel1_IRQHandler -08001c20 g .text 00000002 Default_Handler -08001c24 g O .text 00000010 AHBPrescTable -08000eb4 g F .text 000000be cobs_encode_usart -20000010 g O .data 00000004 wwdg -08001c20 w F .text 00000002 TIM14_IRQHandler -08001c20 w F .text 00000002 DMA1_Channel4_5_IRQHandler -20000030 g O .data 00000004 adc -08000cf4 g F .text 00000030 usart_putc -08001c20 w F .text 00000002 EXTI0_1_IRQHandler -08001bd0 w F .text 00000002 .hidden __aeabi_ldiv0 -20000004 g O .data 00000004 tim3 -2000000c g O .data 00000004 rtc -08000954 g F .text 000000ec usart_dma_init -0800186e g F .text 0000003a memset -08000c38 g F .text 00000060 usart_ack_packet -0800021a g F .text 00000182 main -20000064 g O .data 00000004 flash -080018e8 g F .text 00000000 .hidden __aeabi_uidiv -08000494 g F .text 0000000c SVC_Handler -20000018 g O .data 00000004 i2c1 -20000050 g O .data 00000004 dma1_channel1 -080019fc g F .text 000001cc .hidden __divsi3 -20000090 g O .data 00000004 nvic -0800115c g F .text 00000088 SystemInit -20000174 g O .bss 00000004 _impure_ptr -08001c20 w F .text 00000002 WWDG_IRQHandler -20000000 g .data 00000000 _data -20000084 g O .data 00000004 gpiof -08000d4c g F .text 00000044 DMA1_Channel2_3_IRQHandler -20000080 g O .data 00000004 gpiod -20001000 g *ABS* 00000000 _estack -080019f4 g F .text 00000008 .hidden __aeabi_uidivmod -20000068 g O .data 00000004 ob -20000094 g .data 00000000 _edata -20000038 g O .data 00000004 spi1 -08000c98 g F .text 0000005c usart_dma_fifo_push -2000005c g O .data 00000004 dma1_channel4 -08000000 g O .isr_vector 00000000 g_pfnVectors -080011e4 g F .text 000000ec SystemCoreClockUpdate -08001630 g F .text 000000a0 LL_PLL_ConfigSystemClock_HSE -08001bd0 w F .text 00000002 .hidden __aeabi_idiv0 -20000014 g O .data 00000004 iwdg -08001c20 w F .text 00000002 FLASH_IRQHandler -08001048 g F .text 0000001c cobs_decode_incremental_initialize -08000a40 g F .text 00000128 USART1_IRQHandler -080005f0 g F .text 000000a0 adc_configure_scope_mode -080018a8 g F .text 0000002a strlen -08001c20 w F .text 00000002 TIM1_BRK_UP_TRG_COM_IRQHandler -20000078 g O .data 00000004 gpiob -20000034 g O .data 00000004 tim1 -2000008c g O .data 00000004 systick -08001bc8 g F .text 00000008 .hidden __aeabi_idivmod -20000040 g O .data 00000004 tim16 - - - -Disassembly of section .text: - -080000c0 <NVIC_EnableIRQ>: - \brief Enable External Interrupt - \details Enables a device-specific interrupt in the NVIC interrupt controller. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - 80000c0: b580 push {r7, lr} - 80000c2: b082 sub sp, #8 - 80000c4: af00 add r7, sp, #0 - 80000c6: 0002 movs r2, r0 - 80000c8: 1dfb adds r3, r7, #7 - 80000ca: 701a strb r2, [r3, #0] - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - 80000cc: 1dfb adds r3, r7, #7 - 80000ce: 781b ldrb r3, [r3, #0] - 80000d0: 001a movs r2, r3 - 80000d2: 231f movs r3, #31 - 80000d4: 401a ands r2, r3 - 80000d6: 4b04 ldr r3, [pc, #16] ; (80000e8 <NVIC_EnableIRQ+0x28>) - 80000d8: 2101 movs r1, #1 - 80000da: 4091 lsls r1, r2 - 80000dc: 000a movs r2, r1 - 80000de: 601a str r2, [r3, #0] -} - 80000e0: 46c0 nop ; (mov r8, r8) - 80000e2: 46bd mov sp, r7 - 80000e4: b002 add sp, #8 - 80000e6: bd80 pop {r7, pc} - 80000e8: e000e100 .word 0xe000e100 - -080000ec <NVIC_SetPriority>: - \note The priority cannot be set for every core interrupt. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - 80000ec: b590 push {r4, r7, lr} - 80000ee: b083 sub sp, #12 - 80000f0: af00 add r7, sp, #0 - 80000f2: 0002 movs r2, r0 - 80000f4: 6039 str r1, [r7, #0] - 80000f6: 1dfb adds r3, r7, #7 - 80000f8: 701a strb r2, [r3, #0] - if ((int32_t)(IRQn) < 0) - 80000fa: 1dfb adds r3, r7, #7 - 80000fc: 781b ldrb r3, [r3, #0] - 80000fe: 2b7f cmp r3, #127 ; 0x7f - 8000100: d932 bls.n 8000168 <NVIC_SetPriority+0x7c> - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8000102: 4a2f ldr r2, [pc, #188] ; (80001c0 <NVIC_SetPriority+0xd4>) - 8000104: 1dfb adds r3, r7, #7 - 8000106: 781b ldrb r3, [r3, #0] - 8000108: 0019 movs r1, r3 - 800010a: 230f movs r3, #15 - 800010c: 400b ands r3, r1 - 800010e: 3b08 subs r3, #8 - 8000110: 089b lsrs r3, r3, #2 - 8000112: 3306 adds r3, #6 - 8000114: 009b lsls r3, r3, #2 - 8000116: 18d3 adds r3, r2, r3 - 8000118: 3304 adds r3, #4 - 800011a: 681b ldr r3, [r3, #0] - 800011c: 1dfa adds r2, r7, #7 - 800011e: 7812 ldrb r2, [r2, #0] - 8000120: 0011 movs r1, r2 - 8000122: 2203 movs r2, #3 - 8000124: 400a ands r2, r1 - 8000126: 00d2 lsls r2, r2, #3 - 8000128: 21ff movs r1, #255 ; 0xff - 800012a: 4091 lsls r1, r2 - 800012c: 000a movs r2, r1 - 800012e: 43d2 mvns r2, r2 - 8000130: 401a ands r2, r3 - 8000132: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 8000134: 683b ldr r3, [r7, #0] - 8000136: 019b lsls r3, r3, #6 - 8000138: 22ff movs r2, #255 ; 0xff - 800013a: 401a ands r2, r3 - 800013c: 1dfb adds r3, r7, #7 - 800013e: 781b ldrb r3, [r3, #0] - 8000140: 0018 movs r0, r3 - 8000142: 2303 movs r3, #3 - 8000144: 4003 ands r3, r0 - 8000146: 00db lsls r3, r3, #3 - 8000148: 409a lsls r2, r3 - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 800014a: 481d ldr r0, [pc, #116] ; (80001c0 <NVIC_SetPriority+0xd4>) - 800014c: 1dfb adds r3, r7, #7 - 800014e: 781b ldrb r3, [r3, #0] - 8000150: 001c movs r4, r3 - 8000152: 230f movs r3, #15 - 8000154: 4023 ands r3, r4 - 8000156: 3b08 subs r3, #8 - 8000158: 089b lsrs r3, r3, #2 - 800015a: 430a orrs r2, r1 - 800015c: 3306 adds r3, #6 - 800015e: 009b lsls r3, r3, #2 - 8000160: 18c3 adds r3, r0, r3 - 8000162: 3304 adds r3, #4 - 8000164: 601a str r2, [r3, #0] - else - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - 8000166: e027 b.n 80001b8 <NVIC_SetPriority+0xcc> - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8000168: 4a16 ldr r2, [pc, #88] ; (80001c4 <NVIC_SetPriority+0xd8>) - 800016a: 1dfb adds r3, r7, #7 - 800016c: 781b ldrb r3, [r3, #0] - 800016e: b25b sxtb r3, r3 - 8000170: 089b lsrs r3, r3, #2 - 8000172: 33c0 adds r3, #192 ; 0xc0 - 8000174: 009b lsls r3, r3, #2 - 8000176: 589b ldr r3, [r3, r2] - 8000178: 1dfa adds r2, r7, #7 - 800017a: 7812 ldrb r2, [r2, #0] - 800017c: 0011 movs r1, r2 - 800017e: 2203 movs r2, #3 - 8000180: 400a ands r2, r1 - 8000182: 00d2 lsls r2, r2, #3 - 8000184: 21ff movs r1, #255 ; 0xff - 8000186: 4091 lsls r1, r2 - 8000188: 000a movs r2, r1 - 800018a: 43d2 mvns r2, r2 - 800018c: 401a ands r2, r3 - 800018e: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 8000190: 683b ldr r3, [r7, #0] - 8000192: 019b lsls r3, r3, #6 - 8000194: 22ff movs r2, #255 ; 0xff - 8000196: 401a ands r2, r3 - 8000198: 1dfb adds r3, r7, #7 - 800019a: 781b ldrb r3, [r3, #0] - 800019c: 0018 movs r0, r3 - 800019e: 2303 movs r3, #3 - 80001a0: 4003 ands r3, r0 - 80001a2: 00db lsls r3, r3, #3 - 80001a4: 409a lsls r2, r3 - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80001a6: 4807 ldr r0, [pc, #28] ; (80001c4 <NVIC_SetPriority+0xd8>) - 80001a8: 1dfb adds r3, r7, #7 - 80001aa: 781b ldrb r3, [r3, #0] - 80001ac: b25b sxtb r3, r3 - 80001ae: 089b lsrs r3, r3, #2 - 80001b0: 430a orrs r2, r1 - 80001b2: 33c0 adds r3, #192 ; 0xc0 - 80001b4: 009b lsls r3, r3, #2 - 80001b6: 501a str r2, [r3, r0] -} - 80001b8: 46c0 nop ; (mov r8, r8) - 80001ba: 46bd mov sp, r7 - 80001bc: b003 add sp, #12 - 80001be: bd90 pop {r4, r7, pc} - 80001c0: e000ed00 .word 0xe000ed00 - 80001c4: e000e100 .word 0xe000e100 - -080001c8 <SysTick_Config>: - \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the - function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - 80001c8: b580 push {r7, lr} - 80001ca: b082 sub sp, #8 - 80001cc: af00 add r7, sp, #0 - 80001ce: 6078 str r0, [r7, #4] - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 80001d0: 687b ldr r3, [r7, #4] - 80001d2: 1e5a subs r2, r3, #1 - 80001d4: 2380 movs r3, #128 ; 0x80 - 80001d6: 045b lsls r3, r3, #17 - 80001d8: 429a cmp r2, r3 - 80001da: d301 bcc.n 80001e0 <SysTick_Config+0x18> - { - return (1UL); /* Reload value impossible */ - 80001dc: 2301 movs r3, #1 - 80001de: e010 b.n 8000202 <SysTick_Config+0x3a> - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 80001e0: 4b0a ldr r3, [pc, #40] ; (800020c <SysTick_Config+0x44>) - 80001e2: 687a ldr r2, [r7, #4] - 80001e4: 3a01 subs r2, #1 - 80001e6: 605a str r2, [r3, #4] - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 80001e8: 2301 movs r3, #1 - 80001ea: 425b negs r3, r3 - 80001ec: 2103 movs r1, #3 - 80001ee: 0018 movs r0, r3 - 80001f0: f7ff ff7c bl 80000ec <NVIC_SetPriority> - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80001f4: 4b05 ldr r3, [pc, #20] ; (800020c <SysTick_Config+0x44>) - 80001f6: 2200 movs r2, #0 - 80001f8: 609a str r2, [r3, #8] - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80001fa: 4b04 ldr r3, [pc, #16] ; (800020c <SysTick_Config+0x44>) - 80001fc: 2207 movs r2, #7 - 80001fe: 601a str r2, [r3, #0] - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ - 8000200: 2300 movs r3, #0 -} - 8000202: 0018 movs r0, r3 - 8000204: 46bd mov sp, r7 - 8000206: b002 add sp, #8 - 8000208: bd80 pop {r7, pc} - 800020a: 46c0 nop ; (mov r8, r8) - 800020c: e000e010 .word 0xe000e010 - -08000210 <update_leds>: -#include "serial.h" - - -volatile unsigned int sys_time_seconds = 0; - -void update_leds() { - 8000210: b580 push {r7, lr} - 8000212: af00 add r7, sp, #0 - -} - 8000214: 46c0 nop ; (mov r8, r8) - 8000216: 46bd mov sp, r7 - 8000218: bd80 pop {r7, pc} - -0800021a <main>: - unsigned int usb, ocxo, error, _nc1, _nc2, _nc3, pps, sd_card; - }; - unsigned int arr[8]; -} leds; - -int main(void) { - 800021a: b580 push {r7, lr} - 800021c: af00 add r7, sp, #0 - RCC->CR |= RCC_CR_HSEON; - 800021e: 4b53 ldr r3, [pc, #332] ; (800036c <main+0x152>) - 8000220: 681a ldr r2, [r3, #0] - 8000222: 4b52 ldr r3, [pc, #328] ; (800036c <main+0x152>) - 8000224: 2180 movs r1, #128 ; 0x80 - 8000226: 0249 lsls r1, r1, #9 - 8000228: 430a orrs r2, r1 - 800022a: 601a str r2, [r3, #0] - while (!(RCC->CR&RCC_CR_HSERDY)); - 800022c: 46c0 nop ; (mov r8, r8) - 800022e: 4b4f ldr r3, [pc, #316] ; (800036c <main+0x152>) - 8000230: 681a ldr r2, [r3, #0] - 8000232: 2380 movs r3, #128 ; 0x80 - 8000234: 029b lsls r3, r3, #10 - 8000236: 4013 ands r3, r2 - 8000238: d0f9 beq.n 800022e <main+0x14> - RCC->CFGR &= ~RCC_CFGR_PLLMUL_Msk & ~RCC_CFGR_SW_Msk & ~RCC_CFGR_PPRE_Msk & ~RCC_CFGR_HPRE_Msk; - 800023a: 4b4c ldr r3, [pc, #304] ; (800036c <main+0x152>) - 800023c: 685a ldr r2, [r3, #4] - 800023e: 4b4b ldr r3, [pc, #300] ; (800036c <main+0x152>) - 8000240: 494b ldr r1, [pc, #300] ; (8000370 <main+0x156>) - 8000242: 400a ands r2, r1 - 8000244: 605a str r2, [r3, #4] - RCC->CFGR |= ((6-2)<<RCC_CFGR_PLLMUL_Pos) | RCC_CFGR_PLLSRC_HSE_PREDIV; /* PLL x6 -> 48.0MHz */ - 8000246: 4b49 ldr r3, [pc, #292] ; (800036c <main+0x152>) - 8000248: 685a ldr r2, [r3, #4] - 800024a: 4b48 ldr r3, [pc, #288] ; (800036c <main+0x152>) - 800024c: 2188 movs r1, #136 ; 0x88 - 800024e: 0349 lsls r1, r1, #13 - 8000250: 430a orrs r2, r1 - 8000252: 605a str r2, [r3, #4] - RCC->CR |= RCC_CR_PLLON; - 8000254: 4b45 ldr r3, [pc, #276] ; (800036c <main+0x152>) - 8000256: 681a ldr r2, [r3, #0] - 8000258: 4b44 ldr r3, [pc, #272] ; (800036c <main+0x152>) - 800025a: 2180 movs r1, #128 ; 0x80 - 800025c: 0449 lsls r1, r1, #17 - 800025e: 430a orrs r2, r1 - 8000260: 601a str r2, [r3, #0] - while (!(RCC->CR&RCC_CR_PLLRDY)); - 8000262: 46c0 nop ; (mov r8, r8) - 8000264: 4b41 ldr r3, [pc, #260] ; (800036c <main+0x152>) - 8000266: 681a ldr r2, [r3, #0] - 8000268: 2380 movs r3, #128 ; 0x80 - 800026a: 049b lsls r3, r3, #18 - 800026c: 4013 ands r3, r2 - 800026e: d0f9 beq.n 8000264 <main+0x4a> - RCC->CFGR |= (2<<RCC_CFGR_SW_Pos); - 8000270: 4b3e ldr r3, [pc, #248] ; (800036c <main+0x152>) - 8000272: 685a ldr r2, [r3, #4] - 8000274: 4b3d ldr r3, [pc, #244] ; (800036c <main+0x152>) - 8000276: 2102 movs r1, #2 - 8000278: 430a orrs r2, r1 - 800027a: 605a str r2, [r3, #4] - SystemCoreClockUpdate(); - 800027c: f000 ffb2 bl 80011e4 <SystemCoreClockUpdate> - SysTick_Config(SystemCoreClock/10); /* 100ms interval */ - 8000280: 4b3c ldr r3, [pc, #240] ; (8000374 <main+0x15a>) - 8000282: 681b ldr r3, [r3, #0] - 8000284: 210a movs r1, #10 - 8000286: 0018 movs r0, r3 - 8000288: f001 fb2e bl 80018e8 <__udivsi3> - 800028c: 0003 movs r3, r0 - 800028e: 0018 movs r0, r3 - 8000290: f7ff ff9a bl 80001c8 <SysTick_Config> - NVIC_EnableIRQ(SysTick_IRQn); - 8000294: 2301 movs r3, #1 - 8000296: 425b negs r3, r3 - 8000298: 0018 movs r0, r3 - 800029a: f7ff ff11 bl 80000c0 <NVIC_EnableIRQ> - NVIC_SetPriority(SysTick_IRQn, 3<<5); - 800029e: 2301 movs r3, #1 - 80002a0: 425b negs r3, r3 - 80002a2: 2160 movs r1, #96 ; 0x60 - 80002a4: 0018 movs r0, r3 - 80002a6: f7ff ff21 bl 80000ec <NVIC_SetPriority> - - /* Turn on lots of neat things */ - RCC->AHBENR |= RCC_AHBENR_DMAEN | RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_FLITFEN | RCC_AHBENR_CRCEN; - 80002aa: 4b30 ldr r3, [pc, #192] ; (800036c <main+0x152>) - 80002ac: 695a ldr r2, [r3, #20] - 80002ae: 4b2f ldr r3, [pc, #188] ; (800036c <main+0x152>) - 80002b0: 4931 ldr r1, [pc, #196] ; (8000378 <main+0x15e>) - 80002b2: 430a orrs r2, r1 - 80002b4: 615a str r2, [r3, #20] - RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN | RCC_APB2ENR_SPI1EN | RCC_APB2ENR_DBGMCUEN |\ - 80002b6: 4b2d ldr r3, [pc, #180] ; (800036c <main+0x152>) - 80002b8: 699a ldr r2, [r3, #24] - 80002ba: 4b2c ldr r3, [pc, #176] ; (800036c <main+0x152>) - 80002bc: 492f ldr r1, [pc, #188] ; (800037c <main+0x162>) - 80002be: 430a orrs r2, r1 - 80002c0: 619a str r2, [r3, #24] - RCC_APB2ENR_TIM1EN | RCC_APB2ENR_TIM16EN | RCC_APB2ENR_USART1EN; - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - 80002c2: 4b2a ldr r3, [pc, #168] ; (800036c <main+0x152>) - 80002c4: 69da ldr r2, [r3, #28] - 80002c6: 4b29 ldr r3, [pc, #164] ; (800036c <main+0x152>) - 80002c8: 2102 movs r1, #2 - 80002ca: 430a orrs r2, r1 - 80002cc: 61da str r2, [r3, #28] - - GPIOA->MODER |= - 80002ce: 2390 movs r3, #144 ; 0x90 - 80002d0: 05db lsls r3, r3, #23 - 80002d2: 681a ldr r2, [r3, #0] - 80002d4: 2390 movs r3, #144 ; 0x90 - 80002d6: 05db lsls r3, r3, #23 - 80002d8: 4929 ldr r1, [pc, #164] ; (8000380 <main+0x166>) - 80002da: 430a orrs r2, r1 - 80002dc: 601a str r2, [r3, #0] - | (2<<GPIO_MODER_MODER7_Pos) /* PA7 - MOSI */ - | (2<<GPIO_MODER_MODER9_Pos) /* PA9 - HOST_RX */ - | (2<<GPIO_MODER_MODER10_Pos);/* PA10 - HOST_TX */ - - /* Set shift register IO GPIO output speed */ - GPIOA->OSPEEDR |= - 80002de: 2390 movs r3, #144 ; 0x90 - 80002e0: 05db lsls r3, r3, #23 - 80002e2: 689a ldr r2, [r3, #8] - 80002e4: 2390 movs r3, #144 ; 0x90 - 80002e6: 05db lsls r3, r3, #23 - 80002e8: 4926 ldr r1, [pc, #152] ; (8000384 <main+0x16a>) - 80002ea: 430a orrs r2, r1 - 80002ec: 609a str r2, [r3, #8] - | (2<<GPIO_OSPEEDR_OSPEEDR4_Pos) /* SD_CS */ - | (2<<GPIO_OSPEEDR_OSPEEDR5_Pos) /* SCK */ - | (2<<GPIO_OSPEEDR_OSPEEDR7_Pos) /* MOSI */ - | (2<<GPIO_OSPEEDR_OSPEEDR9_Pos); /* HOST_RX */ - - GPIOA->AFR[0] = (0<<GPIO_AFRL_AFRL5_Pos) | (0<<GPIO_AFRL_AFRL6_Pos) | (0<<GPIO_AFRL_AFRL7_Pos); - 80002ee: 2390 movs r3, #144 ; 0x90 - 80002f0: 05db lsls r3, r3, #23 - 80002f2: 2200 movs r2, #0 - 80002f4: 621a str r2, [r3, #32] - GPIOA->AFR[1] = (1<<8) | (1<<4); - 80002f6: 2390 movs r3, #144 ; 0x90 - 80002f8: 05db lsls r3, r3, #23 - 80002fa: 2288 movs r2, #136 ; 0x88 - 80002fc: 0052 lsls r2, r2, #1 - 80002fe: 625a str r2, [r3, #36] ; 0x24 - - GPIOB->MODER |= - 8000300: 4a21 ldr r2, [pc, #132] ; (8000388 <main+0x16e>) - 8000302: 4b21 ldr r3, [pc, #132] ; (8000388 <main+0x16e>) - 8000304: 6812 ldr r2, [r2, #0] - 8000306: 601a str r2, [r3, #0] - (0<<GPIO_MODER_MODER1_Pos); /* PB0 - LINE_POL */ - - SPI1->CR1 = - 8000308: 4b20 ldr r3, [pc, #128] ; (800038c <main+0x172>) - 800030a: 22c9 movs r2, #201 ; 0xc9 - 800030c: 0092 lsls r2, r2, #2 - 800030e: 601a str r2, [r3, #0] - SPI_CR1_SSM - | SPI_CR1_SSI - | (4<<SPI_CR1_BR_Pos) /* /32 ~1.5MHz */ - | SPI_CR1_MSTR; - SPI1->CR2 = (7<<SPI_CR2_DS_Pos); - 8000310: 4b1e ldr r3, [pc, #120] ; (800038c <main+0x172>) - 8000312: 22e0 movs r2, #224 ; 0xe0 - 8000314: 00d2 lsls r2, r2, #3 - 8000316: 605a str r2, [r3, #4] - SPI1->CR1 |= SPI_CR1_SPE; - 8000318: 4b1c ldr r3, [pc, #112] ; (800038c <main+0x172>) - 800031a: 681a ldr r2, [r3, #0] - 800031c: 4b1b ldr r3, [pc, #108] ; (800038c <main+0x172>) - 800031e: 2140 movs r1, #64 ; 0x40 - 8000320: 430a orrs r2, r1 - 8000322: 601a str r2, [r3, #0] - - NVIC_EnableIRQ(SPI1_IRQn); - 8000324: 2019 movs r0, #25 - 8000326: f7ff fecb bl 80000c0 <NVIC_EnableIRQ> - NVIC_SetPriority(SPI1_IRQn, 2<<5); - 800032a: 2140 movs r1, #64 ; 0x40 - 800032c: 2019 movs r0, #25 - 800032e: f7ff fedd bl 80000ec <NVIC_SetPriority> - - TIM16->CR2 = 0; - 8000332: 4b17 ldr r3, [pc, #92] ; (8000390 <main+0x176>) - 8000334: 2200 movs r2, #0 - 8000336: 605a str r2, [r3, #4] - TIM16->DIER = TIM_DIER_UIE; - 8000338: 4b15 ldr r3, [pc, #84] ; (8000390 <main+0x176>) - 800033a: 2201 movs r2, #1 - 800033c: 60da str r2, [r3, #12] - TIM16->PSC = 48-1; /* 1us */ - 800033e: 4b14 ldr r3, [pc, #80] ; (8000390 <main+0x176>) - 8000340: 222f movs r2, #47 ; 0x2f - 8000342: 629a str r2, [r3, #40] ; 0x28 - TIM16->ARR = 1000-1; /* 1ms */ - 8000344: 4b12 ldr r3, [pc, #72] ; (8000390 <main+0x176>) - 8000346: 4a13 ldr r2, [pc, #76] ; (8000394 <main+0x17a>) - 8000348: 62da str r2, [r3, #44] ; 0x2c - TIM16->CR1 = TIM_CR1_CEN; - 800034a: 4b11 ldr r3, [pc, #68] ; (8000390 <main+0x176>) - 800034c: 2201 movs r2, #1 - 800034e: 601a str r2, [r3, #0] - - NVIC_EnableIRQ(TIM16_IRQn); - 8000350: 2015 movs r0, #21 - 8000352: f7ff feb5 bl 80000c0 <NVIC_EnableIRQ> - NVIC_SetPriority(TIM16_IRQn, 2<<5); - 8000356: 2140 movs r1, #64 ; 0x40 - 8000358: 2015 movs r0, #21 - 800035a: f7ff fec7 bl 80000ec <NVIC_SetPriority> - - adc_configure_scope_mode(1000000); - 800035e: 4b0e ldr r3, [pc, #56] ; (8000398 <main+0x17e>) - 8000360: 0018 movs r0, r3 - 8000362: f000 f945 bl 80005f0 <adc_configure_scope_mode> - - usart_dma_init(); - 8000366: f000 faf5 bl 8000954 <usart_dma_init> - - while (42) { - 800036a: e7fe b.n 800036a <main+0x150> - 800036c: 40021000 .word 0x40021000 - 8000370: ffc3f80c .word 0xffc3f80c - 8000374: 20000000 .word 0x20000000 - 8000378: 00060051 .word 0x00060051 - 800037c: 00425a01 .word 0x00425a01 - 8000380: 0028a970 .word 0x0028a970 - 8000384: 00088a80 .word 0x00088a80 - 8000388: 48000400 .word 0x48000400 - 800038c: 40013000 .word 0x40013000 - 8000390: 40014400 .word 0x40014400 - 8000394: 000003e7 .word 0x000003e7 - 8000398: 000f4240 .word 0x000f4240 - -0800039c <SPI1_IRQHandler>: - //for (int i=0; i<10000; i++) ; - //leds.error = 100; - } -} - -void SPI1_IRQHandler(void) { - 800039c: b580 push {r7, lr} - 800039e: af00 add r7, sp, #0 - if (SPI1->SR & SPI_SR_TXE) { - 80003a0: 4b08 ldr r3, [pc, #32] ; (80003c4 <SPI1_IRQHandler+0x28>) - 80003a2: 689b ldr r3, [r3, #8] - 80003a4: 2202 movs r2, #2 - 80003a6: 4013 ands r3, r2 - 80003a8: d009 beq.n 80003be <SPI1_IRQHandler+0x22> - /* LED_STB */ - GPIOA->BSRR = 1<<3; - 80003aa: 2390 movs r3, #144 ; 0x90 - 80003ac: 05db lsls r3, r3, #23 - 80003ae: 2208 movs r2, #8 - 80003b0: 619a str r2, [r3, #24] - SPI1->CR2 &= ~SPI_CR2_TXEIE; - 80003b2: 4b04 ldr r3, [pc, #16] ; (80003c4 <SPI1_IRQHandler+0x28>) - 80003b4: 685a ldr r2, [r3, #4] - 80003b6: 4b03 ldr r3, [pc, #12] ; (80003c4 <SPI1_IRQHandler+0x28>) - 80003b8: 2180 movs r1, #128 ; 0x80 - 80003ba: 438a bics r2, r1 - 80003bc: 605a str r2, [r3, #4] - } -} - 80003be: 46c0 nop ; (mov r8, r8) - 80003c0: 46bd mov sp, r7 - 80003c2: bd80 pop {r7, pc} - 80003c4: 40013000 .word 0x40013000 - -080003c8 <TIM16_IRQHandler>: - -void TIM16_IRQHandler(void) { - 80003c8: b580 push {r7, lr} - 80003ca: b082 sub sp, #8 - 80003cc: af00 add r7, sp, #0 - static int leds_update_counter = 0; - if (TIM16->SR & TIM_SR_UIF) { - 80003ce: 4b28 ldr r3, [pc, #160] ; (8000470 <TIM16_IRQHandler+0xa8>) - 80003d0: 691b ldr r3, [r3, #16] - 80003d2: 2201 movs r2, #1 - 80003d4: 4013 ands r3, r2 - 80003d6: d047 beq.n 8000468 <TIM16_IRQHandler+0xa0> - TIM16->SR &= ~TIM_SR_UIF; - 80003d8: 4b25 ldr r3, [pc, #148] ; (8000470 <TIM16_IRQHandler+0xa8>) - 80003da: 691a ldr r2, [r3, #16] - 80003dc: 4b24 ldr r3, [pc, #144] ; (8000470 <TIM16_IRQHandler+0xa8>) - 80003de: 2101 movs r1, #1 - 80003e0: 438a bics r2, r1 - 80003e2: 611a str r2, [r3, #16] - - uint8_t bits = 0, mask = 1; - 80003e4: 1dfb adds r3, r7, #7 - 80003e6: 2200 movs r2, #0 - 80003e8: 701a strb r2, [r3, #0] - 80003ea: 1dbb adds r3, r7, #6 - 80003ec: 2201 movs r2, #1 - 80003ee: 701a strb r2, [r3, #0] - for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) { - 80003f0: 2300 movs r3, #0 - 80003f2: 603b str r3, [r7, #0] - 80003f4: e01d b.n 8000432 <TIM16_IRQHandler+0x6a> - if (leds.arr[i]) { - 80003f6: 4b1f ldr r3, [pc, #124] ; (8000474 <TIM16_IRQHandler+0xac>) - 80003f8: 683a ldr r2, [r7, #0] - 80003fa: 0092 lsls r2, r2, #2 - 80003fc: 58d3 ldr r3, [r2, r3] - 80003fe: 2b00 cmp r3, #0 - 8000400: d00f beq.n 8000422 <TIM16_IRQHandler+0x5a> - leds.arr[i]--; - 8000402: 4b1c ldr r3, [pc, #112] ; (8000474 <TIM16_IRQHandler+0xac>) - 8000404: 683a ldr r2, [r7, #0] - 8000406: 0092 lsls r2, r2, #2 - 8000408: 58d3 ldr r3, [r2, r3] - 800040a: 1e59 subs r1, r3, #1 - 800040c: 4b19 ldr r3, [pc, #100] ; (8000474 <TIM16_IRQHandler+0xac>) - 800040e: 683a ldr r2, [r7, #0] - 8000410: 0092 lsls r2, r2, #2 - 8000412: 50d1 str r1, [r2, r3] - bits |= mask; - 8000414: 1dfb adds r3, r7, #7 - 8000416: 1df9 adds r1, r7, #7 - 8000418: 1dba adds r2, r7, #6 - 800041a: 7809 ldrb r1, [r1, #0] - 800041c: 7812 ldrb r2, [r2, #0] - 800041e: 430a orrs r2, r1 - 8000420: 701a strb r2, [r3, #0] - } - mask <<= 1; - 8000422: 1dba adds r2, r7, #6 - 8000424: 1dbb adds r3, r7, #6 - 8000426: 781b ldrb r3, [r3, #0] - 8000428: 18db adds r3, r3, r3 - 800042a: 7013 strb r3, [r2, #0] - for (size_t i=0; i<sizeof(leds)/sizeof(leds.arr[0]); i++) { - 800042c: 683b ldr r3, [r7, #0] - 800042e: 3301 adds r3, #1 - 8000430: 603b str r3, [r7, #0] - 8000432: 683b ldr r3, [r7, #0] - 8000434: 2b07 cmp r3, #7 - 8000436: d9de bls.n 80003f6 <TIM16_IRQHandler+0x2e> - } - - if (leds_update_counter++ == 10) { - 8000438: 4b0f ldr r3, [pc, #60] ; (8000478 <TIM16_IRQHandler+0xb0>) - 800043a: 681b ldr r3, [r3, #0] - 800043c: 1c59 adds r1, r3, #1 - 800043e: 4a0e ldr r2, [pc, #56] ; (8000478 <TIM16_IRQHandler+0xb0>) - 8000440: 6011 str r1, [r2, #0] - 8000442: 2b0a cmp r3, #10 - 8000444: d110 bne.n 8000468 <TIM16_IRQHandler+0xa0> - leds_update_counter = 0; - 8000446: 4b0c ldr r3, [pc, #48] ; (8000478 <TIM16_IRQHandler+0xb0>) - 8000448: 2200 movs r2, #0 - 800044a: 601a str r2, [r3, #0] - - /* Workaround for SPI hardware bug: Even if configured to 8-bit mode, the SPI will do a 16-bit transfer if the - * data register is accessed through a 16-bit write. Unfortunately, the STMCube register defs define DR as an - * uint16_t, so we have to do some magic here to force an 8-bit write. */ - *((volatile uint8_t*)&(SPI1->DR)) = bits; - 800044c: 4a0b ldr r2, [pc, #44] ; (800047c <TIM16_IRQHandler+0xb4>) - 800044e: 1dfb adds r3, r7, #7 - 8000450: 781b ldrb r3, [r3, #0] - 8000452: 7013 strb r3, [r2, #0] - SPI1->CR2 |= SPI_CR2_TXEIE; - 8000454: 4b0a ldr r3, [pc, #40] ; (8000480 <TIM16_IRQHandler+0xb8>) - 8000456: 685a ldr r2, [r3, #4] - 8000458: 4b09 ldr r3, [pc, #36] ; (8000480 <TIM16_IRQHandler+0xb8>) - 800045a: 2180 movs r1, #128 ; 0x80 - 800045c: 430a orrs r2, r1 - 800045e: 605a str r2, [r3, #4] - GPIOA->BRR = 1<<3; - 8000460: 2390 movs r3, #144 ; 0x90 - 8000462: 05db lsls r3, r3, #23 - 8000464: 2208 movs r2, #8 - 8000466: 629a str r2, [r3, #40] ; 0x28 - } - } -} - 8000468: 46c0 nop ; (mov r8, r8) - 800046a: 46bd mov sp, r7 - 800046c: b002 add sp, #8 - 800046e: bd80 pop {r7, pc} - 8000470: 40014400 .word 0x40014400 - 8000474: 20000178 .word 0x20000178 - 8000478: 20000098 .word 0x20000098 - 800047c: 4001300c .word 0x4001300c - 8000480: 40013000 .word 0x40013000 - -08000484 <NMI_Handler>: - -void NMI_Handler(void) { - 8000484: b580 push {r7, lr} - 8000486: af00 add r7, sp, #0 - asm volatile ("bkpt"); - 8000488: be00 bkpt 0x0000 -} - 800048a: 46c0 nop ; (mov r8, r8) - 800048c: 46bd mov sp, r7 - 800048e: bd80 pop {r7, pc} - -08000490 <HardFault_Handler>: - -void HardFault_Handler(void) __attribute__((naked)); -void HardFault_Handler() { - asm volatile ("bkpt"); - 8000490: be00 bkpt 0x0000 -} - 8000492: 46c0 nop ; (mov r8, r8) - -08000494 <SVC_Handler>: - -void SVC_Handler(void) { - 8000494: b580 push {r7, lr} - 8000496: af00 add r7, sp, #0 - asm volatile ("bkpt"); - 8000498: be00 bkpt 0x0000 -} - 800049a: 46c0 nop ; (mov r8, r8) - 800049c: 46bd mov sp, r7 - 800049e: bd80 pop {r7, pc} - -080004a0 <PendSV_Handler>: - - -void PendSV_Handler(void) { - 80004a0: b580 push {r7, lr} - 80004a2: af00 add r7, sp, #0 - asm volatile ("bkpt"); - 80004a4: be00 bkpt 0x0000 -} - 80004a6: 46c0 nop ; (mov r8, r8) - 80004a8: 46bd mov sp, r7 - 80004aa: bd80 pop {r7, pc} - -080004ac <SysTick_Handler>: - -void SysTick_Handler(void) { - 80004ac: b580 push {r7, lr} - 80004ae: af00 add r7, sp, #0 - static int n = 0; - if (n++ == 10) { - 80004b0: 4b0a ldr r3, [pc, #40] ; (80004dc <SysTick_Handler+0x30>) - 80004b2: 681b ldr r3, [r3, #0] - 80004b4: 1c59 adds r1, r3, #1 - 80004b6: 4a09 ldr r2, [pc, #36] ; (80004dc <SysTick_Handler+0x30>) - 80004b8: 6011 str r1, [r2, #0] - 80004ba: 2b0a cmp r3, #10 - 80004bc: d10a bne.n 80004d4 <SysTick_Handler+0x28> - n = 0; - 80004be: 4b07 ldr r3, [pc, #28] ; (80004dc <SysTick_Handler+0x30>) - 80004c0: 2200 movs r2, #0 - 80004c2: 601a str r2, [r3, #0] - sys_time_seconds++; - 80004c4: 4b06 ldr r3, [pc, #24] ; (80004e0 <SysTick_Handler+0x34>) - 80004c6: 681b ldr r3, [r3, #0] - 80004c8: 1c5a adds r2, r3, #1 - 80004ca: 4b05 ldr r3, [pc, #20] ; (80004e0 <SysTick_Handler+0x34>) - 80004cc: 601a str r2, [r3, #0] - leds.pps = 100; /* ms */ - 80004ce: 4b05 ldr r3, [pc, #20] ; (80004e4 <SysTick_Handler+0x38>) - 80004d0: 2264 movs r2, #100 ; 0x64 - 80004d2: 619a str r2, [r3, #24] - } -} - 80004d4: 46c0 nop ; (mov r8, r8) - 80004d6: 46bd mov sp, r7 - 80004d8: bd80 pop {r7, pc} - 80004da: 46c0 nop ; (mov r8, r8) - 80004dc: 2000009c .word 0x2000009c - 80004e0: 20000094 .word 0x20000094 - 80004e4: 20000178 .word 0x20000178 - -080004e8 <NVIC_EnableIRQ>: -{ - 80004e8: b580 push {r7, lr} - 80004ea: b082 sub sp, #8 - 80004ec: af00 add r7, sp, #0 - 80004ee: 0002 movs r2, r0 - 80004f0: 1dfb adds r3, r7, #7 - 80004f2: 701a strb r2, [r3, #0] - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - 80004f4: 1dfb adds r3, r7, #7 - 80004f6: 781b ldrb r3, [r3, #0] - 80004f8: 001a movs r2, r3 - 80004fa: 231f movs r3, #31 - 80004fc: 401a ands r2, r3 - 80004fe: 4b04 ldr r3, [pc, #16] ; (8000510 <NVIC_EnableIRQ+0x28>) - 8000500: 2101 movs r1, #1 - 8000502: 4091 lsls r1, r2 - 8000504: 000a movs r2, r1 - 8000506: 601a str r2, [r3, #0] -} - 8000508: 46c0 nop ; (mov r8, r8) - 800050a: 46bd mov sp, r7 - 800050c: b002 add sp, #8 - 800050e: bd80 pop {r7, pc} - 8000510: e000e100 .word 0xe000e100 - -08000514 <NVIC_SetPriority>: -{ - 8000514: b590 push {r4, r7, lr} - 8000516: b083 sub sp, #12 - 8000518: af00 add r7, sp, #0 - 800051a: 0002 movs r2, r0 - 800051c: 6039 str r1, [r7, #0] - 800051e: 1dfb adds r3, r7, #7 - 8000520: 701a strb r2, [r3, #0] - if ((int32_t)(IRQn) < 0) - 8000522: 1dfb adds r3, r7, #7 - 8000524: 781b ldrb r3, [r3, #0] - 8000526: 2b7f cmp r3, #127 ; 0x7f - 8000528: d932 bls.n 8000590 <NVIC_SetPriority+0x7c> - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 800052a: 4a2f ldr r2, [pc, #188] ; (80005e8 <NVIC_SetPriority+0xd4>) - 800052c: 1dfb adds r3, r7, #7 - 800052e: 781b ldrb r3, [r3, #0] - 8000530: 0019 movs r1, r3 - 8000532: 230f movs r3, #15 - 8000534: 400b ands r3, r1 - 8000536: 3b08 subs r3, #8 - 8000538: 089b lsrs r3, r3, #2 - 800053a: 3306 adds r3, #6 - 800053c: 009b lsls r3, r3, #2 - 800053e: 18d3 adds r3, r2, r3 - 8000540: 3304 adds r3, #4 - 8000542: 681b ldr r3, [r3, #0] - 8000544: 1dfa adds r2, r7, #7 - 8000546: 7812 ldrb r2, [r2, #0] - 8000548: 0011 movs r1, r2 - 800054a: 2203 movs r2, #3 - 800054c: 400a ands r2, r1 - 800054e: 00d2 lsls r2, r2, #3 - 8000550: 21ff movs r1, #255 ; 0xff - 8000552: 4091 lsls r1, r2 - 8000554: 000a movs r2, r1 - 8000556: 43d2 mvns r2, r2 - 8000558: 401a ands r2, r3 - 800055a: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 800055c: 683b ldr r3, [r7, #0] - 800055e: 019b lsls r3, r3, #6 - 8000560: 22ff movs r2, #255 ; 0xff - 8000562: 401a ands r2, r3 - 8000564: 1dfb adds r3, r7, #7 - 8000566: 781b ldrb r3, [r3, #0] - 8000568: 0018 movs r0, r3 - 800056a: 2303 movs r3, #3 - 800056c: 4003 ands r3, r0 - 800056e: 00db lsls r3, r3, #3 - 8000570: 409a lsls r2, r3 - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8000572: 481d ldr r0, [pc, #116] ; (80005e8 <NVIC_SetPriority+0xd4>) - 8000574: 1dfb adds r3, r7, #7 - 8000576: 781b ldrb r3, [r3, #0] - 8000578: 001c movs r4, r3 - 800057a: 230f movs r3, #15 - 800057c: 4023 ands r3, r4 - 800057e: 3b08 subs r3, #8 - 8000580: 089b lsrs r3, r3, #2 - 8000582: 430a orrs r2, r1 - 8000584: 3306 adds r3, #6 - 8000586: 009b lsls r3, r3, #2 - 8000588: 18c3 adds r3, r0, r3 - 800058a: 3304 adds r3, #4 - 800058c: 601a str r2, [r3, #0] -} - 800058e: e027 b.n 80005e0 <NVIC_SetPriority+0xcc> - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8000590: 4a16 ldr r2, [pc, #88] ; (80005ec <NVIC_SetPriority+0xd8>) - 8000592: 1dfb adds r3, r7, #7 - 8000594: 781b ldrb r3, [r3, #0] - 8000596: b25b sxtb r3, r3 - 8000598: 089b lsrs r3, r3, #2 - 800059a: 33c0 adds r3, #192 ; 0xc0 - 800059c: 009b lsls r3, r3, #2 - 800059e: 589b ldr r3, [r3, r2] - 80005a0: 1dfa adds r2, r7, #7 - 80005a2: 7812 ldrb r2, [r2, #0] - 80005a4: 0011 movs r1, r2 - 80005a6: 2203 movs r2, #3 - 80005a8: 400a ands r2, r1 - 80005aa: 00d2 lsls r2, r2, #3 - 80005ac: 21ff movs r1, #255 ; 0xff - 80005ae: 4091 lsls r1, r2 - 80005b0: 000a movs r2, r1 - 80005b2: 43d2 mvns r2, r2 - 80005b4: 401a ands r2, r3 - 80005b6: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 80005b8: 683b ldr r3, [r7, #0] - 80005ba: 019b lsls r3, r3, #6 - 80005bc: 22ff movs r2, #255 ; 0xff - 80005be: 401a ands r2, r3 - 80005c0: 1dfb adds r3, r7, #7 - 80005c2: 781b ldrb r3, [r3, #0] - 80005c4: 0018 movs r0, r3 - 80005c6: 2303 movs r3, #3 - 80005c8: 4003 ands r3, r0 - 80005ca: 00db lsls r3, r3, #3 - 80005cc: 409a lsls r2, r3 - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80005ce: 4807 ldr r0, [pc, #28] ; (80005ec <NVIC_SetPriority+0xd8>) - 80005d0: 1dfb adds r3, r7, #7 - 80005d2: 781b ldrb r3, [r3, #0] - 80005d4: b25b sxtb r3, r3 - 80005d6: 089b lsrs r3, r3, #2 - 80005d8: 430a orrs r2, r1 - 80005da: 33c0 adds r3, #192 ; 0xc0 - 80005dc: 009b lsls r3, r3, #2 - 80005de: 501a str r2, [r3, r0] -} - 80005e0: 46c0 nop ; (mov r8, r8) - 80005e2: 46bd mov sp, r7 - 80005e4: b003 add sp, #12 - 80005e6: bd90 pop {r4, r7, pc} - 80005e8: e000ed00 .word 0xe000ed00 - 80005ec: e000e100 .word 0xe000e100 - -080005f0 <adc_configure_scope_mode>: -static void adc_timer_init(int psc, int ivl); -static void adc_dma_launch(void); - - -/* Mode that can be used for debugging */ -void adc_configure_scope_mode(int sampling_interval_ns) { - 80005f0: b580 push {r7, lr} - 80005f2: b084 sub sp, #16 - 80005f4: af00 add r7, sp, #0 - 80005f6: 6078 str r0, [r7, #4] - adc_dma_init(); - 80005f8: f000 f84a bl 8000690 <adc_dma_init> - - /* Clock from PCLK/4 instead of the internal exclusive high-speed RC oscillator. */ - ADC1->CFGR2 = (2<<ADC_CFGR2_CKMODE_Pos); /* Use PCLK/4=12MHz */ - 80005fc: 4b20 ldr r3, [pc, #128] ; (8000680 <adc_configure_scope_mode+0x90>) - 80005fe: 2280 movs r2, #128 ; 0x80 - 8000600: 0612 lsls r2, r2, #24 - 8000602: 611a str r2, [r3, #16] - /* Sampling time 239.5 ADC clock cycles -> total conversion time 38.5us*/ - ADC1->SMPR = (7<<ADC_SMPR_SMP_Pos); - 8000604: 4b1e ldr r3, [pc, #120] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000606: 2207 movs r2, #7 - 8000608: 615a str r2, [r3, #20] - - /* Setup DMA and triggering */ - /* Trigger from TIM1 TRGO */ - ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | (2<<ADC_CFGR1_EXTEN_Pos) | (1<<ADC_CFGR1_EXTSEL_Pos); - 800060a: 4b1d ldr r3, [pc, #116] ; (8000680 <adc_configure_scope_mode+0x90>) - 800060c: 4a1d ldr r2, [pc, #116] ; (8000684 <adc_configure_scope_mode+0x94>) - 800060e: 60da str r2, [r3, #12] - ADC1->CHSELR = ADC_CHSELR_CHSEL2; - 8000610: 4b1b ldr r3, [pc, #108] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000612: 2204 movs r2, #4 - 8000614: 629a str r2, [r3, #40] ; 0x28 - /* Perform self-calibration */ - ADC1->CR |= ADC_CR_ADCAL; - 8000616: 4b1a ldr r3, [pc, #104] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000618: 689a ldr r2, [r3, #8] - 800061a: 4b19 ldr r3, [pc, #100] ; (8000680 <adc_configure_scope_mode+0x90>) - 800061c: 2180 movs r1, #128 ; 0x80 - 800061e: 0609 lsls r1, r1, #24 - 8000620: 430a orrs r2, r1 - 8000622: 609a str r2, [r3, #8] - while (ADC1->CR & ADC_CR_ADCAL) - 8000624: 46c0 nop ; (mov r8, r8) - 8000626: 4b16 ldr r3, [pc, #88] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000628: 689b ldr r3, [r3, #8] - 800062a: 2b00 cmp r3, #0 - 800062c: dbfb blt.n 8000626 <adc_configure_scope_mode+0x36> - ; - /* Enable conversion */ - ADC1->CR |= ADC_CR_ADEN; - 800062e: 4b14 ldr r3, [pc, #80] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000630: 689a ldr r2, [r3, #8] - 8000632: 4b13 ldr r3, [pc, #76] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000634: 2101 movs r1, #1 - 8000636: 430a orrs r2, r1 - 8000638: 609a str r2, [r3, #8] - ADC1->CR |= ADC_CR_ADSTART; - 800063a: 4b11 ldr r3, [pc, #68] ; (8000680 <adc_configure_scope_mode+0x90>) - 800063c: 689a ldr r2, [r3, #8] - 800063e: 4b10 ldr r3, [pc, #64] ; (8000680 <adc_configure_scope_mode+0x90>) - 8000640: 2104 movs r1, #4 - 8000642: 430a orrs r2, r1 - 8000644: 609a str r2, [r3, #8] - - /* An ADC conversion takes 1.1667us, so to be sure we don't get data overruns we limit sampling to every 1.5us. - Since we don't have a spare PLL to generate the ADC sample clock and re-configuring the system clock just for this - would be overkill we round to 250ns increments. The minimum sampling rate is about 60Hz due to timer resolution. */ - int cycles = sampling_interval_ns > 1500 ? sampling_interval_ns/250 : 6; - 8000646: 687b ldr r3, [r7, #4] - 8000648: 4a0f ldr r2, [pc, #60] ; (8000688 <adc_configure_scope_mode+0x98>) - 800064a: 4293 cmp r3, r2 - 800064c: dd06 ble.n 800065c <adc_configure_scope_mode+0x6c> - 800064e: 687b ldr r3, [r7, #4] - 8000650: 21fa movs r1, #250 ; 0xfa - 8000652: 0018 movs r0, r3 - 8000654: f001 f9d2 bl 80019fc <__divsi3> - 8000658: 0003 movs r3, r0 - 800065a: e000 b.n 800065e <adc_configure_scope_mode+0x6e> - 800065c: 2306 movs r3, #6 - 800065e: 60fb str r3, [r7, #12] - if (cycles > 0xffff) - 8000660: 68fa ldr r2, [r7, #12] - 8000662: 2380 movs r3, #128 ; 0x80 - 8000664: 025b lsls r3, r3, #9 - 8000666: 429a cmp r2, r3 - 8000668: db01 blt.n 800066e <adc_configure_scope_mode+0x7e> - cycles = 0xffff; - 800066a: 4b08 ldr r3, [pc, #32] ; (800068c <adc_configure_scope_mode+0x9c>) - 800066c: 60fb str r3, [r7, #12] - adc_timer_init(12/*250ns/tick*/, cycles); - 800066e: 68fb ldr r3, [r7, #12] - 8000670: 0019 movs r1, r3 - 8000672: 200c movs r0, #12 - 8000674: f000 f85a bl 800072c <adc_timer_init> -} - 8000678: 46c0 nop ; (mov r8, r8) - 800067a: 46bd mov sp, r7 - 800067c: b004 add sp, #16 - 800067e: bd80 pop {r7, pc} - 8000680: 40012400 .word 0x40012400 - 8000684: 00000843 .word 0x00000843 - 8000688: 000005dc .word 0x000005dc - 800068c: 0000ffff .word 0x0000ffff - -08000690 <adc_dma_init>: - -static void adc_dma_init() { - 8000690: b580 push {r7, lr} - 8000692: af00 add r7, sp, #0 - /* Configure DMA 1 Channel 1 to get rid of all the data */ - DMA1_Channel1->CPAR = (unsigned int)&ADC1->DR; - 8000694: 4b0b ldr r3, [pc, #44] ; (80006c4 <adc_dma_init+0x34>) - 8000696: 4a0c ldr r2, [pc, #48] ; (80006c8 <adc_dma_init+0x38>) - 8000698: 609a str r2, [r3, #8] - DMA1_Channel1->CCR = (0<<DMA_CCR_PL_Pos); - 800069a: 4b0a ldr r3, [pc, #40] ; (80006c4 <adc_dma_init+0x34>) - 800069c: 2200 movs r2, #0 - 800069e: 601a str r2, [r3, #0] - DMA1_Channel1->CCR |= - 80006a0: 4b08 ldr r3, [pc, #32] ; (80006c4 <adc_dma_init+0x34>) - 80006a2: 681a ldr r2, [r3, #0] - 80006a4: 4b07 ldr r3, [pc, #28] ; (80006c4 <adc_dma_init+0x34>) - 80006a6: 4909 ldr r1, [pc, #36] ; (80006cc <adc_dma_init+0x3c>) - 80006a8: 430a orrs r2, r1 - 80006aa: 601a str r2, [r3, #0] - | (1<<DMA_CCR_PSIZE_Pos) /* 16 bit */ - | DMA_CCR_MINC - | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ - - /* triggered on half-transfer and on transfer completion. We use this to send out the ADC data and to trap into GDB. */ - NVIC_EnableIRQ(DMA1_Channel1_IRQn); - 80006ac: 2009 movs r0, #9 - 80006ae: f7ff ff1b bl 80004e8 <NVIC_EnableIRQ> - NVIC_SetPriority(DMA1_Channel1_IRQn, 2<<5); - 80006b2: 2140 movs r1, #64 ; 0x40 - 80006b4: 2009 movs r0, #9 - 80006b6: f7ff ff2d bl 8000514 <NVIC_SetPriority> - - adc_dma_launch(); - 80006ba: f000 f809 bl 80006d0 <adc_dma_launch> -} - 80006be: 46c0 nop ; (mov r8, r8) - 80006c0: 46bd mov sp, r7 - 80006c2: bd80 pop {r7, pc} - 80006c4: 40020008 .word 0x40020008 - 80006c8: 40012440 .word 0x40012440 - 80006cc: 00000582 .word 0x00000582 - -080006d0 <adc_dma_launch>: - -void adc_dma_launch() { - 80006d0: b580 push {r7, lr} - 80006d2: af00 add r7, sp, #0 - DMA1_Channel1->CCR &= ~DMA_CCR_EN; /* Disable channel */ - 80006d4: 4b12 ldr r3, [pc, #72] ; (8000720 <adc_dma_launch+0x50>) - 80006d6: 681a ldr r2, [r3, #0] - 80006d8: 4b11 ldr r3, [pc, #68] ; (8000720 <adc_dma_launch+0x50>) - 80006da: 2101 movs r1, #1 - 80006dc: 438a bics r2, r1 - 80006de: 601a str r2, [r3, #0] - current_buf = !current_buf; - 80006e0: 4b10 ldr r3, [pc, #64] ; (8000724 <adc_dma_launch+0x54>) - 80006e2: 681b ldr r3, [r3, #0] - 80006e4: 425a negs r2, r3 - 80006e6: 4153 adcs r3, r2 - 80006e8: b2db uxtb r3, r3 - 80006ea: 001a movs r2, r3 - 80006ec: 4b0d ldr r3, [pc, #52] ; (8000724 <adc_dma_launch+0x54>) - 80006ee: 601a str r2, [r3, #0] - DMA1_Channel1->CMAR = (unsigned int)&(adc_pkt[current_buf].data); - 80006f0: 4b0c ldr r3, [pc, #48] ; (8000724 <adc_dma_launch+0x54>) - 80006f2: 681a ldr r2, [r3, #0] - 80006f4: 0013 movs r3, r2 - 80006f6: 00db lsls r3, r3, #3 - 80006f8: 189b adds r3, r3, r2 - 80006fa: 00db lsls r3, r3, #3 - 80006fc: 3308 adds r3, #8 - 80006fe: 001a movs r2, r3 - 8000700: 4b09 ldr r3, [pc, #36] ; (8000728 <adc_dma_launch+0x58>) - 8000702: 18d2 adds r2, r2, r3 - 8000704: 4b06 ldr r3, [pc, #24] ; (8000720 <adc_dma_launch+0x50>) - 8000706: 60da str r2, [r3, #12] - DMA1_Channel1->CNDTR = ARRAY_LEN(adc_pkt[current_buf].data); - 8000708: 4b05 ldr r3, [pc, #20] ; (8000720 <adc_dma_launch+0x50>) - 800070a: 2220 movs r2, #32 - 800070c: 605a str r2, [r3, #4] - DMA1_Channel1->CCR |= DMA_CCR_EN; /* Enable channel */ - 800070e: 4b04 ldr r3, [pc, #16] ; (8000720 <adc_dma_launch+0x50>) - 8000710: 681a ldr r2, [r3, #0] - 8000712: 4b03 ldr r3, [pc, #12] ; (8000720 <adc_dma_launch+0x50>) - 8000714: 2101 movs r1, #1 - 8000716: 430a orrs r2, r1 - 8000718: 601a str r2, [r3, #0] -} - 800071a: 46c0 nop ; (mov r8, r8) - 800071c: 46bd mov sp, r7 - 800071e: bd80 pop {r7, pc} - 8000720: 40020008 .word 0x40020008 - 8000724: 20000134 .word 0x20000134 - 8000728: 200000a0 .word 0x200000a0 - -0800072c <adc_timer_init>: - -static void adc_timer_init(int psc, int ivl) { - 800072c: b580 push {r7, lr} - 800072e: b082 sub sp, #8 - 8000730: af00 add r7, sp, #0 - 8000732: 6078 str r0, [r7, #4] - 8000734: 6039 str r1, [r7, #0] - TIM1->BDTR = TIM_BDTR_MOE; /* MOE is needed even though we only "output" a chip-internal signal TODO: Verify this. */ - 8000736: 4b15 ldr r3, [pc, #84] ; (800078c <adc_timer_init+0x60>) - 8000738: 2280 movs r2, #128 ; 0x80 - 800073a: 0212 lsls r2, r2, #8 - 800073c: 645a str r2, [r3, #68] ; 0x44 - TIM1->CCMR2 = (6<<TIM_CCMR2_OC4M_Pos); /* PWM Mode 1 to get a clean trigger signal */ - 800073e: 4b13 ldr r3, [pc, #76] ; (800078c <adc_timer_init+0x60>) - 8000740: 22c0 movs r2, #192 ; 0xc0 - 8000742: 01d2 lsls r2, r2, #7 - 8000744: 61da str r2, [r3, #28] - TIM1->CCER = TIM_CCER_CC4E; /* Enable capture/compare unit 4 connected to ADC */ - 8000746: 4b11 ldr r3, [pc, #68] ; (800078c <adc_timer_init+0x60>) - 8000748: 2280 movs r2, #128 ; 0x80 - 800074a: 0152 lsls r2, r2, #5 - 800074c: 621a str r2, [r3, #32] - TIM1->CCR4 = 1; /* Trigger at start of timer cycle */ - 800074e: 4b0f ldr r3, [pc, #60] ; (800078c <adc_timer_init+0x60>) - 8000750: 2201 movs r2, #1 - 8000752: 641a str r2, [r3, #64] ; 0x40 - /* Set prescaler and interval */ - TIM1->PSC = psc-1; - 8000754: 687b ldr r3, [r7, #4] - 8000756: 1e5a subs r2, r3, #1 - 8000758: 4b0c ldr r3, [pc, #48] ; (800078c <adc_timer_init+0x60>) - 800075a: 629a str r2, [r3, #40] ; 0x28 - TIM1->ARR = ivl-1; - 800075c: 683b ldr r3, [r7, #0] - 800075e: 1e5a subs r2, r3, #1 - 8000760: 4b0a ldr r3, [pc, #40] ; (800078c <adc_timer_init+0x60>) - 8000762: 62da str r2, [r3, #44] ; 0x2c - /* Preload all values */ - TIM1->EGR |= TIM_EGR_UG; - 8000764: 4b09 ldr r3, [pc, #36] ; (800078c <adc_timer_init+0x60>) - 8000766: 695a ldr r2, [r3, #20] - 8000768: 4b08 ldr r3, [pc, #32] ; (800078c <adc_timer_init+0x60>) - 800076a: 2101 movs r1, #1 - 800076c: 430a orrs r2, r1 - 800076e: 615a str r2, [r3, #20] - TIM1->CR1 = TIM_CR1_ARPE; - 8000770: 4b06 ldr r3, [pc, #24] ; (800078c <adc_timer_init+0x60>) - 8000772: 2280 movs r2, #128 ; 0x80 - 8000774: 601a str r2, [r3, #0] - /* And... go! */ - TIM1->CR1 |= TIM_CR1_CEN; - 8000776: 4b05 ldr r3, [pc, #20] ; (800078c <adc_timer_init+0x60>) - 8000778: 681a ldr r2, [r3, #0] - 800077a: 4b04 ldr r3, [pc, #16] ; (800078c <adc_timer_init+0x60>) - 800077c: 2101 movs r1, #1 - 800077e: 430a orrs r2, r1 - 8000780: 601a str r2, [r3, #0] -} - 8000782: 46c0 nop ; (mov r8, r8) - 8000784: 46bd mov sp, r7 - 8000786: b002 add sp, #8 - 8000788: bd80 pop {r7, pc} - 800078a: 46c0 nop ; (mov r8, r8) - 800078c: 40012c00 .word 0x40012c00 - -08000790 <gdb_dump>: - -/* This acts as a no-op that provides a convenient point to set a breakpoint for the debug scope logic */ -static void gdb_dump(void) { - 8000790: b580 push {r7, lr} - 8000792: af00 add r7, sp, #0 -} - 8000794: 46c0 nop ; (mov r8, r8) - 8000796: 46bd mov sp, r7 - 8000798: bd80 pop {r7, pc} - -0800079a <DMA1_Channel1_IRQHandler>: - -void DMA1_Channel1_IRQHandler(void) { - 800079a: b580 push {r7, lr} - 800079c: b082 sub sp, #8 - 800079e: af00 add r7, sp, #0 - uint32_t isr = DMA1->ISR; - 80007a0: 4b1a ldr r3, [pc, #104] ; (800080c <DMA1_Channel1_IRQHandler+0x72>) - 80007a2: 681b ldr r3, [r3, #0] - 80007a4: 607b str r3, [r7, #4] - /* Clear the interrupt flag */ - DMA1->IFCR |= DMA_IFCR_CGIF1; - 80007a6: 4b19 ldr r3, [pc, #100] ; (800080c <DMA1_Channel1_IRQHandler+0x72>) - 80007a8: 685a ldr r2, [r3, #4] - 80007aa: 4b18 ldr r3, [pc, #96] ; (800080c <DMA1_Channel1_IRQHandler+0x72>) - 80007ac: 2101 movs r1, #1 - 80007ae: 430a orrs r2, r1 - 80007b0: 605a str r2, [r3, #4] - adc_dma_launch(); - 80007b2: f7ff ff8d bl 80006d0 <adc_dma_launch> - - gdb_dump(); - 80007b6: f7ff ffeb bl 8000790 <gdb_dump> - - adc_pkt[!current_buf].seq = current_seq++; - 80007ba: 4b15 ldr r3, [pc, #84] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>) - 80007bc: 881a ldrh r2, [r3, #0] - 80007be: 1c53 adds r3, r2, #1 - 80007c0: b299 uxth r1, r3 - 80007c2: 4b13 ldr r3, [pc, #76] ; (8000810 <DMA1_Channel1_IRQHandler+0x76>) - 80007c4: 8019 strh r1, [r3, #0] - 80007c6: 4b13 ldr r3, [pc, #76] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>) - 80007c8: 681b ldr r3, [r3, #0] - 80007ca: 4259 negs r1, r3 - 80007cc: 414b adcs r3, r1 - 80007ce: b2db uxtb r3, r3 - 80007d0: 0018 movs r0, r3 - 80007d2: 4911 ldr r1, [pc, #68] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>) - 80007d4: 0003 movs r3, r0 - 80007d6: 00db lsls r3, r3, #3 - 80007d8: 181b adds r3, r3, r0 - 80007da: 00db lsls r3, r3, #3 - 80007dc: 18cb adds r3, r1, r3 - 80007de: 3306 adds r3, #6 - 80007e0: 801a strh r2, [r3, #0] - /* Ignore return value since we can't do anything here. Overruns are logged in serial.c. */ - usart_send_packet_nonblocking(&adc_pkt[!current_buf].ll, sizeof(adc_pkt[!current_buf])); - 80007e2: 4b0c ldr r3, [pc, #48] ; (8000814 <DMA1_Channel1_IRQHandler+0x7a>) - 80007e4: 681b ldr r3, [r3, #0] - 80007e6: 425a negs r2, r3 - 80007e8: 4153 adcs r3, r2 - 80007ea: b2db uxtb r3, r3 - 80007ec: 001a movs r2, r3 - 80007ee: 0013 movs r3, r2 - 80007f0: 00db lsls r3, r3, #3 - 80007f2: 189b adds r3, r3, r2 - 80007f4: 00db lsls r3, r3, #3 - 80007f6: 4a08 ldr r2, [pc, #32] ; (8000818 <DMA1_Channel1_IRQHandler+0x7e>) - 80007f8: 189b adds r3, r3, r2 - 80007fa: 2148 movs r1, #72 ; 0x48 - 80007fc: 0018 movs r0, r3 - 80007fe: f000 fac7 bl 8000d90 <usart_send_packet_nonblocking> - adc_buf[i] = -255; - } - } - } - */ -} - 8000802: 46c0 nop ; (mov r8, r8) - 8000804: 46bd mov sp, r7 - 8000806: b002 add sp, #8 - 8000808: bd80 pop {r7, pc} - 800080a: 46c0 nop ; (mov r8, r8) - 800080c: 40020000 .word 0x40020000 - 8000810: 20000130 .word 0x20000130 - 8000814: 20000134 .word 0x20000134 - 8000818: 200000a0 .word 0x200000a0 - -0800081c <NVIC_EnableIRQ>: -{ - 800081c: b580 push {r7, lr} - 800081e: b082 sub sp, #8 - 8000820: af00 add r7, sp, #0 - 8000822: 0002 movs r2, r0 - 8000824: 1dfb adds r3, r7, #7 - 8000826: 701a strb r2, [r3, #0] - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - 8000828: 1dfb adds r3, r7, #7 - 800082a: 781b ldrb r3, [r3, #0] - 800082c: 001a movs r2, r3 - 800082e: 231f movs r3, #31 - 8000830: 401a ands r2, r3 - 8000832: 4b04 ldr r3, [pc, #16] ; (8000844 <NVIC_EnableIRQ+0x28>) - 8000834: 2101 movs r1, #1 - 8000836: 4091 lsls r1, r2 - 8000838: 000a movs r2, r1 - 800083a: 601a str r2, [r3, #0] -} - 800083c: 46c0 nop ; (mov r8, r8) - 800083e: 46bd mov sp, r7 - 8000840: b002 add sp, #8 - 8000842: bd80 pop {r7, pc} - 8000844: e000e100 .word 0xe000e100 - -08000848 <NVIC_DisableIRQ>: -{ - 8000848: b580 push {r7, lr} - 800084a: b082 sub sp, #8 - 800084c: af00 add r7, sp, #0 - 800084e: 0002 movs r2, r0 - 8000850: 1dfb adds r3, r7, #7 - 8000852: 701a strb r2, [r3, #0] - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); - 8000854: 1dfb adds r3, r7, #7 - 8000856: 781b ldrb r3, [r3, #0] - 8000858: 001a movs r2, r3 - 800085a: 231f movs r3, #31 - 800085c: 4013 ands r3, r2 - 800085e: 4905 ldr r1, [pc, #20] ; (8000874 <NVIC_DisableIRQ+0x2c>) - 8000860: 2201 movs r2, #1 - 8000862: 409a lsls r2, r3 - 8000864: 0013 movs r3, r2 - 8000866: 2280 movs r2, #128 ; 0x80 - 8000868: 508b str r3, [r1, r2] -} - 800086a: 46c0 nop ; (mov r8, r8) - 800086c: 46bd mov sp, r7 - 800086e: b002 add sp, #8 - 8000870: bd80 pop {r7, pc} - 8000872: 46c0 nop ; (mov r8, r8) - 8000874: e000e100 .word 0xe000e100 - -08000878 <NVIC_SetPriority>: -{ - 8000878: b590 push {r4, r7, lr} - 800087a: b083 sub sp, #12 - 800087c: af00 add r7, sp, #0 - 800087e: 0002 movs r2, r0 - 8000880: 6039 str r1, [r7, #0] - 8000882: 1dfb adds r3, r7, #7 - 8000884: 701a strb r2, [r3, #0] - if ((int32_t)(IRQn) < 0) - 8000886: 1dfb adds r3, r7, #7 - 8000888: 781b ldrb r3, [r3, #0] - 800088a: 2b7f cmp r3, #127 ; 0x7f - 800088c: d932 bls.n 80008f4 <NVIC_SetPriority+0x7c> - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 800088e: 4a2f ldr r2, [pc, #188] ; (800094c <NVIC_SetPriority+0xd4>) - 8000890: 1dfb adds r3, r7, #7 - 8000892: 781b ldrb r3, [r3, #0] - 8000894: 0019 movs r1, r3 - 8000896: 230f movs r3, #15 - 8000898: 400b ands r3, r1 - 800089a: 3b08 subs r3, #8 - 800089c: 089b lsrs r3, r3, #2 - 800089e: 3306 adds r3, #6 - 80008a0: 009b lsls r3, r3, #2 - 80008a2: 18d3 adds r3, r2, r3 - 80008a4: 3304 adds r3, #4 - 80008a6: 681b ldr r3, [r3, #0] - 80008a8: 1dfa adds r2, r7, #7 - 80008aa: 7812 ldrb r2, [r2, #0] - 80008ac: 0011 movs r1, r2 - 80008ae: 2203 movs r2, #3 - 80008b0: 400a ands r2, r1 - 80008b2: 00d2 lsls r2, r2, #3 - 80008b4: 21ff movs r1, #255 ; 0xff - 80008b6: 4091 lsls r1, r2 - 80008b8: 000a movs r2, r1 - 80008ba: 43d2 mvns r2, r2 - 80008bc: 401a ands r2, r3 - 80008be: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 80008c0: 683b ldr r3, [r7, #0] - 80008c2: 019b lsls r3, r3, #6 - 80008c4: 22ff movs r2, #255 ; 0xff - 80008c6: 401a ands r2, r3 - 80008c8: 1dfb adds r3, r7, #7 - 80008ca: 781b ldrb r3, [r3, #0] - 80008cc: 0018 movs r0, r3 - 80008ce: 2303 movs r3, #3 - 80008d0: 4003 ands r3, r0 - 80008d2: 00db lsls r3, r3, #3 - 80008d4: 409a lsls r2, r3 - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80008d6: 481d ldr r0, [pc, #116] ; (800094c <NVIC_SetPriority+0xd4>) - 80008d8: 1dfb adds r3, r7, #7 - 80008da: 781b ldrb r3, [r3, #0] - 80008dc: 001c movs r4, r3 - 80008de: 230f movs r3, #15 - 80008e0: 4023 ands r3, r4 - 80008e2: 3b08 subs r3, #8 - 80008e4: 089b lsrs r3, r3, #2 - 80008e6: 430a orrs r2, r1 - 80008e8: 3306 adds r3, #6 - 80008ea: 009b lsls r3, r3, #2 - 80008ec: 18c3 adds r3, r0, r3 - 80008ee: 3304 adds r3, #4 - 80008f0: 601a str r2, [r3, #0] -} - 80008f2: e027 b.n 8000944 <NVIC_SetPriority+0xcc> - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 80008f4: 4a16 ldr r2, [pc, #88] ; (8000950 <NVIC_SetPriority+0xd8>) - 80008f6: 1dfb adds r3, r7, #7 - 80008f8: 781b ldrb r3, [r3, #0] - 80008fa: b25b sxtb r3, r3 - 80008fc: 089b lsrs r3, r3, #2 - 80008fe: 33c0 adds r3, #192 ; 0xc0 - 8000900: 009b lsls r3, r3, #2 - 8000902: 589b ldr r3, [r3, r2] - 8000904: 1dfa adds r2, r7, #7 - 8000906: 7812 ldrb r2, [r2, #0] - 8000908: 0011 movs r1, r2 - 800090a: 2203 movs r2, #3 - 800090c: 400a ands r2, r1 - 800090e: 00d2 lsls r2, r2, #3 - 8000910: 21ff movs r1, #255 ; 0xff - 8000912: 4091 lsls r1, r2 - 8000914: 000a movs r2, r1 - 8000916: 43d2 mvns r2, r2 - 8000918: 401a ands r2, r3 - 800091a: 0011 movs r1, r2 - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - 800091c: 683b ldr r3, [r7, #0] - 800091e: 019b lsls r3, r3, #6 - 8000920: 22ff movs r2, #255 ; 0xff - 8000922: 401a ands r2, r3 - 8000924: 1dfb adds r3, r7, #7 - 8000926: 781b ldrb r3, [r3, #0] - 8000928: 0018 movs r0, r3 - 800092a: 2303 movs r3, #3 - 800092c: 4003 ands r3, r0 - 800092e: 00db lsls r3, r3, #3 - 8000930: 409a lsls r2, r3 - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - 8000932: 4807 ldr r0, [pc, #28] ; (8000950 <NVIC_SetPriority+0xd8>) - 8000934: 1dfb adds r3, r7, #7 - 8000936: 781b ldrb r3, [r3, #0] - 8000938: b25b sxtb r3, r3 - 800093a: 089b lsrs r3, r3, #2 - 800093c: 430a orrs r2, r1 - 800093e: 33c0 adds r3, #192 ; 0xc0 - 8000940: 009b lsls r3, r3, #2 - 8000942: 501a str r2, [r3, r0] -} - 8000944: 46c0 nop ; (mov r8, r8) - 8000946: 46bd mov sp, r7 - 8000948: b003 add sp, #12 - 800094a: bd90 pop {r4, r7, pc} - 800094c: e000ed00 .word 0xe000ed00 - 8000950: e000e100 .word 0xe000e100 - -08000954 <usart_dma_init>: - -static void usart_schedule_dma(void); -static int usart_putc_nonblocking(uint8_t c); - - -void usart_dma_init() { - 8000954: b580 push {r7, lr} - 8000956: b082 sub sp, #8 - 8000958: af00 add r7, sp, #0 - usart_tx_buf.xfr_start = -1; - 800095a: 4b30 ldr r3, [pc, #192] ; (8000a1c <usart_dma_init+0xc8>) - 800095c: 2201 movs r2, #1 - 800095e: 4252 negs r2, r2 - 8000960: 601a str r2, [r3, #0] - usart_tx_buf.xfr_end = 0; - 8000962: 4b2e ldr r3, [pc, #184] ; (8000a1c <usart_dma_init+0xc8>) - 8000964: 2200 movs r2, #0 - 8000966: 605a str r2, [r3, #4] - usart_tx_buf.wr_pos = 0; - 8000968: 4b2c ldr r3, [pc, #176] ; (8000a1c <usart_dma_init+0xc8>) - 800096a: 2200 movs r2, #0 - 800096c: 615a str r2, [r3, #20] - usart_tx_buf.wr_idx = 0; - 800096e: 4b2b ldr r3, [pc, #172] ; (8000a1c <usart_dma_init+0xc8>) - 8000970: 2200 movs r2, #0 - 8000972: 619a str r2, [r3, #24] - usart_tx_buf.cur_packet = -1; - 8000974: 4b29 ldr r3, [pc, #164] ; (8000a1c <usart_dma_init+0xc8>) - 8000976: 2201 movs r2, #1 - 8000978: 4252 negs r2, r2 - 800097a: 609a str r2, [r3, #8] - usart_tx_buf.retransmit_rq = 0; - 800097c: 4b27 ldr r3, [pc, #156] ; (8000a1c <usart_dma_init+0xc8>) - 800097e: 2200 movs r2, #0 - 8000980: 60da str r2, [r3, #12] - usart_tx_buf.wraparound = 0; - 8000982: 4b26 ldr r3, [pc, #152] ; (8000a1c <usart_dma_init+0xc8>) - 8000984: 2200 movs r2, #0 - 8000986: 611a str r2, [r3, #16] - for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++) - 8000988: 2300 movs r3, #0 - 800098a: 607b str r3, [r7, #4] - 800098c: e00b b.n 80009a6 <usart_dma_init+0x52> - usart_tx_buf.packet_end[i] = -1; - 800098e: 4a23 ldr r2, [pc, #140] ; (8000a1c <usart_dma_init+0xc8>) - 8000990: 687b ldr r3, [r7, #4] - 8000992: 3306 adds r3, #6 - 8000994: 009b lsls r3, r3, #2 - 8000996: 18d3 adds r3, r2, r3 - 8000998: 3304 adds r3, #4 - 800099a: 2201 movs r2, #1 - 800099c: 4252 negs r2, r2 - 800099e: 601a str r2, [r3, #0] - for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++) - 80009a0: 687b ldr r3, [r7, #4] - 80009a2: 3301 adds r3, #1 - 80009a4: 607b str r3, [r7, #4] - 80009a6: 687b ldr r3, [r7, #4] - 80009a8: 2b07 cmp r3, #7 - 80009aa: d9f0 bls.n 800098e <usart_dma_init+0x3a> - - cobs_decode_incremental_initialize(&cobs_state); - 80009ac: 4b1c ldr r3, [pc, #112] ; (8000a20 <usart_dma_init+0xcc>) - 80009ae: 0018 movs r0, r3 - 80009b0: f000 fb4a bl 8001048 <cobs_decode_incremental_initialize> - - /* Configure DMA 1 Channel 2 to handle uart transmission */ - DMA1_Channel2->CPAR = (uint32_t)&(USART1->TDR); - 80009b4: 4b1b ldr r3, [pc, #108] ; (8000a24 <usart_dma_init+0xd0>) - 80009b6: 4a1c ldr r2, [pc, #112] ; (8000a28 <usart_dma_init+0xd4>) - 80009b8: 609a str r2, [r3, #8] - DMA1_Channel2->CCR = (0<<DMA_CCR_PL_Pos) - 80009ba: 4b1a ldr r3, [pc, #104] ; (8000a24 <usart_dma_init+0xd0>) - 80009bc: 2292 movs r2, #146 ; 0x92 - 80009be: 601a str r2, [r3, #0] - | (0<<DMA_CCR_MSIZE_Pos) /* 8 bit */ - | (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */ - | DMA_CCR_MINC - | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ - - DMA1_Channel3->CMAR = (uint32_t)&(CRC->DR); - 80009c0: 4b1a ldr r3, [pc, #104] ; (8000a2c <usart_dma_init+0xd8>) - 80009c2: 4a1b ldr r2, [pc, #108] ; (8000a30 <usart_dma_init+0xdc>) - 80009c4: 60da str r2, [r3, #12] - DMA1_Channel3->CCR = (1<<DMA_CCR_PL_Pos) - 80009c6: 4b19 ldr r3, [pc, #100] ; (8000a2c <usart_dma_init+0xd8>) - 80009c8: 4a1a ldr r2, [pc, #104] ; (8000a34 <usart_dma_init+0xe0>) - 80009ca: 601a str r2, [r3, #0] - | (0<<DMA_CCR_PSIZE_Pos) /* 8 bit */ - | DMA_CCR_PINC - | DMA_CCR_TCIE; /* Enable transfer complete interrupt. */ - - /* triggered on transfer completion. We use this to process the ADC data */ - NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); - 80009cc: 200a movs r0, #10 - 80009ce: f7ff ff25 bl 800081c <NVIC_EnableIRQ> - NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1<<5); - 80009d2: 2120 movs r1, #32 - 80009d4: 200a movs r0, #10 - 80009d6: f7ff ff4f bl 8000878 <NVIC_SetPriority> - - USART1->CR1 = /* 8-bit -> M1, M0 clear */ - 80009da: 4b17 ldr r3, [pc, #92] ; (8000a38 <usart_dma_init+0xe4>) - 80009dc: 4a17 ldr r2, [pc, #92] ; (8000a3c <usart_dma_init+0xe8>) - 80009de: 601a str r2, [r3, #0] - /* Set divider for 115.2kBd @48MHz system clock. */ - //USART1->BRR = 417; - - //USART1->BRR = 48; /* 1MBd */ - //USART1->BRR = 96; /* 500kBd */ - USART1->BRR = 192; /* 250kBd */ - 80009e0: 4b15 ldr r3, [pc, #84] ; (8000a38 <usart_dma_init+0xe4>) - 80009e2: 22c0 movs r2, #192 ; 0xc0 - 80009e4: 60da str r2, [r3, #12] - //USART1->BRR = 208; /* 230400 */ - - USART1->CR2 = USART_CR2_TXINV | USART_CR2_RXINV; - 80009e6: 4b14 ldr r3, [pc, #80] ; (8000a38 <usart_dma_init+0xe4>) - 80009e8: 22c0 movs r2, #192 ; 0xc0 - 80009ea: 0292 lsls r2, r2, #10 - 80009ec: 605a str r2, [r3, #4] - - USART1->CR3 |= USART_CR3_DMAT; /* TX DMA enable */ - 80009ee: 4b12 ldr r3, [pc, #72] ; (8000a38 <usart_dma_init+0xe4>) - 80009f0: 689a ldr r2, [r3, #8] - 80009f2: 4b11 ldr r3, [pc, #68] ; (8000a38 <usart_dma_init+0xe4>) - 80009f4: 2180 movs r1, #128 ; 0x80 - 80009f6: 430a orrs r2, r1 - 80009f8: 609a str r2, [r3, #8] - - /* Enable receive interrupt */ - NVIC_EnableIRQ(USART1_IRQn); - 80009fa: 201b movs r0, #27 - 80009fc: f7ff ff0e bl 800081c <NVIC_EnableIRQ> - NVIC_SetPriority(USART1_IRQn, 3<<5); - 8000a00: 2160 movs r1, #96 ; 0x60 - 8000a02: 201b movs r0, #27 - 8000a04: f7ff ff38 bl 8000878 <NVIC_SetPriority> - - /* And... go! */ - USART1->CR1 |= USART_CR1_UE; - 8000a08: 4b0b ldr r3, [pc, #44] ; (8000a38 <usart_dma_init+0xe4>) - 8000a0a: 681a ldr r2, [r3, #0] - 8000a0c: 4b0a ldr r3, [pc, #40] ; (8000a38 <usart_dma_init+0xe4>) - 8000a0e: 2101 movs r1, #1 - 8000a10: 430a orrs r2, r1 - 8000a12: 601a str r2, [r3, #0] -} - 8000a14: 46c0 nop ; (mov r8, r8) - 8000a16: 46bd mov sp, r7 - 8000a18: b002 add sp, #8 - 8000a1a: bd80 pop {r7, pc} - 8000a1c: 20000198 .word 0x20000198 - 8000a20: 20000148 .word 0x20000148 - 8000a24: 4002001c .word 0x4002001c - 8000a28: 40013828 .word 0x40013828 - 8000a2c: 40020030 .word 0x40020030 - 8000a30: 40023000 .word 0x40023000 - 8000a34: 00001042 .word 0x00001042 - 8000a38: 40013800 .word 0x40013800 - 8000a3c: 0000202c .word 0x0000202c - -08000a40 <USART1_IRQHandler>: - -void USART1_IRQHandler() { - 8000a40: b580 push {r7, lr} - 8000a42: b086 sub sp, #24 - 8000a44: af00 add r7, sp, #0 - uint32_t isr = USART1->ISR; - 8000a46: 4b40 ldr r3, [pc, #256] ; (8000b48 <USART1_IRQHandler+0x108>) - 8000a48: 69db ldr r3, [r3, #28] - 8000a4a: 613b str r3, [r7, #16] - - if (isr & USART_ISR_ORE) { - 8000a4c: 693b ldr r3, [r7, #16] - 8000a4e: 2208 movs r2, #8 - 8000a50: 4013 ands r3, r2 - 8000a52: d008 beq.n 8000a66 <USART1_IRQHandler+0x26> - USART1->ICR = USART_ICR_ORECF; - 8000a54: 4b3c ldr r3, [pc, #240] ; (8000b48 <USART1_IRQHandler+0x108>) - 8000a56: 2208 movs r2, #8 - 8000a58: 621a str r2, [r3, #32] - rx_overruns++; - 8000a5a: 4b3c ldr r3, [pc, #240] ; (8000b4c <USART1_IRQHandler+0x10c>) - 8000a5c: 681b ldr r3, [r3, #0] - 8000a5e: 1c5a adds r2, r3, #1 - 8000a60: 4b3a ldr r3, [pc, #232] ; (8000b4c <USART1_IRQHandler+0x10c>) - 8000a62: 601a str r2, [r3, #0] - return; - 8000a64: e06c b.n 8000b40 <USART1_IRQHandler+0x100> - } - - if (isr & USART_ISR_RXNE) { - 8000a66: 693b ldr r3, [r7, #16] - 8000a68: 2220 movs r2, #32 - 8000a6a: 4013 ands r3, r2 - 8000a6c: d100 bne.n 8000a70 <USART1_IRQHandler+0x30> - 8000a6e: e067 b.n 8000b40 <USART1_IRQHandler+0x100> - uint8_t c = USART1->RDR; - 8000a70: 4b35 ldr r3, [pc, #212] ; (8000b48 <USART1_IRQHandler+0x108>) - 8000a72: 8c9b ldrh r3, [r3, #36] ; 0x24 - 8000a74: b29a uxth r2, r3 - 8000a76: 210f movs r1, #15 - 8000a78: 187b adds r3, r7, r1 - 8000a7a: 701a strb r2, [r3, #0] - - int rc = cobs_decode_incremental(&cobs_state, (char *)rx_buf, sizeof(rx_buf), c); - 8000a7c: 187b adds r3, r7, r1 - 8000a7e: 781b ldrb r3, [r3, #0] - 8000a80: 4933 ldr r1, [pc, #204] ; (8000b50 <USART1_IRQHandler+0x110>) - 8000a82: 4834 ldr r0, [pc, #208] ; (8000b54 <USART1_IRQHandler+0x114>) - 8000a84: 2220 movs r2, #32 - 8000a86: f000 faed bl 8001064 <cobs_decode_incremental> - 8000a8a: 0003 movs r3, r0 - 8000a8c: 60bb str r3, [r7, #8] - if (rc == 0) /* packet still incomplete */ - 8000a8e: 68bb ldr r3, [r7, #8] - 8000a90: 2b00 cmp r3, #0 - 8000a92: d054 beq.n 8000b3e <USART1_IRQHandler+0xfe> - return; - - if (rc < 0) { - 8000a94: 68bb ldr r3, [r7, #8] - 8000a96: 2b00 cmp r3, #0 - 8000a98: da05 bge.n 8000aa6 <USART1_IRQHandler+0x66> - rx_framing_errors++; - 8000a9a: 4b2f ldr r3, [pc, #188] ; (8000b58 <USART1_IRQHandler+0x118>) - 8000a9c: 681b ldr r3, [r3, #0] - 8000a9e: 1c5a adds r2, r3, #1 - 8000aa0: 4b2d ldr r3, [pc, #180] ; (8000b58 <USART1_IRQHandler+0x118>) - 8000aa2: 601a str r2, [r3, #0] - return; - 8000aa4: e04c b.n 8000b40 <USART1_IRQHandler+0x100> - } - - /* A complete frame received */ - if (rc != 2) { - 8000aa6: 68bb ldr r3, [r7, #8] - 8000aa8: 2b02 cmp r3, #2 - 8000aaa: d005 beq.n 8000ab8 <USART1_IRQHandler+0x78> - rx_protocol_errors++; - 8000aac: 4b2b ldr r3, [pc, #172] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000aae: 681b ldr r3, [r3, #0] - 8000ab0: 1c5a adds r2, r3, #1 - 8000ab2: 4b2a ldr r3, [pc, #168] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000ab4: 601a str r2, [r3, #0] - return; - 8000ab6: e043 b.n 8000b40 <USART1_IRQHandler+0x100> - } - - volatile struct ctrl_pkt *pkt = (volatile struct ctrl_pkt *)rx_buf; - 8000ab8: 4b25 ldr r3, [pc, #148] ; (8000b50 <USART1_IRQHandler+0x110>) - 8000aba: 607b str r3, [r7, #4] - - switch (pkt->type) { - 8000abc: 687b ldr r3, [r7, #4] - 8000abe: 781b ldrb r3, [r3, #0] - 8000ac0: b2db uxtb r3, r3 - 8000ac2: 2b03 cmp r3, #3 - 8000ac4: d026 beq.n 8000b14 <USART1_IRQHandler+0xd4> - 8000ac6: dc30 bgt.n 8000b2a <USART1_IRQHandler+0xea> - 8000ac8: 2b01 cmp r3, #1 - 8000aca: d002 beq.n 8000ad2 <USART1_IRQHandler+0x92> - 8000acc: 2b02 cmp r3, #2 - 8000ace: d013 beq.n 8000af8 <USART1_IRQHandler+0xb8> - 8000ad0: e02b b.n 8000b2a <USART1_IRQHandler+0xea> - case CTRL_PKT_RESET: - for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++) - 8000ad2: 2300 movs r3, #0 - 8000ad4: 617b str r3, [r7, #20] - 8000ad6: e00b b.n 8000af0 <USART1_IRQHandler+0xb0> - usart_tx_buf.packet_end[i] = -1; - 8000ad8: 4a21 ldr r2, [pc, #132] ; (8000b60 <USART1_IRQHandler+0x120>) - 8000ada: 697b ldr r3, [r7, #20] - 8000adc: 3306 adds r3, #6 - 8000ade: 009b lsls r3, r3, #2 - 8000ae0: 18d3 adds r3, r2, r3 - 8000ae2: 3304 adds r3, #4 - 8000ae4: 2201 movs r2, #1 - 8000ae6: 4252 negs r2, r2 - 8000ae8: 601a str r2, [r3, #0] - for (size_t i=0; i<ARRAY_LEN(usart_tx_buf.packet_end); i++) - 8000aea: 697b ldr r3, [r7, #20] - 8000aec: 3301 adds r3, #1 - 8000aee: 617b str r3, [r7, #20] - 8000af0: 697b ldr r3, [r7, #20] - 8000af2: 2b07 cmp r3, #7 - 8000af4: d9f0 bls.n 8000ad8 <USART1_IRQHandler+0x98> - break; - 8000af6: e021 b.n 8000b3c <USART1_IRQHandler+0xfc> - - case CTRL_PKT_ACK: - if (usart_ack_packet(pkt->orig_id)) - 8000af8: 687b ldr r3, [r7, #4] - 8000afa: 785b ldrb r3, [r3, #1] - 8000afc: b2db uxtb r3, r3 - 8000afe: 0018 movs r0, r3 - 8000b00: f000 f89a bl 8000c38 <usart_ack_packet> - 8000b04: 1e03 subs r3, r0, #0 - 8000b06: d016 beq.n 8000b36 <USART1_IRQHandler+0xf6> - rx_protocol_errors++; - 8000b08: 4b14 ldr r3, [pc, #80] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000b0a: 681b ldr r3, [r3, #0] - 8000b0c: 1c5a adds r2, r3, #1 - 8000b0e: 4b13 ldr r3, [pc, #76] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000b10: 601a str r2, [r3, #0] - break; - 8000b12: e010 b.n 8000b36 <USART1_IRQHandler+0xf6> - - case CTRL_PKT_RETRANSMIT: - usart_tx_buf.retransmit_rq = 1; - 8000b14: 4b12 ldr r3, [pc, #72] ; (8000b60 <USART1_IRQHandler+0x120>) - 8000b16: 2201 movs r2, #1 - 8000b18: 60da str r2, [r3, #12] - if (!(DMA1_Channel2->CCR & DMA_CCR_EN)) - 8000b1a: 4b12 ldr r3, [pc, #72] ; (8000b64 <USART1_IRQHandler+0x124>) - 8000b1c: 681b ldr r3, [r3, #0] - 8000b1e: 2201 movs r2, #1 - 8000b20: 4013 ands r3, r2 - 8000b22: d10a bne.n 8000b3a <USART1_IRQHandler+0xfa> - usart_schedule_dma(); - 8000b24: f000 f820 bl 8000b68 <usart_schedule_dma> - break; - 8000b28: e007 b.n 8000b3a <USART1_IRQHandler+0xfa> - - default: - rx_protocol_errors++; - 8000b2a: 4b0c ldr r3, [pc, #48] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000b2c: 681b ldr r3, [r3, #0] - 8000b2e: 1c5a adds r2, r3, #1 - 8000b30: 4b0a ldr r3, [pc, #40] ; (8000b5c <USART1_IRQHandler+0x11c>) - 8000b32: 601a str r2, [r3, #0] - } - return; - 8000b34: e004 b.n 8000b40 <USART1_IRQHandler+0x100> - break; - 8000b36: 46c0 nop ; (mov r8, r8) - 8000b38: e002 b.n 8000b40 <USART1_IRQHandler+0x100> - break; - 8000b3a: 46c0 nop ; (mov r8, r8) - return; - 8000b3c: e000 b.n 8000b40 <USART1_IRQHandler+0x100> - return; - 8000b3e: 46c0 nop ; (mov r8, r8) - } -} - 8000b40: 46bd mov sp, r7 - 8000b42: b006 add sp, #24 - 8000b44: bd80 pop {r7, pc} - 8000b46: 46c0 nop ; (mov r8, r8) - 8000b48: 40013800 .word 0x40013800 - 8000b4c: 2000013c .word 0x2000013c - 8000b50: 20000150 .word 0x20000150 - 8000b54: 20000148 .word 0x20000148 - 8000b58: 20000140 .word 0x20000140 - 8000b5c: 20000144 .word 0x20000144 - 8000b60: 20000198 .word 0x20000198 - 8000b64: 4002001c .word 0x4002001c - -08000b68 <usart_schedule_dma>: - - -void usart_schedule_dma() { - 8000b68: b580 push {r7, lr} - 8000b6a: b086 sub sp, #24 - 8000b6c: af00 add r7, sp, #0 - /* This function is only called when the DMA channel is disabled. This means we don't have to guard it in IRQ - * disables. */ - volatile struct dma_tx_buf *buf = &usart_tx_buf; - 8000b6e: 4b30 ldr r3, [pc, #192] ; (8000c30 <usart_schedule_dma+0xc8>) - 8000b70: 60bb str r3, [r7, #8] - - ssize_t next_start, next_idx; - if (buf->wraparound) { - 8000b72: 68bb ldr r3, [r7, #8] - 8000b74: 691b ldr r3, [r3, #16] - 8000b76: 2b00 cmp r3, #0 - 8000b78: d008 beq.n 8000b8c <usart_schedule_dma+0x24> - buf->wraparound = 0; - 8000b7a: 68bb ldr r3, [r7, #8] - 8000b7c: 2200 movs r2, #0 - 8000b7e: 611a str r2, [r3, #16] - next_idx = buf->cur_packet; - 8000b80: 68bb ldr r3, [r7, #8] - 8000b82: 689b ldr r3, [r3, #8] - 8000b84: 613b str r3, [r7, #16] - next_start = 0; - 8000b86: 2300 movs r3, #0 - 8000b88: 617b str r3, [r7, #20] - 8000b8a: e016 b.n 8000bba <usart_schedule_dma+0x52> - - } else if (buf->retransmit_rq) { - 8000b8c: 68bb ldr r3, [r7, #8] - 8000b8e: 68db ldr r3, [r3, #12] - 8000b90: 2b00 cmp r3, #0 - 8000b92: d009 beq.n 8000ba8 <usart_schedule_dma+0x40> - buf->retransmit_rq = 0; - 8000b94: 68bb ldr r3, [r7, #8] - 8000b96: 2200 movs r2, #0 - 8000b98: 60da str r2, [r3, #12] - next_idx = buf->cur_packet; - 8000b9a: 68bb ldr r3, [r7, #8] - 8000b9c: 689b ldr r3, [r3, #8] - 8000b9e: 613b str r3, [r7, #16] - next_start = buf->xfr_start; - 8000ba0: 68bb ldr r3, [r7, #8] - 8000ba2: 681b ldr r3, [r3, #0] - 8000ba4: 617b str r3, [r7, #20] - 8000ba6: e008 b.n 8000bba <usart_schedule_dma+0x52> - - } else { - next_idx = (buf->cur_packet + 1) % ARRAY_LEN(usart_tx_buf.packet_end); - 8000ba8: 68bb ldr r3, [r7, #8] - 8000baa: 689b ldr r3, [r3, #8] - 8000bac: 3301 adds r3, #1 - 8000bae: 2207 movs r2, #7 - 8000bb0: 4013 ands r3, r2 - 8000bb2: 613b str r3, [r7, #16] - next_start = buf->xfr_end; - 8000bb4: 68bb ldr r3, [r7, #8] - 8000bb6: 685b ldr r3, [r3, #4] - 8000bb8: 617b str r3, [r7, #20] - } - - ssize_t next_end = buf->packet_end[next_idx]; - 8000bba: 68ba ldr r2, [r7, #8] - 8000bbc: 693b ldr r3, [r7, #16] - 8000bbe: 3306 adds r3, #6 - 8000bc0: 009b lsls r3, r3, #2 - 8000bc2: 18d3 adds r3, r2, r3 - 8000bc4: 3304 adds r3, #4 - 8000bc6: 681b ldr r3, [r3, #0] - 8000bc8: 607b str r3, [r7, #4] - - /* Nothing to trasnmit */ - if (next_end == -1) - 8000bca: 687b ldr r3, [r7, #4] - 8000bcc: 3301 adds r3, #1 - 8000bce: d02b beq.n 8000c28 <usart_schedule_dma+0xc0> - return; - - ssize_t xfr_len; - if (next_end > next_start) /* no wraparound */ - 8000bd0: 687a ldr r2, [r7, #4] - 8000bd2: 697b ldr r3, [r7, #20] - 8000bd4: 429a cmp r2, r3 - 8000bd6: dd04 ble.n 8000be2 <usart_schedule_dma+0x7a> - xfr_len = next_end - next_start; - 8000bd8: 687a ldr r2, [r7, #4] - 8000bda: 697b ldr r3, [r7, #20] - 8000bdc: 1ad3 subs r3, r2, r3 - 8000bde: 60fb str r3, [r7, #12] - 8000be0: e004 b.n 8000bec <usart_schedule_dma+0x84> - else /* wraparound */ - xfr_len = sizeof(buf->data) - next_start; /* schedule transfer until end of buffer */ - 8000be2: 697b ldr r3, [r7, #20] - 8000be4: 2280 movs r2, #128 ; 0x80 - 8000be6: 0092 lsls r2, r2, #2 - 8000be8: 1ad3 subs r3, r2, r3 - 8000bea: 60fb str r3, [r7, #12] - - buf->xfr_start = next_start; - 8000bec: 68bb ldr r3, [r7, #8] - 8000bee: 697a ldr r2, [r7, #20] - 8000bf0: 601a str r2, [r3, #0] - buf->xfr_end = (next_start + xfr_len) % sizeof(buf->data); /* handle wraparound */ - 8000bf2: 697a ldr r2, [r7, #20] - 8000bf4: 68fb ldr r3, [r7, #12] - 8000bf6: 18d3 adds r3, r2, r3 - 8000bf8: 05db lsls r3, r3, #23 - 8000bfa: 0dda lsrs r2, r3, #23 - 8000bfc: 68bb ldr r3, [r7, #8] - 8000bfe: 605a str r2, [r3, #4] - buf->cur_packet = next_idx; - 8000c00: 68bb ldr r3, [r7, #8] - 8000c02: 693a ldr r2, [r7, #16] - 8000c04: 609a str r2, [r3, #8] - - /* initiate transmission of new buffer */ - DMA1_Channel2->CMAR = (uint32_t)(buf->data + next_start); - 8000c06: 68bb ldr r3, [r7, #8] - 8000c08: 333c adds r3, #60 ; 0x3c - 8000c0a: 001a movs r2, r3 - 8000c0c: 697b ldr r3, [r7, #20] - 8000c0e: 18d2 adds r2, r2, r3 - 8000c10: 4b08 ldr r3, [pc, #32] ; (8000c34 <usart_schedule_dma+0xcc>) - 8000c12: 60da str r2, [r3, #12] - DMA1_Channel2->CNDTR = xfr_len; - 8000c14: 4b07 ldr r3, [pc, #28] ; (8000c34 <usart_schedule_dma+0xcc>) - 8000c16: 68fa ldr r2, [r7, #12] - 8000c18: 605a str r2, [r3, #4] - DMA1_Channel2->CCR |= DMA_CCR_EN; - 8000c1a: 4b06 ldr r3, [pc, #24] ; (8000c34 <usart_schedule_dma+0xcc>) - 8000c1c: 681a ldr r2, [r3, #0] - 8000c1e: 4b05 ldr r3, [pc, #20] ; (8000c34 <usart_schedule_dma+0xcc>) - 8000c20: 2101 movs r1, #1 - 8000c22: 430a orrs r2, r1 - 8000c24: 601a str r2, [r3, #0] - 8000c26: e000 b.n 8000c2a <usart_schedule_dma+0xc2> - return; - 8000c28: 46c0 nop ; (mov r8, r8) -} - 8000c2a: 46bd mov sp, r7 - 8000c2c: b006 add sp, #24 - 8000c2e: bd80 pop {r7, pc} - 8000c30: 20000198 .word 0x20000198 - 8000c34: 4002001c .word 0x4002001c - -08000c38 <usart_ack_packet>: - -int usart_ack_packet(uint8_t idx) { - 8000c38: b580 push {r7, lr} - 8000c3a: b082 sub sp, #8 - 8000c3c: af00 add r7, sp, #0 - 8000c3e: 0002 movs r2, r0 - 8000c40: 1dfb adds r3, r7, #7 - 8000c42: 701a strb r2, [r3, #0] - if (idx > ARRAY_LEN(usart_tx_buf.packet_end)) - 8000c44: 1dfb adds r3, r7, #7 - 8000c46: 781b ldrb r3, [r3, #0] - 8000c48: 2b08 cmp r3, #8 - 8000c4a: d902 bls.n 8000c52 <usart_ack_packet+0x1a> - return -EINVAL; - 8000c4c: 2316 movs r3, #22 - 8000c4e: 425b negs r3, r3 - 8000c50: e01a b.n 8000c88 <usart_ack_packet+0x50> - - if (idx != usart_tx_buf.cur_packet) - 8000c52: 1dfb adds r3, r7, #7 - 8000c54: 781a ldrb r2, [r3, #0] - 8000c56: 4b0e ldr r3, [pc, #56] ; (8000c90 <usart_ack_packet+0x58>) - 8000c58: 689b ldr r3, [r3, #8] - 8000c5a: 429a cmp r2, r3 - 8000c5c: d002 beq.n 8000c64 <usart_ack_packet+0x2c> - return -EINVAL; - 8000c5e: 2316 movs r3, #22 - 8000c60: 425b negs r3, r3 - 8000c62: e011 b.n 8000c88 <usart_ack_packet+0x50> - - usart_tx_buf.packet_end[idx] = -1; - 8000c64: 1dfb adds r3, r7, #7 - 8000c66: 781b ldrb r3, [r3, #0] - 8000c68: 4a09 ldr r2, [pc, #36] ; (8000c90 <usart_ack_packet+0x58>) - 8000c6a: 3306 adds r3, #6 - 8000c6c: 009b lsls r3, r3, #2 - 8000c6e: 18d3 adds r3, r2, r3 - 8000c70: 3304 adds r3, #4 - 8000c72: 2201 movs r2, #1 - 8000c74: 4252 negs r2, r2 - 8000c76: 601a str r2, [r3, #0] - - /* If the DMA stream is idle right now, schedule the next transfer */ - if (!(DMA1_Channel2->CCR & DMA_CCR_EN)) - 8000c78: 4b06 ldr r3, [pc, #24] ; (8000c94 <usart_ack_packet+0x5c>) - 8000c7a: 681b ldr r3, [r3, #0] - 8000c7c: 2201 movs r2, #1 - 8000c7e: 4013 ands r3, r2 - 8000c80: d101 bne.n 8000c86 <usart_ack_packet+0x4e> - usart_schedule_dma(); - 8000c82: f7ff ff71 bl 8000b68 <usart_schedule_dma> - return 0; - 8000c86: 2300 movs r3, #0 -} - 8000c88: 0018 movs r0, r3 - 8000c8a: 46bd mov sp, r7 - 8000c8c: b002 add sp, #8 - 8000c8e: bd80 pop {r7, pc} - 8000c90: 20000198 .word 0x20000198 - 8000c94: 4002001c .word 0x4002001c - -08000c98 <usart_dma_fifo_push>: - -int usart_dma_fifo_push(volatile struct dma_tx_buf *buf, uint8_t c) { - 8000c98: b580 push {r7, lr} - 8000c9a: b082 sub sp, #8 - 8000c9c: af00 add r7, sp, #0 - 8000c9e: 6078 str r0, [r7, #4] - 8000ca0: 000a movs r2, r1 - 8000ca2: 1cfb adds r3, r7, #3 - 8000ca4: 701a strb r2, [r3, #0] - /* This function must be guarded by IRQ disable since the IRQ may schedule a new transfer and charge pos/start. */ - NVIC_DisableIRQ(DMA1_Channel2_3_IRQn); - 8000ca6: 200a movs r0, #10 - 8000ca8: f7ff fdce bl 8000848 <NVIC_DisableIRQ> - - if (buf->wr_pos == buf->xfr_start) { - 8000cac: 687b ldr r3, [r7, #4] - 8000cae: 695a ldr r2, [r3, #20] - 8000cb0: 687b ldr r3, [r7, #4] - 8000cb2: 681b ldr r3, [r3, #0] - 8000cb4: 429a cmp r2, r3 - 8000cb6: d105 bne.n 8000cc4 <usart_dma_fifo_push+0x2c> - NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); - 8000cb8: 200a movs r0, #10 - 8000cba: f7ff fdaf bl 800081c <NVIC_EnableIRQ> - return -EBUSY; - 8000cbe: 2310 movs r3, #16 - 8000cc0: 425b negs r3, r3 - 8000cc2: e013 b.n 8000cec <usart_dma_fifo_push+0x54> - } - - buf->data[buf->wr_pos] = c; - 8000cc4: 687b ldr r3, [r7, #4] - 8000cc6: 695b ldr r3, [r3, #20] - 8000cc8: 687a ldr r2, [r7, #4] - 8000cca: 213c movs r1, #60 ; 0x3c - 8000ccc: 18d3 adds r3, r2, r3 - 8000cce: 185b adds r3, r3, r1 - 8000cd0: 1cfa adds r2, r7, #3 - 8000cd2: 7812 ldrb r2, [r2, #0] - 8000cd4: 701a strb r2, [r3, #0] - buf->wr_pos = (buf->wr_pos + 1) % sizeof(buf->data); - 8000cd6: 687b ldr r3, [r7, #4] - 8000cd8: 695b ldr r3, [r3, #20] - 8000cda: 3301 adds r3, #1 - 8000cdc: 05db lsls r3, r3, #23 - 8000cde: 0dda lsrs r2, r3, #23 - 8000ce0: 687b ldr r3, [r7, #4] - 8000ce2: 615a str r2, [r3, #20] - - NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); - 8000ce4: 200a movs r0, #10 - 8000ce6: f7ff fd99 bl 800081c <NVIC_EnableIRQ> - return 0; - 8000cea: 2300 movs r3, #0 -} - 8000cec: 0018 movs r0, r3 - 8000cee: 46bd mov sp, r7 - 8000cf0: b002 add sp, #8 - 8000cf2: bd80 pop {r7, pc} - -08000cf4 <usart_putc>: - -int usart_putc(uint8_t c) { - 8000cf4: b580 push {r7, lr} - 8000cf6: b082 sub sp, #8 - 8000cf8: af00 add r7, sp, #0 - 8000cfa: 0002 movs r2, r0 - 8000cfc: 1dfb adds r3, r7, #7 - 8000cfe: 701a strb r2, [r3, #0] - /* push char to fifo, busy-loop if stalled to wait for USART to empty fifo via DMA */ - while (usart_dma_fifo_push(&usart_tx_buf, c) == -EBUSY) { - 8000d00: 46c0 nop ; (mov r8, r8) - 8000d02: 1dfb adds r3, r7, #7 - 8000d04: 781a ldrb r2, [r3, #0] - 8000d06: 4b06 ldr r3, [pc, #24] ; (8000d20 <usart_putc+0x2c>) - 8000d08: 0011 movs r1, r2 - 8000d0a: 0018 movs r0, r3 - 8000d0c: f7ff ffc4 bl 8000c98 <usart_dma_fifo_push> - 8000d10: 0003 movs r3, r0 - 8000d12: 3310 adds r3, #16 - 8000d14: d0f5 beq.n 8000d02 <usart_putc+0xe> - /* idle */ - } - return 0; - 8000d16: 2300 movs r3, #0 -} - 8000d18: 0018 movs r0, r3 - 8000d1a: 46bd mov sp, r7 - 8000d1c: b002 add sp, #8 - 8000d1e: bd80 pop {r7, pc} - 8000d20: 20000198 .word 0x20000198 - -08000d24 <usart_putc_nonblocking>: - -int usart_putc_nonblocking(uint8_t c) { - 8000d24: b580 push {r7, lr} - 8000d26: b082 sub sp, #8 - 8000d28: af00 add r7, sp, #0 - 8000d2a: 0002 movs r2, r0 - 8000d2c: 1dfb adds r3, r7, #7 - 8000d2e: 701a strb r2, [r3, #0] - return usart_dma_fifo_push(&usart_tx_buf, c); - 8000d30: 1dfb adds r3, r7, #7 - 8000d32: 781a ldrb r2, [r3, #0] - 8000d34: 4b04 ldr r3, [pc, #16] ; (8000d48 <usart_putc_nonblocking+0x24>) - 8000d36: 0011 movs r1, r2 - 8000d38: 0018 movs r0, r3 - 8000d3a: f7ff ffad bl 8000c98 <usart_dma_fifo_push> - 8000d3e: 0003 movs r3, r0 -} - 8000d40: 0018 movs r0, r3 - 8000d42: 46bd mov sp, r7 - 8000d44: b002 add sp, #8 - 8000d46: bd80 pop {r7, pc} - 8000d48: 20000198 .word 0x20000198 - -08000d4c <DMA1_Channel2_3_IRQHandler>: - - -void DMA1_Channel2_3_IRQHandler(void) { - 8000d4c: b580 push {r7, lr} - 8000d4e: af00 add r7, sp, #0 - /* Transfer complete */ - DMA1->IFCR |= DMA_IFCR_CTCIF2; - 8000d50: 4b0c ldr r3, [pc, #48] ; (8000d84 <DMA1_Channel2_3_IRQHandler+0x38>) - 8000d52: 685a ldr r2, [r3, #4] - 8000d54: 4b0b ldr r3, [pc, #44] ; (8000d84 <DMA1_Channel2_3_IRQHandler+0x38>) - 8000d56: 2120 movs r1, #32 - 8000d58: 430a orrs r2, r1 - 8000d5a: 605a str r2, [r3, #4] - - DMA1_Channel2->CCR &= ~DMA_CCR_EN; - 8000d5c: 4b0a ldr r3, [pc, #40] ; (8000d88 <DMA1_Channel2_3_IRQHandler+0x3c>) - 8000d5e: 681a ldr r2, [r3, #0] - 8000d60: 4b09 ldr r3, [pc, #36] ; (8000d88 <DMA1_Channel2_3_IRQHandler+0x3c>) - 8000d62: 2101 movs r1, #1 - 8000d64: 438a bics r2, r1 - 8000d66: 601a str r2, [r3, #0] - if (usart_tx_buf.retransmit_rq || usart_tx_buf.wraparound) - 8000d68: 4b08 ldr r3, [pc, #32] ; (8000d8c <DMA1_Channel2_3_IRQHandler+0x40>) - 8000d6a: 68db ldr r3, [r3, #12] - 8000d6c: 2b00 cmp r3, #0 - 8000d6e: d103 bne.n 8000d78 <DMA1_Channel2_3_IRQHandler+0x2c> - 8000d70: 4b06 ldr r3, [pc, #24] ; (8000d8c <DMA1_Channel2_3_IRQHandler+0x40>) - 8000d72: 691b ldr r3, [r3, #16] - 8000d74: 2b00 cmp r3, #0 - 8000d76: d001 beq.n 8000d7c <DMA1_Channel2_3_IRQHandler+0x30> - usart_schedule_dma(); - 8000d78: f7ff fef6 bl 8000b68 <usart_schedule_dma> -} - 8000d7c: 46c0 nop ; (mov r8, r8) - 8000d7e: 46bd mov sp, r7 - 8000d80: bd80 pop {r7, pc} - 8000d82: 46c0 nop ; (mov r8, r8) - 8000d84: 40020000 .word 0x40020000 - 8000d88: 4002001c .word 0x4002001c - 8000d8c: 20000198 .word 0x20000198 - -08000d90 <usart_send_packet_nonblocking>: - -/* len is the packet length including headers */ -int usart_send_packet_nonblocking(struct ll_pkt *pkt, size_t pkt_len) { - 8000d90: b590 push {r4, r7, lr} - 8000d92: b085 sub sp, #20 - 8000d94: af00 add r7, sp, #0 - 8000d96: 6078 str r0, [r7, #4] - 8000d98: 6039 str r1, [r7, #0] - - if (usart_tx_buf.packet_end[usart_tx_buf.wr_idx] != -1) { - 8000d9a: 4b41 ldr r3, [pc, #260] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000d9c: 699b ldr r3, [r3, #24] - 8000d9e: 4a40 ldr r2, [pc, #256] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000da0: 3306 adds r3, #6 - 8000da2: 009b lsls r3, r3, #2 - 8000da4: 18d3 adds r3, r2, r3 - 8000da6: 3304 adds r3, #4 - 8000da8: 681b ldr r3, [r3, #0] - 8000daa: 3301 adds r3, #1 - 8000dac: d007 beq.n 8000dbe <usart_send_packet_nonblocking+0x2e> - /* Find a free slot for this packet */ - tx_overruns++; - 8000dae: 4b3d ldr r3, [pc, #244] ; (8000ea4 <usart_send_packet_nonblocking+0x114>) - 8000db0: 681b ldr r3, [r3, #0] - 8000db2: 1c5a adds r2, r3, #1 - 8000db4: 4b3b ldr r3, [pc, #236] ; (8000ea4 <usart_send_packet_nonblocking+0x114>) - 8000db6: 601a str r2, [r3, #0] - return -EBUSY; - 8000db8: 2310 movs r3, #16 - 8000dba: 425b negs r3, r3 - 8000dbc: e06c b.n 8000e98 <usart_send_packet_nonblocking+0x108> - } - - pkt->pid = usart_tx_buf.wr_idx; - 8000dbe: 4b38 ldr r3, [pc, #224] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000dc0: 699b ldr r3, [r3, #24] - 8000dc2: b2da uxtb r2, r3 - 8000dc4: 687b ldr r3, [r7, #4] - 8000dc6: 711a strb r2, [r3, #4] - pkt->_pad = 0; - 8000dc8: 687b ldr r3, [r7, #4] - 8000dca: 2200 movs r2, #0 - 8000dcc: 715a strb r2, [r3, #5] - - /* make the value this wonky-ass CRC implementation produces match zlib etc. */ - CRC->CR = CRC_CR_REV_OUT | (1<<CRC_CR_REV_IN_Pos) | CRC_CR_RESET; - 8000dce: 4b36 ldr r3, [pc, #216] ; (8000ea8 <usart_send_packet_nonblocking+0x118>) - 8000dd0: 22a1 movs r2, #161 ; 0xa1 - 8000dd2: 609a str r2, [r3, #8] - for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++) - 8000dd4: 2304 movs r3, #4 - 8000dd6: 60fb str r3, [r7, #12] - 8000dd8: e008 b.n 8000dec <usart_send_packet_nonblocking+0x5c> - CRC->DR = ((uint8_t *)pkt)[i]; - 8000dda: 687a ldr r2, [r7, #4] - 8000ddc: 68fb ldr r3, [r7, #12] - 8000dde: 18d3 adds r3, r2, r3 - 8000de0: 781a ldrb r2, [r3, #0] - 8000de2: 4b31 ldr r3, [pc, #196] ; (8000ea8 <usart_send_packet_nonblocking+0x118>) - 8000de4: 601a str r2, [r3, #0] - for (size_t i=offsetof(struct ll_pkt, pid); i<pkt_len; i++) - 8000de6: 68fb ldr r3, [r7, #12] - 8000de8: 3301 adds r3, #1 - 8000dea: 60fb str r3, [r7, #12] - 8000dec: 68fa ldr r2, [r7, #12] - 8000dee: 683b ldr r3, [r7, #0] - 8000df0: 429a cmp r2, r3 - 8000df2: d3f2 bcc.n 8000dda <usart_send_packet_nonblocking+0x4a> - - pkt->crc32 = ~CRC->DR; - 8000df4: 4b2c ldr r3, [pc, #176] ; (8000ea8 <usart_send_packet_nonblocking+0x118>) - 8000df6: 681b ldr r3, [r3, #0] - 8000df8: 43da mvns r2, r3 - 8000dfa: 687b ldr r3, [r7, #4] - 8000dfc: 21ff movs r1, #255 ; 0xff - 8000dfe: 4011 ands r1, r2 - 8000e00: 000c movs r4, r1 - 8000e02: 7819 ldrb r1, [r3, #0] - 8000e04: 2000 movs r0, #0 - 8000e06: 4001 ands r1, r0 - 8000e08: 1c08 adds r0, r1, #0 - 8000e0a: 1c21 adds r1, r4, #0 - 8000e0c: 4301 orrs r1, r0 - 8000e0e: 7019 strb r1, [r3, #0] - 8000e10: 0a11 lsrs r1, r2, #8 - 8000e12: 20ff movs r0, #255 ; 0xff - 8000e14: 4001 ands r1, r0 - 8000e16: 000c movs r4, r1 - 8000e18: 7859 ldrb r1, [r3, #1] - 8000e1a: 2000 movs r0, #0 - 8000e1c: 4001 ands r1, r0 - 8000e1e: 1c08 adds r0, r1, #0 - 8000e20: 1c21 adds r1, r4, #0 - 8000e22: 4301 orrs r1, r0 - 8000e24: 7059 strb r1, [r3, #1] - 8000e26: 0c11 lsrs r1, r2, #16 - 8000e28: 20ff movs r0, #255 ; 0xff - 8000e2a: 4001 ands r1, r0 - 8000e2c: 000c movs r4, r1 - 8000e2e: 7899 ldrb r1, [r3, #2] - 8000e30: 2000 movs r0, #0 - 8000e32: 4001 ands r1, r0 - 8000e34: 1c08 adds r0, r1, #0 - 8000e36: 1c21 adds r1, r4, #0 - 8000e38: 4301 orrs r1, r0 - 8000e3a: 7099 strb r1, [r3, #2] - 8000e3c: 0e10 lsrs r0, r2, #24 - 8000e3e: 78da ldrb r2, [r3, #3] - 8000e40: 2100 movs r1, #0 - 8000e42: 400a ands r2, r1 - 8000e44: 1c11 adds r1, r2, #0 - 8000e46: 1c02 adds r2, r0, #0 - 8000e48: 430a orrs r2, r1 - 8000e4a: 70da strb r2, [r3, #3] - - int rc = cobs_encode_usart((int (*)(char))usart_putc_nonblocking, (char *)pkt, pkt_len); - 8000e4c: 683a ldr r2, [r7, #0] - 8000e4e: 6879 ldr r1, [r7, #4] - 8000e50: 4b16 ldr r3, [pc, #88] ; (8000eac <usart_send_packet_nonblocking+0x11c>) - 8000e52: 0018 movs r0, r3 - 8000e54: f000 f82e bl 8000eb4 <cobs_encode_usart> - 8000e58: 0003 movs r3, r0 - 8000e5a: 60bb str r3, [r7, #8] - if (rc) - 8000e5c: 68bb ldr r3, [r7, #8] - 8000e5e: 2b00 cmp r3, #0 - 8000e60: d001 beq.n 8000e66 <usart_send_packet_nonblocking+0xd6> - return rc; - 8000e62: 68bb ldr r3, [r7, #8] - 8000e64: e018 b.n 8000e98 <usart_send_packet_nonblocking+0x108> - - usart_tx_buf.packet_end[usart_tx_buf.wr_idx] = usart_tx_buf.wr_pos; - 8000e66: 4b0e ldr r3, [pc, #56] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000e68: 6998 ldr r0, [r3, #24] - 8000e6a: 4b0d ldr r3, [pc, #52] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000e6c: 695a ldr r2, [r3, #20] - 8000e6e: 490c ldr r1, [pc, #48] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000e70: 1d83 adds r3, r0, #6 - 8000e72: 009b lsls r3, r3, #2 - 8000e74: 18cb adds r3, r1, r3 - 8000e76: 3304 adds r3, #4 - 8000e78: 601a str r2, [r3, #0] - usart_tx_buf.wr_idx = (usart_tx_buf.wr_idx + 1) % ARRAY_LEN(usart_tx_buf.packet_end); - 8000e7a: 4b09 ldr r3, [pc, #36] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000e7c: 699b ldr r3, [r3, #24] - 8000e7e: 3301 adds r3, #1 - 8000e80: 2207 movs r2, #7 - 8000e82: 401a ands r2, r3 - 8000e84: 4b06 ldr r3, [pc, #24] ; (8000ea0 <usart_send_packet_nonblocking+0x110>) - 8000e86: 619a str r2, [r3, #24] - - if (!(DMA1_Channel2->CCR & DMA_CCR_EN)) - 8000e88: 4b09 ldr r3, [pc, #36] ; (8000eb0 <usart_send_packet_nonblocking+0x120>) - 8000e8a: 681b ldr r3, [r3, #0] - 8000e8c: 2201 movs r2, #1 - 8000e8e: 4013 ands r3, r2 - 8000e90: d101 bne.n 8000e96 <usart_send_packet_nonblocking+0x106> - usart_schedule_dma(); - 8000e92: f7ff fe69 bl 8000b68 <usart_schedule_dma> - return 0; - 8000e96: 2300 movs r3, #0 -} - 8000e98: 0018 movs r0, r3 - 8000e9a: 46bd mov sp, r7 - 8000e9c: b005 add sp, #20 - 8000e9e: bd90 pop {r4, r7, pc} - 8000ea0: 20000198 .word 0x20000198 - 8000ea4: 20000138 .word 0x20000138 - 8000ea8: 40023000 .word 0x40023000 - 8000eac: 08000d25 .word 0x08000d25 - 8000eb0: 4002001c .word 0x4002001c - -08000eb4 <cobs_encode_usart>: - -#include "serial.h" -#include "cobs.h" - -int cobs_encode_usart(int (*output)(char), char *src, size_t srclen) { - 8000eb4: b580 push {r7, lr} - 8000eb6: b08a sub sp, #40 ; 0x28 - 8000eb8: af00 add r7, sp, #0 - 8000eba: 60f8 str r0, [r7, #12] - 8000ebc: 60b9 str r1, [r7, #8] - 8000ebe: 607a str r2, [r7, #4] - if (srclen > 254) - 8000ec0: 687b ldr r3, [r7, #4] - 8000ec2: 2bfe cmp r3, #254 ; 0xfe - 8000ec4: d902 bls.n 8000ecc <cobs_encode_usart+0x18> - return -1; - 8000ec6: 2301 movs r3, #1 - 8000ec8: 425b negs r3, r3 - 8000eca: e04e b.n 8000f6a <cobs_encode_usart+0xb6> - - size_t p = 0; - 8000ecc: 2300 movs r3, #0 - 8000ece: 627b str r3, [r7, #36] ; 0x24 - while (p <= srclen) { - 8000ed0: e03c b.n 8000f4c <cobs_encode_usart+0x98> - - char val; - if (p != 0 && src[p-1] != 0) { - 8000ed2: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000ed4: 2b00 cmp r3, #0 - 8000ed6: d00f beq.n 8000ef8 <cobs_encode_usart+0x44> - 8000ed8: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000eda: 3b01 subs r3, #1 - 8000edc: 68ba ldr r2, [r7, #8] - 8000ede: 18d3 adds r3, r2, r3 - 8000ee0: 781b ldrb r3, [r3, #0] - 8000ee2: 2b00 cmp r3, #0 - 8000ee4: d008 beq.n 8000ef8 <cobs_encode_usart+0x44> - val = src[p-1]; - 8000ee6: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000ee8: 3b01 subs r3, #1 - 8000eea: 68ba ldr r2, [r7, #8] - 8000eec: 18d2 adds r2, r2, r3 - 8000eee: 2323 movs r3, #35 ; 0x23 - 8000ef0: 18fb adds r3, r7, r3 - 8000ef2: 7812 ldrb r2, [r2, #0] - 8000ef4: 701a strb r2, [r3, #0] - 8000ef6: e019 b.n 8000f2c <cobs_encode_usart+0x78> - - } else { - size_t q = p; - 8000ef8: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000efa: 61fb str r3, [r7, #28] - while (q < srclen && src[q] != 0) - 8000efc: e002 b.n 8000f04 <cobs_encode_usart+0x50> - q++; - 8000efe: 69fb ldr r3, [r7, #28] - 8000f00: 3301 adds r3, #1 - 8000f02: 61fb str r3, [r7, #28] - while (q < srclen && src[q] != 0) - 8000f04: 69fa ldr r2, [r7, #28] - 8000f06: 687b ldr r3, [r7, #4] - 8000f08: 429a cmp r2, r3 - 8000f0a: d205 bcs.n 8000f18 <cobs_encode_usart+0x64> - 8000f0c: 68ba ldr r2, [r7, #8] - 8000f0e: 69fb ldr r3, [r7, #28] - 8000f10: 18d3 adds r3, r2, r3 - 8000f12: 781b ldrb r3, [r3, #0] - 8000f14: 2b00 cmp r3, #0 - 8000f16: d1f2 bne.n 8000efe <cobs_encode_usart+0x4a> - val = (char)q-p+1; - 8000f18: 69fb ldr r3, [r7, #28] - 8000f1a: b2da uxtb r2, r3 - 8000f1c: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000f1e: b2db uxtb r3, r3 - 8000f20: 1ad3 subs r3, r2, r3 - 8000f22: b2da uxtb r2, r3 - 8000f24: 2323 movs r3, #35 ; 0x23 - 8000f26: 18fb adds r3, r7, r3 - 8000f28: 3201 adds r2, #1 - 8000f2a: 701a strb r2, [r3, #0] - } - - int rv = output(val); - 8000f2c: 2323 movs r3, #35 ; 0x23 - 8000f2e: 18fb adds r3, r7, r3 - 8000f30: 781a ldrb r2, [r3, #0] - 8000f32: 68fb ldr r3, [r7, #12] - 8000f34: 0010 movs r0, r2 - 8000f36: 4798 blx r3 - 8000f38: 0003 movs r3, r0 - 8000f3a: 617b str r3, [r7, #20] - if (rv) - 8000f3c: 697b ldr r3, [r7, #20] - 8000f3e: 2b00 cmp r3, #0 - 8000f40: d001 beq.n 8000f46 <cobs_encode_usart+0x92> - return rv; - 8000f42: 697b ldr r3, [r7, #20] - 8000f44: e011 b.n 8000f6a <cobs_encode_usart+0xb6> - p++; - 8000f46: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000f48: 3301 adds r3, #1 - 8000f4a: 627b str r3, [r7, #36] ; 0x24 - while (p <= srclen) { - 8000f4c: 6a7a ldr r2, [r7, #36] ; 0x24 - 8000f4e: 687b ldr r3, [r7, #4] - 8000f50: 429a cmp r2, r3 - 8000f52: d9be bls.n 8000ed2 <cobs_encode_usart+0x1e> - } - - int rv = output(0); - 8000f54: 68fb ldr r3, [r7, #12] - 8000f56: 2000 movs r0, #0 - 8000f58: 4798 blx r3 - 8000f5a: 0003 movs r3, r0 - 8000f5c: 61bb str r3, [r7, #24] - if (rv) - 8000f5e: 69bb ldr r3, [r7, #24] - 8000f60: 2b00 cmp r3, #0 - 8000f62: d001 beq.n 8000f68 <cobs_encode_usart+0xb4> - return rv; - 8000f64: 69bb ldr r3, [r7, #24] - 8000f66: e000 b.n 8000f6a <cobs_encode_usart+0xb6> - - return 0; - 8000f68: 2300 movs r3, #0 -} - 8000f6a: 0018 movs r0, r3 - 8000f6c: 46bd mov sp, r7 - 8000f6e: b00a add sp, #40 ; 0x28 - 8000f70: bd80 pop {r7, pc} - -08000f72 <cobs_decode>: - @ ensures \result == -1; - @ - @ complete behaviors; - @ disjoint behaviors; - @*/ -ssize_t cobs_decode(char *dst, size_t dstlen, char *src, size_t srclen) { - 8000f72: b580 push {r7, lr} - 8000f74: b088 sub sp, #32 - 8000f76: af00 add r7, sp, #0 - 8000f78: 60f8 str r0, [r7, #12] - 8000f7a: 60b9 str r1, [r7, #8] - 8000f7c: 607a str r2, [r7, #4] - 8000f7e: 603b str r3, [r7, #0] - if (dstlen > 65535 || srclen > 65535) - 8000f80: 68ba ldr r2, [r7, #8] - 8000f82: 2380 movs r3, #128 ; 0x80 - 8000f84: 025b lsls r3, r3, #9 - 8000f86: 429a cmp r2, r3 - 8000f88: d204 bcs.n 8000f94 <cobs_decode+0x22> - 8000f8a: 683a ldr r2, [r7, #0] - 8000f8c: 2380 movs r3, #128 ; 0x80 - 8000f8e: 025b lsls r3, r3, #9 - 8000f90: 429a cmp r2, r3 - 8000f92: d302 bcc.n 8000f9a <cobs_decode+0x28> - return -1; - 8000f94: 2301 movs r3, #1 - 8000f96: 425b negs r3, r3 - 8000f98: e052 b.n 8001040 <cobs_decode+0xce> - - if (srclen < 1) - 8000f9a: 683b ldr r3, [r7, #0] - 8000f9c: 2b00 cmp r3, #0 - 8000f9e: d102 bne.n 8000fa6 <cobs_decode+0x34> - return -1; - 8000fa0: 2301 movs r3, #1 - 8000fa2: 425b negs r3, r3 - 8000fa4: e04c b.n 8001040 <cobs_decode+0xce> - - if (dstlen < srclen) - 8000fa6: 68ba ldr r2, [r7, #8] - 8000fa8: 683b ldr r3, [r7, #0] - 8000faa: 429a cmp r2, r3 - 8000fac: d202 bcs.n 8000fb4 <cobs_decode+0x42> - return -1; - 8000fae: 2301 movs r3, #1 - 8000fb0: 425b negs r3, r3 - 8000fb2: e045 b.n 8001040 <cobs_decode+0xce> - - size_t p = 1; - 8000fb4: 2301 movs r3, #1 - 8000fb6: 61fb str r3, [r7, #28] - size_t c = (unsigned char)src[0]; - 8000fb8: 687b ldr r3, [r7, #4] - 8000fba: 781b ldrb r3, [r3, #0] - 8000fbc: 61bb str r3, [r7, #24] - //@ assert 0 <= c < 256; - //@ assert 0 <= c; - //@ assert c < 256; - if (c == 0) - 8000fbe: 69bb ldr r3, [r7, #24] - 8000fc0: 2b00 cmp r3, #0 - 8000fc2: d124 bne.n 800100e <cobs_decode+0x9c> - return -2; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ - 8000fc4: 2302 movs r3, #2 - 8000fc6: 425b negs r3, r3 - 8000fc8: e03a b.n 8001040 <cobs_decode+0xce> - @ loop assigns dst[0..dstlen-1], p, c; - @ loop variant srclen-p; - @*/ - while (p < srclen && src[p]) { - char val; - c--; - 8000fca: 69bb ldr r3, [r7, #24] - 8000fcc: 3b01 subs r3, #1 - 8000fce: 61bb str r3, [r7, #24] - - //@ assert src[p] != 0; - if (c == 0) { - 8000fd0: 69bb ldr r3, [r7, #24] - 8000fd2: 2b00 cmp r3, #0 - 8000fd4: d109 bne.n 8000fea <cobs_decode+0x78> - c = (unsigned char)src[p]; - 8000fd6: 687a ldr r2, [r7, #4] - 8000fd8: 69fb ldr r3, [r7, #28] - 8000fda: 18d3 adds r3, r2, r3 - 8000fdc: 781b ldrb r3, [r3, #0] - 8000fde: 61bb str r3, [r7, #24] - val = 0; - 8000fe0: 2317 movs r3, #23 - 8000fe2: 18fb adds r3, r7, r3 - 8000fe4: 2200 movs r2, #0 - 8000fe6: 701a strb r2, [r3, #0] - 8000fe8: e006 b.n 8000ff8 <cobs_decode+0x86> - } else { - val = src[p]; - 8000fea: 687a ldr r2, [r7, #4] - 8000fec: 69fb ldr r3, [r7, #28] - 8000fee: 18d2 adds r2, r2, r3 - 8000ff0: 2317 movs r3, #23 - 8000ff2: 18fb adds r3, r7, r3 - 8000ff4: 7812 ldrb r2, [r2, #0] - 8000ff6: 701a strb r2, [r3, #0] - } - - //@ assert 0 <= p-1 <= dstlen-1; - dst[p-1] = val; - 8000ff8: 69fb ldr r3, [r7, #28] - 8000ffa: 3b01 subs r3, #1 - 8000ffc: 68fa ldr r2, [r7, #12] - 8000ffe: 18d3 adds r3, r2, r3 - 8001000: 2217 movs r2, #23 - 8001002: 18ba adds r2, r7, r2 - 8001004: 7812 ldrb r2, [r2, #0] - 8001006: 701a strb r2, [r3, #0] - p++; - 8001008: 69fb ldr r3, [r7, #28] - 800100a: 3301 adds r3, #1 - 800100c: 61fb str r3, [r7, #28] - while (p < srclen && src[p]) { - 800100e: 69fa ldr r2, [r7, #28] - 8001010: 683b ldr r3, [r7, #0] - 8001012: 429a cmp r2, r3 - 8001014: d205 bcs.n 8001022 <cobs_decode+0xb0> - 8001016: 687a ldr r2, [r7, #4] - 8001018: 69fb ldr r3, [r7, #28] - 800101a: 18d3 adds r3, r2, r3 - 800101c: 781b ldrb r3, [r3, #0] - 800101e: 2b00 cmp r3, #0 - 8001020: d1d3 bne.n 8000fca <cobs_decode+0x58> - } - - if (p == srclen) - 8001022: 69fa ldr r2, [r7, #28] - 8001024: 683b ldr r3, [r7, #0] - 8001026: 429a cmp r2, r3 - 8001028: d102 bne.n 8001030 <cobs_decode+0xbe> - return -2; /* Invalid framing. The terminating null byte should always be present in the input buffer. */ - 800102a: 2302 movs r3, #2 - 800102c: 425b negs r3, r3 - 800102e: e007 b.n 8001040 <cobs_decode+0xce> - - if (c != 1) - 8001030: 69bb ldr r3, [r7, #24] - 8001032: 2b01 cmp r3, #1 - 8001034: d002 beq.n 800103c <cobs_decode+0xca> - return -3; /* Invalid framing. The skip counter does not hit the end of the frame. */ - 8001036: 2303 movs r3, #3 - 8001038: 425b negs r3, r3 - 800103a: e001 b.n 8001040 <cobs_decode+0xce> - - //@ assert 0 < p <= srclen <= 65535; - //@ assert src[p] == 0; - //@ assert \forall integer i; 1 <= i < p ==> src[i] != 0; - return p-1; - 800103c: 69fb ldr r3, [r7, #28] - 800103e: 3b01 subs r3, #1 -} - 8001040: 0018 movs r0, r3 - 8001042: 46bd mov sp, r7 - 8001044: b008 add sp, #32 - 8001046: bd80 pop {r7, pc} - -08001048 <cobs_decode_incremental_initialize>: - -void cobs_decode_incremental_initialize(struct cobs_decode_state *state) { - 8001048: b580 push {r7, lr} - 800104a: b082 sub sp, #8 - 800104c: af00 add r7, sp, #0 - 800104e: 6078 str r0, [r7, #4] - state->p = 0; - 8001050: 687b ldr r3, [r7, #4] - 8001052: 2200 movs r2, #0 - 8001054: 601a str r2, [r3, #0] - state->c = 0; - 8001056: 687b ldr r3, [r7, #4] - 8001058: 2200 movs r2, #0 - 800105a: 605a str r2, [r3, #4] -} - 800105c: 46c0 nop ; (mov r8, r8) - 800105e: 46bd mov sp, r7 - 8001060: b002 add sp, #8 - 8001062: bd80 pop {r7, pc} - -08001064 <cobs_decode_incremental>: - -int cobs_decode_incremental(struct cobs_decode_state *state, char *dst, size_t dstlen, char src) { - 8001064: b580 push {r7, lr} - 8001066: b088 sub sp, #32 - 8001068: af00 add r7, sp, #0 - 800106a: 60f8 str r0, [r7, #12] - 800106c: 60b9 str r1, [r7, #8] - 800106e: 607a str r2, [r7, #4] - 8001070: 001a movs r2, r3 - 8001072: 1cfb adds r3, r7, #3 - 8001074: 701a strb r2, [r3, #0] - if (state->p == 0) { - 8001076: 68fb ldr r3, [r7, #12] - 8001078: 681b ldr r3, [r3, #0] - 800107a: 2b00 cmp r3, #0 - 800107c: d10e bne.n 800109c <cobs_decode_incremental+0x38> - if (src == 0) - 800107e: 1cfb adds r3, r7, #3 - 8001080: 781b ldrb r3, [r3, #0] - 8001082: 2b00 cmp r3, #0 - 8001084: d054 beq.n 8001130 <cobs_decode_incremental+0xcc> - goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ - state->c = (unsigned char)src; - 8001086: 1cfb adds r3, r7, #3 - 8001088: 781a ldrb r2, [r3, #0] - 800108a: 68fb ldr r3, [r7, #12] - 800108c: 605a str r2, [r3, #4] - state->p++; - 800108e: 68fb ldr r3, [r7, #12] - 8001090: 681b ldr r3, [r3, #0] - 8001092: 1c5a adds r2, r3, #1 - 8001094: 68fb ldr r3, [r7, #12] - 8001096: 601a str r2, [r3, #0] - return 0; - 8001098: 2300 movs r3, #0 - 800109a: e050 b.n 800113e <cobs_decode_incremental+0xda> - } - - if (!src) { - 800109c: 1cfb adds r3, r7, #3 - 800109e: 781b ldrb r3, [r3, #0] - 80010a0: 2b00 cmp r3, #0 - 80010a2: d10d bne.n 80010c0 <cobs_decode_incremental+0x5c> - if (state->c != 1) - 80010a4: 68fb ldr r3, [r7, #12] - 80010a6: 685b ldr r3, [r3, #4] - 80010a8: 2b01 cmp r3, #1 - 80010aa: d139 bne.n 8001120 <cobs_decode_incremental+0xbc> - goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */ - int rv = state->p-1; - 80010ac: 68fb ldr r3, [r7, #12] - 80010ae: 681b ldr r3, [r3, #0] - 80010b0: 3b01 subs r3, #1 - 80010b2: 617b str r3, [r7, #20] - cobs_decode_incremental_initialize(state); - 80010b4: 68fb ldr r3, [r7, #12] - 80010b6: 0018 movs r0, r3 - 80010b8: f7ff ffc6 bl 8001048 <cobs_decode_incremental_initialize> - return rv; - 80010bc: 697b ldr r3, [r7, #20] - 80010be: e03e b.n 800113e <cobs_decode_incremental+0xda> - } - - char val; - state->c--; - 80010c0: 68fb ldr r3, [r7, #12] - 80010c2: 685b ldr r3, [r3, #4] - 80010c4: 1e5a subs r2, r3, #1 - 80010c6: 68fb ldr r3, [r7, #12] - 80010c8: 605a str r2, [r3, #4] - - if (state->c == 0) { - 80010ca: 68fb ldr r3, [r7, #12] - 80010cc: 685b ldr r3, [r3, #4] - 80010ce: 2b00 cmp r3, #0 - 80010d0: d108 bne.n 80010e4 <cobs_decode_incremental+0x80> - state->c = (unsigned char)src; - 80010d2: 1cfb adds r3, r7, #3 - 80010d4: 781a ldrb r2, [r3, #0] - 80010d6: 68fb ldr r3, [r7, #12] - 80010d8: 605a str r2, [r3, #4] - val = 0; - 80010da: 231f movs r3, #31 - 80010dc: 18fb adds r3, r7, r3 - 80010de: 2200 movs r2, #0 - 80010e0: 701a strb r2, [r3, #0] - 80010e2: e004 b.n 80010ee <cobs_decode_incremental+0x8a> - } else { - val = src; - 80010e4: 231f movs r3, #31 - 80010e6: 18fb adds r3, r7, r3 - 80010e8: 1cfa adds r2, r7, #3 - 80010ea: 7812 ldrb r2, [r2, #0] - 80010ec: 701a strb r2, [r3, #0] - } - - size_t pos = state->p-1; - 80010ee: 68fb ldr r3, [r7, #12] - 80010f0: 681b ldr r3, [r3, #0] - 80010f2: 3b01 subs r3, #1 - 80010f4: 61bb str r3, [r7, #24] - if (pos >= dstlen) - 80010f6: 69ba ldr r2, [r7, #24] - 80010f8: 687b ldr r3, [r7, #4] - 80010fa: 429a cmp r2, r3 - 80010fc: d302 bcc.n 8001104 <cobs_decode_incremental+0xa0> - return -2; /* output buffer too small */ - 80010fe: 2302 movs r3, #2 - 8001100: 425b negs r3, r3 - 8001102: e01c b.n 800113e <cobs_decode_incremental+0xda> - dst[pos] = val; - 8001104: 68ba ldr r2, [r7, #8] - 8001106: 69bb ldr r3, [r7, #24] - 8001108: 18d3 adds r3, r2, r3 - 800110a: 221f movs r2, #31 - 800110c: 18ba adds r2, r7, r2 - 800110e: 7812 ldrb r2, [r2, #0] - 8001110: 701a strb r2, [r3, #0] - state->p++; - 8001112: 68fb ldr r3, [r7, #12] - 8001114: 681b ldr r3, [r3, #0] - 8001116: 1c5a adds r2, r3, #1 - 8001118: 68fb ldr r3, [r7, #12] - 800111a: 601a str r2, [r3, #0] - return 0; - 800111c: 2300 movs r3, #0 - 800111e: e00e b.n 800113e <cobs_decode_incremental+0xda> - goto errout; /* Invalid framing. The skip counter does not hit the end of the frame. */ - 8001120: 46c0 nop ; (mov r8, r8) - -errout: - cobs_decode_incremental_initialize(state); - 8001122: 68fb ldr r3, [r7, #12] - 8001124: 0018 movs r0, r3 - 8001126: f7ff ff8f bl 8001048 <cobs_decode_incremental_initialize> - return -1; - 800112a: 2301 movs r3, #1 - 800112c: 425b negs r3, r3 - 800112e: e006 b.n 800113e <cobs_decode_incremental+0xda> - goto empty_errout; /* invalid framing. An empty frame would be [...] 00 01 00, not [...] 00 00 */ - 8001130: 46c0 nop ; (mov r8, r8) - -empty_errout: - cobs_decode_incremental_initialize(state); - 8001132: 68fb ldr r3, [r7, #12] - 8001134: 0018 movs r0, r3 - 8001136: f7ff ff87 bl 8001048 <cobs_decode_incremental_initialize> - return -3; - 800113a: 2303 movs r3, #3 - 800113c: 425b negs r3, r3 -} - 800113e: 0018 movs r0, r3 - 8001140: 46bd mov sp, r7 - 8001142: b008 add sp, #32 - 8001144: bd80 pop {r7, pc} - 8001146: 1c3c .short 0x1c3c - 8001148: 00000800 .word 0x00000800 - 800114c: 00942000 .word 0x00942000 - 8001150: 00942000 .word 0x00942000 - 8001154: 03d42000 .word 0x03d42000 - 8001158: 00002000 .word 0x00002000 - -0800115c <SystemInit>: - * Initialize the default HSI clock source, vector table location and the PLL configuration is reset. - * @param None - * @retval None - */ -void SystemInit(void) -{ - 800115c: b580 push {r7, lr} - 800115e: af00 add r7, sp, #0 - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001U; - 8001160: 4b1a ldr r3, [pc, #104] ; (80011cc <SystemInit+0x70>) - 8001162: 681a ldr r2, [r3, #0] - 8001164: 4b19 ldr r3, [pc, #100] ; (80011cc <SystemInit+0x70>) - 8001166: 2101 movs r1, #1 - 8001168: 430a orrs r2, r1 - 800116a: 601a str r2, [r3, #0] -#if defined (STM32F051x8) || defined (STM32F058x8) - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ - RCC->CFGR &= (uint32_t)0xF8FFB80CU; -#else - /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ - RCC->CFGR &= (uint32_t)0x08FFB80CU; - 800116c: 4b17 ldr r3, [pc, #92] ; (80011cc <SystemInit+0x70>) - 800116e: 685a ldr r2, [r3, #4] - 8001170: 4b16 ldr r3, [pc, #88] ; (80011cc <SystemInit+0x70>) - 8001172: 4917 ldr r1, [pc, #92] ; (80011d0 <SystemInit+0x74>) - 8001174: 400a ands r2, r1 - 8001176: 605a str r2, [r3, #4] -#endif /* STM32F051x8 or STM32F058x8 */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFFU; - 8001178: 4b14 ldr r3, [pc, #80] ; (80011cc <SystemInit+0x70>) - 800117a: 681a ldr r2, [r3, #0] - 800117c: 4b13 ldr r3, [pc, #76] ; (80011cc <SystemInit+0x70>) - 800117e: 4915 ldr r1, [pc, #84] ; (80011d4 <SystemInit+0x78>) - 8001180: 400a ands r2, r1 - 8001182: 601a str r2, [r3, #0] - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFFU; - 8001184: 4b11 ldr r3, [pc, #68] ; (80011cc <SystemInit+0x70>) - 8001186: 681a ldr r2, [r3, #0] - 8001188: 4b10 ldr r3, [pc, #64] ; (80011cc <SystemInit+0x70>) - 800118a: 4913 ldr r1, [pc, #76] ; (80011d8 <SystemInit+0x7c>) - 800118c: 400a ands r2, r1 - 800118e: 601a str r2, [r3, #0] - - /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - RCC->CFGR &= (uint32_t)0xFFC0FFFFU; - 8001190: 4b0e ldr r3, [pc, #56] ; (80011cc <SystemInit+0x70>) - 8001192: 685a ldr r2, [r3, #4] - 8001194: 4b0d ldr r3, [pc, #52] ; (80011cc <SystemInit+0x70>) - 8001196: 4911 ldr r1, [pc, #68] ; (80011dc <SystemInit+0x80>) - 8001198: 400a ands r2, r1 - 800119a: 605a str r2, [r3, #4] - - /* Reset PREDIV[3:0] bits */ - RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U; - 800119c: 4b0b ldr r3, [pc, #44] ; (80011cc <SystemInit+0x70>) - 800119e: 6ada ldr r2, [r3, #44] ; 0x2c - 80011a0: 4b0a ldr r3, [pc, #40] ; (80011cc <SystemInit+0x70>) - 80011a2: 210f movs r1, #15 - 80011a4: 438a bics r2, r1 - 80011a6: 62da str r2, [r3, #44] ; 0x2c -#elif defined (STM32F091xC) || defined (STM32F098xx) - /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFF0FEACU; -#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC) - /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */ - RCC->CFGR3 &= (uint32_t)0xFFFFFEECU; - 80011a8: 4b08 ldr r3, [pc, #32] ; (80011cc <SystemInit+0x70>) - 80011aa: 6b1a ldr r2, [r3, #48] ; 0x30 - 80011ac: 4b07 ldr r3, [pc, #28] ; (80011cc <SystemInit+0x70>) - 80011ae: 490c ldr r1, [pc, #48] ; (80011e0 <SystemInit+0x84>) - 80011b0: 400a ands r2, r1 - 80011b2: 631a str r2, [r3, #48] ; 0x30 -#else - #warning "No target selected" -#endif - - /* Reset HSI14 bit */ - RCC->CR2 &= (uint32_t)0xFFFFFFFEU; - 80011b4: 4b05 ldr r3, [pc, #20] ; (80011cc <SystemInit+0x70>) - 80011b6: 6b5a ldr r2, [r3, #52] ; 0x34 - 80011b8: 4b04 ldr r3, [pc, #16] ; (80011cc <SystemInit+0x70>) - 80011ba: 2101 movs r1, #1 - 80011bc: 438a bics r2, r1 - 80011be: 635a str r2, [r3, #52] ; 0x34 - - /* Disable all interrupts */ - RCC->CIR = 0x00000000U; - 80011c0: 4b02 ldr r3, [pc, #8] ; (80011cc <SystemInit+0x70>) - 80011c2: 2200 movs r2, #0 - 80011c4: 609a str r2, [r3, #8] - -} - 80011c6: 46c0 nop ; (mov r8, r8) - 80011c8: 46bd mov sp, r7 - 80011ca: bd80 pop {r7, pc} - 80011cc: 40021000 .word 0x40021000 - 80011d0: 08ffb80c .word 0x08ffb80c - 80011d4: fef6ffff .word 0xfef6ffff - 80011d8: fffbffff .word 0xfffbffff - 80011dc: ffc0ffff .word 0xffc0ffff - 80011e0: fffffeec .word 0xfffffeec - -080011e4 <SystemCoreClockUpdate>: - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - 80011e4: b580 push {r7, lr} - 80011e6: b084 sub sp, #16 - 80011e8: af00 add r7, sp, #0 - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - 80011ea: 2300 movs r3, #0 - 80011ec: 60fb str r3, [r7, #12] - 80011ee: 2300 movs r3, #0 - 80011f0: 60bb str r3, [r7, #8] - 80011f2: 2300 movs r3, #0 - 80011f4: 607b str r3, [r7, #4] - 80011f6: 2300 movs r3, #0 - 80011f8: 603b str r3, [r7, #0] - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - 80011fa: 4b31 ldr r3, [pc, #196] ; (80012c0 <SystemCoreClockUpdate+0xdc>) - 80011fc: 685b ldr r3, [r3, #4] - 80011fe: 220c movs r2, #12 - 8001200: 4013 ands r3, r2 - 8001202: 60fb str r3, [r7, #12] - - switch (tmp) - 8001204: 68fb ldr r3, [r7, #12] - 8001206: 2b08 cmp r3, #8 - 8001208: d011 beq.n 800122e <SystemCoreClockUpdate+0x4a> - 800120a: 68fb ldr r3, [r7, #12] - 800120c: 2b08 cmp r3, #8 - 800120e: d841 bhi.n 8001294 <SystemCoreClockUpdate+0xb0> - 8001210: 68fb ldr r3, [r7, #12] - 8001212: 2b00 cmp r3, #0 - 8001214: d003 beq.n 800121e <SystemCoreClockUpdate+0x3a> - 8001216: 68fb ldr r3, [r7, #12] - 8001218: 2b04 cmp r3, #4 - 800121a: d004 beq.n 8001226 <SystemCoreClockUpdate+0x42> - 800121c: e03a b.n 8001294 <SystemCoreClockUpdate+0xb0> - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - 800121e: 4b29 ldr r3, [pc, #164] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 8001220: 4a29 ldr r2, [pc, #164] ; (80012c8 <SystemCoreClockUpdate+0xe4>) - 8001222: 601a str r2, [r3, #0] - break; - 8001224: e03a b.n 800129c <SystemCoreClockUpdate+0xb8> - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - 8001226: 4b27 ldr r3, [pc, #156] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 8001228: 4a27 ldr r2, [pc, #156] ; (80012c8 <SystemCoreClockUpdate+0xe4>) - 800122a: 601a str r2, [r3, #0] - break; - 800122c: e036 b.n 800129c <SystemCoreClockUpdate+0xb8> - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - 800122e: 4b24 ldr r3, [pc, #144] ; (80012c0 <SystemCoreClockUpdate+0xdc>) - 8001230: 685a ldr r2, [r3, #4] - 8001232: 23f0 movs r3, #240 ; 0xf0 - 8001234: 039b lsls r3, r3, #14 - 8001236: 4013 ands r3, r2 - 8001238: 60bb str r3, [r7, #8] - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - 800123a: 4b21 ldr r3, [pc, #132] ; (80012c0 <SystemCoreClockUpdate+0xdc>) - 800123c: 685a ldr r2, [r3, #4] - 800123e: 2380 movs r3, #128 ; 0x80 - 8001240: 025b lsls r3, r3, #9 - 8001242: 4013 ands r3, r2 - 8001244: 607b str r3, [r7, #4] - pllmull = ( pllmull >> 18) + 2; - 8001246: 68bb ldr r3, [r7, #8] - 8001248: 0c9b lsrs r3, r3, #18 - 800124a: 3302 adds r3, #2 - 800124c: 60bb str r3, [r7, #8] - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - 800124e: 4b1c ldr r3, [pc, #112] ; (80012c0 <SystemCoreClockUpdate+0xdc>) - 8001250: 6adb ldr r3, [r3, #44] ; 0x2c - 8001252: 220f movs r2, #15 - 8001254: 4013 ands r3, r2 - 8001256: 3301 adds r3, #1 - 8001258: 603b str r3, [r7, #0] - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - 800125a: 687a ldr r2, [r7, #4] - 800125c: 2380 movs r3, #128 ; 0x80 - 800125e: 025b lsls r3, r3, #9 - 8001260: 429a cmp r2, r3 - 8001262: d10a bne.n 800127a <SystemCoreClockUpdate+0x96> - { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - 8001264: 6839 ldr r1, [r7, #0] - 8001266: 4818 ldr r0, [pc, #96] ; (80012c8 <SystemCoreClockUpdate+0xe4>) - 8001268: f000 fb3e bl 80018e8 <__udivsi3> - 800126c: 0003 movs r3, r0 - 800126e: 001a movs r2, r3 - 8001270: 68bb ldr r3, [r7, #8] - 8001272: 435a muls r2, r3 - 8001274: 4b13 ldr r3, [pc, #76] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 8001276: 601a str r2, [r3, #0] - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || - STM32F091xC || STM32F098xx || STM32F030xC */ - } - break; - 8001278: e010 b.n 800129c <SystemCoreClockUpdate+0xb8> - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - 800127a: 68b9 ldr r1, [r7, #8] - 800127c: 000a movs r2, r1 - 800127e: 0152 lsls r2, r2, #5 - 8001280: 1a52 subs r2, r2, r1 - 8001282: 0193 lsls r3, r2, #6 - 8001284: 1a9b subs r3, r3, r2 - 8001286: 00db lsls r3, r3, #3 - 8001288: 185b adds r3, r3, r1 - 800128a: 021b lsls r3, r3, #8 - 800128c: 001a movs r2, r3 - 800128e: 4b0d ldr r3, [pc, #52] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 8001290: 601a str r2, [r3, #0] - break; - 8001292: e003 b.n 800129c <SystemCoreClockUpdate+0xb8> - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - 8001294: 4b0b ldr r3, [pc, #44] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 8001296: 4a0c ldr r2, [pc, #48] ; (80012c8 <SystemCoreClockUpdate+0xe4>) - 8001298: 601a str r2, [r3, #0] - break; - 800129a: 46c0 nop ; (mov r8, r8) - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - 800129c: 4b08 ldr r3, [pc, #32] ; (80012c0 <SystemCoreClockUpdate+0xdc>) - 800129e: 685b ldr r3, [r3, #4] - 80012a0: 091b lsrs r3, r3, #4 - 80012a2: 220f movs r2, #15 - 80012a4: 4013 ands r3, r2 - 80012a6: 4a09 ldr r2, [pc, #36] ; (80012cc <SystemCoreClockUpdate+0xe8>) - 80012a8: 5cd3 ldrb r3, [r2, r3] - 80012aa: 60fb str r3, [r7, #12] - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; - 80012ac: 4b05 ldr r3, [pc, #20] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 80012ae: 681a ldr r2, [r3, #0] - 80012b0: 68fb ldr r3, [r7, #12] - 80012b2: 40da lsrs r2, r3 - 80012b4: 4b03 ldr r3, [pc, #12] ; (80012c4 <SystemCoreClockUpdate+0xe0>) - 80012b6: 601a str r2, [r3, #0] -} - 80012b8: 46c0 nop ; (mov r8, r8) - 80012ba: 46bd mov sp, r7 - 80012bc: b004 add sp, #16 - 80012be: bd80 pop {r7, pc} - 80012c0: 40021000 .word 0x40021000 - 80012c4: 20000000 .word 0x20000000 - 80012c8: 007a1200 .word 0x007a1200 - 80012cc: 08001c24 .word 0x08001c24 - -080012d0 <LL_RCC_HSE_EnableBypass>: - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - 80012d0: b580 push {r7, lr} - 80012d2: af00 add r7, sp, #0 - SET_BIT(RCC->CR, RCC_CR_HSEBYP); - 80012d4: 4b04 ldr r3, [pc, #16] ; (80012e8 <LL_RCC_HSE_EnableBypass+0x18>) - 80012d6: 681a ldr r2, [r3, #0] - 80012d8: 4b03 ldr r3, [pc, #12] ; (80012e8 <LL_RCC_HSE_EnableBypass+0x18>) - 80012da: 2180 movs r1, #128 ; 0x80 - 80012dc: 02c9 lsls r1, r1, #11 - 80012de: 430a orrs r2, r1 - 80012e0: 601a str r2, [r3, #0] -} - 80012e2: 46c0 nop ; (mov r8, r8) - 80012e4: 46bd mov sp, r7 - 80012e6: bd80 pop {r7, pc} - 80012e8: 40021000 .word 0x40021000 - -080012ec <LL_RCC_HSE_DisableBypass>: - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - 80012ec: b580 push {r7, lr} - 80012ee: af00 add r7, sp, #0 - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - 80012f0: 4b04 ldr r3, [pc, #16] ; (8001304 <LL_RCC_HSE_DisableBypass+0x18>) - 80012f2: 681a ldr r2, [r3, #0] - 80012f4: 4b03 ldr r3, [pc, #12] ; (8001304 <LL_RCC_HSE_DisableBypass+0x18>) - 80012f6: 4904 ldr r1, [pc, #16] ; (8001308 <LL_RCC_HSE_DisableBypass+0x1c>) - 80012f8: 400a ands r2, r1 - 80012fa: 601a str r2, [r3, #0] -} - 80012fc: 46c0 nop ; (mov r8, r8) - 80012fe: 46bd mov sp, r7 - 8001300: bd80 pop {r7, pc} - 8001302: 46c0 nop ; (mov r8, r8) - 8001304: 40021000 .word 0x40021000 - 8001308: fffbffff .word 0xfffbffff - -0800130c <LL_RCC_HSE_Enable>: - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - 800130c: b580 push {r7, lr} - 800130e: af00 add r7, sp, #0 - SET_BIT(RCC->CR, RCC_CR_HSEON); - 8001310: 4b04 ldr r3, [pc, #16] ; (8001324 <LL_RCC_HSE_Enable+0x18>) - 8001312: 681a ldr r2, [r3, #0] - 8001314: 4b03 ldr r3, [pc, #12] ; (8001324 <LL_RCC_HSE_Enable+0x18>) - 8001316: 2180 movs r1, #128 ; 0x80 - 8001318: 0249 lsls r1, r1, #9 - 800131a: 430a orrs r2, r1 - 800131c: 601a str r2, [r3, #0] -} - 800131e: 46c0 nop ; (mov r8, r8) - 8001320: 46bd mov sp, r7 - 8001322: bd80 pop {r7, pc} - 8001324: 40021000 .word 0x40021000 - -08001328 <LL_RCC_HSE_IsReady>: - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - 8001328: b580 push {r7, lr} - 800132a: af00 add r7, sp, #0 - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); - 800132c: 4b06 ldr r3, [pc, #24] ; (8001348 <LL_RCC_HSE_IsReady+0x20>) - 800132e: 681a ldr r2, [r3, #0] - 8001330: 2380 movs r3, #128 ; 0x80 - 8001332: 029b lsls r3, r3, #10 - 8001334: 4013 ands r3, r2 - 8001336: 4a05 ldr r2, [pc, #20] ; (800134c <LL_RCC_HSE_IsReady+0x24>) - 8001338: 4694 mov ip, r2 - 800133a: 4463 add r3, ip - 800133c: 425a negs r2, r3 - 800133e: 4153 adcs r3, r2 - 8001340: b2db uxtb r3, r3 -} - 8001342: 0018 movs r0, r3 - 8001344: 46bd mov sp, r7 - 8001346: bd80 pop {r7, pc} - 8001348: 40021000 .word 0x40021000 - 800134c: fffe0000 .word 0xfffe0000 - -08001350 <LL_RCC_HSI_Enable>: - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - 8001350: b580 push {r7, lr} - 8001352: af00 add r7, sp, #0 - SET_BIT(RCC->CR, RCC_CR_HSION); - 8001354: 4b04 ldr r3, [pc, #16] ; (8001368 <LL_RCC_HSI_Enable+0x18>) - 8001356: 681a ldr r2, [r3, #0] - 8001358: 4b03 ldr r3, [pc, #12] ; (8001368 <LL_RCC_HSI_Enable+0x18>) - 800135a: 2101 movs r1, #1 - 800135c: 430a orrs r2, r1 - 800135e: 601a str r2, [r3, #0] -} - 8001360: 46c0 nop ; (mov r8, r8) - 8001362: 46bd mov sp, r7 - 8001364: bd80 pop {r7, pc} - 8001366: 46c0 nop ; (mov r8, r8) - 8001368: 40021000 .word 0x40021000 - -0800136c <LL_RCC_HSI_IsReady>: - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - 800136c: b580 push {r7, lr} - 800136e: af00 add r7, sp, #0 - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); - 8001370: 4b05 ldr r3, [pc, #20] ; (8001388 <LL_RCC_HSI_IsReady+0x1c>) - 8001372: 681b ldr r3, [r3, #0] - 8001374: 2202 movs r2, #2 - 8001376: 4013 ands r3, r2 - 8001378: 3b02 subs r3, #2 - 800137a: 425a negs r2, r3 - 800137c: 4153 adcs r3, r2 - 800137e: b2db uxtb r3, r3 -} - 8001380: 0018 movs r0, r3 - 8001382: 46bd mov sp, r7 - 8001384: bd80 pop {r7, pc} - 8001386: 46c0 nop ; (mov r8, r8) - 8001388: 40021000 .word 0x40021000 - -0800138c <LL_RCC_SetSysClkSource>: - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - 800138c: b580 push {r7, lr} - 800138e: b082 sub sp, #8 - 8001390: af00 add r7, sp, #0 - 8001392: 6078 str r0, [r7, #4] - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); - 8001394: 4b06 ldr r3, [pc, #24] ; (80013b0 <LL_RCC_SetSysClkSource+0x24>) - 8001396: 685b ldr r3, [r3, #4] - 8001398: 2203 movs r2, #3 - 800139a: 4393 bics r3, r2 - 800139c: 0019 movs r1, r3 - 800139e: 4b04 ldr r3, [pc, #16] ; (80013b0 <LL_RCC_SetSysClkSource+0x24>) - 80013a0: 687a ldr r2, [r7, #4] - 80013a2: 430a orrs r2, r1 - 80013a4: 605a str r2, [r3, #4] -} - 80013a6: 46c0 nop ; (mov r8, r8) - 80013a8: 46bd mov sp, r7 - 80013aa: b002 add sp, #8 - 80013ac: bd80 pop {r7, pc} - 80013ae: 46c0 nop ; (mov r8, r8) - 80013b0: 40021000 .word 0x40021000 - -080013b4 <LL_RCC_GetSysClkSource>: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI48 (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - 80013b4: b580 push {r7, lr} - 80013b6: af00 add r7, sp, #0 - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); - 80013b8: 4b03 ldr r3, [pc, #12] ; (80013c8 <LL_RCC_GetSysClkSource+0x14>) - 80013ba: 685b ldr r3, [r3, #4] - 80013bc: 220c movs r2, #12 - 80013be: 4013 ands r3, r2 -} - 80013c0: 0018 movs r0, r3 - 80013c2: 46bd mov sp, r7 - 80013c4: bd80 pop {r7, pc} - 80013c6: 46c0 nop ; (mov r8, r8) - 80013c8: 40021000 .word 0x40021000 - -080013cc <LL_RCC_SetAHBPrescaler>: - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - 80013cc: b580 push {r7, lr} - 80013ce: b082 sub sp, #8 - 80013d0: af00 add r7, sp, #0 - 80013d2: 6078 str r0, [r7, #4] - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); - 80013d4: 4b06 ldr r3, [pc, #24] ; (80013f0 <LL_RCC_SetAHBPrescaler+0x24>) - 80013d6: 685b ldr r3, [r3, #4] - 80013d8: 22f0 movs r2, #240 ; 0xf0 - 80013da: 4393 bics r3, r2 - 80013dc: 0019 movs r1, r3 - 80013de: 4b04 ldr r3, [pc, #16] ; (80013f0 <LL_RCC_SetAHBPrescaler+0x24>) - 80013e0: 687a ldr r2, [r7, #4] - 80013e2: 430a orrs r2, r1 - 80013e4: 605a str r2, [r3, #4] -} - 80013e6: 46c0 nop ; (mov r8, r8) - 80013e8: 46bd mov sp, r7 - 80013ea: b002 add sp, #8 - 80013ec: bd80 pop {r7, pc} - 80013ee: 46c0 nop ; (mov r8, r8) - 80013f0: 40021000 .word 0x40021000 - -080013f4 <LL_RCC_SetAPB1Prescaler>: - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - 80013f4: b580 push {r7, lr} - 80013f6: b082 sub sp, #8 - 80013f8: af00 add r7, sp, #0 - 80013fa: 6078 str r0, [r7, #4] - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); - 80013fc: 4b06 ldr r3, [pc, #24] ; (8001418 <LL_RCC_SetAPB1Prescaler+0x24>) - 80013fe: 685b ldr r3, [r3, #4] - 8001400: 4a06 ldr r2, [pc, #24] ; (800141c <LL_RCC_SetAPB1Prescaler+0x28>) - 8001402: 4013 ands r3, r2 - 8001404: 0019 movs r1, r3 - 8001406: 4b04 ldr r3, [pc, #16] ; (8001418 <LL_RCC_SetAPB1Prescaler+0x24>) - 8001408: 687a ldr r2, [r7, #4] - 800140a: 430a orrs r2, r1 - 800140c: 605a str r2, [r3, #4] -} - 800140e: 46c0 nop ; (mov r8, r8) - 8001410: 46bd mov sp, r7 - 8001412: b002 add sp, #8 - 8001414: bd80 pop {r7, pc} - 8001416: 46c0 nop ; (mov r8, r8) - 8001418: 40021000 .word 0x40021000 - 800141c: fffff8ff .word 0xfffff8ff - -08001420 <LL_RCC_PLL_Enable>: - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - 8001420: b580 push {r7, lr} - 8001422: af00 add r7, sp, #0 - SET_BIT(RCC->CR, RCC_CR_PLLON); - 8001424: 4b04 ldr r3, [pc, #16] ; (8001438 <LL_RCC_PLL_Enable+0x18>) - 8001426: 681a ldr r2, [r3, #0] - 8001428: 4b03 ldr r3, [pc, #12] ; (8001438 <LL_RCC_PLL_Enable+0x18>) - 800142a: 2180 movs r1, #128 ; 0x80 - 800142c: 0449 lsls r1, r1, #17 - 800142e: 430a orrs r2, r1 - 8001430: 601a str r2, [r3, #0] -} - 8001432: 46c0 nop ; (mov r8, r8) - 8001434: 46bd mov sp, r7 - 8001436: bd80 pop {r7, pc} - 8001438: 40021000 .word 0x40021000 - -0800143c <LL_RCC_PLL_IsReady>: - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - 800143c: b580 push {r7, lr} - 800143e: af00 add r7, sp, #0 - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); - 8001440: 4b07 ldr r3, [pc, #28] ; (8001460 <LL_RCC_PLL_IsReady+0x24>) - 8001442: 681a ldr r2, [r3, #0] - 8001444: 2380 movs r3, #128 ; 0x80 - 8001446: 049b lsls r3, r3, #18 - 8001448: 4013 ands r3, r2 - 800144a: 22fe movs r2, #254 ; 0xfe - 800144c: 0612 lsls r2, r2, #24 - 800144e: 4694 mov ip, r2 - 8001450: 4463 add r3, ip - 8001452: 425a negs r2, r3 - 8001454: 4153 adcs r3, r2 - 8001456: b2db uxtb r3, r3 -} - 8001458: 0018 movs r0, r3 - 800145a: 46bd mov sp, r7 - 800145c: bd80 pop {r7, pc} - 800145e: 46c0 nop ; (mov r8, r8) - 8001460: 40021000 .word 0x40021000 - -08001464 <LL_RCC_PLL_ConfigDomain_SYS>: - * @arg @ref LL_RCC_PLL_MUL_15 - * @arg @ref LL_RCC_PLL_MUL_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul) -{ - 8001464: b580 push {r7, lr} - 8001466: b082 sub sp, #8 - 8001468: af00 add r7, sp, #0 - 800146a: 6078 str r0, [r7, #4] - 800146c: 6039 str r1, [r7, #0] - MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul); - 800146e: 4b0e ldr r3, [pc, #56] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) - 8001470: 685b ldr r3, [r3, #4] - 8001472: 4a0e ldr r2, [pc, #56] ; (80014ac <LL_RCC_PLL_ConfigDomain_SYS+0x48>) - 8001474: 4013 ands r3, r2 - 8001476: 0019 movs r1, r3 - 8001478: 687a ldr r2, [r7, #4] - 800147a: 2380 movs r3, #128 ; 0x80 - 800147c: 025b lsls r3, r3, #9 - 800147e: 401a ands r2, r3 - 8001480: 683b ldr r3, [r7, #0] - 8001482: 431a orrs r2, r3 - 8001484: 4b08 ldr r3, [pc, #32] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) - 8001486: 430a orrs r2, r1 - 8001488: 605a str r2, [r3, #4] - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV)); - 800148a: 4b07 ldr r3, [pc, #28] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) - 800148c: 6adb ldr r3, [r3, #44] ; 0x2c - 800148e: 220f movs r2, #15 - 8001490: 4393 bics r3, r2 - 8001492: 0019 movs r1, r3 - 8001494: 687b ldr r3, [r7, #4] - 8001496: 220f movs r2, #15 - 8001498: 401a ands r2, r3 - 800149a: 4b03 ldr r3, [pc, #12] ; (80014a8 <LL_RCC_PLL_ConfigDomain_SYS+0x44>) - 800149c: 430a orrs r2, r1 - 800149e: 62da str r2, [r3, #44] ; 0x2c -} - 80014a0: 46c0 nop ; (mov r8, r8) - 80014a2: 46bd mov sp, r7 - 80014a4: b002 add sp, #8 - 80014a6: bd80 pop {r7, pc} - 80014a8: 40021000 .word 0x40021000 - 80014ac: ffc2ffff .word 0xffc2ffff - -080014b0 <LL_InitTick>: - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - 80014b0: b580 push {r7, lr} - 80014b2: b082 sub sp, #8 - 80014b4: af00 add r7, sp, #0 - 80014b6: 6078 str r0, [r7, #4] - 80014b8: 6039 str r1, [r7, #0] - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - 80014ba: 6839 ldr r1, [r7, #0] - 80014bc: 6878 ldr r0, [r7, #4] - 80014be: f000 fa13 bl 80018e8 <__udivsi3> - 80014c2: 0003 movs r3, r0 - 80014c4: 001a movs r2, r3 - 80014c6: 4b06 ldr r3, [pc, #24] ; (80014e0 <LL_InitTick+0x30>) - 80014c8: 3a01 subs r2, #1 - 80014ca: 605a str r2, [r3, #4] - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 80014cc: 4b04 ldr r3, [pc, #16] ; (80014e0 <LL_InitTick+0x30>) - 80014ce: 2200 movs r2, #0 - 80014d0: 609a str r2, [r3, #8] - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 80014d2: 4b03 ldr r3, [pc, #12] ; (80014e0 <LL_InitTick+0x30>) - 80014d4: 2205 movs r2, #5 - 80014d6: 601a str r2, [r3, #0] - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - 80014d8: 46c0 nop ; (mov r8, r8) - 80014da: 46bd mov sp, r7 - 80014dc: b002 add sp, #8 - 80014de: bd80 pop {r7, pc} - 80014e0: e000e010 .word 0xe000e010 - -080014e4 <LL_FLASH_SetLatency>: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - 80014e4: b580 push {r7, lr} - 80014e6: b082 sub sp, #8 - 80014e8: af00 add r7, sp, #0 - 80014ea: 6078 str r0, [r7, #4] - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); - 80014ec: 4b06 ldr r3, [pc, #24] ; (8001508 <LL_FLASH_SetLatency+0x24>) - 80014ee: 681b ldr r3, [r3, #0] - 80014f0: 2201 movs r2, #1 - 80014f2: 4393 bics r3, r2 - 80014f4: 0019 movs r1, r3 - 80014f6: 4b04 ldr r3, [pc, #16] ; (8001508 <LL_FLASH_SetLatency+0x24>) - 80014f8: 687a ldr r2, [r7, #4] - 80014fa: 430a orrs r2, r1 - 80014fc: 601a str r2, [r3, #0] -} - 80014fe: 46c0 nop ; (mov r8, r8) - 8001500: 46bd mov sp, r7 - 8001502: b002 add sp, #8 - 8001504: bd80 pop {r7, pc} - 8001506: 46c0 nop ; (mov r8, r8) - 8001508: 40022000 .word 0x40022000 - -0800150c <LL_FLASH_GetLatency>: - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - 800150c: b580 push {r7, lr} - 800150e: af00 add r7, sp, #0 - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); - 8001510: 4b03 ldr r3, [pc, #12] ; (8001520 <LL_FLASH_GetLatency+0x14>) - 8001512: 681b ldr r3, [r3, #0] - 8001514: 2201 movs r2, #1 - 8001516: 4013 ands r3, r2 -} - 8001518: 0018 movs r0, r3 - 800151a: 46bd mov sp, r7 - 800151c: bd80 pop {r7, pc} - 800151e: 46c0 nop ; (mov r8, r8) - 8001520: 40022000 .word 0x40022000 - -08001524 <LL_Init1msTick>: - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - 8001524: b580 push {r7, lr} - 8001526: b082 sub sp, #8 - 8001528: af00 add r7, sp, #0 - 800152a: 6078 str r0, [r7, #4] - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); - 800152c: 23fa movs r3, #250 ; 0xfa - 800152e: 009a lsls r2, r3, #2 - 8001530: 687b ldr r3, [r7, #4] - 8001532: 0011 movs r1, r2 - 8001534: 0018 movs r0, r3 - 8001536: f7ff ffbb bl 80014b0 <LL_InitTick> -} - 800153a: 46c0 nop ; (mov r8, r8) - 800153c: 46bd mov sp, r7 - 800153e: b002 add sp, #8 - 8001540: bd80 pop {r7, pc} - -08001542 <LL_mDelay>: - * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -void LL_mDelay(uint32_t Delay) -{ - 8001542: b580 push {r7, lr} - 8001544: b084 sub sp, #16 - 8001546: af00 add r7, sp, #0 - 8001548: 6078 str r0, [r7, #4] - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - 800154a: 4b0e ldr r3, [pc, #56] ; (8001584 <LL_mDelay+0x42>) - 800154c: 681b ldr r3, [r3, #0] - 800154e: 60fb str r3, [r7, #12] - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - 8001550: 68fb ldr r3, [r7, #12] - - /* Add a period to guaranty minimum wait */ - if (Delay < LL_MAX_DELAY) - 8001552: 687b ldr r3, [r7, #4] - 8001554: 3301 adds r3, #1 - 8001556: d00c beq.n 8001572 <LL_mDelay+0x30> - { - Delay++; - 8001558: 687b ldr r3, [r7, #4] - 800155a: 3301 adds r3, #1 - 800155c: 607b str r3, [r7, #4] - } - - while (Delay) - 800155e: e008 b.n 8001572 <LL_mDelay+0x30> - { - if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - 8001560: 4b08 ldr r3, [pc, #32] ; (8001584 <LL_mDelay+0x42>) - 8001562: 681a ldr r2, [r3, #0] - 8001564: 2380 movs r3, #128 ; 0x80 - 8001566: 025b lsls r3, r3, #9 - 8001568: 4013 ands r3, r2 - 800156a: d002 beq.n 8001572 <LL_mDelay+0x30> - { - Delay--; - 800156c: 687b ldr r3, [r7, #4] - 800156e: 3b01 subs r3, #1 - 8001570: 607b str r3, [r7, #4] - while (Delay) - 8001572: 687b ldr r3, [r7, #4] - 8001574: 2b00 cmp r3, #0 - 8001576: d1f3 bne.n 8001560 <LL_mDelay+0x1e> - } - } -} - 8001578: 46c0 nop ; (mov r8, r8) - 800157a: 46c0 nop ; (mov r8, r8) - 800157c: 46bd mov sp, r7 - 800157e: b004 add sp, #16 - 8001580: bd80 pop {r7, pc} - 8001582: 46c0 nop ; (mov r8, r8) - 8001584: e000e010 .word 0xe000e010 - -08001588 <LL_SetSystemCoreClock>: - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - 8001588: b580 push {r7, lr} - 800158a: b082 sub sp, #8 - 800158c: af00 add r7, sp, #0 - 800158e: 6078 str r0, [r7, #4] - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; - 8001590: 4b03 ldr r3, [pc, #12] ; (80015a0 <LL_SetSystemCoreClock+0x18>) - 8001592: 687a ldr r2, [r7, #4] - 8001594: 601a str r2, [r3, #0] -} - 8001596: 46c0 nop ; (mov r8, r8) - 8001598: 46bd mov sp, r7 - 800159a: b002 add sp, #8 - 800159c: bd80 pop {r7, pc} - 800159e: 46c0 nop ; (mov r8, r8) - 80015a0: 20000000 .word 0x20000000 - -080015a4 <LL_PLL_ConfigSystemClock_HSI>: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - 80015a4: b590 push {r4, r7, lr} - 80015a6: b085 sub sp, #20 - 80015a8: af00 add r7, sp, #0 - 80015aa: 6078 str r0, [r7, #4] - 80015ac: 6039 str r1, [r7, #0] - ErrorStatus status = SUCCESS; - 80015ae: 230f movs r3, #15 - 80015b0: 18fb adds r3, r7, r3 - 80015b2: 2201 movs r2, #1 - 80015b4: 701a strb r2, [r3, #0] - uint32_t pllfreq = 0U; - 80015b6: 2300 movs r3, #0 - 80015b8: 60bb str r3, [r7, #8] - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - 80015ba: f000 f8d4 bl 8001766 <UTILS_PLL_IsBusy> - 80015be: 0003 movs r3, r0 - 80015c0: 2b01 cmp r3, #1 - 80015c2: d128 bne.n 8001616 <LL_PLL_ConfigSystemClock_HSI+0x72> -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - /* Check PREDIV value */ - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); -#else - /* Force PREDIV value to 2 */ - UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2; - 80015c4: 687b ldr r3, [r7, #4] - 80015c6: 2201 movs r2, #1 - 80015c8: 605a str r2, [r3, #4] -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); - 80015ca: 687b ldr r3, [r7, #4] - 80015cc: 4a17 ldr r2, [pc, #92] ; (800162c <LL_PLL_ConfigSystemClock_HSI+0x88>) - 80015ce: 0019 movs r1, r3 - 80015d0: 0010 movs r0, r2 - 80015d2: f000 f8ab bl 800172c <UTILS_GetPLLOutputFrequency> - 80015d6: 0003 movs r3, r0 - 80015d8: 60bb str r3, [r7, #8] - - /* Enable HSI if not enabled */ - if (LL_RCC_HSI_IsReady() != 1U) - 80015da: f7ff fec7 bl 800136c <LL_RCC_HSI_IsReady> - 80015de: 0003 movs r3, r0 - 80015e0: 2b01 cmp r3, #1 - 80015e2: d007 beq.n 80015f4 <LL_PLL_ConfigSystemClock_HSI+0x50> - { - LL_RCC_HSI_Enable(); - 80015e4: f7ff feb4 bl 8001350 <LL_RCC_HSI_Enable> - while (LL_RCC_HSI_IsReady() != 1U) - 80015e8: 46c0 nop ; (mov r8, r8) - 80015ea: f7ff febf bl 800136c <LL_RCC_HSI_IsReady> - 80015ee: 0003 movs r3, r0 - 80015f0: 2b01 cmp r3, #1 - 80015f2: d1fa bne.n 80015ea <LL_PLL_ConfigSystemClock_HSI+0x46> - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul); - 80015f4: 687b ldr r3, [r7, #4] - 80015f6: 681b ldr r3, [r3, #0] - 80015f8: 0019 movs r1, r3 - 80015fa: 2000 movs r0, #0 - 80015fc: f7ff ff32 bl 8001464 <LL_RCC_PLL_ConfigDomain_SYS> -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - 8001600: 230f movs r3, #15 - 8001602: 18fc adds r4, r7, r3 - 8001604: 683a ldr r2, [r7, #0] - 8001606: 68bb ldr r3, [r7, #8] - 8001608: 0011 movs r1, r2 - 800160a: 0018 movs r0, r3 - 800160c: f000 f8be bl 800178c <UTILS_EnablePLLAndSwitchSystem> - 8001610: 0003 movs r3, r0 - 8001612: 7023 strb r3, [r4, #0] - 8001614: e003 b.n 800161e <LL_PLL_ConfigSystemClock_HSI+0x7a> - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - 8001616: 230f movs r3, #15 - 8001618: 18fb adds r3, r7, r3 - 800161a: 2200 movs r2, #0 - 800161c: 701a strb r2, [r3, #0] - } - - return status; - 800161e: 230f movs r3, #15 - 8001620: 18fb adds r3, r7, r3 - 8001622: 781b ldrb r3, [r3, #0] -} - 8001624: 0018 movs r0, r3 - 8001626: 46bd mov sp, r7 - 8001628: b005 add sp, #20 - 800162a: bd90 pop {r4, r7, pc} - 800162c: 007a1200 .word 0x007a1200 - -08001630 <LL_PLL_ConfigSystemClock_HSE>: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - 8001630: b590 push {r4, r7, lr} - 8001632: b087 sub sp, #28 - 8001634: af00 add r7, sp, #0 - 8001636: 60f8 str r0, [r7, #12] - 8001638: 60b9 str r1, [r7, #8] - 800163a: 607a str r2, [r7, #4] - 800163c: 603b str r3, [r7, #0] - ErrorStatus status = SUCCESS; - 800163e: 2317 movs r3, #23 - 8001640: 18fb adds r3, r7, r3 - 8001642: 2201 movs r2, #1 - 8001644: 701a strb r2, [r3, #0] - uint32_t pllfreq = 0U; - 8001646: 2300 movs r3, #0 - 8001648: 613b str r3, [r7, #16] - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - 800164a: f000 f88c bl 8001766 <UTILS_PLL_IsBusy> - 800164e: 0003 movs r3, r0 - 8001650: 2b01 cmp r3, #1 - 8001652: d132 bne.n 80016ba <LL_PLL_ConfigSystemClock_HSE+0x8a> -#else - assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv)); -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); - 8001654: 687a ldr r2, [r7, #4] - 8001656: 68fb ldr r3, [r7, #12] - 8001658: 0011 movs r1, r2 - 800165a: 0018 movs r0, r3 - 800165c: f000 f866 bl 800172c <UTILS_GetPLLOutputFrequency> - 8001660: 0003 movs r3, r0 - 8001662: 613b str r3, [r7, #16] - - /* Enable HSE if not enabled */ - if (LL_RCC_HSE_IsReady() != 1U) - 8001664: f7ff fe60 bl 8001328 <LL_RCC_HSE_IsReady> - 8001668: 0003 movs r3, r0 - 800166a: 2b01 cmp r3, #1 - 800166c: d00f beq.n 800168e <LL_PLL_ConfigSystemClock_HSE+0x5e> - { - /* Check if need to enable HSE bypass feature or not */ - if (HSEBypass == LL_UTILS_HSEBYPASS_ON) - 800166e: 68bb ldr r3, [r7, #8] - 8001670: 2b01 cmp r3, #1 - 8001672: d102 bne.n 800167a <LL_PLL_ConfigSystemClock_HSE+0x4a> - { - LL_RCC_HSE_EnableBypass(); - 8001674: f7ff fe2c bl 80012d0 <LL_RCC_HSE_EnableBypass> - 8001678: e001 b.n 800167e <LL_PLL_ConfigSystemClock_HSE+0x4e> - } - else - { - LL_RCC_HSE_DisableBypass(); - 800167a: f7ff fe37 bl 80012ec <LL_RCC_HSE_DisableBypass> - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - 800167e: f7ff fe45 bl 800130c <LL_RCC_HSE_Enable> - while (LL_RCC_HSE_IsReady() != 1U) - 8001682: 46c0 nop ; (mov r8, r8) - 8001684: f7ff fe50 bl 8001328 <LL_RCC_HSE_IsReady> - 8001688: 0003 movs r3, r0 - 800168a: 2b01 cmp r3, #1 - 800168c: d1fa bne.n 8001684 <LL_PLL_ConfigSystemClock_HSE+0x54> - - /* Configure PLL */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC_HSE_PREDIV | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul); - 800168e: 687b ldr r3, [r7, #4] - 8001690: 685b ldr r3, [r3, #4] - 8001692: 2280 movs r2, #128 ; 0x80 - 8001694: 0252 lsls r2, r2, #9 - 8001696: 431a orrs r2, r3 - 8001698: 687b ldr r3, [r7, #4] - 800169a: 681b ldr r3, [r3, #0] - 800169c: 0019 movs r1, r3 - 800169e: 0010 movs r0, r2 - 80016a0: f7ff fee0 bl 8001464 <LL_RCC_PLL_ConfigDomain_SYS> -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - 80016a4: 2317 movs r3, #23 - 80016a6: 18fc adds r4, r7, r3 - 80016a8: 683a ldr r2, [r7, #0] - 80016aa: 693b ldr r3, [r7, #16] - 80016ac: 0011 movs r1, r2 - 80016ae: 0018 movs r0, r3 - 80016b0: f000 f86c bl 800178c <UTILS_EnablePLLAndSwitchSystem> - 80016b4: 0003 movs r3, r0 - 80016b6: 7023 strb r3, [r4, #0] - 80016b8: e003 b.n 80016c2 <LL_PLL_ConfigSystemClock_HSE+0x92> - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - 80016ba: 2317 movs r3, #23 - 80016bc: 18fb adds r3, r7, r3 - 80016be: 2200 movs r2, #0 - 80016c0: 701a strb r2, [r3, #0] - } - - return status; - 80016c2: 2317 movs r3, #23 - 80016c4: 18fb adds r3, r7, r3 - 80016c6: 781b ldrb r3, [r3, #0] -} - 80016c8: 0018 movs r0, r3 - 80016ca: 46bd mov sp, r7 - 80016cc: b007 add sp, #28 - 80016ce: bd90 pop {r4, r7, pc} - -080016d0 <UTILS_SetFlashLatency>: - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency) -{ - 80016d0: b580 push {r7, lr} - 80016d2: b084 sub sp, #16 - 80016d4: af00 add r7, sp, #0 - 80016d6: 6078 str r0, [r7, #4] - ErrorStatus status = SUCCESS; - 80016d8: 210f movs r1, #15 - 80016da: 187b adds r3, r7, r1 - 80016dc: 2201 movs r2, #1 - 80016de: 701a strb r2, [r3, #0] - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - 80016e0: 2300 movs r3, #0 - 80016e2: 60bb str r3, [r7, #8] - - /* Frequency cannot be equal to 0 */ - if (Frequency == 0U) - 80016e4: 687b ldr r3, [r7, #4] - 80016e6: 2b00 cmp r3, #0 - 80016e8: d103 bne.n 80016f2 <UTILS_SetFlashLatency+0x22> - { - status = ERROR; - 80016ea: 187b adds r3, r7, r1 - 80016ec: 2200 movs r2, #0 - 80016ee: 701a strb r2, [r3, #0] - 80016f0: e013 b.n 800171a <UTILS_SetFlashLatency+0x4a> - } - else - { - if (Frequency > UTILS_LATENCY1_FREQ) - 80016f2: 687b ldr r3, [r7, #4] - 80016f4: 4a0c ldr r2, [pc, #48] ; (8001728 <UTILS_SetFlashLatency+0x58>) - 80016f6: 4293 cmp r3, r2 - 80016f8: d901 bls.n 80016fe <UTILS_SetFlashLatency+0x2e> - { - /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - 80016fa: 2301 movs r3, #1 - 80016fc: 60bb str r3, [r7, #8] - } - /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */ - - LL_FLASH_SetLatency(latency); - 80016fe: 68bb ldr r3, [r7, #8] - 8001700: 0018 movs r0, r3 - 8001702: f7ff feef bl 80014e4 <LL_FLASH_SetLatency> - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (LL_FLASH_GetLatency() != latency) - 8001706: f7ff ff01 bl 800150c <LL_FLASH_GetLatency> - 800170a: 0002 movs r2, r0 - 800170c: 68bb ldr r3, [r7, #8] - 800170e: 4293 cmp r3, r2 - 8001710: d003 beq.n 800171a <UTILS_SetFlashLatency+0x4a> - { - status = ERROR; - 8001712: 230f movs r3, #15 - 8001714: 18fb adds r3, r7, r3 - 8001716: 2200 movs r2, #0 - 8001718: 701a strb r2, [r3, #0] - } - } - return status; - 800171a: 230f movs r3, #15 - 800171c: 18fb adds r3, r7, r3 - 800171e: 781b ldrb r3, [r3, #0] -} - 8001720: 0018 movs r0, r3 - 8001722: 46bd mov sp, r7 - 8001724: b004 add sp, #16 - 8001726: bd80 pop {r7, pc} - 8001728: 016e3600 .word 0x016e3600 - -0800172c <UTILS_GetPLLOutputFrequency>: - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @retval PLL output frequency (in Hz) - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) -{ - 800172c: b580 push {r7, lr} - 800172e: b084 sub sp, #16 - 8001730: af00 add r7, sp, #0 - 8001732: 6078 str r0, [r7, #4] - 8001734: 6039 str r1, [r7, #0] - uint32_t pllfreq = 0U; - 8001736: 2300 movs r3, #0 - 8001738: 60fb str r3, [r7, #12] - /* The application software must set correctly the PLL multiplication factor to - be in the range 16-48MHz */ -#if defined(RCC_PLLSRC_PREDIV1_SUPPORT) - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); -#else - pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul); - 800173a: 683b ldr r3, [r7, #0] - 800173c: 685b ldr r3, [r3, #4] - 800173e: 3301 adds r3, #1 - 8001740: 0019 movs r1, r3 - 8001742: 6878 ldr r0, [r7, #4] - 8001744: f000 f8d0 bl 80018e8 <__udivsi3> - 8001748: 0003 movs r3, r0 - 800174a: 0019 movs r1, r3 - 800174c: 683b ldr r3, [r7, #0] - 800174e: 681b ldr r3, [r3, #0] - 8001750: 0c9b lsrs r3, r3, #18 - 8001752: 220f movs r2, #15 - 8001754: 4013 ands r3, r2 - 8001756: 3302 adds r3, #2 - 8001758: 434b muls r3, r1 - 800175a: 60fb str r3, [r7, #12] -#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/ - assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); - - return pllfreq; - 800175c: 68fb ldr r3, [r7, #12] -} - 800175e: 0018 movs r0, r3 - 8001760: 46bd mov sp, r7 - 8001762: b004 add sp, #16 - 8001764: bd80 pop {r7, pc} - -08001766 <UTILS_PLL_IsBusy>: - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - 8001766: b580 push {r7, lr} - 8001768: b082 sub sp, #8 - 800176a: af00 add r7, sp, #0 - ErrorStatus status = SUCCESS; - 800176c: 1dfb adds r3, r7, #7 - 800176e: 2201 movs r2, #1 - 8001770: 701a strb r2, [r3, #0] - - /* Check if PLL is busy*/ - if (LL_RCC_PLL_IsReady() != 0U) - 8001772: f7ff fe63 bl 800143c <LL_RCC_PLL_IsReady> - 8001776: 1e03 subs r3, r0, #0 - 8001778: d002 beq.n 8001780 <UTILS_PLL_IsBusy+0x1a> - { - /* PLL configuration cannot be modified */ - status = ERROR; - 800177a: 1dfb adds r3, r7, #7 - 800177c: 2200 movs r2, #0 - 800177e: 701a strb r2, [r3, #0] - } - - - return status; - 8001780: 1dfb adds r3, r7, #7 - 8001782: 781b ldrb r3, [r3, #0] -} - 8001784: 0018 movs r0, r3 - 8001786: 46bd mov sp, r7 - 8001788: b002 add sp, #8 - 800178a: bd80 pop {r7, pc} - -0800178c <UTILS_EnablePLLAndSwitchSystem>: - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - 800178c: b590 push {r4, r7, lr} - 800178e: b085 sub sp, #20 - 8001790: af00 add r7, sp, #0 - 8001792: 6078 str r0, [r7, #4] - 8001794: 6039 str r1, [r7, #0] - ErrorStatus status = SUCCESS; - 8001796: 200f movs r0, #15 - 8001798: 183b adds r3, r7, r0 - 800179a: 2201 movs r2, #1 - 800179c: 701a strb r2, [r3, #0] - uint32_t sysclk_frequency_current = 0U; - 800179e: 2300 movs r3, #0 - 80017a0: 60bb str r3, [r7, #8] - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - - /* Calculate current SYSCLK frequency */ - sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[(UTILS_ClkInitStruct->AHBCLKDivider & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE]); - 80017a2: 4b2e ldr r3, [pc, #184] ; (800185c <UTILS_EnablePLLAndSwitchSystem+0xd0>) - 80017a4: 681a ldr r2, [r3, #0] - 80017a6: 683b ldr r3, [r7, #0] - 80017a8: 681b ldr r3, [r3, #0] - 80017aa: 091b lsrs r3, r3, #4 - 80017ac: 210f movs r1, #15 - 80017ae: 400b ands r3, r1 - 80017b0: 492b ldr r1, [pc, #172] ; (8001860 <UTILS_EnablePLLAndSwitchSystem+0xd4>) - 80017b2: 5ccb ldrb r3, [r1, r3] - 80017b4: 409a lsls r2, r3 - 80017b6: 0013 movs r3, r2 - 80017b8: 60bb str r3, [r7, #8] - - /* Increasing the number of wait states because of higher CPU frequency */ - if (sysclk_frequency_current < SYSCLK_Frequency) - 80017ba: 68ba ldr r2, [r7, #8] - 80017bc: 687b ldr r3, [r7, #4] - 80017be: 429a cmp r2, r3 - 80017c0: d206 bcs.n 80017d0 <UTILS_EnablePLLAndSwitchSystem+0x44> - { - /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - 80017c2: 183c adds r4, r7, r0 - 80017c4: 687b ldr r3, [r7, #4] - 80017c6: 0018 movs r0, r3 - 80017c8: f7ff ff82 bl 80016d0 <UTILS_SetFlashLatency> - 80017cc: 0003 movs r3, r0 - 80017ce: 7023 strb r3, [r4, #0] - } - - /* Update system clock configuration */ - if (status == SUCCESS) - 80017d0: 230f movs r3, #15 - 80017d2: 18fb adds r3, r7, r3 - 80017d4: 781b ldrb r3, [r3, #0] - 80017d6: 2b01 cmp r3, #1 - 80017d8: d11a bne.n 8001810 <UTILS_EnablePLLAndSwitchSystem+0x84> - { - /* Enable PLL */ - LL_RCC_PLL_Enable(); - 80017da: f7ff fe21 bl 8001420 <LL_RCC_PLL_Enable> - while (LL_RCC_PLL_IsReady() != 1U) - 80017de: 46c0 nop ; (mov r8, r8) - 80017e0: f7ff fe2c bl 800143c <LL_RCC_PLL_IsReady> - 80017e4: 0003 movs r3, r0 - 80017e6: 2b01 cmp r3, #1 - 80017e8: d1fa bne.n 80017e0 <UTILS_EnablePLLAndSwitchSystem+0x54> - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - 80017ea: 683b ldr r3, [r7, #0] - 80017ec: 681b ldr r3, [r3, #0] - 80017ee: 0018 movs r0, r3 - 80017f0: f7ff fdec bl 80013cc <LL_RCC_SetAHBPrescaler> - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - 80017f4: 2002 movs r0, #2 - 80017f6: f7ff fdc9 bl 800138c <LL_RCC_SetSysClkSource> - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - 80017fa: 46c0 nop ; (mov r8, r8) - 80017fc: f7ff fdda bl 80013b4 <LL_RCC_GetSysClkSource> - 8001800: 0003 movs r3, r0 - 8001802: 2b08 cmp r3, #8 - 8001804: d1fa bne.n 80017fc <UTILS_EnablePLLAndSwitchSystem+0x70> - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1 & APB2 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - 8001806: 683b ldr r3, [r7, #0] - 8001808: 685b ldr r3, [r3, #4] - 800180a: 0018 movs r0, r3 - 800180c: f7ff fdf2 bl 80013f4 <LL_RCC_SetAPB1Prescaler> - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (sysclk_frequency_current > SYSCLK_Frequency) - 8001810: 68ba ldr r2, [r7, #8] - 8001812: 687b ldr r3, [r7, #4] - 8001814: 429a cmp r2, r3 - 8001816: d907 bls.n 8001828 <UTILS_EnablePLLAndSwitchSystem+0x9c> - { - /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(SYSCLK_Frequency); - 8001818: 230f movs r3, #15 - 800181a: 18fc adds r4, r7, r3 - 800181c: 687b ldr r3, [r7, #4] - 800181e: 0018 movs r0, r3 - 8001820: f7ff ff56 bl 80016d0 <UTILS_SetFlashLatency> - 8001824: 0003 movs r3, r0 - 8001826: 7023 strb r3, [r4, #0] - } - - /* Update SystemCoreClock variable */ - if (status == SUCCESS) - 8001828: 230f movs r3, #15 - 800182a: 18fb adds r3, r7, r3 - 800182c: 781b ldrb r3, [r3, #0] - 800182e: 2b01 cmp r3, #1 - 8001830: d10c bne.n 800184c <UTILS_EnablePLLAndSwitchSystem+0xc0> - { - LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider)); - 8001832: 683b ldr r3, [r7, #0] - 8001834: 681b ldr r3, [r3, #0] - 8001836: 091b lsrs r3, r3, #4 - 8001838: 220f movs r2, #15 - 800183a: 4013 ands r3, r2 - 800183c: 4a08 ldr r2, [pc, #32] ; (8001860 <UTILS_EnablePLLAndSwitchSystem+0xd4>) - 800183e: 5cd3 ldrb r3, [r2, r3] - 8001840: 001a movs r2, r3 - 8001842: 687b ldr r3, [r7, #4] - 8001844: 40d3 lsrs r3, r2 - 8001846: 0018 movs r0, r3 - 8001848: f7ff fe9e bl 8001588 <LL_SetSystemCoreClock> - } - - return status; - 800184c: 230f movs r3, #15 - 800184e: 18fb adds r3, r7, r3 - 8001850: 781b ldrb r3, [r3, #0] -} - 8001852: 0018 movs r0, r3 - 8001854: 46bd mov sp, r7 - 8001856: b005 add sp, #20 - 8001858: bd90 pop {r4, r7, pc} - 800185a: 46c0 nop ; (mov r8, r8) - 800185c: 20000000 .word 0x20000000 - 8001860: 08001c24 .word 0x08001c24 - -08001864 <__sinit>: -#include <stdbool.h> - -int __errno = 0; -void *_impure_ptr = NULL; - -void __sinit(void) { - 8001864: b580 push {r7, lr} - 8001866: af00 add r7, sp, #0 -} - 8001868: 46c0 nop ; (mov r8, r8) - 800186a: 46bd mov sp, r7 - 800186c: bd80 pop {r7, pc} - -0800186e <memset>: - -void *memset(void *s, int c, size_t n) { - 800186e: b580 push {r7, lr} - 8001870: b086 sub sp, #24 - 8001872: af00 add r7, sp, #0 - 8001874: 60f8 str r0, [r7, #12] - 8001876: 60b9 str r1, [r7, #8] - 8001878: 607a str r2, [r7, #4] - char *end = (char *)s + n; - 800187a: 68fa ldr r2, [r7, #12] - 800187c: 687b ldr r3, [r7, #4] - 800187e: 18d3 adds r3, r2, r3 - 8001880: 613b str r3, [r7, #16] - for (char *p = (char *)s; p < end; p++) - 8001882: 68fb ldr r3, [r7, #12] - 8001884: 617b str r3, [r7, #20] - 8001886: e006 b.n 8001896 <memset+0x28> - *p = (char)c; - 8001888: 68bb ldr r3, [r7, #8] - 800188a: b2da uxtb r2, r3 - 800188c: 697b ldr r3, [r7, #20] - 800188e: 701a strb r2, [r3, #0] - for (char *p = (char *)s; p < end; p++) - 8001890: 697b ldr r3, [r7, #20] - 8001892: 3301 adds r3, #1 - 8001894: 617b str r3, [r7, #20] - 8001896: 697a ldr r2, [r7, #20] - 8001898: 693b ldr r3, [r7, #16] - 800189a: 429a cmp r2, r3 - 800189c: d3f4 bcc.n 8001888 <memset+0x1a> - return s; - 800189e: 68fb ldr r3, [r7, #12] -} - 80018a0: 0018 movs r0, r3 - 80018a2: 46bd mov sp, r7 - 80018a4: b006 add sp, #24 - 80018a6: bd80 pop {r7, pc} - -080018a8 <strlen>: - -size_t strlen(const char *s) { - 80018a8: b580 push {r7, lr} - 80018aa: b084 sub sp, #16 - 80018ac: af00 add r7, sp, #0 - 80018ae: 6078 str r0, [r7, #4] - const char *start = s; - 80018b0: 687b ldr r3, [r7, #4] - 80018b2: 60fb str r3, [r7, #12] - while (*s++); - 80018b4: 46c0 nop ; (mov r8, r8) - 80018b6: 687b ldr r3, [r7, #4] - 80018b8: 1c5a adds r2, r3, #1 - 80018ba: 607a str r2, [r7, #4] - 80018bc: 781b ldrb r3, [r3, #0] - 80018be: 2b00 cmp r3, #0 - 80018c0: d1f9 bne.n 80018b6 <strlen+0xe> - return s - start - 1; - 80018c2: 687a ldr r2, [r7, #4] - 80018c4: 68fb ldr r3, [r7, #12] - 80018c6: 1ad3 subs r3, r2, r3 - 80018c8: 3b01 subs r3, #1 -} - 80018ca: 0018 movs r0, r3 - 80018cc: 46bd mov sp, r7 - 80018ce: b004 add sp, #16 - 80018d0: bd80 pop {r7, pc} - -080018d2 <__assert_func>: - -void __assert_func(bool value) { - 80018d2: b580 push {r7, lr} - 80018d4: b082 sub sp, #8 - 80018d6: af00 add r7, sp, #0 - 80018d8: 0002 movs r2, r0 - 80018da: 1dfb adds r3, r7, #7 - 80018dc: 701a strb r2, [r3, #0] -} - 80018de: 46c0 nop ; (mov r8, r8) - 80018e0: 46bd mov sp, r7 - 80018e2: b002 add sp, #8 - 80018e4: bd80 pop {r7, pc} - ... - -080018e8 <__udivsi3>: - 80018e8: 2200 movs r2, #0 - 80018ea: 0843 lsrs r3, r0, #1 - 80018ec: 428b cmp r3, r1 - 80018ee: d374 bcc.n 80019da <__udivsi3+0xf2> - 80018f0: 0903 lsrs r3, r0, #4 - 80018f2: 428b cmp r3, r1 - 80018f4: d35f bcc.n 80019b6 <__udivsi3+0xce> - 80018f6: 0a03 lsrs r3, r0, #8 - 80018f8: 428b cmp r3, r1 - 80018fa: d344 bcc.n 8001986 <__udivsi3+0x9e> - 80018fc: 0b03 lsrs r3, r0, #12 - 80018fe: 428b cmp r3, r1 - 8001900: d328 bcc.n 8001954 <__udivsi3+0x6c> - 8001902: 0c03 lsrs r3, r0, #16 - 8001904: 428b cmp r3, r1 - 8001906: d30d bcc.n 8001924 <__udivsi3+0x3c> - 8001908: 22ff movs r2, #255 ; 0xff - 800190a: 0209 lsls r1, r1, #8 - 800190c: ba12 rev r2, r2 - 800190e: 0c03 lsrs r3, r0, #16 - 8001910: 428b cmp r3, r1 - 8001912: d302 bcc.n 800191a <__udivsi3+0x32> - 8001914: 1212 asrs r2, r2, #8 - 8001916: 0209 lsls r1, r1, #8 - 8001918: d065 beq.n 80019e6 <__udivsi3+0xfe> - 800191a: 0b03 lsrs r3, r0, #12 - 800191c: 428b cmp r3, r1 - 800191e: d319 bcc.n 8001954 <__udivsi3+0x6c> - 8001920: e000 b.n 8001924 <__udivsi3+0x3c> - 8001922: 0a09 lsrs r1, r1, #8 - 8001924: 0bc3 lsrs r3, r0, #15 - 8001926: 428b cmp r3, r1 - 8001928: d301 bcc.n 800192e <__udivsi3+0x46> - 800192a: 03cb lsls r3, r1, #15 - 800192c: 1ac0 subs r0, r0, r3 - 800192e: 4152 adcs r2, r2 - 8001930: 0b83 lsrs r3, r0, #14 - 8001932: 428b cmp r3, r1 - 8001934: d301 bcc.n 800193a <__udivsi3+0x52> - 8001936: 038b lsls r3, r1, #14 - 8001938: 1ac0 subs r0, r0, r3 - 800193a: 4152 adcs r2, r2 - 800193c: 0b43 lsrs r3, r0, #13 - 800193e: 428b cmp r3, r1 - 8001940: d301 bcc.n 8001946 <__udivsi3+0x5e> - 8001942: 034b lsls r3, r1, #13 - 8001944: 1ac0 subs r0, r0, r3 - 8001946: 4152 adcs r2, r2 - 8001948: 0b03 lsrs r3, r0, #12 - 800194a: 428b cmp r3, r1 - 800194c: d301 bcc.n 8001952 <__udivsi3+0x6a> - 800194e: 030b lsls r3, r1, #12 - 8001950: 1ac0 subs r0, r0, r3 - 8001952: 4152 adcs r2, r2 - 8001954: 0ac3 lsrs r3, r0, #11 - 8001956: 428b cmp r3, r1 - 8001958: d301 bcc.n 800195e <__udivsi3+0x76> - 800195a: 02cb lsls r3, r1, #11 - 800195c: 1ac0 subs r0, r0, r3 - 800195e: 4152 adcs r2, r2 - 8001960: 0a83 lsrs r3, r0, #10 - 8001962: 428b cmp r3, r1 - 8001964: d301 bcc.n 800196a <__udivsi3+0x82> - 8001966: 028b lsls r3, r1, #10 - 8001968: 1ac0 subs r0, r0, r3 - 800196a: 4152 adcs r2, r2 - 800196c: 0a43 lsrs r3, r0, #9 - 800196e: 428b cmp r3, r1 - 8001970: d301 bcc.n 8001976 <__udivsi3+0x8e> - 8001972: 024b lsls r3, r1, #9 - 8001974: 1ac0 subs r0, r0, r3 - 8001976: 4152 adcs r2, r2 - 8001978: 0a03 lsrs r3, r0, #8 - 800197a: 428b cmp r3, r1 - 800197c: d301 bcc.n 8001982 <__udivsi3+0x9a> - 800197e: 020b lsls r3, r1, #8 - 8001980: 1ac0 subs r0, r0, r3 - 8001982: 4152 adcs r2, r2 - 8001984: d2cd bcs.n 8001922 <__udivsi3+0x3a> - 8001986: 09c3 lsrs r3, r0, #7 - 8001988: 428b cmp r3, r1 - 800198a: d301 bcc.n 8001990 <__udivsi3+0xa8> - 800198c: 01cb lsls r3, r1, #7 - 800198e: 1ac0 subs r0, r0, r3 - 8001990: 4152 adcs r2, r2 - 8001992: 0983 lsrs r3, r0, #6 - 8001994: 428b cmp r3, r1 - 8001996: d301 bcc.n 800199c <__udivsi3+0xb4> - 8001998: 018b lsls r3, r1, #6 - 800199a: 1ac0 subs r0, r0, r3 - 800199c: 4152 adcs r2, r2 - 800199e: 0943 lsrs r3, r0, #5 - 80019a0: 428b cmp r3, r1 - 80019a2: d301 bcc.n 80019a8 <__udivsi3+0xc0> - 80019a4: 014b lsls r3, r1, #5 - 80019a6: 1ac0 subs r0, r0, r3 - 80019a8: 4152 adcs r2, r2 - 80019aa: 0903 lsrs r3, r0, #4 - 80019ac: 428b cmp r3, r1 - 80019ae: d301 bcc.n 80019b4 <__udivsi3+0xcc> - 80019b0: 010b lsls r3, r1, #4 - 80019b2: 1ac0 subs r0, r0, r3 - 80019b4: 4152 adcs r2, r2 - 80019b6: 08c3 lsrs r3, r0, #3 - 80019b8: 428b cmp r3, r1 - 80019ba: d301 bcc.n 80019c0 <__udivsi3+0xd8> - 80019bc: 00cb lsls r3, r1, #3 - 80019be: 1ac0 subs r0, r0, r3 - 80019c0: 4152 adcs r2, r2 - 80019c2: 0883 lsrs r3, r0, #2 - 80019c4: 428b cmp r3, r1 - 80019c6: d301 bcc.n 80019cc <__udivsi3+0xe4> - 80019c8: 008b lsls r3, r1, #2 - 80019ca: 1ac0 subs r0, r0, r3 - 80019cc: 4152 adcs r2, r2 - 80019ce: 0843 lsrs r3, r0, #1 - 80019d0: 428b cmp r3, r1 - 80019d2: d301 bcc.n 80019d8 <__udivsi3+0xf0> - 80019d4: 004b lsls r3, r1, #1 - 80019d6: 1ac0 subs r0, r0, r3 - 80019d8: 4152 adcs r2, r2 - 80019da: 1a41 subs r1, r0, r1 - 80019dc: d200 bcs.n 80019e0 <__udivsi3+0xf8> - 80019de: 4601 mov r1, r0 - 80019e0: 4152 adcs r2, r2 - 80019e2: 4610 mov r0, r2 - 80019e4: 4770 bx lr - 80019e6: e7ff b.n 80019e8 <__udivsi3+0x100> - 80019e8: b501 push {r0, lr} - 80019ea: 2000 movs r0, #0 - 80019ec: f000 f8f0 bl 8001bd0 <__aeabi_idiv0> - 80019f0: bd02 pop {r1, pc} - 80019f2: 46c0 nop ; (mov r8, r8) - -080019f4 <__aeabi_uidivmod>: - 80019f4: 2900 cmp r1, #0 - 80019f6: d0f7 beq.n 80019e8 <__udivsi3+0x100> - 80019f8: e776 b.n 80018e8 <__udivsi3> - 80019fa: 4770 bx lr - -080019fc <__divsi3>: - 80019fc: 4603 mov r3, r0 - 80019fe: 430b orrs r3, r1 - 8001a00: d47f bmi.n 8001b02 <__divsi3+0x106> - 8001a02: 2200 movs r2, #0 - 8001a04: 0843 lsrs r3, r0, #1 - 8001a06: 428b cmp r3, r1 - 8001a08: d374 bcc.n 8001af4 <__divsi3+0xf8> - 8001a0a: 0903 lsrs r3, r0, #4 - 8001a0c: 428b cmp r3, r1 - 8001a0e: d35f bcc.n 8001ad0 <__divsi3+0xd4> - 8001a10: 0a03 lsrs r3, r0, #8 - 8001a12: 428b cmp r3, r1 - 8001a14: d344 bcc.n 8001aa0 <__divsi3+0xa4> - 8001a16: 0b03 lsrs r3, r0, #12 - 8001a18: 428b cmp r3, r1 - 8001a1a: d328 bcc.n 8001a6e <__divsi3+0x72> - 8001a1c: 0c03 lsrs r3, r0, #16 - 8001a1e: 428b cmp r3, r1 - 8001a20: d30d bcc.n 8001a3e <__divsi3+0x42> - 8001a22: 22ff movs r2, #255 ; 0xff - 8001a24: 0209 lsls r1, r1, #8 - 8001a26: ba12 rev r2, r2 - 8001a28: 0c03 lsrs r3, r0, #16 - 8001a2a: 428b cmp r3, r1 - 8001a2c: d302 bcc.n 8001a34 <__divsi3+0x38> - 8001a2e: 1212 asrs r2, r2, #8 - 8001a30: 0209 lsls r1, r1, #8 - 8001a32: d065 beq.n 8001b00 <__divsi3+0x104> - 8001a34: 0b03 lsrs r3, r0, #12 - 8001a36: 428b cmp r3, r1 - 8001a38: d319 bcc.n 8001a6e <__divsi3+0x72> - 8001a3a: e000 b.n 8001a3e <__divsi3+0x42> - 8001a3c: 0a09 lsrs r1, r1, #8 - 8001a3e: 0bc3 lsrs r3, r0, #15 - 8001a40: 428b cmp r3, r1 - 8001a42: d301 bcc.n 8001a48 <__divsi3+0x4c> - 8001a44: 03cb lsls r3, r1, #15 - 8001a46: 1ac0 subs r0, r0, r3 - 8001a48: 4152 adcs r2, r2 - 8001a4a: 0b83 lsrs r3, r0, #14 - 8001a4c: 428b cmp r3, r1 - 8001a4e: d301 bcc.n 8001a54 <__divsi3+0x58> - 8001a50: 038b lsls r3, r1, #14 - 8001a52: 1ac0 subs r0, r0, r3 - 8001a54: 4152 adcs r2, r2 - 8001a56: 0b43 lsrs r3, r0, #13 - 8001a58: 428b cmp r3, r1 - 8001a5a: d301 bcc.n 8001a60 <__divsi3+0x64> - 8001a5c: 034b lsls r3, r1, #13 - 8001a5e: 1ac0 subs r0, r0, r3 - 8001a60: 4152 adcs r2, r2 - 8001a62: 0b03 lsrs r3, r0, #12 - 8001a64: 428b cmp r3, r1 - 8001a66: d301 bcc.n 8001a6c <__divsi3+0x70> - 8001a68: 030b lsls r3, r1, #12 - 8001a6a: 1ac0 subs r0, r0, r3 - 8001a6c: 4152 adcs r2, r2 - 8001a6e: 0ac3 lsrs r3, r0, #11 - 8001a70: 428b cmp r3, r1 - 8001a72: d301 bcc.n 8001a78 <__divsi3+0x7c> - 8001a74: 02cb lsls r3, r1, #11 - 8001a76: 1ac0 subs r0, r0, r3 - 8001a78: 4152 adcs r2, r2 - 8001a7a: 0a83 lsrs r3, r0, #10 - 8001a7c: 428b cmp r3, r1 - 8001a7e: d301 bcc.n 8001a84 <__divsi3+0x88> - 8001a80: 028b lsls r3, r1, #10 - 8001a82: 1ac0 subs r0, r0, r3 - 8001a84: 4152 adcs r2, r2 - 8001a86: 0a43 lsrs r3, r0, #9 - 8001a88: 428b cmp r3, r1 - 8001a8a: d301 bcc.n 8001a90 <__divsi3+0x94> - 8001a8c: 024b lsls r3, r1, #9 - 8001a8e: 1ac0 subs r0, r0, r3 - 8001a90: 4152 adcs r2, r2 - 8001a92: 0a03 lsrs r3, r0, #8 - 8001a94: 428b cmp r3, r1 - 8001a96: d301 bcc.n 8001a9c <__divsi3+0xa0> - 8001a98: 020b lsls r3, r1, #8 - 8001a9a: 1ac0 subs r0, r0, r3 - 8001a9c: 4152 adcs r2, r2 - 8001a9e: d2cd bcs.n 8001a3c <__divsi3+0x40> - 8001aa0: 09c3 lsrs r3, r0, #7 - 8001aa2: 428b cmp r3, r1 - 8001aa4: d301 bcc.n 8001aaa <__divsi3+0xae> - 8001aa6: 01cb lsls r3, r1, #7 - 8001aa8: 1ac0 subs r0, r0, r3 - 8001aaa: 4152 adcs r2, r2 - 8001aac: 0983 lsrs r3, r0, #6 - 8001aae: 428b cmp r3, r1 - 8001ab0: d301 bcc.n 8001ab6 <__divsi3+0xba> - 8001ab2: 018b lsls r3, r1, #6 - 8001ab4: 1ac0 subs r0, r0, r3 - 8001ab6: 4152 adcs r2, r2 - 8001ab8: 0943 lsrs r3, r0, #5 - 8001aba: 428b cmp r3, r1 - 8001abc: d301 bcc.n 8001ac2 <__divsi3+0xc6> - 8001abe: 014b lsls r3, r1, #5 - 8001ac0: 1ac0 subs r0, r0, r3 - 8001ac2: 4152 adcs r2, r2 - 8001ac4: 0903 lsrs r3, r0, #4 - 8001ac6: 428b cmp r3, r1 - 8001ac8: d301 bcc.n 8001ace <__divsi3+0xd2> - 8001aca: 010b lsls r3, r1, #4 - 8001acc: 1ac0 subs r0, r0, r3 - 8001ace: 4152 adcs r2, r2 - 8001ad0: 08c3 lsrs r3, r0, #3 - 8001ad2: 428b cmp r3, r1 - 8001ad4: d301 bcc.n 8001ada <__divsi3+0xde> - 8001ad6: 00cb lsls r3, r1, #3 - 8001ad8: 1ac0 subs r0, r0, r3 - 8001ada: 4152 adcs r2, r2 - 8001adc: 0883 lsrs r3, r0, #2 - 8001ade: 428b cmp r3, r1 - 8001ae0: d301 bcc.n 8001ae6 <__divsi3+0xea> - 8001ae2: 008b lsls r3, r1, #2 - 8001ae4: 1ac0 subs r0, r0, r3 - 8001ae6: 4152 adcs r2, r2 - 8001ae8: 0843 lsrs r3, r0, #1 - 8001aea: 428b cmp r3, r1 - 8001aec: d301 bcc.n 8001af2 <__divsi3+0xf6> - 8001aee: 004b lsls r3, r1, #1 - 8001af0: 1ac0 subs r0, r0, r3 - 8001af2: 4152 adcs r2, r2 - 8001af4: 1a41 subs r1, r0, r1 - 8001af6: d200 bcs.n 8001afa <__divsi3+0xfe> - 8001af8: 4601 mov r1, r0 - 8001afa: 4152 adcs r2, r2 - 8001afc: 4610 mov r0, r2 - 8001afe: 4770 bx lr - 8001b00: e05d b.n 8001bbe <__divsi3+0x1c2> - 8001b02: 0fca lsrs r2, r1, #31 - 8001b04: d000 beq.n 8001b08 <__divsi3+0x10c> - 8001b06: 4249 negs r1, r1 - 8001b08: 1003 asrs r3, r0, #32 - 8001b0a: d300 bcc.n 8001b0e <__divsi3+0x112> - 8001b0c: 4240 negs r0, r0 - 8001b0e: 4053 eors r3, r2 - 8001b10: 2200 movs r2, #0 - 8001b12: 469c mov ip, r3 - 8001b14: 0903 lsrs r3, r0, #4 - 8001b16: 428b cmp r3, r1 - 8001b18: d32d bcc.n 8001b76 <__divsi3+0x17a> - 8001b1a: 0a03 lsrs r3, r0, #8 - 8001b1c: 428b cmp r3, r1 - 8001b1e: d312 bcc.n 8001b46 <__divsi3+0x14a> - 8001b20: 22fc movs r2, #252 ; 0xfc - 8001b22: 0189 lsls r1, r1, #6 - 8001b24: ba12 rev r2, r2 - 8001b26: 0a03 lsrs r3, r0, #8 - 8001b28: 428b cmp r3, r1 - 8001b2a: d30c bcc.n 8001b46 <__divsi3+0x14a> - 8001b2c: 0189 lsls r1, r1, #6 - 8001b2e: 1192 asrs r2, r2, #6 - 8001b30: 428b cmp r3, r1 - 8001b32: d308 bcc.n 8001b46 <__divsi3+0x14a> - 8001b34: 0189 lsls r1, r1, #6 - 8001b36: 1192 asrs r2, r2, #6 - 8001b38: 428b cmp r3, r1 - 8001b3a: d304 bcc.n 8001b46 <__divsi3+0x14a> - 8001b3c: 0189 lsls r1, r1, #6 - 8001b3e: d03a beq.n 8001bb6 <__divsi3+0x1ba> - 8001b40: 1192 asrs r2, r2, #6 - 8001b42: e000 b.n 8001b46 <__divsi3+0x14a> - 8001b44: 0989 lsrs r1, r1, #6 - 8001b46: 09c3 lsrs r3, r0, #7 - 8001b48: 428b cmp r3, r1 - 8001b4a: d301 bcc.n 8001b50 <__divsi3+0x154> - 8001b4c: 01cb lsls r3, r1, #7 - 8001b4e: 1ac0 subs r0, r0, r3 - 8001b50: 4152 adcs r2, r2 - 8001b52: 0983 lsrs r3, r0, #6 - 8001b54: 428b cmp r3, r1 - 8001b56: d301 bcc.n 8001b5c <__divsi3+0x160> - 8001b58: 018b lsls r3, r1, #6 - 8001b5a: 1ac0 subs r0, r0, r3 - 8001b5c: 4152 adcs r2, r2 - 8001b5e: 0943 lsrs r3, r0, #5 - 8001b60: 428b cmp r3, r1 - 8001b62: d301 bcc.n 8001b68 <__divsi3+0x16c> - 8001b64: 014b lsls r3, r1, #5 - 8001b66: 1ac0 subs r0, r0, r3 - 8001b68: 4152 adcs r2, r2 - 8001b6a: 0903 lsrs r3, r0, #4 - 8001b6c: 428b cmp r3, r1 - 8001b6e: d301 bcc.n 8001b74 <__divsi3+0x178> - 8001b70: 010b lsls r3, r1, #4 - 8001b72: 1ac0 subs r0, r0, r3 - 8001b74: 4152 adcs r2, r2 - 8001b76: 08c3 lsrs r3, r0, #3 - 8001b78: 428b cmp r3, r1 - 8001b7a: d301 bcc.n 8001b80 <__divsi3+0x184> - 8001b7c: 00cb lsls r3, r1, #3 - 8001b7e: 1ac0 subs r0, r0, r3 - 8001b80: 4152 adcs r2, r2 - 8001b82: 0883 lsrs r3, r0, #2 - 8001b84: 428b cmp r3, r1 - 8001b86: d301 bcc.n 8001b8c <__divsi3+0x190> - 8001b88: 008b lsls r3, r1, #2 - 8001b8a: 1ac0 subs r0, r0, r3 - 8001b8c: 4152 adcs r2, r2 - 8001b8e: d2d9 bcs.n 8001b44 <__divsi3+0x148> - 8001b90: 0843 lsrs r3, r0, #1 - 8001b92: 428b cmp r3, r1 - 8001b94: d301 bcc.n 8001b9a <__divsi3+0x19e> - 8001b96: 004b lsls r3, r1, #1 - 8001b98: 1ac0 subs r0, r0, r3 - 8001b9a: 4152 adcs r2, r2 - 8001b9c: 1a41 subs r1, r0, r1 - 8001b9e: d200 bcs.n 8001ba2 <__divsi3+0x1a6> - 8001ba0: 4601 mov r1, r0 - 8001ba2: 4663 mov r3, ip - 8001ba4: 4152 adcs r2, r2 - 8001ba6: 105b asrs r3, r3, #1 - 8001ba8: 4610 mov r0, r2 - 8001baa: d301 bcc.n 8001bb0 <__divsi3+0x1b4> - 8001bac: 4240 negs r0, r0 - 8001bae: 2b00 cmp r3, #0 - 8001bb0: d500 bpl.n 8001bb4 <__divsi3+0x1b8> - 8001bb2: 4249 negs r1, r1 - 8001bb4: 4770 bx lr - 8001bb6: 4663 mov r3, ip - 8001bb8: 105b asrs r3, r3, #1 - 8001bba: d300 bcc.n 8001bbe <__divsi3+0x1c2> - 8001bbc: 4240 negs r0, r0 - 8001bbe: b501 push {r0, lr} - 8001bc0: 2000 movs r0, #0 - 8001bc2: f000 f805 bl 8001bd0 <__aeabi_idiv0> - 8001bc6: bd02 pop {r1, pc} - -08001bc8 <__aeabi_idivmod>: - 8001bc8: 2900 cmp r1, #0 - 8001bca: d0f8 beq.n 8001bbe <__divsi3+0x1c2> - 8001bcc: e716 b.n 80019fc <__divsi3> - 8001bce: 4770 bx lr - -08001bd0 <__aeabi_idiv0>: - 8001bd0: 4770 bx lr - 8001bd2: 46c0 nop ; (mov r8, r8) - -08001bd4 <Reset_Handler>: - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - 8001bd4: 480c ldr r0, [pc, #48] ; (8001c08 <LoopForever+0x2>) - mov sp, r0 /* set stack pointer */ - 8001bd6: 4685 mov sp, r0 - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - 8001bd8: 2100 movs r1, #0 - b LoopCopyDataInit - 8001bda: e003 b.n 8001be4 <LoopCopyDataInit> - -08001bdc <CopyDataInit>: - -CopyDataInit: - ldr r3, =_sidata - 8001bdc: 4b0b ldr r3, [pc, #44] ; (8001c0c <LoopForever+0x6>) - ldr r3, [r3, r1] - 8001bde: 585b ldr r3, [r3, r1] - str r3, [r0, r1] - 8001be0: 5043 str r3, [r0, r1] - adds r1, r1, #4 - 8001be2: 3104 adds r1, #4 - -08001be4 <LoopCopyDataInit>: - -LoopCopyDataInit: - ldr r0, =_sdata - 8001be4: 480a ldr r0, [pc, #40] ; (8001c10 <LoopForever+0xa>) - ldr r3, =_edata - 8001be6: 4b0b ldr r3, [pc, #44] ; (8001c14 <LoopForever+0xe>) - adds r2, r0, r1 - 8001be8: 1842 adds r2, r0, r1 - cmp r2, r3 - 8001bea: 429a cmp r2, r3 - bcc CopyDataInit - 8001bec: d3f6 bcc.n 8001bdc <CopyDataInit> - ldr r2, =_sbss - 8001bee: 4a0a ldr r2, [pc, #40] ; (8001c18 <LoopForever+0x12>) - b LoopFillZerobss - 8001bf0: e002 b.n 8001bf8 <LoopFillZerobss> - -08001bf2 <FillZerobss>: -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - 8001bf2: 2300 movs r3, #0 - str r3, [r2] - 8001bf4: 6013 str r3, [r2, #0] - adds r2, r2, #4 - 8001bf6: 3204 adds r2, #4 - -08001bf8 <LoopFillZerobss>: - - -LoopFillZerobss: - ldr r3, = _ebss - 8001bf8: 4b08 ldr r3, [pc, #32] ; (8001c1c <LoopForever+0x16>) - cmp r2, r3 - 8001bfa: 429a cmp r2, r3 - bcc FillZerobss - 8001bfc: d3f9 bcc.n 8001bf2 <FillZerobss> - -/* Call the clock system intitialization function.*/ - bl SystemInit - 8001bfe: f7ff faad bl 800115c <SystemInit> -/* Call static constructors */ -// bl __libc_init_array -/* Call the application's entry point.*/ - bl main - 8001c02: f7fe fb0a bl 800021a <main> - -08001c06 <LoopForever>: - -LoopForever: - b LoopForever - 8001c06: e7fe b.n 8001c06 <LoopForever> - ldr r0, =_estack - 8001c08: 20001000 .word 0x20001000 - ldr r3, =_sidata - 8001c0c: 08001c3c .word 0x08001c3c - ldr r0, =_sdata - 8001c10: 20000000 .word 0x20000000 - ldr r3, =_edata - 8001c14: 20000094 .word 0x20000094 - ldr r2, =_sbss - 8001c18: 20000094 .word 0x20000094 - ldr r3, = _ebss - 8001c1c: 200003d4 .word 0x200003d4 - -08001c20 <ADC1_IRQHandler>: - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - 8001c20: e7fe b.n 8001c20 <ADC1_IRQHandler> - ... - -08001c24 <AHBPrescTable>: - ... - 8001c2c: 0201 0403 0706 0908 ........ - -08001c34 <APBPrescTable>: - 8001c34: 0000 0000 0201 0403 ........ |